1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "sid.h" 27 #include "r600_dpm.h" 28 #include "si_dpm.h" 29 #include "atom.h" 30 #include <linux/math64.h> 31 #include <linux/seq_file.h> 32 33 #define MC_CG_ARB_FREQ_F0 0x0a 34 #define MC_CG_ARB_FREQ_F1 0x0b 35 #define MC_CG_ARB_FREQ_F2 0x0c 36 #define MC_CG_ARB_FREQ_F3 0x0d 37 38 #define SMC_RAM_END 0x20000 39 40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 41 42 static const struct si_cac_config_reg cac_weights_tahiti[] = 43 { 44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 104 { 0xFFFFFFFF } 105 }; 106 107 static const struct si_cac_config_reg lcac_tahiti[] = 108 { 109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0xFFFFFFFF } 196 197 }; 198 199 static const struct si_cac_config_reg cac_override_tahiti[] = 200 { 201 { 0xFFFFFFFF } 202 }; 203 204 static const struct si_powertune_data powertune_data_tahiti = 205 { 206 ((1 << 16) | 27027), 207 6, 208 0, 209 4, 210 95, 211 { 212 0UL, 213 0UL, 214 4521550UL, 215 309631529UL, 216 -1270850L, 217 4513710L, 218 40 219 }, 220 595000000UL, 221 12, 222 { 223 0, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0 231 }, 232 true 233 }; 234 235 static const struct si_dte_data dte_data_tahiti = 236 { 237 { 1159409, 0, 0, 0, 0 }, 238 { 777, 0, 0, 0, 0 }, 239 2, 240 54000, 241 127000, 242 25, 243 2, 244 10, 245 13, 246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 249 85, 250 false 251 }; 252 253 static const struct si_dte_data dte_data_tahiti_le = 254 { 255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 257 0x5, 258 0xAFC8, 259 0x64, 260 0x32, 261 1, 262 0, 263 0x10, 264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 267 85, 268 true 269 }; 270 271 static const struct si_dte_data dte_data_tahiti_pro = 272 { 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 274 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 275 5, 276 45000, 277 100, 278 0xA, 279 1, 280 0, 281 0x10, 282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 285 90, 286 true 287 }; 288 289 static const struct si_dte_data dte_data_new_zealand = 290 { 291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 293 0x5, 294 0xAFC8, 295 0x69, 296 0x32, 297 1, 298 0, 299 0x10, 300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 303 85, 304 true 305 }; 306 307 static const struct si_dte_data dte_data_aruba_pro = 308 { 309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 310 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 311 5, 312 45000, 313 100, 314 0xA, 315 1, 316 0, 317 0x10, 318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 321 90, 322 true 323 }; 324 325 static const struct si_dte_data dte_data_malta = 326 { 327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 328 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 329 5, 330 45000, 331 100, 332 0xA, 333 1, 334 0, 335 0x10, 336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 339 90, 340 true 341 }; 342 343 struct si_cac_config_reg cac_weights_pitcairn[] = 344 { 345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 405 { 0xFFFFFFFF } 406 }; 407 408 static const struct si_cac_config_reg lcac_pitcairn[] = 409 { 410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497 }; 498 499 static const struct si_cac_config_reg cac_override_pitcairn[] = 500 { 501 { 0xFFFFFFFF } 502 }; 503 504 static const struct si_powertune_data powertune_data_pitcairn = 505 { 506 ((1 << 16) | 27027), 507 5, 508 0, 509 6, 510 100, 511 { 512 51600000UL, 513 1800000UL, 514 7194395UL, 515 309631529UL, 516 -1270850L, 517 4513710L, 518 100 519 }, 520 117830498UL, 521 12, 522 { 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0 531 }, 532 true 533 }; 534 535 static const struct si_dte_data dte_data_pitcairn = 536 { 537 { 0, 0, 0, 0, 0 }, 538 { 0, 0, 0, 0, 0 }, 539 0, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 0, 550 false 551 }; 552 553 static const struct si_dte_data dte_data_curacao_xt = 554 { 555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 556 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 557 5, 558 45000, 559 100, 560 0xA, 561 1, 562 0, 563 0x10, 564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 567 90, 568 true 569 }; 570 571 static const struct si_dte_data dte_data_curacao_pro = 572 { 573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 574 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 5, 576 45000, 577 100, 578 0xA, 579 1, 580 0, 581 0x10, 582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 585 90, 586 true 587 }; 588 589 static const struct si_dte_data dte_data_neptune_xt = 590 { 591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 592 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 593 5, 594 45000, 595 100, 596 0xA, 597 1, 598 0, 599 0x10, 600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 603 90, 604 true 605 }; 606 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 608 { 609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 669 { 0xFFFFFFFF } 670 }; 671 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 673 { 674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 734 { 0xFFFFFFFF } 735 }; 736 737 static const struct si_cac_config_reg cac_weights_heathrow[] = 738 { 739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 799 { 0xFFFFFFFF } 800 }; 801 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 803 { 804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 864 { 0xFFFFFFFF } 865 }; 866 867 static const struct si_cac_config_reg cac_weights_cape_verde[] = 868 { 869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 929 { 0xFFFFFFFF } 930 }; 931 932 static const struct si_cac_config_reg lcac_cape_verde[] = 933 { 934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0xFFFFFFFF } 989 }; 990 991 static const struct si_cac_config_reg cac_override_cape_verde[] = 992 { 993 { 0xFFFFFFFF } 994 }; 995 996 static const struct si_powertune_data powertune_data_cape_verde = 997 { 998 ((1 << 16) | 0x6993), 999 5, 1000 0, 1001 7, 1002 105, 1003 { 1004 0UL, 1005 0UL, 1006 7194395UL, 1007 309631529UL, 1008 -1270850L, 1009 4513710L, 1010 100 1011 }, 1012 117830498UL, 1013 12, 1014 { 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0 1023 }, 1024 true 1025 }; 1026 1027 static const struct si_dte_data dte_data_cape_verde = 1028 { 1029 { 0, 0, 0, 0, 0 }, 1030 { 0, 0, 0, 0, 0 }, 1031 0, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 0, 1042 false 1043 }; 1044 1045 static const struct si_dte_data dte_data_venus_xtx = 1046 { 1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1049 5, 1050 55000, 1051 0x69, 1052 0xA, 1053 1, 1054 0, 1055 0x3, 1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 90, 1060 true 1061 }; 1062 1063 static const struct si_dte_data dte_data_venus_xt = 1064 { 1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1067 5, 1068 55000, 1069 0x69, 1070 0xA, 1071 1, 1072 0, 1073 0x3, 1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 90, 1078 true 1079 }; 1080 1081 static const struct si_dte_data dte_data_venus_pro = 1082 { 1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1085 5, 1086 55000, 1087 0x69, 1088 0xA, 1089 1, 1090 0, 1091 0x3, 1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 90, 1096 true 1097 }; 1098 1099 struct si_cac_config_reg cac_weights_oland[] = 1100 { 1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1161 { 0xFFFFFFFF } 1162 }; 1163 1164 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1165 { 1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0xFFFFFFFF } 1227 }; 1228 1229 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1230 { 1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1291 { 0xFFFFFFFF } 1292 }; 1293 1294 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1295 { 1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1356 { 0xFFFFFFFF } 1357 }; 1358 1359 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1360 { 1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0xFFFFFFFF } 1422 }; 1423 1424 static const struct si_cac_config_reg lcac_oland[] = 1425 { 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469 }; 1470 1471 static const struct si_cac_config_reg lcac_mars_pro[] = 1472 { 1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0xFFFFFFFF } 1516 }; 1517 1518 static const struct si_cac_config_reg cac_override_oland[] = 1519 { 1520 { 0xFFFFFFFF } 1521 }; 1522 1523 static const struct si_powertune_data powertune_data_oland = 1524 { 1525 ((1 << 16) | 0x6993), 1526 5, 1527 0, 1528 7, 1529 105, 1530 { 1531 0UL, 1532 0UL, 1533 7194395UL, 1534 309631529UL, 1535 -1270850L, 1536 4513710L, 1537 100 1538 }, 1539 117830498UL, 1540 12, 1541 { 1542 0, 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0 1550 }, 1551 true 1552 }; 1553 1554 static const struct si_powertune_data powertune_data_mars_pro = 1555 { 1556 ((1 << 16) | 0x6993), 1557 5, 1558 0, 1559 7, 1560 105, 1561 { 1562 0UL, 1563 0UL, 1564 7194395UL, 1565 309631529UL, 1566 -1270850L, 1567 4513710L, 1568 100 1569 }, 1570 117830498UL, 1571 12, 1572 { 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0 1581 }, 1582 true 1583 }; 1584 1585 static const struct si_dte_data dte_data_oland = 1586 { 1587 { 0, 0, 0, 0, 0 }, 1588 { 0, 0, 0, 0, 0 }, 1589 0, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 0, 1600 false 1601 }; 1602 1603 static const struct si_dte_data dte_data_mars_pro = 1604 { 1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1606 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1607 5, 1608 55000, 1609 105, 1610 0xA, 1611 1, 1612 0, 1613 0x10, 1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1617 90, 1618 true 1619 }; 1620 1621 static const struct si_dte_data dte_data_sun_xt = 1622 { 1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1624 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1625 5, 1626 55000, 1627 105, 1628 0xA, 1629 1, 1630 0, 1631 0x10, 1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1635 90, 1636 true 1637 }; 1638 1639 1640 static const struct si_cac_config_reg cac_weights_hainan[] = 1641 { 1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1702 { 0xFFFFFFFF } 1703 }; 1704 1705 static const struct si_powertune_data powertune_data_hainan = 1706 { 1707 ((1 << 16) | 0x6993), 1708 5, 1709 0, 1710 9, 1711 105, 1712 { 1713 0UL, 1714 0UL, 1715 7194395UL, 1716 309631529UL, 1717 -1270850L, 1718 4513710L, 1719 100 1720 }, 1721 117830498UL, 1722 12, 1723 { 1724 0, 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0 1732 }, 1733 true 1734 }; 1735 1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1740 1741 extern int si_mc_load_microcode(struct radeon_device *rdev); 1742 1743 static int si_populate_voltage_value(struct radeon_device *rdev, 1744 const struct atom_voltage_table *table, 1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1746 static int si_get_std_voltage_value(struct radeon_device *rdev, 1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1748 u16 *std_voltage); 1749 static int si_write_smc_soft_register(struct radeon_device *rdev, 1750 u16 reg_offset, u32 value); 1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1752 struct rv7xx_pl *pl, 1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1754 static int si_calculate_sclk_params(struct radeon_device *rdev, 1755 u32 engine_clock, 1756 SISLANDS_SMC_SCLK_VALUE *sclk); 1757 1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1759 { 1760 struct si_power_info *pi = rdev->pm.dpm.priv; 1761 1762 return pi; 1763 } 1764 1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1766 u16 v, s32 t, u32 ileakage, u32 *leakage) 1767 { 1768 s64 kt, kv, leakage_w, i_leakage, vddc; 1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1770 s64 tmp; 1771 1772 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1773 vddc = div64_s64(drm_int2fixp(v), 1000); 1774 temperature = div64_s64(drm_int2fixp(t), 1000); 1775 1776 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1777 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1778 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1779 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1780 t_ref = drm_int2fixp(coeff->t_ref); 1781 1782 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1783 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1784 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1785 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1786 1787 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1788 1789 *leakage = drm_fixp2int(leakage_w * 1000); 1790 } 1791 1792 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1793 const struct ni_leakage_coeffients *coeff, 1794 u16 v, 1795 s32 t, 1796 u32 i_leakage, 1797 u32 *leakage) 1798 { 1799 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1800 } 1801 1802 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1803 const u32 fixed_kt, u16 v, 1804 u32 ileakage, u32 *leakage) 1805 { 1806 s64 kt, kv, leakage_w, i_leakage, vddc; 1807 1808 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1809 vddc = div64_s64(drm_int2fixp(v), 1000); 1810 1811 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1812 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1813 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1814 1815 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1816 1817 *leakage = drm_fixp2int(leakage_w * 1000); 1818 } 1819 1820 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1821 const struct ni_leakage_coeffients *coeff, 1822 const u32 fixed_kt, 1823 u16 v, 1824 u32 i_leakage, 1825 u32 *leakage) 1826 { 1827 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1828 } 1829 1830 1831 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1832 struct si_dte_data *dte_data) 1833 { 1834 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1835 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1836 u32 k = dte_data->k; 1837 u32 t_max = dte_data->max_t; 1838 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1839 u32 t_0 = dte_data->t0; 1840 u32 i; 1841 1842 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1843 dte_data->tdep_count = 3; 1844 1845 for (i = 0; i < k; i++) { 1846 dte_data->r[i] = 1847 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1848 (p_limit2 * (u32)100); 1849 } 1850 1851 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1852 1853 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1854 dte_data->tdep_r[i] = dte_data->r[4]; 1855 } 1856 } else { 1857 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1858 } 1859 } 1860 1861 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1862 { 1863 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1864 struct si_power_info *si_pi = si_get_pi(rdev); 1865 bool update_dte_from_pl2 = false; 1866 1867 if (rdev->family == CHIP_TAHITI) { 1868 si_pi->cac_weights = cac_weights_tahiti; 1869 si_pi->lcac_config = lcac_tahiti; 1870 si_pi->cac_override = cac_override_tahiti; 1871 si_pi->powertune_data = &powertune_data_tahiti; 1872 si_pi->dte_data = dte_data_tahiti; 1873 1874 switch (rdev->pdev->device) { 1875 case 0x6798: 1876 si_pi->dte_data.enable_dte_by_default = true; 1877 break; 1878 case 0x6799: 1879 si_pi->dte_data = dte_data_new_zealand; 1880 break; 1881 case 0x6790: 1882 case 0x6791: 1883 case 0x6792: 1884 case 0x679E: 1885 si_pi->dte_data = dte_data_aruba_pro; 1886 update_dte_from_pl2 = true; 1887 break; 1888 case 0x679B: 1889 si_pi->dte_data = dte_data_malta; 1890 update_dte_from_pl2 = true; 1891 break; 1892 case 0x679A: 1893 si_pi->dte_data = dte_data_tahiti_pro; 1894 update_dte_from_pl2 = true; 1895 break; 1896 default: 1897 if (si_pi->dte_data.enable_dte_by_default == true) 1898 DRM_ERROR("DTE is not enabled!\n"); 1899 break; 1900 } 1901 } else if (rdev->family == CHIP_PITCAIRN) { 1902 switch (rdev->pdev->device) { 1903 case 0x6810: 1904 case 0x6818: 1905 si_pi->cac_weights = cac_weights_pitcairn; 1906 si_pi->lcac_config = lcac_pitcairn; 1907 si_pi->cac_override = cac_override_pitcairn; 1908 si_pi->powertune_data = &powertune_data_pitcairn; 1909 si_pi->dte_data = dte_data_curacao_xt; 1910 update_dte_from_pl2 = true; 1911 break; 1912 case 0x6819: 1913 case 0x6811: 1914 si_pi->cac_weights = cac_weights_pitcairn; 1915 si_pi->lcac_config = lcac_pitcairn; 1916 si_pi->cac_override = cac_override_pitcairn; 1917 si_pi->powertune_data = &powertune_data_pitcairn; 1918 si_pi->dte_data = dte_data_curacao_pro; 1919 update_dte_from_pl2 = true; 1920 break; 1921 case 0x6800: 1922 case 0x6806: 1923 si_pi->cac_weights = cac_weights_pitcairn; 1924 si_pi->lcac_config = lcac_pitcairn; 1925 si_pi->cac_override = cac_override_pitcairn; 1926 si_pi->powertune_data = &powertune_data_pitcairn; 1927 si_pi->dte_data = dte_data_neptune_xt; 1928 update_dte_from_pl2 = true; 1929 break; 1930 default: 1931 si_pi->cac_weights = cac_weights_pitcairn; 1932 si_pi->lcac_config = lcac_pitcairn; 1933 si_pi->cac_override = cac_override_pitcairn; 1934 si_pi->powertune_data = &powertune_data_pitcairn; 1935 si_pi->dte_data = dte_data_pitcairn; 1936 break; 1937 } 1938 } else if (rdev->family == CHIP_VERDE) { 1939 si_pi->lcac_config = lcac_cape_verde; 1940 si_pi->cac_override = cac_override_cape_verde; 1941 si_pi->powertune_data = &powertune_data_cape_verde; 1942 1943 switch (rdev->pdev->device) { 1944 case 0x683B: 1945 case 0x683F: 1946 case 0x6829: 1947 case 0x6835: 1948 si_pi->cac_weights = cac_weights_cape_verde_pro; 1949 si_pi->dte_data = dte_data_cape_verde; 1950 break; 1951 case 0x682C: 1952 si_pi->cac_weights = cac_weights_cape_verde_pro; 1953 si_pi->dte_data = dte_data_sun_xt; 1954 break; 1955 case 0x6825: 1956 case 0x6827: 1957 si_pi->cac_weights = cac_weights_heathrow; 1958 si_pi->dte_data = dte_data_cape_verde; 1959 break; 1960 case 0x6824: 1961 case 0x682D: 1962 si_pi->cac_weights = cac_weights_chelsea_xt; 1963 si_pi->dte_data = dte_data_cape_verde; 1964 break; 1965 case 0x682F: 1966 si_pi->cac_weights = cac_weights_chelsea_pro; 1967 si_pi->dte_data = dte_data_cape_verde; 1968 break; 1969 case 0x6820: 1970 si_pi->cac_weights = cac_weights_heathrow; 1971 si_pi->dte_data = dte_data_venus_xtx; 1972 break; 1973 case 0x6821: 1974 si_pi->cac_weights = cac_weights_heathrow; 1975 si_pi->dte_data = dte_data_venus_xt; 1976 break; 1977 case 0x6823: 1978 case 0x682B: 1979 case 0x6822: 1980 case 0x682A: 1981 si_pi->cac_weights = cac_weights_chelsea_pro; 1982 si_pi->dte_data = dte_data_venus_pro; 1983 break; 1984 default: 1985 si_pi->cac_weights = cac_weights_cape_verde; 1986 si_pi->dte_data = dte_data_cape_verde; 1987 break; 1988 } 1989 } else if (rdev->family == CHIP_OLAND) { 1990 switch (rdev->pdev->device) { 1991 case 0x6601: 1992 case 0x6621: 1993 case 0x6603: 1994 case 0x6605: 1995 si_pi->cac_weights = cac_weights_mars_pro; 1996 si_pi->lcac_config = lcac_mars_pro; 1997 si_pi->cac_override = cac_override_oland; 1998 si_pi->powertune_data = &powertune_data_mars_pro; 1999 si_pi->dte_data = dte_data_mars_pro; 2000 update_dte_from_pl2 = true; 2001 break; 2002 case 0x6600: 2003 case 0x6606: 2004 case 0x6620: 2005 case 0x6604: 2006 si_pi->cac_weights = cac_weights_mars_xt; 2007 si_pi->lcac_config = lcac_mars_pro; 2008 si_pi->cac_override = cac_override_oland; 2009 si_pi->powertune_data = &powertune_data_mars_pro; 2010 si_pi->dte_data = dte_data_mars_pro; 2011 update_dte_from_pl2 = true; 2012 break; 2013 case 0x6611: 2014 case 0x6613: 2015 case 0x6608: 2016 si_pi->cac_weights = cac_weights_oland_pro; 2017 si_pi->lcac_config = lcac_mars_pro; 2018 si_pi->cac_override = cac_override_oland; 2019 si_pi->powertune_data = &powertune_data_mars_pro; 2020 si_pi->dte_data = dte_data_mars_pro; 2021 update_dte_from_pl2 = true; 2022 break; 2023 case 0x6610: 2024 si_pi->cac_weights = cac_weights_oland_xt; 2025 si_pi->lcac_config = lcac_mars_pro; 2026 si_pi->cac_override = cac_override_oland; 2027 si_pi->powertune_data = &powertune_data_mars_pro; 2028 si_pi->dte_data = dte_data_mars_pro; 2029 update_dte_from_pl2 = true; 2030 break; 2031 default: 2032 si_pi->cac_weights = cac_weights_oland; 2033 si_pi->lcac_config = lcac_oland; 2034 si_pi->cac_override = cac_override_oland; 2035 si_pi->powertune_data = &powertune_data_oland; 2036 si_pi->dte_data = dte_data_oland; 2037 break; 2038 } 2039 } else if (rdev->family == CHIP_HAINAN) { 2040 si_pi->cac_weights = cac_weights_hainan; 2041 si_pi->lcac_config = lcac_oland; 2042 si_pi->cac_override = cac_override_oland; 2043 si_pi->powertune_data = &powertune_data_hainan; 2044 si_pi->dte_data = dte_data_sun_xt; 2045 update_dte_from_pl2 = true; 2046 } else { 2047 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2048 return; 2049 } 2050 2051 ni_pi->enable_power_containment = false; 2052 ni_pi->enable_cac = false; 2053 ni_pi->enable_sq_ramping = false; 2054 si_pi->enable_dte = false; 2055 2056 if (si_pi->powertune_data->enable_powertune_by_default) { 2057 ni_pi->enable_power_containment= true; 2058 ni_pi->enable_cac = true; 2059 if (si_pi->dte_data.enable_dte_by_default) { 2060 si_pi->enable_dte = true; 2061 if (update_dte_from_pl2) 2062 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2063 2064 } 2065 ni_pi->enable_sq_ramping = true; 2066 } 2067 2068 ni_pi->driver_calculate_cac_leakage = true; 2069 ni_pi->cac_configuration_required = true; 2070 2071 if (ni_pi->cac_configuration_required) { 2072 ni_pi->support_cac_long_term_average = true; 2073 si_pi->dyn_powertune_data.l2_lta_window_size = 2074 si_pi->powertune_data->l2_lta_window_size_default; 2075 si_pi->dyn_powertune_data.lts_truncate = 2076 si_pi->powertune_data->lts_truncate_default; 2077 } else { 2078 ni_pi->support_cac_long_term_average = false; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2080 si_pi->dyn_powertune_data.lts_truncate = 0; 2081 } 2082 2083 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2084 } 2085 2086 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2087 { 2088 return 1; 2089 } 2090 2091 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2092 { 2093 u32 xclk; 2094 u32 wintime; 2095 u32 cac_window; 2096 u32 cac_window_size; 2097 2098 xclk = radeon_get_xclk(rdev); 2099 2100 if (xclk == 0) 2101 return 0; 2102 2103 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2104 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2105 2106 wintime = (cac_window_size * 100) / xclk; 2107 2108 return wintime; 2109 } 2110 2111 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2112 { 2113 return power_in_watts; 2114 } 2115 2116 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2117 bool adjust_polarity, 2118 u32 tdp_adjustment, 2119 u32 *tdp_limit, 2120 u32 *near_tdp_limit) 2121 { 2122 u32 adjustment_delta, max_tdp_limit; 2123 2124 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2125 return -EINVAL; 2126 2127 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2128 2129 if (adjust_polarity) { 2130 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2131 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2132 } else { 2133 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2134 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2135 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2137 else 2138 *near_tdp_limit = 0; 2139 } 2140 2141 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2142 return -EINVAL; 2143 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2144 return -EINVAL; 2145 2146 return 0; 2147 } 2148 2149 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2150 struct radeon_ps *radeon_state) 2151 { 2152 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2153 struct si_power_info *si_pi = si_get_pi(rdev); 2154 2155 if (ni_pi->enable_power_containment) { 2156 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2157 PP_SIslands_PAPMParameters *papm_parm; 2158 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2159 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2160 u32 tdp_limit; 2161 u32 near_tdp_limit; 2162 int ret; 2163 2164 if (scaling_factor == 0) 2165 return -EINVAL; 2166 2167 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2168 2169 ret = si_calculate_adjusted_tdp_limits(rdev, 2170 false, /* ??? */ 2171 rdev->pm.dpm.tdp_adjustment, 2172 &tdp_limit, 2173 &near_tdp_limit); 2174 if (ret) 2175 return ret; 2176 2177 smc_table->dpm2Params.TDPLimit = 2178 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2179 smc_table->dpm2Params.NearTDPLimit = 2180 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2181 smc_table->dpm2Params.SafePowerLimit = 2182 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2183 2184 ret = si_copy_bytes_to_smc(rdev, 2185 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2186 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2187 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2188 sizeof(u32) * 3, 2189 si_pi->sram_end); 2190 if (ret) 2191 return ret; 2192 2193 if (si_pi->enable_ppm) { 2194 papm_parm = &si_pi->papm_parm; 2195 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2196 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2197 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2198 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2199 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2200 papm_parm->PlatformPowerLimit = 0xffffffff; 2201 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2202 2203 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2204 (u8 *)papm_parm, 2205 sizeof(PP_SIslands_PAPMParameters), 2206 si_pi->sram_end); 2207 if (ret) 2208 return ret; 2209 } 2210 } 2211 return 0; 2212 } 2213 2214 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2215 struct radeon_ps *radeon_state) 2216 { 2217 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2218 struct si_power_info *si_pi = si_get_pi(rdev); 2219 2220 if (ni_pi->enable_power_containment) { 2221 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2222 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2223 int ret; 2224 2225 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2226 2227 smc_table->dpm2Params.NearTDPLimit = 2228 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2229 smc_table->dpm2Params.SafePowerLimit = 2230 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2231 2232 ret = si_copy_bytes_to_smc(rdev, 2233 (si_pi->state_table_start + 2234 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2235 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2236 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2237 sizeof(u32) * 2, 2238 si_pi->sram_end); 2239 if (ret) 2240 return ret; 2241 } 2242 2243 return 0; 2244 } 2245 2246 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2247 const u16 prev_std_vddc, 2248 const u16 curr_std_vddc) 2249 { 2250 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2251 u64 prev_vddc = (u64)prev_std_vddc; 2252 u64 curr_vddc = (u64)curr_std_vddc; 2253 u64 pwr_efficiency_ratio, n, d; 2254 2255 if ((prev_vddc == 0) || (curr_vddc == 0)) 2256 return 0; 2257 2258 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2259 d = prev_vddc * prev_vddc; 2260 pwr_efficiency_ratio = div64_u64(n, d); 2261 2262 if (pwr_efficiency_ratio > (u64)0xFFFF) 2263 return 0; 2264 2265 return (u16)pwr_efficiency_ratio; 2266 } 2267 2268 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2269 struct radeon_ps *radeon_state) 2270 { 2271 struct si_power_info *si_pi = si_get_pi(rdev); 2272 2273 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2274 radeon_state->vclk && radeon_state->dclk) 2275 return true; 2276 2277 return false; 2278 } 2279 2280 static int si_populate_power_containment_values(struct radeon_device *rdev, 2281 struct radeon_ps *radeon_state, 2282 SISLANDS_SMC_SWSTATE *smc_state) 2283 { 2284 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2285 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2286 struct ni_ps *state = ni_get_ps(radeon_state); 2287 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2288 u32 prev_sclk; 2289 u32 max_sclk; 2290 u32 min_sclk; 2291 u16 prev_std_vddc; 2292 u16 curr_std_vddc; 2293 int i; 2294 u16 pwr_efficiency_ratio; 2295 u8 max_ps_percent; 2296 bool disable_uvd_power_tune; 2297 int ret; 2298 2299 if (ni_pi->enable_power_containment == false) 2300 return 0; 2301 2302 if (state->performance_level_count == 0) 2303 return -EINVAL; 2304 2305 if (smc_state->levelCount != state->performance_level_count) 2306 return -EINVAL; 2307 2308 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2309 2310 smc_state->levels[0].dpm2.MaxPS = 0; 2311 smc_state->levels[0].dpm2.NearTDPDec = 0; 2312 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2313 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2314 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2315 2316 for (i = 1; i < state->performance_level_count; i++) { 2317 prev_sclk = state->performance_levels[i-1].sclk; 2318 max_sclk = state->performance_levels[i].sclk; 2319 if (i == 1) 2320 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2321 else 2322 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2323 2324 if (prev_sclk > max_sclk) 2325 return -EINVAL; 2326 2327 if ((max_ps_percent == 0) || 2328 (prev_sclk == max_sclk) || 2329 disable_uvd_power_tune) { 2330 min_sclk = max_sclk; 2331 } else if (i == 1) { 2332 min_sclk = prev_sclk; 2333 } else { 2334 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2335 } 2336 2337 if (min_sclk < state->performance_levels[0].sclk) 2338 min_sclk = state->performance_levels[0].sclk; 2339 2340 if (min_sclk == 0) 2341 return -EINVAL; 2342 2343 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2344 state->performance_levels[i-1].vddc, &vddc); 2345 if (ret) 2346 return ret; 2347 2348 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2349 if (ret) 2350 return ret; 2351 2352 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2353 state->performance_levels[i].vddc, &vddc); 2354 if (ret) 2355 return ret; 2356 2357 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2358 if (ret) 2359 return ret; 2360 2361 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2362 prev_std_vddc, curr_std_vddc); 2363 2364 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2365 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2366 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2367 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2368 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2369 } 2370 2371 return 0; 2372 } 2373 2374 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2375 struct radeon_ps *radeon_state, 2376 SISLANDS_SMC_SWSTATE *smc_state) 2377 { 2378 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2379 struct ni_ps *state = ni_get_ps(radeon_state); 2380 u32 sq_power_throttle, sq_power_throttle2; 2381 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2382 int i; 2383 2384 if (state->performance_level_count == 0) 2385 return -EINVAL; 2386 2387 if (smc_state->levelCount != state->performance_level_count) 2388 return -EINVAL; 2389 2390 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2391 return -EINVAL; 2392 2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2394 enable_sq_ramping = false; 2395 2396 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2397 enable_sq_ramping = false; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 for (i = 0; i < state->performance_level_count; i++) { 2409 sq_power_throttle = 0; 2410 sq_power_throttle2 = 0; 2411 2412 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2413 enable_sq_ramping) { 2414 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2415 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2416 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2417 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2418 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2419 } else { 2420 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2421 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2422 } 2423 2424 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2425 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2426 } 2427 2428 return 0; 2429 } 2430 2431 static int si_enable_power_containment(struct radeon_device *rdev, 2432 struct radeon_ps *radeon_new_state, 2433 bool enable) 2434 { 2435 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2436 PPSMC_Result smc_result; 2437 int ret = 0; 2438 2439 if (ni_pi->enable_power_containment) { 2440 if (enable) { 2441 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2442 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2443 if (smc_result != PPSMC_Result_OK) { 2444 ret = -EINVAL; 2445 ni_pi->pc_enabled = false; 2446 } else { 2447 ni_pi->pc_enabled = true; 2448 } 2449 } 2450 } else { 2451 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2452 if (smc_result != PPSMC_Result_OK) 2453 ret = -EINVAL; 2454 ni_pi->pc_enabled = false; 2455 } 2456 } 2457 2458 return ret; 2459 } 2460 2461 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2462 { 2463 struct si_power_info *si_pi = si_get_pi(rdev); 2464 int ret = 0; 2465 struct si_dte_data *dte_data = &si_pi->dte_data; 2466 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2467 u32 table_size; 2468 u8 tdep_count; 2469 u32 i; 2470 2471 if (dte_data == NULL) 2472 si_pi->enable_dte = false; 2473 2474 if (si_pi->enable_dte == false) 2475 return 0; 2476 2477 if (dte_data->k <= 0) 2478 return -EINVAL; 2479 2480 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2481 if (dte_tables == NULL) { 2482 si_pi->enable_dte = false; 2483 return -ENOMEM; 2484 } 2485 2486 table_size = dte_data->k; 2487 2488 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2489 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2490 2491 tdep_count = dte_data->tdep_count; 2492 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2493 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2494 2495 dte_tables->K = cpu_to_be32(table_size); 2496 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2497 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2498 dte_tables->WindowSize = dte_data->window_size; 2499 dte_tables->temp_select = dte_data->temp_select; 2500 dte_tables->DTE_mode = dte_data->dte_mode; 2501 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2502 2503 if (tdep_count > 0) 2504 table_size--; 2505 2506 for (i = 0; i < table_size; i++) { 2507 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2508 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2509 } 2510 2511 dte_tables->Tdep_count = tdep_count; 2512 2513 for (i = 0; i < (u32)tdep_count; i++) { 2514 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2515 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2516 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2517 } 2518 2519 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2520 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2521 kfree(dte_tables); 2522 2523 return ret; 2524 } 2525 2526 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2527 u16 *max, u16 *min) 2528 { 2529 struct si_power_info *si_pi = si_get_pi(rdev); 2530 struct radeon_cac_leakage_table *table = 2531 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2532 u32 i; 2533 u32 v0_loadline; 2534 2535 2536 if (table == NULL) 2537 return -EINVAL; 2538 2539 *max = 0; 2540 *min = 0xFFFF; 2541 2542 for (i = 0; i < table->count; i++) { 2543 if (table->entries[i].vddc > *max) 2544 *max = table->entries[i].vddc; 2545 if (table->entries[i].vddc < *min) 2546 *min = table->entries[i].vddc; 2547 } 2548 2549 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2550 return -EINVAL; 2551 2552 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2553 2554 if (v0_loadline > 0xFFFFUL) 2555 return -EINVAL; 2556 2557 *min = (u16)v0_loadline; 2558 2559 if ((*min > *max) || (*max == 0) || (*min == 0)) 2560 return -EINVAL; 2561 2562 return 0; 2563 } 2564 2565 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2566 { 2567 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2568 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2569 } 2570 2571 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2572 PP_SIslands_CacConfig *cac_tables, 2573 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2574 u16 t0, u16 t_step) 2575 { 2576 struct si_power_info *si_pi = si_get_pi(rdev); 2577 u32 leakage; 2578 unsigned int i, j; 2579 s32 t; 2580 u32 smc_leakage; 2581 u32 scaling_factor; 2582 u16 voltage; 2583 2584 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2585 2586 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2587 t = (1000 * (i * t_step + t0)); 2588 2589 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2590 voltage = vddc_max - (vddc_step * j); 2591 2592 si_calculate_leakage_for_v_and_t(rdev, 2593 &si_pi->powertune_data->leakage_coefficients, 2594 voltage, 2595 t, 2596 si_pi->dyn_powertune_data.cac_leakage, 2597 &leakage); 2598 2599 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2600 2601 if (smc_leakage > 0xFFFF) 2602 smc_leakage = 0xFFFF; 2603 2604 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2605 cpu_to_be16((u16)smc_leakage); 2606 } 2607 } 2608 return 0; 2609 } 2610 2611 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2612 PP_SIslands_CacConfig *cac_tables, 2613 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2614 { 2615 struct si_power_info *si_pi = si_get_pi(rdev); 2616 u32 leakage; 2617 unsigned int i, j; 2618 u32 smc_leakage; 2619 u32 scaling_factor; 2620 u16 voltage; 2621 2622 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2623 2624 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2625 voltage = vddc_max - (vddc_step * j); 2626 2627 si_calculate_leakage_for_v(rdev, 2628 &si_pi->powertune_data->leakage_coefficients, 2629 si_pi->powertune_data->fixed_kt, 2630 voltage, 2631 si_pi->dyn_powertune_data.cac_leakage, 2632 &leakage); 2633 2634 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2635 2636 if (smc_leakage > 0xFFFF) 2637 smc_leakage = 0xFFFF; 2638 2639 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2640 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2641 cpu_to_be16((u16)smc_leakage); 2642 } 2643 return 0; 2644 } 2645 2646 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2647 { 2648 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2649 struct si_power_info *si_pi = si_get_pi(rdev); 2650 PP_SIslands_CacConfig *cac_tables = NULL; 2651 u16 vddc_max, vddc_min, vddc_step; 2652 u16 t0, t_step; 2653 u32 load_line_slope, reg; 2654 int ret = 0; 2655 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2656 2657 if (ni_pi->enable_cac == false) 2658 return 0; 2659 2660 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2661 if (!cac_tables) 2662 return -ENOMEM; 2663 2664 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2665 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2666 WREG32(CG_CAC_CTRL, reg); 2667 2668 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2669 si_pi->dyn_powertune_data.dc_pwr_value = 2670 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2671 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2672 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2673 2674 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2675 2676 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2677 if (ret) 2678 goto done_free; 2679 2680 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2681 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2682 t_step = 4; 2683 t0 = 60; 2684 2685 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2686 ret = si_init_dte_leakage_table(rdev, cac_tables, 2687 vddc_max, vddc_min, vddc_step, 2688 t0, t_step); 2689 else 2690 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2691 vddc_max, vddc_min, vddc_step); 2692 if (ret) 2693 goto done_free; 2694 2695 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2696 2697 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2698 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2699 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2700 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2701 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2702 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2703 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2704 cac_tables->calculation_repeats = cpu_to_be32(2); 2705 cac_tables->dc_cac = cpu_to_be32(0); 2706 cac_tables->log2_PG_LKG_SCALE = 12; 2707 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2708 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2709 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2710 2711 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2712 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2713 2714 if (ret) 2715 goto done_free; 2716 2717 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2718 2719 done_free: 2720 if (ret) { 2721 ni_pi->enable_cac = false; 2722 ni_pi->enable_power_containment = false; 2723 } 2724 2725 kfree(cac_tables); 2726 2727 return 0; 2728 } 2729 2730 static int si_program_cac_config_registers(struct radeon_device *rdev, 2731 const struct si_cac_config_reg *cac_config_regs) 2732 { 2733 const struct si_cac_config_reg *config_regs = cac_config_regs; 2734 u32 data = 0, offset; 2735 2736 if (!config_regs) 2737 return -EINVAL; 2738 2739 while (config_regs->offset != 0xFFFFFFFF) { 2740 switch (config_regs->type) { 2741 case SISLANDS_CACCONFIG_CGIND: 2742 offset = SMC_CG_IND_START + config_regs->offset; 2743 if (offset < SMC_CG_IND_END) 2744 data = RREG32_SMC(offset); 2745 break; 2746 default: 2747 data = RREG32(config_regs->offset << 2); 2748 break; 2749 } 2750 2751 data &= ~config_regs->mask; 2752 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2753 2754 switch (config_regs->type) { 2755 case SISLANDS_CACCONFIG_CGIND: 2756 offset = SMC_CG_IND_START + config_regs->offset; 2757 if (offset < SMC_CG_IND_END) 2758 WREG32_SMC(offset, data); 2759 break; 2760 default: 2761 WREG32(config_regs->offset << 2, data); 2762 break; 2763 } 2764 config_regs++; 2765 } 2766 return 0; 2767 } 2768 2769 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2770 { 2771 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2772 struct si_power_info *si_pi = si_get_pi(rdev); 2773 int ret; 2774 2775 if ((ni_pi->enable_cac == false) || 2776 (ni_pi->cac_configuration_required == false)) 2777 return 0; 2778 2779 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2780 if (ret) 2781 return ret; 2782 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2783 if (ret) 2784 return ret; 2785 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2786 if (ret) 2787 return ret; 2788 2789 return 0; 2790 } 2791 2792 static int si_enable_smc_cac(struct radeon_device *rdev, 2793 struct radeon_ps *radeon_new_state, 2794 bool enable) 2795 { 2796 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2797 struct si_power_info *si_pi = si_get_pi(rdev); 2798 PPSMC_Result smc_result; 2799 int ret = 0; 2800 2801 if (ni_pi->enable_cac) { 2802 if (enable) { 2803 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2804 if (ni_pi->support_cac_long_term_average) { 2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2806 if (smc_result != PPSMC_Result_OK) 2807 ni_pi->support_cac_long_term_average = false; 2808 } 2809 2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2811 if (smc_result != PPSMC_Result_OK) { 2812 ret = -EINVAL; 2813 ni_pi->cac_enabled = false; 2814 } else { 2815 ni_pi->cac_enabled = true; 2816 } 2817 2818 if (si_pi->enable_dte) { 2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2820 if (smc_result != PPSMC_Result_OK) 2821 ret = -EINVAL; 2822 } 2823 } 2824 } else if (ni_pi->cac_enabled) { 2825 if (si_pi->enable_dte) 2826 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2827 2828 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2829 2830 ni_pi->cac_enabled = false; 2831 2832 if (ni_pi->support_cac_long_term_average) 2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2834 } 2835 } 2836 return ret; 2837 } 2838 2839 static int si_init_smc_spll_table(struct radeon_device *rdev) 2840 { 2841 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2842 struct si_power_info *si_pi = si_get_pi(rdev); 2843 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2844 SISLANDS_SMC_SCLK_VALUE sclk_params; 2845 u32 fb_div, p_div; 2846 u32 clk_s, clk_v; 2847 u32 sclk = 0; 2848 int ret = 0; 2849 u32 tmp; 2850 int i; 2851 2852 if (si_pi->spll_table_start == 0) 2853 return -EINVAL; 2854 2855 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2856 if (spll_table == NULL) 2857 return -ENOMEM; 2858 2859 for (i = 0; i < 256; i++) { 2860 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2861 if (ret) 2862 break; 2863 2864 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2865 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2866 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2867 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2868 2869 fb_div &= ~0x00001FFF; 2870 fb_div >>= 1; 2871 clk_v >>= 6; 2872 2873 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2874 ret = -EINVAL; 2875 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2876 ret = -EINVAL; 2877 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2878 ret = -EINVAL; 2879 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2880 ret = -EINVAL; 2881 2882 if (ret) 2883 break; 2884 2885 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2886 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2887 spll_table->freq[i] = cpu_to_be32(tmp); 2888 2889 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2890 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2891 spll_table->ss[i] = cpu_to_be32(tmp); 2892 2893 sclk += 512; 2894 } 2895 2896 2897 if (!ret) 2898 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2899 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2900 si_pi->sram_end); 2901 2902 if (ret) 2903 ni_pi->enable_power_containment = false; 2904 2905 kfree(spll_table); 2906 2907 return ret; 2908 } 2909 2910 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2911 struct radeon_ps *rps) 2912 { 2913 struct ni_ps *ps = ni_get_ps(rps); 2914 struct radeon_clock_and_voltage_limits *max_limits; 2915 bool disable_mclk_switching = false; 2916 bool disable_sclk_switching = false; 2917 u32 mclk, sclk; 2918 u16 vddc, vddci; 2919 int i; 2920 2921 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2922 ni_dpm_vblank_too_short(rdev)) 2923 disable_mclk_switching = true; 2924 2925 if (rps->vclk || rps->dclk) { 2926 disable_mclk_switching = true; 2927 disable_sclk_switching = true; 2928 } 2929 2930 if (rdev->pm.dpm.ac_power) 2931 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2932 else 2933 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2934 2935 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2936 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2937 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2938 } 2939 if (rdev->pm.dpm.ac_power == false) { 2940 for (i = 0; i < ps->performance_level_count; i++) { 2941 if (ps->performance_levels[i].mclk > max_limits->mclk) 2942 ps->performance_levels[i].mclk = max_limits->mclk; 2943 if (ps->performance_levels[i].sclk > max_limits->sclk) 2944 ps->performance_levels[i].sclk = max_limits->sclk; 2945 if (ps->performance_levels[i].vddc > max_limits->vddc) 2946 ps->performance_levels[i].vddc = max_limits->vddc; 2947 if (ps->performance_levels[i].vddci > max_limits->vddci) 2948 ps->performance_levels[i].vddci = max_limits->vddci; 2949 } 2950 } 2951 2952 /* XXX validate the min clocks required for display */ 2953 2954 if (disable_mclk_switching) { 2955 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2956 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2957 } else { 2958 mclk = ps->performance_levels[0].mclk; 2959 vddci = ps->performance_levels[0].vddci; 2960 } 2961 2962 if (disable_sclk_switching) { 2963 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2964 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2965 } else { 2966 sclk = ps->performance_levels[0].sclk; 2967 vddc = ps->performance_levels[0].vddc; 2968 } 2969 2970 /* adjusted low state */ 2971 ps->performance_levels[0].sclk = sclk; 2972 ps->performance_levels[0].mclk = mclk; 2973 ps->performance_levels[0].vddc = vddc; 2974 ps->performance_levels[0].vddci = vddci; 2975 2976 if (disable_sclk_switching) { 2977 sclk = ps->performance_levels[0].sclk; 2978 for (i = 1; i < ps->performance_level_count; i++) { 2979 if (sclk < ps->performance_levels[i].sclk) 2980 sclk = ps->performance_levels[i].sclk; 2981 } 2982 for (i = 0; i < ps->performance_level_count; i++) { 2983 ps->performance_levels[i].sclk = sclk; 2984 ps->performance_levels[i].vddc = vddc; 2985 } 2986 } else { 2987 for (i = 1; i < ps->performance_level_count; i++) { 2988 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2989 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2990 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2991 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2992 } 2993 } 2994 2995 if (disable_mclk_switching) { 2996 mclk = ps->performance_levels[0].mclk; 2997 for (i = 1; i < ps->performance_level_count; i++) { 2998 if (mclk < ps->performance_levels[i].mclk) 2999 mclk = ps->performance_levels[i].mclk; 3000 } 3001 for (i = 0; i < ps->performance_level_count; i++) { 3002 ps->performance_levels[i].mclk = mclk; 3003 ps->performance_levels[i].vddci = vddci; 3004 } 3005 } else { 3006 for (i = 1; i < ps->performance_level_count; i++) { 3007 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3008 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3009 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3010 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3011 } 3012 } 3013 3014 for (i = 0; i < ps->performance_level_count; i++) 3015 btc_adjust_clock_combinations(rdev, max_limits, 3016 &ps->performance_levels[i]); 3017 3018 for (i = 0; i < ps->performance_level_count; i++) { 3019 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3020 ps->performance_levels[i].sclk, 3021 max_limits->vddc, &ps->performance_levels[i].vddc); 3022 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3023 ps->performance_levels[i].mclk, 3024 max_limits->vddci, &ps->performance_levels[i].vddci); 3025 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3026 ps->performance_levels[i].mclk, 3027 max_limits->vddc, &ps->performance_levels[i].vddc); 3028 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3029 rdev->clock.current_dispclk, 3030 max_limits->vddc, &ps->performance_levels[i].vddc); 3031 } 3032 3033 for (i = 0; i < ps->performance_level_count; i++) { 3034 btc_apply_voltage_delta_rules(rdev, 3035 max_limits->vddc, max_limits->vddci, 3036 &ps->performance_levels[i].vddc, 3037 &ps->performance_levels[i].vddci); 3038 } 3039 3040 ps->dc_compatible = true; 3041 for (i = 0; i < ps->performance_level_count; i++) { 3042 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3043 ps->dc_compatible = false; 3044 } 3045 3046 } 3047 3048 #if 0 3049 static int si_read_smc_soft_register(struct radeon_device *rdev, 3050 u16 reg_offset, u32 *value) 3051 { 3052 struct si_power_info *si_pi = si_get_pi(rdev); 3053 3054 return si_read_smc_sram_dword(rdev, 3055 si_pi->soft_regs_start + reg_offset, value, 3056 si_pi->sram_end); 3057 } 3058 #endif 3059 3060 static int si_write_smc_soft_register(struct radeon_device *rdev, 3061 u16 reg_offset, u32 value) 3062 { 3063 struct si_power_info *si_pi = si_get_pi(rdev); 3064 3065 return si_write_smc_sram_dword(rdev, 3066 si_pi->soft_regs_start + reg_offset, 3067 value, si_pi->sram_end); 3068 } 3069 3070 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3071 { 3072 bool ret = false; 3073 u32 tmp, width, row, column, bank, density; 3074 bool is_memory_gddr5, is_special; 3075 3076 tmp = RREG32(MC_SEQ_MISC0); 3077 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3078 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3079 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3080 3081 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3082 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3083 3084 tmp = RREG32(MC_ARB_RAMCFG); 3085 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3086 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3087 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3088 3089 density = (1 << (row + column - 20 + bank)) * width; 3090 3091 if ((rdev->pdev->device == 0x6819) && 3092 is_memory_gddr5 && is_special && (density == 0x400)) 3093 ret = true; 3094 3095 return ret; 3096 } 3097 3098 static void si_get_leakage_vddc(struct radeon_device *rdev) 3099 { 3100 struct si_power_info *si_pi = si_get_pi(rdev); 3101 u16 vddc, count = 0; 3102 int i, ret; 3103 3104 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3105 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3106 3107 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3108 si_pi->leakage_voltage.entries[count].voltage = vddc; 3109 si_pi->leakage_voltage.entries[count].leakage_index = 3110 SISLANDS_LEAKAGE_INDEX0 + i; 3111 count++; 3112 } 3113 } 3114 si_pi->leakage_voltage.count = count; 3115 } 3116 3117 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3118 u32 index, u16 *leakage_voltage) 3119 { 3120 struct si_power_info *si_pi = si_get_pi(rdev); 3121 int i; 3122 3123 if (leakage_voltage == NULL) 3124 return -EINVAL; 3125 3126 if ((index & 0xff00) != 0xff00) 3127 return -EINVAL; 3128 3129 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3130 return -EINVAL; 3131 3132 if (index < SISLANDS_LEAKAGE_INDEX0) 3133 return -EINVAL; 3134 3135 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3136 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3137 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3138 return 0; 3139 } 3140 } 3141 return -EAGAIN; 3142 } 3143 3144 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3145 { 3146 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3147 bool want_thermal_protection; 3148 enum radeon_dpm_event_src dpm_event_src; 3149 3150 switch (sources) { 3151 case 0: 3152 default: 3153 want_thermal_protection = false; 3154 break; 3155 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3156 want_thermal_protection = true; 3157 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3158 break; 3159 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3160 want_thermal_protection = true; 3161 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3162 break; 3163 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3164 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3165 want_thermal_protection = true; 3166 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3167 break; 3168 } 3169 3170 if (want_thermal_protection) { 3171 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3172 if (pi->thermal_protection) 3173 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3174 } else { 3175 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3176 } 3177 } 3178 3179 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3180 enum radeon_dpm_auto_throttle_src source, 3181 bool enable) 3182 { 3183 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3184 3185 if (enable) { 3186 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3187 pi->active_auto_throttle_sources |= 1 << source; 3188 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3189 } 3190 } else { 3191 if (pi->active_auto_throttle_sources & (1 << source)) { 3192 pi->active_auto_throttle_sources &= ~(1 << source); 3193 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3194 } 3195 } 3196 } 3197 3198 static void si_start_dpm(struct radeon_device *rdev) 3199 { 3200 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3201 } 3202 3203 static void si_stop_dpm(struct radeon_device *rdev) 3204 { 3205 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3206 } 3207 3208 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3209 { 3210 if (enable) 3211 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3212 else 3213 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3214 3215 } 3216 3217 #if 0 3218 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3219 u32 thermal_level) 3220 { 3221 PPSMC_Result ret; 3222 3223 if (thermal_level == 0) { 3224 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3225 if (ret == PPSMC_Result_OK) 3226 return 0; 3227 else 3228 return -EINVAL; 3229 } 3230 return 0; 3231 } 3232 3233 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3234 { 3235 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3236 } 3237 #endif 3238 3239 #if 0 3240 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3241 { 3242 if (ac_power) 3243 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3244 0 : -EINVAL; 3245 3246 return 0; 3247 } 3248 #endif 3249 3250 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3251 PPSMC_Msg msg, u32 parameter) 3252 { 3253 WREG32(SMC_SCRATCH0, parameter); 3254 return si_send_msg_to_smc(rdev, msg); 3255 } 3256 3257 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3258 { 3259 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3260 return -EINVAL; 3261 3262 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3263 0 : -EINVAL; 3264 } 3265 3266 int si_dpm_force_performance_level(struct radeon_device *rdev, 3267 enum radeon_dpm_forced_level level) 3268 { 3269 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3270 struct ni_ps *ps = ni_get_ps(rps); 3271 u32 levels = ps->performance_level_count; 3272 3273 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3274 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3275 return -EINVAL; 3276 3277 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3278 return -EINVAL; 3279 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3280 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3281 return -EINVAL; 3282 3283 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3284 return -EINVAL; 3285 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3286 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3287 return -EINVAL; 3288 3289 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3290 return -EINVAL; 3291 } 3292 3293 rdev->pm.dpm.forced_level = level; 3294 3295 return 0; 3296 } 3297 3298 static int si_set_boot_state(struct radeon_device *rdev) 3299 { 3300 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3301 0 : -EINVAL; 3302 } 3303 3304 static int si_set_sw_state(struct radeon_device *rdev) 3305 { 3306 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3307 0 : -EINVAL; 3308 } 3309 3310 static int si_halt_smc(struct radeon_device *rdev) 3311 { 3312 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3313 return -EINVAL; 3314 3315 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3316 0 : -EINVAL; 3317 } 3318 3319 static int si_resume_smc(struct radeon_device *rdev) 3320 { 3321 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3322 return -EINVAL; 3323 3324 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3325 0 : -EINVAL; 3326 } 3327 3328 static void si_dpm_start_smc(struct radeon_device *rdev) 3329 { 3330 si_program_jump_on_start(rdev); 3331 si_start_smc(rdev); 3332 si_start_smc_clock(rdev); 3333 } 3334 3335 static void si_dpm_stop_smc(struct radeon_device *rdev) 3336 { 3337 si_reset_smc(rdev); 3338 si_stop_smc_clock(rdev); 3339 } 3340 3341 static int si_process_firmware_header(struct radeon_device *rdev) 3342 { 3343 struct si_power_info *si_pi = si_get_pi(rdev); 3344 u32 tmp; 3345 int ret; 3346 3347 ret = si_read_smc_sram_dword(rdev, 3348 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3349 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3350 &tmp, si_pi->sram_end); 3351 if (ret) 3352 return ret; 3353 3354 si_pi->state_table_start = tmp; 3355 3356 ret = si_read_smc_sram_dword(rdev, 3357 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3358 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3359 &tmp, si_pi->sram_end); 3360 if (ret) 3361 return ret; 3362 3363 si_pi->soft_regs_start = tmp; 3364 3365 ret = si_read_smc_sram_dword(rdev, 3366 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3367 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3368 &tmp, si_pi->sram_end); 3369 if (ret) 3370 return ret; 3371 3372 si_pi->mc_reg_table_start = tmp; 3373 3374 ret = si_read_smc_sram_dword(rdev, 3375 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3376 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3377 &tmp, si_pi->sram_end); 3378 if (ret) 3379 return ret; 3380 3381 si_pi->arb_table_start = tmp; 3382 3383 ret = si_read_smc_sram_dword(rdev, 3384 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3385 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3386 &tmp, si_pi->sram_end); 3387 if (ret) 3388 return ret; 3389 3390 si_pi->cac_table_start = tmp; 3391 3392 ret = si_read_smc_sram_dword(rdev, 3393 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3394 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3395 &tmp, si_pi->sram_end); 3396 if (ret) 3397 return ret; 3398 3399 si_pi->dte_table_start = tmp; 3400 3401 ret = si_read_smc_sram_dword(rdev, 3402 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3403 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3404 &tmp, si_pi->sram_end); 3405 if (ret) 3406 return ret; 3407 3408 si_pi->spll_table_start = tmp; 3409 3410 ret = si_read_smc_sram_dword(rdev, 3411 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3412 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3413 &tmp, si_pi->sram_end); 3414 if (ret) 3415 return ret; 3416 3417 si_pi->papm_cfg_table_start = tmp; 3418 3419 return ret; 3420 } 3421 3422 static void si_read_clock_registers(struct radeon_device *rdev) 3423 { 3424 struct si_power_info *si_pi = si_get_pi(rdev); 3425 3426 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3427 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3428 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3429 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3430 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3431 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3432 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3433 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3434 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3435 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3436 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3437 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3438 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3439 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3440 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3441 } 3442 3443 static void si_enable_thermal_protection(struct radeon_device *rdev, 3444 bool enable) 3445 { 3446 if (enable) 3447 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3448 else 3449 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3450 } 3451 3452 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3453 { 3454 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3455 } 3456 3457 #if 0 3458 static int si_enter_ulp_state(struct radeon_device *rdev) 3459 { 3460 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3461 3462 udelay(25000); 3463 3464 return 0; 3465 } 3466 3467 static int si_exit_ulp_state(struct radeon_device *rdev) 3468 { 3469 int i; 3470 3471 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3472 3473 udelay(7000); 3474 3475 for (i = 0; i < rdev->usec_timeout; i++) { 3476 if (RREG32(SMC_RESP_0) == 1) 3477 break; 3478 udelay(1000); 3479 } 3480 3481 return 0; 3482 } 3483 #endif 3484 3485 static int si_notify_smc_display_change(struct radeon_device *rdev, 3486 bool has_display) 3487 { 3488 PPSMC_Msg msg = has_display ? 3489 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3490 3491 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3492 0 : -EINVAL; 3493 } 3494 3495 static void si_program_response_times(struct radeon_device *rdev) 3496 { 3497 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3498 u32 vddc_dly, acpi_dly, vbi_dly; 3499 u32 reference_clock; 3500 3501 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3502 3503 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3504 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3505 3506 if (voltage_response_time == 0) 3507 voltage_response_time = 1000; 3508 3509 acpi_delay_time = 15000; 3510 vbi_time_out = 100000; 3511 3512 reference_clock = radeon_get_xclk(rdev); 3513 3514 vddc_dly = (voltage_response_time * reference_clock) / 100; 3515 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3516 vbi_dly = (vbi_time_out * reference_clock) / 100; 3517 3518 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3519 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3520 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3521 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3522 } 3523 3524 static void si_program_ds_registers(struct radeon_device *rdev) 3525 { 3526 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3527 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3528 3529 if (eg_pi->sclk_deep_sleep) { 3530 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3531 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3532 ~AUTOSCALE_ON_SS_CLEAR); 3533 } 3534 } 3535 3536 static void si_program_display_gap(struct radeon_device *rdev) 3537 { 3538 u32 tmp, pipe; 3539 int i; 3540 3541 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3542 if (rdev->pm.dpm.new_active_crtc_count > 0) 3543 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3544 else 3545 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3546 3547 if (rdev->pm.dpm.new_active_crtc_count > 1) 3548 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3549 else 3550 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3551 3552 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3553 3554 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3555 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3556 3557 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3558 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3559 /* find the first active crtc */ 3560 for (i = 0; i < rdev->num_crtc; i++) { 3561 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3562 break; 3563 } 3564 if (i == rdev->num_crtc) 3565 pipe = 0; 3566 else 3567 pipe = i; 3568 3569 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3570 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3571 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3572 } 3573 3574 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3575 * This can be a problem on PowerXpress systems or if you want to use the card 3576 * for offscreen rendering or compute if there are no crtcs enabled. 3577 */ 3578 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3579 } 3580 3581 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3582 { 3583 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3584 3585 if (enable) { 3586 if (pi->sclk_ss) 3587 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3588 } else { 3589 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3590 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3591 } 3592 } 3593 3594 static void si_setup_bsp(struct radeon_device *rdev) 3595 { 3596 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3597 u32 xclk = radeon_get_xclk(rdev); 3598 3599 r600_calculate_u_and_p(pi->asi, 3600 xclk, 3601 16, 3602 &pi->bsp, 3603 &pi->bsu); 3604 3605 r600_calculate_u_and_p(pi->pasi, 3606 xclk, 3607 16, 3608 &pi->pbsp, 3609 &pi->pbsu); 3610 3611 3612 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3613 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3614 3615 WREG32(CG_BSP, pi->dsp); 3616 } 3617 3618 static void si_program_git(struct radeon_device *rdev) 3619 { 3620 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3621 } 3622 3623 static void si_program_tp(struct radeon_device *rdev) 3624 { 3625 int i; 3626 enum r600_td td = R600_TD_DFLT; 3627 3628 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3629 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3630 3631 if (td == R600_TD_AUTO) 3632 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3633 else 3634 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3635 3636 if (td == R600_TD_UP) 3637 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3638 3639 if (td == R600_TD_DOWN) 3640 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3641 } 3642 3643 static void si_program_tpp(struct radeon_device *rdev) 3644 { 3645 WREG32(CG_TPC, R600_TPC_DFLT); 3646 } 3647 3648 static void si_program_sstp(struct radeon_device *rdev) 3649 { 3650 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3651 } 3652 3653 static void si_enable_display_gap(struct radeon_device *rdev) 3654 { 3655 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3656 3657 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3658 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3659 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3660 3661 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3662 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3663 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3664 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3665 } 3666 3667 static void si_program_vc(struct radeon_device *rdev) 3668 { 3669 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3670 3671 WREG32(CG_FTV, pi->vrc); 3672 } 3673 3674 static void si_clear_vc(struct radeon_device *rdev) 3675 { 3676 WREG32(CG_FTV, 0); 3677 } 3678 3679 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3680 { 3681 u8 mc_para_index; 3682 3683 if (memory_clock < 10000) 3684 mc_para_index = 0; 3685 else if (memory_clock >= 80000) 3686 mc_para_index = 0x0f; 3687 else 3688 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3689 return mc_para_index; 3690 } 3691 3692 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3693 { 3694 u8 mc_para_index; 3695 3696 if (strobe_mode) { 3697 if (memory_clock < 12500) 3698 mc_para_index = 0x00; 3699 else if (memory_clock > 47500) 3700 mc_para_index = 0x0f; 3701 else 3702 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3703 } else { 3704 if (memory_clock < 65000) 3705 mc_para_index = 0x00; 3706 else if (memory_clock > 135000) 3707 mc_para_index = 0x0f; 3708 else 3709 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3710 } 3711 return mc_para_index; 3712 } 3713 3714 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3715 { 3716 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3717 bool strobe_mode = false; 3718 u8 result = 0; 3719 3720 if (mclk <= pi->mclk_strobe_mode_threshold) 3721 strobe_mode = true; 3722 3723 if (pi->mem_gddr5) 3724 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3725 else 3726 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3727 3728 if (strobe_mode) 3729 result |= SISLANDS_SMC_STROBE_ENABLE; 3730 3731 return result; 3732 } 3733 3734 static int si_upload_firmware(struct radeon_device *rdev) 3735 { 3736 struct si_power_info *si_pi = si_get_pi(rdev); 3737 int ret; 3738 3739 si_reset_smc(rdev); 3740 si_stop_smc_clock(rdev); 3741 3742 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3743 3744 return ret; 3745 } 3746 3747 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3748 const struct atom_voltage_table *table, 3749 const struct radeon_phase_shedding_limits_table *limits) 3750 { 3751 u32 data, num_bits, num_levels; 3752 3753 if ((table == NULL) || (limits == NULL)) 3754 return false; 3755 3756 data = table->mask_low; 3757 3758 num_bits = hweight32(data); 3759 3760 if (num_bits == 0) 3761 return false; 3762 3763 num_levels = (1 << num_bits); 3764 3765 if (table->count != num_levels) 3766 return false; 3767 3768 if (limits->count != (num_levels - 1)) 3769 return false; 3770 3771 return true; 3772 } 3773 3774 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3775 u32 max_voltage_steps, 3776 struct atom_voltage_table *voltage_table) 3777 { 3778 unsigned int i, diff; 3779 3780 if (voltage_table->count <= max_voltage_steps) 3781 return; 3782 3783 diff = voltage_table->count - max_voltage_steps; 3784 3785 for (i= 0; i < max_voltage_steps; i++) 3786 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3787 3788 voltage_table->count = max_voltage_steps; 3789 } 3790 3791 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3792 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3793 struct atom_voltage_table *voltage_table) 3794 { 3795 u32 i; 3796 3797 if (voltage_dependency_table == NULL) 3798 return -EINVAL; 3799 3800 voltage_table->mask_low = 0; 3801 voltage_table->phase_delay = 0; 3802 3803 voltage_table->count = voltage_dependency_table->count; 3804 for (i = 0; i < voltage_table->count; i++) { 3805 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3806 voltage_table->entries[i].smio_low = 0; 3807 } 3808 3809 return 0; 3810 } 3811 3812 static int si_construct_voltage_tables(struct radeon_device *rdev) 3813 { 3814 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3815 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3816 struct si_power_info *si_pi = si_get_pi(rdev); 3817 int ret; 3818 3819 if (pi->voltage_control) { 3820 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3821 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3822 if (ret) 3823 return ret; 3824 3825 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3826 si_trim_voltage_table_to_fit_state_table(rdev, 3827 SISLANDS_MAX_NO_VREG_STEPS, 3828 &eg_pi->vddc_voltage_table); 3829 } else if (si_pi->voltage_control_svi2) { 3830 ret = si_get_svi2_voltage_table(rdev, 3831 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3832 &eg_pi->vddc_voltage_table); 3833 if (ret) 3834 return ret; 3835 } else { 3836 return -EINVAL; 3837 } 3838 3839 if (eg_pi->vddci_control) { 3840 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3841 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3842 if (ret) 3843 return ret; 3844 3845 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3846 si_trim_voltage_table_to_fit_state_table(rdev, 3847 SISLANDS_MAX_NO_VREG_STEPS, 3848 &eg_pi->vddci_voltage_table); 3849 } 3850 if (si_pi->vddci_control_svi2) { 3851 ret = si_get_svi2_voltage_table(rdev, 3852 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3853 &eg_pi->vddci_voltage_table); 3854 if (ret) 3855 return ret; 3856 } 3857 3858 if (pi->mvdd_control) { 3859 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3860 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3861 3862 if (ret) { 3863 pi->mvdd_control = false; 3864 return ret; 3865 } 3866 3867 if (si_pi->mvdd_voltage_table.count == 0) { 3868 pi->mvdd_control = false; 3869 return -EINVAL; 3870 } 3871 3872 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3873 si_trim_voltage_table_to_fit_state_table(rdev, 3874 SISLANDS_MAX_NO_VREG_STEPS, 3875 &si_pi->mvdd_voltage_table); 3876 } 3877 3878 if (si_pi->vddc_phase_shed_control) { 3879 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3880 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3881 if (ret) 3882 si_pi->vddc_phase_shed_control = false; 3883 3884 if ((si_pi->vddc_phase_shed_table.count == 0) || 3885 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3886 si_pi->vddc_phase_shed_control = false; 3887 } 3888 3889 return 0; 3890 } 3891 3892 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3893 const struct atom_voltage_table *voltage_table, 3894 SISLANDS_SMC_STATETABLE *table) 3895 { 3896 unsigned int i; 3897 3898 for (i = 0; i < voltage_table->count; i++) 3899 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3900 } 3901 3902 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3903 SISLANDS_SMC_STATETABLE *table) 3904 { 3905 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3906 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3907 struct si_power_info *si_pi = si_get_pi(rdev); 3908 u8 i; 3909 3910 if (si_pi->voltage_control_svi2) { 3911 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3912 si_pi->svc_gpio_id); 3913 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3914 si_pi->svd_gpio_id); 3915 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3916 2); 3917 } else { 3918 if (eg_pi->vddc_voltage_table.count) { 3919 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3920 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3921 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3922 3923 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3924 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3925 table->maxVDDCIndexInPPTable = i; 3926 break; 3927 } 3928 } 3929 } 3930 3931 if (eg_pi->vddci_voltage_table.count) { 3932 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3933 3934 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3935 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3936 } 3937 3938 3939 if (si_pi->mvdd_voltage_table.count) { 3940 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3941 3942 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3943 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3944 } 3945 3946 if (si_pi->vddc_phase_shed_control) { 3947 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3948 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3949 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3950 3951 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3952 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3953 3954 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3955 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3956 } else { 3957 si_pi->vddc_phase_shed_control = false; 3958 } 3959 } 3960 } 3961 3962 return 0; 3963 } 3964 3965 static int si_populate_voltage_value(struct radeon_device *rdev, 3966 const struct atom_voltage_table *table, 3967 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3968 { 3969 unsigned int i; 3970 3971 for (i = 0; i < table->count; i++) { 3972 if (value <= table->entries[i].value) { 3973 voltage->index = (u8)i; 3974 voltage->value = cpu_to_be16(table->entries[i].value); 3975 break; 3976 } 3977 } 3978 3979 if (i >= table->count) 3980 return -EINVAL; 3981 3982 return 0; 3983 } 3984 3985 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3986 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3987 { 3988 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3989 struct si_power_info *si_pi = si_get_pi(rdev); 3990 3991 if (pi->mvdd_control) { 3992 if (mclk <= pi->mvdd_split_frequency) 3993 voltage->index = 0; 3994 else 3995 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3996 3997 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3998 } 3999 return 0; 4000 } 4001 4002 static int si_get_std_voltage_value(struct radeon_device *rdev, 4003 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4004 u16 *std_voltage) 4005 { 4006 u16 v_index; 4007 bool voltage_found = false; 4008 *std_voltage = be16_to_cpu(voltage->value); 4009 4010 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4011 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4012 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4013 return -EINVAL; 4014 4015 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4016 if (be16_to_cpu(voltage->value) == 4017 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4018 voltage_found = true; 4019 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4020 *std_voltage = 4021 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4022 else 4023 *std_voltage = 4024 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4025 break; 4026 } 4027 } 4028 4029 if (!voltage_found) { 4030 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4031 if (be16_to_cpu(voltage->value) <= 4032 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4033 voltage_found = true; 4034 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4035 *std_voltage = 4036 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4037 else 4038 *std_voltage = 4039 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4040 break; 4041 } 4042 } 4043 } 4044 } else { 4045 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4046 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4047 } 4048 } 4049 4050 return 0; 4051 } 4052 4053 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4054 u16 value, u8 index, 4055 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4056 { 4057 voltage->index = index; 4058 voltage->value = cpu_to_be16(value); 4059 4060 return 0; 4061 } 4062 4063 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4064 const struct radeon_phase_shedding_limits_table *limits, 4065 u16 voltage, u32 sclk, u32 mclk, 4066 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4067 { 4068 unsigned int i; 4069 4070 for (i = 0; i < limits->count; i++) { 4071 if ((voltage <= limits->entries[i].voltage) && 4072 (sclk <= limits->entries[i].sclk) && 4073 (mclk <= limits->entries[i].mclk)) 4074 break; 4075 } 4076 4077 smc_voltage->phase_settings = (u8)i; 4078 4079 return 0; 4080 } 4081 4082 static int si_init_arb_table_index(struct radeon_device *rdev) 4083 { 4084 struct si_power_info *si_pi = si_get_pi(rdev); 4085 u32 tmp; 4086 int ret; 4087 4088 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4089 if (ret) 4090 return ret; 4091 4092 tmp &= 0x00FFFFFF; 4093 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4094 4095 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4096 } 4097 4098 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4099 { 4100 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4101 } 4102 4103 static int si_reset_to_default(struct radeon_device *rdev) 4104 { 4105 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4106 0 : -EINVAL; 4107 } 4108 4109 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4110 { 4111 struct si_power_info *si_pi = si_get_pi(rdev); 4112 u32 tmp; 4113 int ret; 4114 4115 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4116 &tmp, si_pi->sram_end); 4117 if (ret) 4118 return ret; 4119 4120 tmp = (tmp >> 24) & 0xff; 4121 4122 if (tmp == MC_CG_ARB_FREQ_F0) 4123 return 0; 4124 4125 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4126 } 4127 4128 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4129 u32 engine_clock) 4130 { 4131 u32 dram_rows; 4132 u32 dram_refresh_rate; 4133 u32 mc_arb_rfsh_rate; 4134 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4135 4136 if (tmp >= 4) 4137 dram_rows = 16384; 4138 else 4139 dram_rows = 1 << (tmp + 10); 4140 4141 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4142 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4143 4144 return mc_arb_rfsh_rate; 4145 } 4146 4147 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4148 struct rv7xx_pl *pl, 4149 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4150 { 4151 u32 dram_timing; 4152 u32 dram_timing2; 4153 u32 burst_time; 4154 4155 arb_regs->mc_arb_rfsh_rate = 4156 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4157 4158 radeon_atom_set_engine_dram_timings(rdev, 4159 pl->sclk, 4160 pl->mclk); 4161 4162 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4163 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4164 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4165 4166 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4167 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4168 arb_regs->mc_arb_burst_time = (u8)burst_time; 4169 4170 return 0; 4171 } 4172 4173 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4174 struct radeon_ps *radeon_state, 4175 unsigned int first_arb_set) 4176 { 4177 struct si_power_info *si_pi = si_get_pi(rdev); 4178 struct ni_ps *state = ni_get_ps(radeon_state); 4179 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4180 int i, ret = 0; 4181 4182 for (i = 0; i < state->performance_level_count; i++) { 4183 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4184 if (ret) 4185 break; 4186 ret = si_copy_bytes_to_smc(rdev, 4187 si_pi->arb_table_start + 4188 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4189 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4190 (u8 *)&arb_regs, 4191 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4192 si_pi->sram_end); 4193 if (ret) 4194 break; 4195 } 4196 4197 return ret; 4198 } 4199 4200 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4201 struct radeon_ps *radeon_new_state) 4202 { 4203 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4204 SISLANDS_DRIVER_STATE_ARB_INDEX); 4205 } 4206 4207 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4208 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4209 { 4210 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4211 struct si_power_info *si_pi = si_get_pi(rdev); 4212 4213 if (pi->mvdd_control) 4214 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4215 si_pi->mvdd_bootup_value, voltage); 4216 4217 return 0; 4218 } 4219 4220 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4221 struct radeon_ps *radeon_initial_state, 4222 SISLANDS_SMC_STATETABLE *table) 4223 { 4224 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4225 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4226 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4227 struct si_power_info *si_pi = si_get_pi(rdev); 4228 u32 reg; 4229 int ret; 4230 4231 table->initialState.levels[0].mclk.vDLL_CNTL = 4232 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4233 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4234 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4235 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4236 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4237 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4238 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4239 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4240 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4241 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4242 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4243 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4244 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4245 table->initialState.levels[0].mclk.vMPLL_SS = 4246 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4247 table->initialState.levels[0].mclk.vMPLL_SS2 = 4248 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4249 4250 table->initialState.levels[0].mclk.mclk_value = 4251 cpu_to_be32(initial_state->performance_levels[0].mclk); 4252 4253 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4254 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4255 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4256 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4257 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4258 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4259 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4260 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4261 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4262 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4263 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4264 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4265 4266 table->initialState.levels[0].sclk.sclk_value = 4267 cpu_to_be32(initial_state->performance_levels[0].sclk); 4268 4269 table->initialState.levels[0].arbRefreshState = 4270 SISLANDS_INITIAL_STATE_ARB_INDEX; 4271 4272 table->initialState.levels[0].ACIndex = 0; 4273 4274 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4275 initial_state->performance_levels[0].vddc, 4276 &table->initialState.levels[0].vddc); 4277 4278 if (!ret) { 4279 u16 std_vddc; 4280 4281 ret = si_get_std_voltage_value(rdev, 4282 &table->initialState.levels[0].vddc, 4283 &std_vddc); 4284 if (!ret) 4285 si_populate_std_voltage_value(rdev, std_vddc, 4286 table->initialState.levels[0].vddc.index, 4287 &table->initialState.levels[0].std_vddc); 4288 } 4289 4290 if (eg_pi->vddci_control) 4291 si_populate_voltage_value(rdev, 4292 &eg_pi->vddci_voltage_table, 4293 initial_state->performance_levels[0].vddci, 4294 &table->initialState.levels[0].vddci); 4295 4296 if (si_pi->vddc_phase_shed_control) 4297 si_populate_phase_shedding_value(rdev, 4298 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4299 initial_state->performance_levels[0].vddc, 4300 initial_state->performance_levels[0].sclk, 4301 initial_state->performance_levels[0].mclk, 4302 &table->initialState.levels[0].vddc); 4303 4304 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4305 4306 reg = CG_R(0xffff) | CG_L(0); 4307 table->initialState.levels[0].aT = cpu_to_be32(reg); 4308 4309 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4310 4311 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4312 4313 if (pi->mem_gddr5) { 4314 table->initialState.levels[0].strobeMode = 4315 si_get_strobe_mode_settings(rdev, 4316 initial_state->performance_levels[0].mclk); 4317 4318 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4319 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4320 else 4321 table->initialState.levels[0].mcFlags = 0; 4322 } 4323 4324 table->initialState.levelCount = 1; 4325 4326 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4327 4328 table->initialState.levels[0].dpm2.MaxPS = 0; 4329 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4330 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4331 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4332 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4333 4334 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4335 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4336 4337 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4338 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4339 4340 return 0; 4341 } 4342 4343 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4344 SISLANDS_SMC_STATETABLE *table) 4345 { 4346 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4347 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4348 struct si_power_info *si_pi = si_get_pi(rdev); 4349 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4350 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4351 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4352 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4353 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4354 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4355 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4356 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4357 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4358 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4359 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4360 u32 reg; 4361 int ret; 4362 4363 table->ACPIState = table->initialState; 4364 4365 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4366 4367 if (pi->acpi_vddc) { 4368 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4369 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4370 if (!ret) { 4371 u16 std_vddc; 4372 4373 ret = si_get_std_voltage_value(rdev, 4374 &table->ACPIState.levels[0].vddc, &std_vddc); 4375 if (!ret) 4376 si_populate_std_voltage_value(rdev, std_vddc, 4377 table->ACPIState.levels[0].vddc.index, 4378 &table->ACPIState.levels[0].std_vddc); 4379 } 4380 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4381 4382 if (si_pi->vddc_phase_shed_control) { 4383 si_populate_phase_shedding_value(rdev, 4384 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4385 pi->acpi_vddc, 4386 0, 4387 0, 4388 &table->ACPIState.levels[0].vddc); 4389 } 4390 } else { 4391 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4392 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4393 if (!ret) { 4394 u16 std_vddc; 4395 4396 ret = si_get_std_voltage_value(rdev, 4397 &table->ACPIState.levels[0].vddc, &std_vddc); 4398 4399 if (!ret) 4400 si_populate_std_voltage_value(rdev, std_vddc, 4401 table->ACPIState.levels[0].vddc.index, 4402 &table->ACPIState.levels[0].std_vddc); 4403 } 4404 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4405 si_pi->sys_pcie_mask, 4406 si_pi->boot_pcie_gen, 4407 RADEON_PCIE_GEN1); 4408 4409 if (si_pi->vddc_phase_shed_control) 4410 si_populate_phase_shedding_value(rdev, 4411 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4412 pi->min_vddc_in_table, 4413 0, 4414 0, 4415 &table->ACPIState.levels[0].vddc); 4416 } 4417 4418 if (pi->acpi_vddc) { 4419 if (eg_pi->acpi_vddci) 4420 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4421 eg_pi->acpi_vddci, 4422 &table->ACPIState.levels[0].vddci); 4423 } 4424 4425 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4426 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4427 4428 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4429 4430 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4431 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4432 4433 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4434 cpu_to_be32(dll_cntl); 4435 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4436 cpu_to_be32(mclk_pwrmgt_cntl); 4437 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4438 cpu_to_be32(mpll_ad_func_cntl); 4439 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4440 cpu_to_be32(mpll_dq_func_cntl); 4441 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4442 cpu_to_be32(mpll_func_cntl); 4443 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4444 cpu_to_be32(mpll_func_cntl_1); 4445 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4446 cpu_to_be32(mpll_func_cntl_2); 4447 table->ACPIState.levels[0].mclk.vMPLL_SS = 4448 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4449 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4450 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4451 4452 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4453 cpu_to_be32(spll_func_cntl); 4454 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4455 cpu_to_be32(spll_func_cntl_2); 4456 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4457 cpu_to_be32(spll_func_cntl_3); 4458 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4459 cpu_to_be32(spll_func_cntl_4); 4460 4461 table->ACPIState.levels[0].mclk.mclk_value = 0; 4462 table->ACPIState.levels[0].sclk.sclk_value = 0; 4463 4464 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4465 4466 if (eg_pi->dynamic_ac_timing) 4467 table->ACPIState.levels[0].ACIndex = 0; 4468 4469 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4470 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4471 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4472 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4473 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4474 4475 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4476 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4477 4478 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4479 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4480 4481 return 0; 4482 } 4483 4484 static int si_populate_ulv_state(struct radeon_device *rdev, 4485 SISLANDS_SMC_SWSTATE *state) 4486 { 4487 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4488 struct si_power_info *si_pi = si_get_pi(rdev); 4489 struct si_ulv_param *ulv = &si_pi->ulv; 4490 u32 sclk_in_sr = 1350; /* ??? */ 4491 int ret; 4492 4493 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4494 &state->levels[0]); 4495 if (!ret) { 4496 if (eg_pi->sclk_deep_sleep) { 4497 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4498 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4499 else 4500 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4501 } 4502 if (ulv->one_pcie_lane_in_ulv) 4503 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4504 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4505 state->levels[0].ACIndex = 1; 4506 state->levels[0].std_vddc = state->levels[0].vddc; 4507 state->levelCount = 1; 4508 4509 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4510 } 4511 4512 return ret; 4513 } 4514 4515 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4516 { 4517 struct si_power_info *si_pi = si_get_pi(rdev); 4518 struct si_ulv_param *ulv = &si_pi->ulv; 4519 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4520 int ret; 4521 4522 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4523 &arb_regs); 4524 if (ret) 4525 return ret; 4526 4527 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4528 ulv->volt_change_delay); 4529 4530 ret = si_copy_bytes_to_smc(rdev, 4531 si_pi->arb_table_start + 4532 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4533 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4534 (u8 *)&arb_regs, 4535 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4536 si_pi->sram_end); 4537 4538 return ret; 4539 } 4540 4541 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4542 { 4543 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4544 4545 pi->mvdd_split_frequency = 30000; 4546 } 4547 4548 static int si_init_smc_table(struct radeon_device *rdev) 4549 { 4550 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4551 struct si_power_info *si_pi = si_get_pi(rdev); 4552 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4553 const struct si_ulv_param *ulv = &si_pi->ulv; 4554 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4555 int ret; 4556 u32 lane_width; 4557 u32 vr_hot_gpio; 4558 4559 si_populate_smc_voltage_tables(rdev, table); 4560 4561 switch (rdev->pm.int_thermal_type) { 4562 case THERMAL_TYPE_SI: 4563 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4564 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4565 break; 4566 case THERMAL_TYPE_NONE: 4567 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4568 break; 4569 default: 4570 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4571 break; 4572 } 4573 4574 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4575 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4576 4577 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4578 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4579 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4580 } 4581 4582 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4583 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4584 4585 if (pi->mem_gddr5) 4586 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4587 4588 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4589 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4590 4591 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4592 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4593 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4594 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4595 vr_hot_gpio); 4596 } 4597 4598 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4599 if (ret) 4600 return ret; 4601 4602 ret = si_populate_smc_acpi_state(rdev, table); 4603 if (ret) 4604 return ret; 4605 4606 table->driverState = table->initialState; 4607 4608 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4609 SISLANDS_INITIAL_STATE_ARB_INDEX); 4610 if (ret) 4611 return ret; 4612 4613 if (ulv->supported && ulv->pl.vddc) { 4614 ret = si_populate_ulv_state(rdev, &table->ULVState); 4615 if (ret) 4616 return ret; 4617 4618 ret = si_program_ulv_memory_timing_parameters(rdev); 4619 if (ret) 4620 return ret; 4621 4622 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4623 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4624 4625 lane_width = radeon_get_pcie_lanes(rdev); 4626 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4627 } else { 4628 table->ULVState = table->initialState; 4629 } 4630 4631 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4632 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4633 si_pi->sram_end); 4634 } 4635 4636 static int si_calculate_sclk_params(struct radeon_device *rdev, 4637 u32 engine_clock, 4638 SISLANDS_SMC_SCLK_VALUE *sclk) 4639 { 4640 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4641 struct si_power_info *si_pi = si_get_pi(rdev); 4642 struct atom_clock_dividers dividers; 4643 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4644 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4645 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4646 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4647 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4648 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4649 u64 tmp; 4650 u32 reference_clock = rdev->clock.spll.reference_freq; 4651 u32 reference_divider; 4652 u32 fbdiv; 4653 int ret; 4654 4655 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4656 engine_clock, false, ÷rs); 4657 if (ret) 4658 return ret; 4659 4660 reference_divider = 1 + dividers.ref_div; 4661 4662 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4663 do_div(tmp, reference_clock); 4664 fbdiv = (u32) tmp; 4665 4666 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4667 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4668 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4669 4670 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4671 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4672 4673 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4674 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4675 spll_func_cntl_3 |= SPLL_DITHEN; 4676 4677 if (pi->sclk_ss) { 4678 struct radeon_atom_ss ss; 4679 u32 vco_freq = engine_clock * dividers.post_div; 4680 4681 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4682 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4683 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4684 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4685 4686 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4687 cg_spll_spread_spectrum |= CLK_S(clk_s); 4688 cg_spll_spread_spectrum |= SSEN; 4689 4690 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4691 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4692 } 4693 } 4694 4695 sclk->sclk_value = engine_clock; 4696 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4697 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4698 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4699 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4700 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4701 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4702 4703 return 0; 4704 } 4705 4706 static int si_populate_sclk_value(struct radeon_device *rdev, 4707 u32 engine_clock, 4708 SISLANDS_SMC_SCLK_VALUE *sclk) 4709 { 4710 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4711 int ret; 4712 4713 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4714 if (!ret) { 4715 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4716 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4717 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4718 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4719 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4720 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4721 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4722 } 4723 4724 return ret; 4725 } 4726 4727 static int si_populate_mclk_value(struct radeon_device *rdev, 4728 u32 engine_clock, 4729 u32 memory_clock, 4730 SISLANDS_SMC_MCLK_VALUE *mclk, 4731 bool strobe_mode, 4732 bool dll_state_on) 4733 { 4734 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4735 struct si_power_info *si_pi = si_get_pi(rdev); 4736 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4737 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4738 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4739 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4740 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4741 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4742 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4743 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4744 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4745 struct atom_mpll_param mpll_param; 4746 int ret; 4747 4748 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4749 if (ret) 4750 return ret; 4751 4752 mpll_func_cntl &= ~BWCTRL_MASK; 4753 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4754 4755 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4756 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4757 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4758 4759 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4760 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4761 4762 if (pi->mem_gddr5) { 4763 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4764 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4765 YCLK_POST_DIV(mpll_param.post_div); 4766 } 4767 4768 if (pi->mclk_ss) { 4769 struct radeon_atom_ss ss; 4770 u32 freq_nom; 4771 u32 tmp; 4772 u32 reference_clock = rdev->clock.mpll.reference_freq; 4773 4774 if (pi->mem_gddr5) 4775 freq_nom = memory_clock * 4; 4776 else 4777 freq_nom = memory_clock * 2; 4778 4779 tmp = freq_nom / reference_clock; 4780 tmp = tmp * tmp; 4781 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4782 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4783 u32 clks = reference_clock * 5 / ss.rate; 4784 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4785 4786 mpll_ss1 &= ~CLKV_MASK; 4787 mpll_ss1 |= CLKV(clkv); 4788 4789 mpll_ss2 &= ~CLKS_MASK; 4790 mpll_ss2 |= CLKS(clks); 4791 } 4792 } 4793 4794 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4795 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4796 4797 if (dll_state_on) 4798 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4799 else 4800 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4801 4802 mclk->mclk_value = cpu_to_be32(memory_clock); 4803 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4804 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4805 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4806 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4807 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4808 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4809 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4810 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4811 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4812 4813 return 0; 4814 } 4815 4816 static void si_populate_smc_sp(struct radeon_device *rdev, 4817 struct radeon_ps *radeon_state, 4818 SISLANDS_SMC_SWSTATE *smc_state) 4819 { 4820 struct ni_ps *ps = ni_get_ps(radeon_state); 4821 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4822 int i; 4823 4824 for (i = 0; i < ps->performance_level_count - 1; i++) 4825 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4826 4827 smc_state->levels[ps->performance_level_count - 1].bSP = 4828 cpu_to_be32(pi->psp); 4829 } 4830 4831 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4832 struct rv7xx_pl *pl, 4833 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4834 { 4835 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4836 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4837 struct si_power_info *si_pi = si_get_pi(rdev); 4838 int ret; 4839 bool dll_state_on; 4840 u16 std_vddc; 4841 bool gmc_pg = false; 4842 4843 if (eg_pi->pcie_performance_request && 4844 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4845 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4846 else 4847 level->gen2PCIE = (u8)pl->pcie_gen; 4848 4849 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4850 if (ret) 4851 return ret; 4852 4853 level->mcFlags = 0; 4854 4855 if (pi->mclk_stutter_mode_threshold && 4856 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4857 !eg_pi->uvd_enabled && 4858 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4859 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4860 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4861 4862 if (gmc_pg) 4863 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4864 } 4865 4866 if (pi->mem_gddr5) { 4867 if (pl->mclk > pi->mclk_edc_enable_threshold) 4868 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4869 4870 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4871 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4872 4873 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4874 4875 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4876 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4877 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4878 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4879 else 4880 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4881 } else { 4882 dll_state_on = false; 4883 } 4884 } else { 4885 level->strobeMode = si_get_strobe_mode_settings(rdev, 4886 pl->mclk); 4887 4888 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4889 } 4890 4891 ret = si_populate_mclk_value(rdev, 4892 pl->sclk, 4893 pl->mclk, 4894 &level->mclk, 4895 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4896 if (ret) 4897 return ret; 4898 4899 ret = si_populate_voltage_value(rdev, 4900 &eg_pi->vddc_voltage_table, 4901 pl->vddc, &level->vddc); 4902 if (ret) 4903 return ret; 4904 4905 4906 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4907 if (ret) 4908 return ret; 4909 4910 ret = si_populate_std_voltage_value(rdev, std_vddc, 4911 level->vddc.index, &level->std_vddc); 4912 if (ret) 4913 return ret; 4914 4915 if (eg_pi->vddci_control) { 4916 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4917 pl->vddci, &level->vddci); 4918 if (ret) 4919 return ret; 4920 } 4921 4922 if (si_pi->vddc_phase_shed_control) { 4923 ret = si_populate_phase_shedding_value(rdev, 4924 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4925 pl->vddc, 4926 pl->sclk, 4927 pl->mclk, 4928 &level->vddc); 4929 if (ret) 4930 return ret; 4931 } 4932 4933 level->MaxPoweredUpCU = si_pi->max_cu; 4934 4935 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4936 4937 return ret; 4938 } 4939 4940 static int si_populate_smc_t(struct radeon_device *rdev, 4941 struct radeon_ps *radeon_state, 4942 SISLANDS_SMC_SWSTATE *smc_state) 4943 { 4944 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4945 struct ni_ps *state = ni_get_ps(radeon_state); 4946 u32 a_t; 4947 u32 t_l, t_h; 4948 u32 high_bsp; 4949 int i, ret; 4950 4951 if (state->performance_level_count >= 9) 4952 return -EINVAL; 4953 4954 if (state->performance_level_count < 2) { 4955 a_t = CG_R(0xffff) | CG_L(0); 4956 smc_state->levels[0].aT = cpu_to_be32(a_t); 4957 return 0; 4958 } 4959 4960 smc_state->levels[0].aT = cpu_to_be32(0); 4961 4962 for (i = 0; i <= state->performance_level_count - 2; i++) { 4963 ret = r600_calculate_at( 4964 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4965 100 * R600_AH_DFLT, 4966 state->performance_levels[i + 1].sclk, 4967 state->performance_levels[i].sclk, 4968 &t_l, 4969 &t_h); 4970 4971 if (ret) { 4972 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4973 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4974 } 4975 4976 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4977 a_t |= CG_R(t_l * pi->bsp / 20000); 4978 smc_state->levels[i].aT = cpu_to_be32(a_t); 4979 4980 high_bsp = (i == state->performance_level_count - 2) ? 4981 pi->pbsp : pi->bsp; 4982 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4983 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4984 } 4985 4986 return 0; 4987 } 4988 4989 static int si_disable_ulv(struct radeon_device *rdev) 4990 { 4991 struct si_power_info *si_pi = si_get_pi(rdev); 4992 struct si_ulv_param *ulv = &si_pi->ulv; 4993 4994 if (ulv->supported) 4995 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4996 0 : -EINVAL; 4997 4998 return 0; 4999 } 5000 5001 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5002 struct radeon_ps *radeon_state) 5003 { 5004 const struct si_power_info *si_pi = si_get_pi(rdev); 5005 const struct si_ulv_param *ulv = &si_pi->ulv; 5006 const struct ni_ps *state = ni_get_ps(radeon_state); 5007 int i; 5008 5009 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5010 return false; 5011 5012 /* XXX validate against display requirements! */ 5013 5014 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5015 if (rdev->clock.current_dispclk <= 5016 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5017 if (ulv->pl.vddc < 5018 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5019 return false; 5020 } 5021 } 5022 5023 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5024 return false; 5025 5026 return true; 5027 } 5028 5029 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5030 struct radeon_ps *radeon_new_state) 5031 { 5032 const struct si_power_info *si_pi = si_get_pi(rdev); 5033 const struct si_ulv_param *ulv = &si_pi->ulv; 5034 5035 if (ulv->supported) { 5036 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5037 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5038 0 : -EINVAL; 5039 } 5040 return 0; 5041 } 5042 5043 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5044 struct radeon_ps *radeon_state, 5045 SISLANDS_SMC_SWSTATE *smc_state) 5046 { 5047 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5048 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5049 struct si_power_info *si_pi = si_get_pi(rdev); 5050 struct ni_ps *state = ni_get_ps(radeon_state); 5051 int i, ret; 5052 u32 threshold; 5053 u32 sclk_in_sr = 1350; /* ??? */ 5054 5055 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5056 return -EINVAL; 5057 5058 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5059 5060 if (radeon_state->vclk && radeon_state->dclk) { 5061 eg_pi->uvd_enabled = true; 5062 if (eg_pi->smu_uvd_hs) 5063 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5064 } else { 5065 eg_pi->uvd_enabled = false; 5066 } 5067 5068 if (state->dc_compatible) 5069 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5070 5071 smc_state->levelCount = 0; 5072 for (i = 0; i < state->performance_level_count; i++) { 5073 if (eg_pi->sclk_deep_sleep) { 5074 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5075 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5076 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5077 else 5078 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5079 } 5080 } 5081 5082 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5083 &smc_state->levels[i]); 5084 smc_state->levels[i].arbRefreshState = 5085 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5086 5087 if (ret) 5088 return ret; 5089 5090 if (ni_pi->enable_power_containment) 5091 smc_state->levels[i].displayWatermark = 5092 (state->performance_levels[i].sclk < threshold) ? 5093 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5094 else 5095 smc_state->levels[i].displayWatermark = (i < 2) ? 5096 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5097 5098 if (eg_pi->dynamic_ac_timing) 5099 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5100 else 5101 smc_state->levels[i].ACIndex = 0; 5102 5103 smc_state->levelCount++; 5104 } 5105 5106 si_write_smc_soft_register(rdev, 5107 SI_SMC_SOFT_REGISTER_watermark_threshold, 5108 threshold / 512); 5109 5110 si_populate_smc_sp(rdev, radeon_state, smc_state); 5111 5112 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5113 if (ret) 5114 ni_pi->enable_power_containment = false; 5115 5116 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5117 if (ret) 5118 ni_pi->enable_sq_ramping = false; 5119 5120 return si_populate_smc_t(rdev, radeon_state, smc_state); 5121 } 5122 5123 static int si_upload_sw_state(struct radeon_device *rdev, 5124 struct radeon_ps *radeon_new_state) 5125 { 5126 struct si_power_info *si_pi = si_get_pi(rdev); 5127 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5128 int ret; 5129 u32 address = si_pi->state_table_start + 5130 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5131 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5132 ((new_state->performance_level_count - 1) * 5133 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5134 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5135 5136 memset(smc_state, 0, state_size); 5137 5138 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5139 if (ret) 5140 return ret; 5141 5142 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5143 state_size, si_pi->sram_end); 5144 5145 return ret; 5146 } 5147 5148 static int si_upload_ulv_state(struct radeon_device *rdev) 5149 { 5150 struct si_power_info *si_pi = si_get_pi(rdev); 5151 struct si_ulv_param *ulv = &si_pi->ulv; 5152 int ret = 0; 5153 5154 if (ulv->supported && ulv->pl.vddc) { 5155 u32 address = si_pi->state_table_start + 5156 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5157 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5158 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5159 5160 memset(smc_state, 0, state_size); 5161 5162 ret = si_populate_ulv_state(rdev, smc_state); 5163 if (!ret) 5164 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5165 state_size, si_pi->sram_end); 5166 } 5167 5168 return ret; 5169 } 5170 5171 static int si_upload_smc_data(struct radeon_device *rdev) 5172 { 5173 struct radeon_crtc *radeon_crtc = NULL; 5174 int i; 5175 5176 if (rdev->pm.dpm.new_active_crtc_count == 0) 5177 return 0; 5178 5179 for (i = 0; i < rdev->num_crtc; i++) { 5180 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5181 radeon_crtc = rdev->mode_info.crtcs[i]; 5182 break; 5183 } 5184 } 5185 5186 if (radeon_crtc == NULL) 5187 return 0; 5188 5189 if (radeon_crtc->line_time <= 0) 5190 return 0; 5191 5192 if (si_write_smc_soft_register(rdev, 5193 SI_SMC_SOFT_REGISTER_crtc_index, 5194 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5195 return 0; 5196 5197 if (si_write_smc_soft_register(rdev, 5198 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5199 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5200 return 0; 5201 5202 if (si_write_smc_soft_register(rdev, 5203 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5204 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5205 return 0; 5206 5207 return 0; 5208 } 5209 5210 static int si_set_mc_special_registers(struct radeon_device *rdev, 5211 struct si_mc_reg_table *table) 5212 { 5213 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5214 u8 i, j, k; 5215 u32 temp_reg; 5216 5217 for (i = 0, j = table->last; i < table->last; i++) { 5218 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5219 return -EINVAL; 5220 switch (table->mc_reg_address[i].s1 << 2) { 5221 case MC_SEQ_MISC1: 5222 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5223 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5224 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5225 for (k = 0; k < table->num_entries; k++) 5226 table->mc_reg_table_entry[k].mc_data[j] = 5227 ((temp_reg & 0xffff0000)) | 5228 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5229 j++; 5230 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5231 return -EINVAL; 5232 5233 temp_reg = RREG32(MC_PMG_CMD_MRS); 5234 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5235 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5236 for (k = 0; k < table->num_entries; k++) { 5237 table->mc_reg_table_entry[k].mc_data[j] = 5238 (temp_reg & 0xffff0000) | 5239 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5240 if (!pi->mem_gddr5) 5241 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5242 } 5243 j++; 5244 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5245 return -EINVAL; 5246 5247 if (!pi->mem_gddr5) { 5248 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5249 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5250 for (k = 0; k < table->num_entries; k++) 5251 table->mc_reg_table_entry[k].mc_data[j] = 5252 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5253 j++; 5254 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5255 return -EINVAL; 5256 } 5257 break; 5258 case MC_SEQ_RESERVE_M: 5259 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5260 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5261 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5262 for(k = 0; k < table->num_entries; k++) 5263 table->mc_reg_table_entry[k].mc_data[j] = 5264 (temp_reg & 0xffff0000) | 5265 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5266 j++; 5267 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5268 return -EINVAL; 5269 break; 5270 default: 5271 break; 5272 } 5273 } 5274 5275 table->last = j; 5276 5277 return 0; 5278 } 5279 5280 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5281 { 5282 bool result = true; 5283 5284 switch (in_reg) { 5285 case MC_SEQ_RAS_TIMING >> 2: 5286 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5287 break; 5288 case MC_SEQ_CAS_TIMING >> 2: 5289 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5290 break; 5291 case MC_SEQ_MISC_TIMING >> 2: 5292 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5293 break; 5294 case MC_SEQ_MISC_TIMING2 >> 2: 5295 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5296 break; 5297 case MC_SEQ_RD_CTL_D0 >> 2: 5298 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5299 break; 5300 case MC_SEQ_RD_CTL_D1 >> 2: 5301 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5302 break; 5303 case MC_SEQ_WR_CTL_D0 >> 2: 5304 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5305 break; 5306 case MC_SEQ_WR_CTL_D1 >> 2: 5307 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5308 break; 5309 case MC_PMG_CMD_EMRS >> 2: 5310 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5311 break; 5312 case MC_PMG_CMD_MRS >> 2: 5313 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5314 break; 5315 case MC_PMG_CMD_MRS1 >> 2: 5316 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5317 break; 5318 case MC_SEQ_PMG_TIMING >> 2: 5319 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5320 break; 5321 case MC_PMG_CMD_MRS2 >> 2: 5322 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5323 break; 5324 case MC_SEQ_WR_CTL_2 >> 2: 5325 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5326 break; 5327 default: 5328 result = false; 5329 break; 5330 } 5331 5332 return result; 5333 } 5334 5335 static void si_set_valid_flag(struct si_mc_reg_table *table) 5336 { 5337 u8 i, j; 5338 5339 for (i = 0; i < table->last; i++) { 5340 for (j = 1; j < table->num_entries; j++) { 5341 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5342 table->valid_flag |= 1 << i; 5343 break; 5344 } 5345 } 5346 } 5347 } 5348 5349 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5350 { 5351 u32 i; 5352 u16 address; 5353 5354 for (i = 0; i < table->last; i++) 5355 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5356 address : table->mc_reg_address[i].s1; 5357 5358 } 5359 5360 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5361 struct si_mc_reg_table *si_table) 5362 { 5363 u8 i, j; 5364 5365 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5366 return -EINVAL; 5367 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5368 return -EINVAL; 5369 5370 for (i = 0; i < table->last; i++) 5371 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5372 si_table->last = table->last; 5373 5374 for (i = 0; i < table->num_entries; i++) { 5375 si_table->mc_reg_table_entry[i].mclk_max = 5376 table->mc_reg_table_entry[i].mclk_max; 5377 for (j = 0; j < table->last; j++) { 5378 si_table->mc_reg_table_entry[i].mc_data[j] = 5379 table->mc_reg_table_entry[i].mc_data[j]; 5380 } 5381 } 5382 si_table->num_entries = table->num_entries; 5383 5384 return 0; 5385 } 5386 5387 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5388 { 5389 struct si_power_info *si_pi = si_get_pi(rdev); 5390 struct atom_mc_reg_table *table; 5391 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5392 u8 module_index = rv770_get_memory_module_index(rdev); 5393 int ret; 5394 5395 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5396 if (!table) 5397 return -ENOMEM; 5398 5399 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5400 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5401 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5402 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5403 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5404 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5405 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5406 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5407 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5408 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5409 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5410 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5411 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5412 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5413 5414 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5415 if (ret) 5416 goto init_mc_done; 5417 5418 ret = si_copy_vbios_mc_reg_table(table, si_table); 5419 if (ret) 5420 goto init_mc_done; 5421 5422 si_set_s0_mc_reg_index(si_table); 5423 5424 ret = si_set_mc_special_registers(rdev, si_table); 5425 if (ret) 5426 goto init_mc_done; 5427 5428 si_set_valid_flag(si_table); 5429 5430 init_mc_done: 5431 kfree(table); 5432 5433 return ret; 5434 5435 } 5436 5437 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5438 SMC_SIslands_MCRegisters *mc_reg_table) 5439 { 5440 struct si_power_info *si_pi = si_get_pi(rdev); 5441 u32 i, j; 5442 5443 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5444 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5445 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5446 break; 5447 mc_reg_table->address[i].s0 = 5448 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5449 mc_reg_table->address[i].s1 = 5450 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5451 i++; 5452 } 5453 } 5454 mc_reg_table->last = (u8)i; 5455 } 5456 5457 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5458 SMC_SIslands_MCRegisterSet *data, 5459 u32 num_entries, u32 valid_flag) 5460 { 5461 u32 i, j; 5462 5463 for(i = 0, j = 0; j < num_entries; j++) { 5464 if (valid_flag & (1 << j)) { 5465 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5466 i++; 5467 } 5468 } 5469 } 5470 5471 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5472 struct rv7xx_pl *pl, 5473 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5474 { 5475 struct si_power_info *si_pi = si_get_pi(rdev); 5476 u32 i = 0; 5477 5478 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5479 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5480 break; 5481 } 5482 5483 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5484 --i; 5485 5486 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5487 mc_reg_table_data, si_pi->mc_reg_table.last, 5488 si_pi->mc_reg_table.valid_flag); 5489 } 5490 5491 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5492 struct radeon_ps *radeon_state, 5493 SMC_SIslands_MCRegisters *mc_reg_table) 5494 { 5495 struct ni_ps *state = ni_get_ps(radeon_state); 5496 int i; 5497 5498 for (i = 0; i < state->performance_level_count; i++) { 5499 si_convert_mc_reg_table_entry_to_smc(rdev, 5500 &state->performance_levels[i], 5501 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5502 } 5503 } 5504 5505 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5506 struct radeon_ps *radeon_boot_state) 5507 { 5508 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5509 struct si_power_info *si_pi = si_get_pi(rdev); 5510 struct si_ulv_param *ulv = &si_pi->ulv; 5511 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5512 5513 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5514 5515 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5516 5517 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5518 5519 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5520 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5521 5522 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5523 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5524 si_pi->mc_reg_table.last, 5525 si_pi->mc_reg_table.valid_flag); 5526 5527 if (ulv->supported && ulv->pl.vddc != 0) 5528 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5529 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5530 else 5531 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5532 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5533 si_pi->mc_reg_table.last, 5534 si_pi->mc_reg_table.valid_flag); 5535 5536 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5537 5538 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5539 (u8 *)smc_mc_reg_table, 5540 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5541 } 5542 5543 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5544 struct radeon_ps *radeon_new_state) 5545 { 5546 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5547 struct si_power_info *si_pi = si_get_pi(rdev); 5548 u32 address = si_pi->mc_reg_table_start + 5549 offsetof(SMC_SIslands_MCRegisters, 5550 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5551 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5552 5553 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5554 5555 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5556 5557 5558 return si_copy_bytes_to_smc(rdev, address, 5559 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5560 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5561 si_pi->sram_end); 5562 5563 } 5564 5565 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5566 { 5567 if (enable) 5568 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5569 else 5570 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5571 } 5572 5573 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5574 struct radeon_ps *radeon_state) 5575 { 5576 struct ni_ps *state = ni_get_ps(radeon_state); 5577 int i; 5578 u16 pcie_speed, max_speed = 0; 5579 5580 for (i = 0; i < state->performance_level_count; i++) { 5581 pcie_speed = state->performance_levels[i].pcie_gen; 5582 if (max_speed < pcie_speed) 5583 max_speed = pcie_speed; 5584 } 5585 return max_speed; 5586 } 5587 5588 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5589 { 5590 u32 speed_cntl; 5591 5592 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5593 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5594 5595 return (u16)speed_cntl; 5596 } 5597 5598 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5599 struct radeon_ps *radeon_new_state, 5600 struct radeon_ps *radeon_current_state) 5601 { 5602 struct si_power_info *si_pi = si_get_pi(rdev); 5603 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5604 enum radeon_pcie_gen current_link_speed; 5605 5606 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5607 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5608 else 5609 current_link_speed = si_pi->force_pcie_gen; 5610 5611 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5612 si_pi->pspp_notify_required = false; 5613 if (target_link_speed > current_link_speed) { 5614 switch (target_link_speed) { 5615 #if defined(CONFIG_ACPI) 5616 case RADEON_PCIE_GEN3: 5617 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5618 break; 5619 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5620 if (current_link_speed == RADEON_PCIE_GEN2) 5621 break; 5622 case RADEON_PCIE_GEN2: 5623 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5624 break; 5625 #endif 5626 default: 5627 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5628 break; 5629 } 5630 } else { 5631 if (target_link_speed < current_link_speed) 5632 si_pi->pspp_notify_required = true; 5633 } 5634 } 5635 5636 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5637 struct radeon_ps *radeon_new_state, 5638 struct radeon_ps *radeon_current_state) 5639 { 5640 struct si_power_info *si_pi = si_get_pi(rdev); 5641 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5642 u8 request; 5643 5644 if (si_pi->pspp_notify_required) { 5645 if (target_link_speed == RADEON_PCIE_GEN3) 5646 request = PCIE_PERF_REQ_PECI_GEN3; 5647 else if (target_link_speed == RADEON_PCIE_GEN2) 5648 request = PCIE_PERF_REQ_PECI_GEN2; 5649 else 5650 request = PCIE_PERF_REQ_PECI_GEN1; 5651 5652 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5653 (si_get_current_pcie_speed(rdev) > 0)) 5654 return; 5655 5656 #if defined(CONFIG_ACPI) 5657 radeon_acpi_pcie_performance_request(rdev, request, false); 5658 #endif 5659 } 5660 } 5661 5662 #if 0 5663 static int si_ds_request(struct radeon_device *rdev, 5664 bool ds_status_on, u32 count_write) 5665 { 5666 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5667 5668 if (eg_pi->sclk_deep_sleep) { 5669 if (ds_status_on) 5670 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5671 PPSMC_Result_OK) ? 5672 0 : -EINVAL; 5673 else 5674 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5675 PPSMC_Result_OK) ? 0 : -EINVAL; 5676 } 5677 return 0; 5678 } 5679 #endif 5680 5681 static void si_set_max_cu_value(struct radeon_device *rdev) 5682 { 5683 struct si_power_info *si_pi = si_get_pi(rdev); 5684 5685 if (rdev->family == CHIP_VERDE) { 5686 switch (rdev->pdev->device) { 5687 case 0x6820: 5688 case 0x6825: 5689 case 0x6821: 5690 case 0x6823: 5691 case 0x6827: 5692 si_pi->max_cu = 10; 5693 break; 5694 case 0x682D: 5695 case 0x6824: 5696 case 0x682F: 5697 case 0x6826: 5698 si_pi->max_cu = 8; 5699 break; 5700 case 0x6828: 5701 case 0x6830: 5702 case 0x6831: 5703 case 0x6838: 5704 case 0x6839: 5705 case 0x683D: 5706 si_pi->max_cu = 10; 5707 break; 5708 case 0x683B: 5709 case 0x683F: 5710 case 0x6829: 5711 si_pi->max_cu = 8; 5712 break; 5713 default: 5714 si_pi->max_cu = 0; 5715 break; 5716 } 5717 } else { 5718 si_pi->max_cu = 0; 5719 } 5720 } 5721 5722 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5723 struct radeon_clock_voltage_dependency_table *table) 5724 { 5725 u32 i; 5726 int j; 5727 u16 leakage_voltage; 5728 5729 if (table) { 5730 for (i = 0; i < table->count; i++) { 5731 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5732 table->entries[i].v, 5733 &leakage_voltage)) { 5734 case 0: 5735 table->entries[i].v = leakage_voltage; 5736 break; 5737 case -EAGAIN: 5738 return -EINVAL; 5739 case -EINVAL: 5740 default: 5741 break; 5742 } 5743 } 5744 5745 for (j = (table->count - 2); j >= 0; j--) { 5746 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5747 table->entries[j].v : table->entries[j + 1].v; 5748 } 5749 } 5750 return 0; 5751 } 5752 5753 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5754 { 5755 int ret = 0; 5756 5757 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5758 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5759 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5760 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5761 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5762 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5763 return ret; 5764 } 5765 5766 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5767 struct radeon_ps *radeon_new_state, 5768 struct radeon_ps *radeon_current_state) 5769 { 5770 u32 lane_width; 5771 u32 new_lane_width = 5772 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5773 u32 current_lane_width = 5774 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5775 5776 if (new_lane_width != current_lane_width) { 5777 radeon_set_pcie_lanes(rdev, new_lane_width); 5778 lane_width = radeon_get_pcie_lanes(rdev); 5779 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5780 } 5781 } 5782 5783 void si_dpm_setup_asic(struct radeon_device *rdev) 5784 { 5785 int r; 5786 5787 r = si_mc_load_microcode(rdev); 5788 if (r) 5789 DRM_ERROR("Failed to load MC firmware!\n"); 5790 rv770_get_memory_type(rdev); 5791 si_read_clock_registers(rdev); 5792 si_enable_acpi_power_management(rdev); 5793 } 5794 5795 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5796 int min_temp, int max_temp) 5797 { 5798 int low_temp = 0 * 1000; 5799 int high_temp = 255 * 1000; 5800 5801 if (low_temp < min_temp) 5802 low_temp = min_temp; 5803 if (high_temp > max_temp) 5804 high_temp = max_temp; 5805 if (high_temp < low_temp) { 5806 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5807 return -EINVAL; 5808 } 5809 5810 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5811 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5812 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5813 5814 rdev->pm.dpm.thermal.min_temp = low_temp; 5815 rdev->pm.dpm.thermal.max_temp = high_temp; 5816 5817 return 0; 5818 } 5819 5820 int si_dpm_enable(struct radeon_device *rdev) 5821 { 5822 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5823 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5824 struct si_power_info *si_pi = si_get_pi(rdev); 5825 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5826 int ret; 5827 5828 if (si_is_smc_running(rdev)) 5829 return -EINVAL; 5830 if (pi->voltage_control || si_pi->voltage_control_svi2) 5831 si_enable_voltage_control(rdev, true); 5832 if (pi->mvdd_control) 5833 si_get_mvdd_configuration(rdev); 5834 if (pi->voltage_control || si_pi->voltage_control_svi2) { 5835 ret = si_construct_voltage_tables(rdev); 5836 if (ret) { 5837 DRM_ERROR("si_construct_voltage_tables failed\n"); 5838 return ret; 5839 } 5840 } 5841 if (eg_pi->dynamic_ac_timing) { 5842 ret = si_initialize_mc_reg_table(rdev); 5843 if (ret) 5844 eg_pi->dynamic_ac_timing = false; 5845 } 5846 if (pi->dynamic_ss) 5847 si_enable_spread_spectrum(rdev, true); 5848 if (pi->thermal_protection) 5849 si_enable_thermal_protection(rdev, true); 5850 si_setup_bsp(rdev); 5851 si_program_git(rdev); 5852 si_program_tp(rdev); 5853 si_program_tpp(rdev); 5854 si_program_sstp(rdev); 5855 si_enable_display_gap(rdev); 5856 si_program_vc(rdev); 5857 ret = si_upload_firmware(rdev); 5858 if (ret) { 5859 DRM_ERROR("si_upload_firmware failed\n"); 5860 return ret; 5861 } 5862 ret = si_process_firmware_header(rdev); 5863 if (ret) { 5864 DRM_ERROR("si_process_firmware_header failed\n"); 5865 return ret; 5866 } 5867 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5868 if (ret) { 5869 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5870 return ret; 5871 } 5872 ret = si_init_smc_table(rdev); 5873 if (ret) { 5874 DRM_ERROR("si_init_smc_table failed\n"); 5875 return ret; 5876 } 5877 ret = si_init_smc_spll_table(rdev); 5878 if (ret) { 5879 DRM_ERROR("si_init_smc_spll_table failed\n"); 5880 return ret; 5881 } 5882 ret = si_init_arb_table_index(rdev); 5883 if (ret) { 5884 DRM_ERROR("si_init_arb_table_index failed\n"); 5885 return ret; 5886 } 5887 if (eg_pi->dynamic_ac_timing) { 5888 ret = si_populate_mc_reg_table(rdev, boot_ps); 5889 if (ret) { 5890 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5891 return ret; 5892 } 5893 } 5894 ret = si_initialize_smc_cac_tables(rdev); 5895 if (ret) { 5896 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5897 return ret; 5898 } 5899 ret = si_initialize_hardware_cac_manager(rdev); 5900 if (ret) { 5901 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5902 return ret; 5903 } 5904 ret = si_initialize_smc_dte_tables(rdev); 5905 if (ret) { 5906 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5907 return ret; 5908 } 5909 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5910 if (ret) { 5911 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5912 return ret; 5913 } 5914 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5915 if (ret) { 5916 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5917 return ret; 5918 } 5919 si_program_response_times(rdev); 5920 si_program_ds_registers(rdev); 5921 si_dpm_start_smc(rdev); 5922 ret = si_notify_smc_display_change(rdev, false); 5923 if (ret) { 5924 DRM_ERROR("si_notify_smc_display_change failed\n"); 5925 return ret; 5926 } 5927 si_enable_sclk_control(rdev, true); 5928 si_start_dpm(rdev); 5929 5930 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5931 5932 ni_update_current_ps(rdev, boot_ps); 5933 5934 return 0; 5935 } 5936 5937 int si_dpm_late_enable(struct radeon_device *rdev) 5938 { 5939 int ret; 5940 5941 if (rdev->irq.installed && 5942 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5943 PPSMC_Result result; 5944 5945 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5946 if (ret) 5947 return ret; 5948 rdev->irq.dpm_thermal = true; 5949 radeon_irq_set(rdev); 5950 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5951 5952 if (result != PPSMC_Result_OK) 5953 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5954 } 5955 5956 return 0; 5957 } 5958 5959 void si_dpm_disable(struct radeon_device *rdev) 5960 { 5961 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5962 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5963 5964 if (!si_is_smc_running(rdev)) 5965 return; 5966 si_disable_ulv(rdev); 5967 si_clear_vc(rdev); 5968 if (pi->thermal_protection) 5969 si_enable_thermal_protection(rdev, false); 5970 si_enable_power_containment(rdev, boot_ps, false); 5971 si_enable_smc_cac(rdev, boot_ps, false); 5972 si_enable_spread_spectrum(rdev, false); 5973 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5974 si_stop_dpm(rdev); 5975 si_reset_to_default(rdev); 5976 si_dpm_stop_smc(rdev); 5977 si_force_switch_to_arb_f0(rdev); 5978 5979 ni_update_current_ps(rdev, boot_ps); 5980 } 5981 5982 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5983 { 5984 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5985 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5986 struct radeon_ps *new_ps = &requested_ps; 5987 5988 ni_update_requested_ps(rdev, new_ps); 5989 5990 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5991 5992 return 0; 5993 } 5994 5995 static int si_power_control_set_level(struct radeon_device *rdev) 5996 { 5997 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5998 int ret; 5999 6000 ret = si_restrict_performance_levels_before_switch(rdev); 6001 if (ret) 6002 return ret; 6003 ret = si_halt_smc(rdev); 6004 if (ret) 6005 return ret; 6006 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6007 if (ret) 6008 return ret; 6009 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6010 if (ret) 6011 return ret; 6012 ret = si_resume_smc(rdev); 6013 if (ret) 6014 return ret; 6015 ret = si_set_sw_state(rdev); 6016 if (ret) 6017 return ret; 6018 return 0; 6019 } 6020 6021 int si_dpm_set_power_state(struct radeon_device *rdev) 6022 { 6023 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6024 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6025 struct radeon_ps *old_ps = &eg_pi->current_rps; 6026 int ret; 6027 6028 ret = si_disable_ulv(rdev); 6029 if (ret) { 6030 DRM_ERROR("si_disable_ulv failed\n"); 6031 return ret; 6032 } 6033 ret = si_restrict_performance_levels_before_switch(rdev); 6034 if (ret) { 6035 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6036 return ret; 6037 } 6038 if (eg_pi->pcie_performance_request) 6039 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6040 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6041 ret = si_enable_power_containment(rdev, new_ps, false); 6042 if (ret) { 6043 DRM_ERROR("si_enable_power_containment failed\n"); 6044 return ret; 6045 } 6046 ret = si_enable_smc_cac(rdev, new_ps, false); 6047 if (ret) { 6048 DRM_ERROR("si_enable_smc_cac failed\n"); 6049 return ret; 6050 } 6051 ret = si_halt_smc(rdev); 6052 if (ret) { 6053 DRM_ERROR("si_halt_smc failed\n"); 6054 return ret; 6055 } 6056 ret = si_upload_sw_state(rdev, new_ps); 6057 if (ret) { 6058 DRM_ERROR("si_upload_sw_state failed\n"); 6059 return ret; 6060 } 6061 ret = si_upload_smc_data(rdev); 6062 if (ret) { 6063 DRM_ERROR("si_upload_smc_data failed\n"); 6064 return ret; 6065 } 6066 ret = si_upload_ulv_state(rdev); 6067 if (ret) { 6068 DRM_ERROR("si_upload_ulv_state failed\n"); 6069 return ret; 6070 } 6071 if (eg_pi->dynamic_ac_timing) { 6072 ret = si_upload_mc_reg_table(rdev, new_ps); 6073 if (ret) { 6074 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6075 return ret; 6076 } 6077 } 6078 ret = si_program_memory_timing_parameters(rdev, new_ps); 6079 if (ret) { 6080 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6081 return ret; 6082 } 6083 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6084 6085 ret = si_resume_smc(rdev); 6086 if (ret) { 6087 DRM_ERROR("si_resume_smc failed\n"); 6088 return ret; 6089 } 6090 ret = si_set_sw_state(rdev); 6091 if (ret) { 6092 DRM_ERROR("si_set_sw_state failed\n"); 6093 return ret; 6094 } 6095 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6096 if (eg_pi->pcie_performance_request) 6097 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6098 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6099 if (ret) { 6100 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6101 return ret; 6102 } 6103 ret = si_enable_smc_cac(rdev, new_ps, true); 6104 if (ret) { 6105 DRM_ERROR("si_enable_smc_cac failed\n"); 6106 return ret; 6107 } 6108 ret = si_enable_power_containment(rdev, new_ps, true); 6109 if (ret) { 6110 DRM_ERROR("si_enable_power_containment failed\n"); 6111 return ret; 6112 } 6113 6114 ret = si_power_control_set_level(rdev); 6115 if (ret) { 6116 DRM_ERROR("si_power_control_set_level failed\n"); 6117 return ret; 6118 } 6119 6120 return 0; 6121 } 6122 6123 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6124 { 6125 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6126 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6127 6128 ni_update_current_ps(rdev, new_ps); 6129 } 6130 6131 6132 void si_dpm_reset_asic(struct radeon_device *rdev) 6133 { 6134 si_restrict_performance_levels_before_switch(rdev); 6135 si_disable_ulv(rdev); 6136 si_set_boot_state(rdev); 6137 } 6138 6139 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6140 { 6141 si_program_display_gap(rdev); 6142 } 6143 6144 union power_info { 6145 struct _ATOM_POWERPLAY_INFO info; 6146 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6147 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6148 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6149 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6150 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6151 }; 6152 6153 union pplib_clock_info { 6154 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6155 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6156 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6157 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6158 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6159 }; 6160 6161 union pplib_power_state { 6162 struct _ATOM_PPLIB_STATE v1; 6163 struct _ATOM_PPLIB_STATE_V2 v2; 6164 }; 6165 6166 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6167 struct radeon_ps *rps, 6168 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6169 u8 table_rev) 6170 { 6171 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6172 rps->class = le16_to_cpu(non_clock_info->usClassification); 6173 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6174 6175 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6176 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6177 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6178 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6179 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6180 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6181 } else { 6182 rps->vclk = 0; 6183 rps->dclk = 0; 6184 } 6185 6186 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6187 rdev->pm.dpm.boot_ps = rps; 6188 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6189 rdev->pm.dpm.uvd_ps = rps; 6190 } 6191 6192 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6193 struct radeon_ps *rps, int index, 6194 union pplib_clock_info *clock_info) 6195 { 6196 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6197 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6198 struct si_power_info *si_pi = si_get_pi(rdev); 6199 struct ni_ps *ps = ni_get_ps(rps); 6200 u16 leakage_voltage; 6201 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6202 int ret; 6203 6204 ps->performance_level_count = index + 1; 6205 6206 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6207 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6208 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6209 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6210 6211 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6212 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6213 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6214 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6215 si_pi->sys_pcie_mask, 6216 si_pi->boot_pcie_gen, 6217 clock_info->si.ucPCIEGen); 6218 6219 /* patch up vddc if necessary */ 6220 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6221 &leakage_voltage); 6222 if (ret == 0) 6223 pl->vddc = leakage_voltage; 6224 6225 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6226 pi->acpi_vddc = pl->vddc; 6227 eg_pi->acpi_vddci = pl->vddci; 6228 si_pi->acpi_pcie_gen = pl->pcie_gen; 6229 } 6230 6231 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6232 index == 0) { 6233 /* XXX disable for A0 tahiti */ 6234 si_pi->ulv.supported = true; 6235 si_pi->ulv.pl = *pl; 6236 si_pi->ulv.one_pcie_lane_in_ulv = false; 6237 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6238 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6239 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6240 } 6241 6242 if (pi->min_vddc_in_table > pl->vddc) 6243 pi->min_vddc_in_table = pl->vddc; 6244 6245 if (pi->max_vddc_in_table < pl->vddc) 6246 pi->max_vddc_in_table = pl->vddc; 6247 6248 /* patch up boot state */ 6249 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6250 u16 vddc, vddci, mvdd; 6251 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6252 pl->mclk = rdev->clock.default_mclk; 6253 pl->sclk = rdev->clock.default_sclk; 6254 pl->vddc = vddc; 6255 pl->vddci = vddci; 6256 si_pi->mvdd_bootup_value = mvdd; 6257 } 6258 6259 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6260 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6265 } 6266 } 6267 6268 static int si_parse_power_table(struct radeon_device *rdev) 6269 { 6270 struct radeon_mode_info *mode_info = &rdev->mode_info; 6271 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6272 union pplib_power_state *power_state; 6273 int i, j, k, non_clock_array_index, clock_array_index; 6274 union pplib_clock_info *clock_info; 6275 struct _StateArray *state_array; 6276 struct _ClockInfoArray *clock_info_array; 6277 struct _NonClockInfoArray *non_clock_info_array; 6278 union power_info *power_info; 6279 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6280 u16 data_offset; 6281 u8 frev, crev; 6282 u8 *power_state_offset; 6283 struct ni_ps *ps; 6284 6285 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6286 &frev, &crev, &data_offset)) 6287 return -EINVAL; 6288 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6289 6290 state_array = (struct _StateArray *) 6291 (mode_info->atom_context->bios + data_offset + 6292 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6293 clock_info_array = (struct _ClockInfoArray *) 6294 (mode_info->atom_context->bios + data_offset + 6295 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6296 non_clock_info_array = (struct _NonClockInfoArray *) 6297 (mode_info->atom_context->bios + data_offset + 6298 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6299 6300 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6301 state_array->ucNumEntries, GFP_KERNEL); 6302 if (!rdev->pm.dpm.ps) 6303 return -ENOMEM; 6304 power_state_offset = (u8 *)state_array->states; 6305 for (i = 0; i < state_array->ucNumEntries; i++) { 6306 u8 *idx; 6307 power_state = (union pplib_power_state *)power_state_offset; 6308 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6309 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6310 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6311 if (!rdev->pm.power_state[i].clock_info) 6312 return -EINVAL; 6313 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6314 if (ps == NULL) { 6315 kfree(rdev->pm.dpm.ps); 6316 return -ENOMEM; 6317 } 6318 rdev->pm.dpm.ps[i].ps_priv = ps; 6319 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6320 non_clock_info, 6321 non_clock_info_array->ucEntrySize); 6322 k = 0; 6323 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6324 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6325 clock_array_index = idx[j]; 6326 if (clock_array_index >= clock_info_array->ucNumEntries) 6327 continue; 6328 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6329 break; 6330 clock_info = (union pplib_clock_info *) 6331 ((u8 *)&clock_info_array->clockInfo[0] + 6332 (clock_array_index * clock_info_array->ucEntrySize)); 6333 si_parse_pplib_clock_info(rdev, 6334 &rdev->pm.dpm.ps[i], k, 6335 clock_info); 6336 k++; 6337 } 6338 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6339 } 6340 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6341 return 0; 6342 } 6343 6344 int si_dpm_init(struct radeon_device *rdev) 6345 { 6346 struct rv7xx_power_info *pi; 6347 struct evergreen_power_info *eg_pi; 6348 struct ni_power_info *ni_pi; 6349 struct si_power_info *si_pi; 6350 struct atom_clock_dividers dividers; 6351 int ret; 6352 u32 mask; 6353 6354 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6355 if (si_pi == NULL) 6356 return -ENOMEM; 6357 rdev->pm.dpm.priv = si_pi; 6358 ni_pi = &si_pi->ni; 6359 eg_pi = &ni_pi->eg; 6360 pi = &eg_pi->rv7xx; 6361 6362 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6363 if (ret) 6364 si_pi->sys_pcie_mask = 0; 6365 else 6366 si_pi->sys_pcie_mask = mask; 6367 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6368 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6369 6370 si_set_max_cu_value(rdev); 6371 6372 rv770_get_max_vddc(rdev); 6373 si_get_leakage_vddc(rdev); 6374 si_patch_dependency_tables_based_on_leakage(rdev); 6375 6376 pi->acpi_vddc = 0; 6377 eg_pi->acpi_vddci = 0; 6378 pi->min_vddc_in_table = 0; 6379 pi->max_vddc_in_table = 0; 6380 6381 ret = r600_get_platform_caps(rdev); 6382 if (ret) 6383 return ret; 6384 6385 ret = si_parse_power_table(rdev); 6386 if (ret) 6387 return ret; 6388 ret = r600_parse_extended_power_table(rdev); 6389 if (ret) 6390 return ret; 6391 6392 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6393 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6394 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6395 r600_free_extended_power_table(rdev); 6396 return -ENOMEM; 6397 } 6398 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6399 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6400 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6401 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6402 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6403 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6404 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6405 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6406 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6407 6408 if (rdev->pm.dpm.voltage_response_time == 0) 6409 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6410 if (rdev->pm.dpm.backbias_response_time == 0) 6411 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6412 6413 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6414 0, false, ÷rs); 6415 if (ret) 6416 pi->ref_div = dividers.ref_div + 1; 6417 else 6418 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6419 6420 eg_pi->smu_uvd_hs = false; 6421 6422 pi->mclk_strobe_mode_threshold = 40000; 6423 if (si_is_special_1gb_platform(rdev)) 6424 pi->mclk_stutter_mode_threshold = 0; 6425 else 6426 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6427 pi->mclk_edc_enable_threshold = 40000; 6428 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6429 6430 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6431 6432 pi->voltage_control = 6433 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6434 VOLTAGE_OBJ_GPIO_LUT); 6435 if (!pi->voltage_control) { 6436 si_pi->voltage_control_svi2 = 6437 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6438 VOLTAGE_OBJ_SVID2); 6439 if (si_pi->voltage_control_svi2) 6440 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6441 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6442 } 6443 6444 pi->mvdd_control = 6445 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6446 VOLTAGE_OBJ_GPIO_LUT); 6447 6448 eg_pi->vddci_control = 6449 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6450 VOLTAGE_OBJ_GPIO_LUT); 6451 if (!eg_pi->vddci_control) 6452 si_pi->vddci_control_svi2 = 6453 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6454 VOLTAGE_OBJ_SVID2); 6455 6456 si_pi->vddc_phase_shed_control = 6457 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6458 VOLTAGE_OBJ_PHASE_LUT); 6459 6460 rv770_get_engine_memory_ss(rdev); 6461 6462 pi->asi = RV770_ASI_DFLT; 6463 pi->pasi = CYPRESS_HASI_DFLT; 6464 pi->vrc = SISLANDS_VRC_DFLT; 6465 6466 pi->gfx_clock_gating = true; 6467 6468 eg_pi->sclk_deep_sleep = true; 6469 si_pi->sclk_deep_sleep_above_low = false; 6470 6471 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6472 pi->thermal_protection = true; 6473 else 6474 pi->thermal_protection = false; 6475 6476 eg_pi->dynamic_ac_timing = true; 6477 6478 eg_pi->light_sleep = true; 6479 #if defined(CONFIG_ACPI) 6480 eg_pi->pcie_performance_request = 6481 radeon_acpi_is_pcie_performance_request_supported(rdev); 6482 #else 6483 eg_pi->pcie_performance_request = false; 6484 #endif 6485 6486 si_pi->sram_end = SMC_RAM_END; 6487 6488 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6489 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6490 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6491 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6492 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6493 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6494 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6495 6496 si_initialize_powertune_defaults(rdev); 6497 6498 /* make sure dc limits are valid */ 6499 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6500 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6501 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6502 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6503 6504 return 0; 6505 } 6506 6507 void si_dpm_fini(struct radeon_device *rdev) 6508 { 6509 int i; 6510 6511 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6512 kfree(rdev->pm.dpm.ps[i].ps_priv); 6513 } 6514 kfree(rdev->pm.dpm.ps); 6515 kfree(rdev->pm.dpm.priv); 6516 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6517 r600_free_extended_power_table(rdev); 6518 } 6519 6520 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6521 struct seq_file *m) 6522 { 6523 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6524 struct radeon_ps *rps = &eg_pi->current_rps; 6525 struct ni_ps *ps = ni_get_ps(rps); 6526 struct rv7xx_pl *pl; 6527 u32 current_index = 6528 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6529 CURRENT_STATE_INDEX_SHIFT; 6530 6531 if (current_index >= ps->performance_level_count) { 6532 seq_printf(m, "invalid dpm profile %d\n", current_index); 6533 } else { 6534 pl = &ps->performance_levels[current_index]; 6535 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6536 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6537 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6538 } 6539 } 6540