1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include <drm/radeon_drm.h> 32 #include "sid.h" 33 #include "atom.h" 34 #include "si_blit_shaders.h" 35 36 #define SI_PFP_UCODE_SIZE 2144 37 #define SI_PM4_UCODE_SIZE 2144 38 #define SI_CE_UCODE_SIZE 2144 39 #define SI_RLC_UCODE_SIZE 2048 40 #define SI_MC_UCODE_SIZE 7769 41 #define OLAND_MC_UCODE_SIZE 7863 42 43 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); 44 MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 45 MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 46 MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 47 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 48 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 49 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 50 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 51 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 52 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 53 MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 54 MODULE_FIRMWARE("radeon/VERDE_me.bin"); 55 MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 56 MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 57 MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 58 MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 59 MODULE_FIRMWARE("radeon/OLAND_me.bin"); 60 MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 61 MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 62 MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 63 64 extern int r600_ih_ring_alloc(struct radeon_device *rdev); 65 extern void r600_ih_ring_fini(struct radeon_device *rdev); 66 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 67 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 68 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 69 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 70 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 71 extern bool evergreen_is_display_hung(struct radeon_device *rdev); 72 73 #define PCIE_BUS_CLK 10000 74 #define TCLK (PCIE_BUS_CLK / 10) 75 76 /** 77 * si_get_xclk - get the xclk 78 * 79 * @rdev: radeon_device pointer 80 * 81 * Returns the reference clock used by the gfx engine 82 * (SI). 83 */ 84 u32 si_get_xclk(struct radeon_device *rdev) 85 { 86 u32 reference_clock = rdev->clock.spll.reference_freq; 87 u32 tmp; 88 89 tmp = RREG32(CG_CLKPIN_CNTL_2); 90 if (tmp & MUX_TCLK_TO_XCLK) 91 return TCLK; 92 93 tmp = RREG32(CG_CLKPIN_CNTL); 94 if (tmp & XTALIN_DIVIDE) 95 return reference_clock / 4; 96 97 return reference_clock; 98 } 99 100 /* get temperature in millidegrees */ 101 int si_get_temp(struct radeon_device *rdev) 102 { 103 u32 temp; 104 int actual_temp = 0; 105 106 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 107 CTF_TEMP_SHIFT; 108 109 if (temp & 0x200) 110 actual_temp = 255; 111 else 112 actual_temp = temp & 0x1ff; 113 114 actual_temp = (actual_temp * 1000); 115 116 return actual_temp; 117 } 118 119 #define TAHITI_IO_MC_REGS_SIZE 36 120 121 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 122 {0x0000006f, 0x03044000}, 123 {0x00000070, 0x0480c018}, 124 {0x00000071, 0x00000040}, 125 {0x00000072, 0x01000000}, 126 {0x00000074, 0x000000ff}, 127 {0x00000075, 0x00143400}, 128 {0x00000076, 0x08ec0800}, 129 {0x00000077, 0x040000cc}, 130 {0x00000079, 0x00000000}, 131 {0x0000007a, 0x21000409}, 132 {0x0000007c, 0x00000000}, 133 {0x0000007d, 0xe8000000}, 134 {0x0000007e, 0x044408a8}, 135 {0x0000007f, 0x00000003}, 136 {0x00000080, 0x00000000}, 137 {0x00000081, 0x01000000}, 138 {0x00000082, 0x02000000}, 139 {0x00000083, 0x00000000}, 140 {0x00000084, 0xe3f3e4f4}, 141 {0x00000085, 0x00052024}, 142 {0x00000087, 0x00000000}, 143 {0x00000088, 0x66036603}, 144 {0x00000089, 0x01000000}, 145 {0x0000008b, 0x1c0a0000}, 146 {0x0000008c, 0xff010000}, 147 {0x0000008e, 0xffffefff}, 148 {0x0000008f, 0xfff3efff}, 149 {0x00000090, 0xfff3efbf}, 150 {0x00000094, 0x00101101}, 151 {0x00000095, 0x00000fff}, 152 {0x00000096, 0x00116fff}, 153 {0x00000097, 0x60010000}, 154 {0x00000098, 0x10010000}, 155 {0x00000099, 0x00006000}, 156 {0x0000009a, 0x00001000}, 157 {0x0000009f, 0x00a77400} 158 }; 159 160 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 161 {0x0000006f, 0x03044000}, 162 {0x00000070, 0x0480c018}, 163 {0x00000071, 0x00000040}, 164 {0x00000072, 0x01000000}, 165 {0x00000074, 0x000000ff}, 166 {0x00000075, 0x00143400}, 167 {0x00000076, 0x08ec0800}, 168 {0x00000077, 0x040000cc}, 169 {0x00000079, 0x00000000}, 170 {0x0000007a, 0x21000409}, 171 {0x0000007c, 0x00000000}, 172 {0x0000007d, 0xe8000000}, 173 {0x0000007e, 0x044408a8}, 174 {0x0000007f, 0x00000003}, 175 {0x00000080, 0x00000000}, 176 {0x00000081, 0x01000000}, 177 {0x00000082, 0x02000000}, 178 {0x00000083, 0x00000000}, 179 {0x00000084, 0xe3f3e4f4}, 180 {0x00000085, 0x00052024}, 181 {0x00000087, 0x00000000}, 182 {0x00000088, 0x66036603}, 183 {0x00000089, 0x01000000}, 184 {0x0000008b, 0x1c0a0000}, 185 {0x0000008c, 0xff010000}, 186 {0x0000008e, 0xffffefff}, 187 {0x0000008f, 0xfff3efff}, 188 {0x00000090, 0xfff3efbf}, 189 {0x00000094, 0x00101101}, 190 {0x00000095, 0x00000fff}, 191 {0x00000096, 0x00116fff}, 192 {0x00000097, 0x60010000}, 193 {0x00000098, 0x10010000}, 194 {0x00000099, 0x00006000}, 195 {0x0000009a, 0x00001000}, 196 {0x0000009f, 0x00a47400} 197 }; 198 199 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 200 {0x0000006f, 0x03044000}, 201 {0x00000070, 0x0480c018}, 202 {0x00000071, 0x00000040}, 203 {0x00000072, 0x01000000}, 204 {0x00000074, 0x000000ff}, 205 {0x00000075, 0x00143400}, 206 {0x00000076, 0x08ec0800}, 207 {0x00000077, 0x040000cc}, 208 {0x00000079, 0x00000000}, 209 {0x0000007a, 0x21000409}, 210 {0x0000007c, 0x00000000}, 211 {0x0000007d, 0xe8000000}, 212 {0x0000007e, 0x044408a8}, 213 {0x0000007f, 0x00000003}, 214 {0x00000080, 0x00000000}, 215 {0x00000081, 0x01000000}, 216 {0x00000082, 0x02000000}, 217 {0x00000083, 0x00000000}, 218 {0x00000084, 0xe3f3e4f4}, 219 {0x00000085, 0x00052024}, 220 {0x00000087, 0x00000000}, 221 {0x00000088, 0x66036603}, 222 {0x00000089, 0x01000000}, 223 {0x0000008b, 0x1c0a0000}, 224 {0x0000008c, 0xff010000}, 225 {0x0000008e, 0xffffefff}, 226 {0x0000008f, 0xfff3efff}, 227 {0x00000090, 0xfff3efbf}, 228 {0x00000094, 0x00101101}, 229 {0x00000095, 0x00000fff}, 230 {0x00000096, 0x00116fff}, 231 {0x00000097, 0x60010000}, 232 {0x00000098, 0x10010000}, 233 {0x00000099, 0x00006000}, 234 {0x0000009a, 0x00001000}, 235 {0x0000009f, 0x00a37400} 236 }; 237 238 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 239 {0x0000006f, 0x03044000}, 240 {0x00000070, 0x0480c018}, 241 {0x00000071, 0x00000040}, 242 {0x00000072, 0x01000000}, 243 {0x00000074, 0x000000ff}, 244 {0x00000075, 0x00143400}, 245 {0x00000076, 0x08ec0800}, 246 {0x00000077, 0x040000cc}, 247 {0x00000079, 0x00000000}, 248 {0x0000007a, 0x21000409}, 249 {0x0000007c, 0x00000000}, 250 {0x0000007d, 0xe8000000}, 251 {0x0000007e, 0x044408a8}, 252 {0x0000007f, 0x00000003}, 253 {0x00000080, 0x00000000}, 254 {0x00000081, 0x01000000}, 255 {0x00000082, 0x02000000}, 256 {0x00000083, 0x00000000}, 257 {0x00000084, 0xe3f3e4f4}, 258 {0x00000085, 0x00052024}, 259 {0x00000087, 0x00000000}, 260 {0x00000088, 0x66036603}, 261 {0x00000089, 0x01000000}, 262 {0x0000008b, 0x1c0a0000}, 263 {0x0000008c, 0xff010000}, 264 {0x0000008e, 0xffffefff}, 265 {0x0000008f, 0xfff3efff}, 266 {0x00000090, 0xfff3efbf}, 267 {0x00000094, 0x00101101}, 268 {0x00000095, 0x00000fff}, 269 {0x00000096, 0x00116fff}, 270 {0x00000097, 0x60010000}, 271 {0x00000098, 0x10010000}, 272 {0x00000099, 0x00006000}, 273 {0x0000009a, 0x00001000}, 274 {0x0000009f, 0x00a17730} 275 }; 276 277 /* ucode loading */ 278 static int si_mc_load_microcode(struct radeon_device *rdev) 279 { 280 const __be32 *fw_data; 281 u32 running, blackout = 0; 282 u32 *io_mc_regs; 283 int i, ucode_size, regs_size; 284 285 if (!rdev->mc_fw) 286 return -EINVAL; 287 288 switch (rdev->family) { 289 case CHIP_TAHITI: 290 io_mc_regs = (u32 *)&tahiti_io_mc_regs; 291 ucode_size = SI_MC_UCODE_SIZE; 292 regs_size = TAHITI_IO_MC_REGS_SIZE; 293 break; 294 case CHIP_PITCAIRN: 295 io_mc_regs = (u32 *)&pitcairn_io_mc_regs; 296 ucode_size = SI_MC_UCODE_SIZE; 297 regs_size = TAHITI_IO_MC_REGS_SIZE; 298 break; 299 case CHIP_VERDE: 300 default: 301 io_mc_regs = (u32 *)&verde_io_mc_regs; 302 ucode_size = SI_MC_UCODE_SIZE; 303 regs_size = TAHITI_IO_MC_REGS_SIZE; 304 break; 305 case CHIP_OLAND: 306 io_mc_regs = (u32 *)&oland_io_mc_regs; 307 ucode_size = OLAND_MC_UCODE_SIZE; 308 regs_size = TAHITI_IO_MC_REGS_SIZE; 309 break; 310 } 311 312 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 313 314 if (running == 0) { 315 if (running) { 316 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 317 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 318 } 319 320 /* reset the engine and set to writable */ 321 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 322 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 323 324 /* load mc io regs */ 325 for (i = 0; i < regs_size; i++) { 326 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 327 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 328 } 329 /* load the MC ucode */ 330 fw_data = (const __be32 *)rdev->mc_fw->data; 331 for (i = 0; i < ucode_size; i++) 332 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 333 334 /* put the engine back into the active state */ 335 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 336 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 337 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 338 339 /* wait for training to complete */ 340 for (i = 0; i < rdev->usec_timeout; i++) { 341 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 342 break; 343 udelay(1); 344 } 345 for (i = 0; i < rdev->usec_timeout; i++) { 346 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 347 break; 348 udelay(1); 349 } 350 351 if (running) 352 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 353 } 354 355 return 0; 356 } 357 358 static int si_init_microcode(struct radeon_device *rdev) 359 { 360 struct platform_device *pdev; 361 const char *chip_name; 362 const char *rlc_chip_name; 363 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 364 char fw_name[30]; 365 int err; 366 367 DRM_DEBUG("\n"); 368 369 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 370 err = IS_ERR(pdev); 371 if (err) { 372 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 373 return -EINVAL; 374 } 375 376 switch (rdev->family) { 377 case CHIP_TAHITI: 378 chip_name = "TAHITI"; 379 rlc_chip_name = "TAHITI"; 380 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 381 me_req_size = SI_PM4_UCODE_SIZE * 4; 382 ce_req_size = SI_CE_UCODE_SIZE * 4; 383 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 384 mc_req_size = SI_MC_UCODE_SIZE * 4; 385 break; 386 case CHIP_PITCAIRN: 387 chip_name = "PITCAIRN"; 388 rlc_chip_name = "PITCAIRN"; 389 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 390 me_req_size = SI_PM4_UCODE_SIZE * 4; 391 ce_req_size = SI_CE_UCODE_SIZE * 4; 392 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 393 mc_req_size = SI_MC_UCODE_SIZE * 4; 394 break; 395 case CHIP_VERDE: 396 chip_name = "VERDE"; 397 rlc_chip_name = "VERDE"; 398 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 399 me_req_size = SI_PM4_UCODE_SIZE * 4; 400 ce_req_size = SI_CE_UCODE_SIZE * 4; 401 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 402 mc_req_size = SI_MC_UCODE_SIZE * 4; 403 break; 404 case CHIP_OLAND: 405 chip_name = "OLAND"; 406 rlc_chip_name = "OLAND"; 407 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 408 me_req_size = SI_PM4_UCODE_SIZE * 4; 409 ce_req_size = SI_CE_UCODE_SIZE * 4; 410 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 411 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 412 break; 413 default: BUG(); 414 } 415 416 DRM_INFO("Loading %s Microcode\n", chip_name); 417 418 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 419 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 420 if (err) 421 goto out; 422 if (rdev->pfp_fw->size != pfp_req_size) { 423 printk(KERN_ERR 424 "si_cp: Bogus length %zu in firmware \"%s\"\n", 425 rdev->pfp_fw->size, fw_name); 426 err = -EINVAL; 427 goto out; 428 } 429 430 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 431 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 432 if (err) 433 goto out; 434 if (rdev->me_fw->size != me_req_size) { 435 printk(KERN_ERR 436 "si_cp: Bogus length %zu in firmware \"%s\"\n", 437 rdev->me_fw->size, fw_name); 438 err = -EINVAL; 439 } 440 441 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 442 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev); 443 if (err) 444 goto out; 445 if (rdev->ce_fw->size != ce_req_size) { 446 printk(KERN_ERR 447 "si_cp: Bogus length %zu in firmware \"%s\"\n", 448 rdev->ce_fw->size, fw_name); 449 err = -EINVAL; 450 } 451 452 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 453 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 454 if (err) 455 goto out; 456 if (rdev->rlc_fw->size != rlc_req_size) { 457 printk(KERN_ERR 458 "si_rlc: Bogus length %zu in firmware \"%s\"\n", 459 rdev->rlc_fw->size, fw_name); 460 err = -EINVAL; 461 } 462 463 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 464 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); 465 if (err) 466 goto out; 467 if (rdev->mc_fw->size != mc_req_size) { 468 printk(KERN_ERR 469 "si_mc: Bogus length %zu in firmware \"%s\"\n", 470 rdev->mc_fw->size, fw_name); 471 err = -EINVAL; 472 } 473 474 out: 475 platform_device_unregister(pdev); 476 477 if (err) { 478 if (err != -EINVAL) 479 printk(KERN_ERR 480 "si_cp: Failed to load firmware \"%s\"\n", 481 fw_name); 482 release_firmware(rdev->pfp_fw); 483 rdev->pfp_fw = NULL; 484 release_firmware(rdev->me_fw); 485 rdev->me_fw = NULL; 486 release_firmware(rdev->ce_fw); 487 rdev->ce_fw = NULL; 488 release_firmware(rdev->rlc_fw); 489 rdev->rlc_fw = NULL; 490 release_firmware(rdev->mc_fw); 491 rdev->mc_fw = NULL; 492 } 493 return err; 494 } 495 496 /* watermark setup */ 497 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev, 498 struct radeon_crtc *radeon_crtc, 499 struct drm_display_mode *mode, 500 struct drm_display_mode *other_mode) 501 { 502 u32 tmp; 503 /* 504 * Line Buffer Setup 505 * There are 3 line buffers, each one shared by 2 display controllers. 506 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 507 * the display controllers. The paritioning is done via one of four 508 * preset allocations specified in bits 21:20: 509 * 0 - half lb 510 * 2 - whole lb, other crtc must be disabled 511 */ 512 /* this can get tricky if we have two large displays on a paired group 513 * of crtcs. Ideally for multiple large displays we'd assign them to 514 * non-linked crtcs for maximum line buffer allocation. 515 */ 516 if (radeon_crtc->base.enabled && mode) { 517 if (other_mode) 518 tmp = 0; /* 1/2 */ 519 else 520 tmp = 2; /* whole */ 521 } else 522 tmp = 0; 523 524 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, 525 DC_LB_MEMORY_CONFIG(tmp)); 526 527 if (radeon_crtc->base.enabled && mode) { 528 switch (tmp) { 529 case 0: 530 default: 531 return 4096 * 2; 532 case 2: 533 return 8192 * 2; 534 } 535 } 536 537 /* controller not enabled, so no lb used */ 538 return 0; 539 } 540 541 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev) 542 { 543 u32 tmp = RREG32(MC_SHARED_CHMAP); 544 545 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 546 case 0: 547 default: 548 return 1; 549 case 1: 550 return 2; 551 case 2: 552 return 4; 553 case 3: 554 return 8; 555 case 4: 556 return 3; 557 case 5: 558 return 6; 559 case 6: 560 return 10; 561 case 7: 562 return 12; 563 case 8: 564 return 16; 565 } 566 } 567 568 struct dce6_wm_params { 569 u32 dram_channels; /* number of dram channels */ 570 u32 yclk; /* bandwidth per dram data pin in kHz */ 571 u32 sclk; /* engine clock in kHz */ 572 u32 disp_clk; /* display clock in kHz */ 573 u32 src_width; /* viewport width */ 574 u32 active_time; /* active display time in ns */ 575 u32 blank_time; /* blank time in ns */ 576 bool interlaced; /* mode is interlaced */ 577 fixed20_12 vsc; /* vertical scale ratio */ 578 u32 num_heads; /* number of active crtcs */ 579 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 580 u32 lb_size; /* line buffer allocated to pipe */ 581 u32 vtaps; /* vertical scaler taps */ 582 }; 583 584 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) 585 { 586 /* Calculate raw DRAM Bandwidth */ 587 fixed20_12 dram_efficiency; /* 0.7 */ 588 fixed20_12 yclk, dram_channels, bandwidth; 589 fixed20_12 a; 590 591 a.full = dfixed_const(1000); 592 yclk.full = dfixed_const(wm->yclk); 593 yclk.full = dfixed_div(yclk, a); 594 dram_channels.full = dfixed_const(wm->dram_channels * 4); 595 a.full = dfixed_const(10); 596 dram_efficiency.full = dfixed_const(7); 597 dram_efficiency.full = dfixed_div(dram_efficiency, a); 598 bandwidth.full = dfixed_mul(dram_channels, yclk); 599 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 600 601 return dfixed_trunc(bandwidth); 602 } 603 604 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) 605 { 606 /* Calculate DRAM Bandwidth and the part allocated to display. */ 607 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 608 fixed20_12 yclk, dram_channels, bandwidth; 609 fixed20_12 a; 610 611 a.full = dfixed_const(1000); 612 yclk.full = dfixed_const(wm->yclk); 613 yclk.full = dfixed_div(yclk, a); 614 dram_channels.full = dfixed_const(wm->dram_channels * 4); 615 a.full = dfixed_const(10); 616 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 617 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 618 bandwidth.full = dfixed_mul(dram_channels, yclk); 619 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 620 621 return dfixed_trunc(bandwidth); 622 } 623 624 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) 625 { 626 /* Calculate the display Data return Bandwidth */ 627 fixed20_12 return_efficiency; /* 0.8 */ 628 fixed20_12 sclk, bandwidth; 629 fixed20_12 a; 630 631 a.full = dfixed_const(1000); 632 sclk.full = dfixed_const(wm->sclk); 633 sclk.full = dfixed_div(sclk, a); 634 a.full = dfixed_const(10); 635 return_efficiency.full = dfixed_const(8); 636 return_efficiency.full = dfixed_div(return_efficiency, a); 637 a.full = dfixed_const(32); 638 bandwidth.full = dfixed_mul(a, sclk); 639 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 640 641 return dfixed_trunc(bandwidth); 642 } 643 644 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) 645 { 646 return 32; 647 } 648 649 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) 650 { 651 /* Calculate the DMIF Request Bandwidth */ 652 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 653 fixed20_12 disp_clk, sclk, bandwidth; 654 fixed20_12 a, b1, b2; 655 u32 min_bandwidth; 656 657 a.full = dfixed_const(1000); 658 disp_clk.full = dfixed_const(wm->disp_clk); 659 disp_clk.full = dfixed_div(disp_clk, a); 660 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); 661 b1.full = dfixed_mul(a, disp_clk); 662 663 a.full = dfixed_const(1000); 664 sclk.full = dfixed_const(wm->sclk); 665 sclk.full = dfixed_div(sclk, a); 666 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); 667 b2.full = dfixed_mul(a, sclk); 668 669 a.full = dfixed_const(10); 670 disp_clk_request_efficiency.full = dfixed_const(8); 671 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 672 673 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2)); 674 675 a.full = dfixed_const(min_bandwidth); 676 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency); 677 678 return dfixed_trunc(bandwidth); 679 } 680 681 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) 682 { 683 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 684 u32 dram_bandwidth = dce6_dram_bandwidth(wm); 685 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); 686 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); 687 688 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 689 } 690 691 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) 692 { 693 /* Calculate the display mode Average Bandwidth 694 * DisplayMode should contain the source and destination dimensions, 695 * timing, etc. 696 */ 697 fixed20_12 bpp; 698 fixed20_12 line_time; 699 fixed20_12 src_width; 700 fixed20_12 bandwidth; 701 fixed20_12 a; 702 703 a.full = dfixed_const(1000); 704 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 705 line_time.full = dfixed_div(line_time, a); 706 bpp.full = dfixed_const(wm->bytes_per_pixel); 707 src_width.full = dfixed_const(wm->src_width); 708 bandwidth.full = dfixed_mul(src_width, bpp); 709 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 710 bandwidth.full = dfixed_div(bandwidth, line_time); 711 712 return dfixed_trunc(bandwidth); 713 } 714 715 static u32 dce6_latency_watermark(struct dce6_wm_params *wm) 716 { 717 /* First calcualte the latency in ns */ 718 u32 mc_latency = 2000; /* 2000 ns. */ 719 u32 available_bandwidth = dce6_available_bandwidth(wm); 720 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 721 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 722 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 723 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 724 (wm->num_heads * cursor_line_pair_return_time); 725 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 726 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 727 u32 tmp, dmif_size = 12288; 728 fixed20_12 a, b, c; 729 730 if (wm->num_heads == 0) 731 return 0; 732 733 a.full = dfixed_const(2); 734 b.full = dfixed_const(1); 735 if ((wm->vsc.full > a.full) || 736 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 737 (wm->vtaps >= 5) || 738 ((wm->vsc.full >= a.full) && wm->interlaced)) 739 max_src_lines_per_dst_line = 4; 740 else 741 max_src_lines_per_dst_line = 2; 742 743 a.full = dfixed_const(available_bandwidth); 744 b.full = dfixed_const(wm->num_heads); 745 a.full = dfixed_div(a, b); 746 747 b.full = dfixed_const(mc_latency + 512); 748 c.full = dfixed_const(wm->disp_clk); 749 b.full = dfixed_div(b, c); 750 751 c.full = dfixed_const(dmif_size); 752 b.full = dfixed_div(c, b); 753 754 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 755 756 b.full = dfixed_const(1000); 757 c.full = dfixed_const(wm->disp_clk); 758 b.full = dfixed_div(c, b); 759 c.full = dfixed_const(wm->bytes_per_pixel); 760 b.full = dfixed_mul(b, c); 761 762 lb_fill_bw = min(tmp, dfixed_trunc(b)); 763 764 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 765 b.full = dfixed_const(1000); 766 c.full = dfixed_const(lb_fill_bw); 767 b.full = dfixed_div(c, b); 768 a.full = dfixed_div(a, b); 769 line_fill_time = dfixed_trunc(a); 770 771 if (line_fill_time < wm->active_time) 772 return latency; 773 else 774 return latency + (line_fill_time - wm->active_time); 775 776 } 777 778 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 779 { 780 if (dce6_average_bandwidth(wm) <= 781 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) 782 return true; 783 else 784 return false; 785 }; 786 787 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 788 { 789 if (dce6_average_bandwidth(wm) <= 790 (dce6_available_bandwidth(wm) / wm->num_heads)) 791 return true; 792 else 793 return false; 794 }; 795 796 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) 797 { 798 u32 lb_partitions = wm->lb_size / wm->src_width; 799 u32 line_time = wm->active_time + wm->blank_time; 800 u32 latency_tolerant_lines; 801 u32 latency_hiding; 802 fixed20_12 a; 803 804 a.full = dfixed_const(1); 805 if (wm->vsc.full > a.full) 806 latency_tolerant_lines = 1; 807 else { 808 if (lb_partitions <= (wm->vtaps + 1)) 809 latency_tolerant_lines = 1; 810 else 811 latency_tolerant_lines = 2; 812 } 813 814 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 815 816 if (dce6_latency_watermark(wm) <= latency_hiding) 817 return true; 818 else 819 return false; 820 } 821 822 static void dce6_program_watermarks(struct radeon_device *rdev, 823 struct radeon_crtc *radeon_crtc, 824 u32 lb_size, u32 num_heads) 825 { 826 struct drm_display_mode *mode = &radeon_crtc->base.mode; 827 struct dce6_wm_params wm; 828 u32 pixel_period; 829 u32 line_time = 0; 830 u32 latency_watermark_a = 0, latency_watermark_b = 0; 831 u32 priority_a_mark = 0, priority_b_mark = 0; 832 u32 priority_a_cnt = PRIORITY_OFF; 833 u32 priority_b_cnt = PRIORITY_OFF; 834 u32 tmp, arb_control3; 835 fixed20_12 a, b, c; 836 837 if (radeon_crtc->base.enabled && num_heads && mode) { 838 pixel_period = 1000000 / (u32)mode->clock; 839 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 840 priority_a_cnt = 0; 841 priority_b_cnt = 0; 842 843 wm.yclk = rdev->pm.current_mclk * 10; 844 wm.sclk = rdev->pm.current_sclk * 10; 845 wm.disp_clk = mode->clock; 846 wm.src_width = mode->crtc_hdisplay; 847 wm.active_time = mode->crtc_hdisplay * pixel_period; 848 wm.blank_time = line_time - wm.active_time; 849 wm.interlaced = false; 850 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 851 wm.interlaced = true; 852 wm.vsc = radeon_crtc->vsc; 853 wm.vtaps = 1; 854 if (radeon_crtc->rmx_type != RMX_OFF) 855 wm.vtaps = 2; 856 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 857 wm.lb_size = lb_size; 858 if (rdev->family == CHIP_ARUBA) 859 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 860 else 861 wm.dram_channels = si_get_number_of_dram_channels(rdev); 862 wm.num_heads = num_heads; 863 864 /* set for high clocks */ 865 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535); 866 /* set for low clocks */ 867 /* wm.yclk = low clk; wm.sclk = low clk */ 868 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535); 869 870 /* possibly force display priority to high */ 871 /* should really do this at mode validation time... */ 872 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 873 !dce6_average_bandwidth_vs_available_bandwidth(&wm) || 874 !dce6_check_latency_hiding(&wm) || 875 (rdev->disp_priority == 2)) { 876 DRM_DEBUG_KMS("force priority to high\n"); 877 priority_a_cnt |= PRIORITY_ALWAYS_ON; 878 priority_b_cnt |= PRIORITY_ALWAYS_ON; 879 } 880 881 a.full = dfixed_const(1000); 882 b.full = dfixed_const(mode->clock); 883 b.full = dfixed_div(b, a); 884 c.full = dfixed_const(latency_watermark_a); 885 c.full = dfixed_mul(c, b); 886 c.full = dfixed_mul(c, radeon_crtc->hsc); 887 c.full = dfixed_div(c, a); 888 a.full = dfixed_const(16); 889 c.full = dfixed_div(c, a); 890 priority_a_mark = dfixed_trunc(c); 891 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 892 893 a.full = dfixed_const(1000); 894 b.full = dfixed_const(mode->clock); 895 b.full = dfixed_div(b, a); 896 c.full = dfixed_const(latency_watermark_b); 897 c.full = dfixed_mul(c, b); 898 c.full = dfixed_mul(c, radeon_crtc->hsc); 899 c.full = dfixed_div(c, a); 900 a.full = dfixed_const(16); 901 c.full = dfixed_div(c, a); 902 priority_b_mark = dfixed_trunc(c); 903 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 904 } 905 906 /* select wm A */ 907 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 908 tmp = arb_control3; 909 tmp &= ~LATENCY_WATERMARK_MASK(3); 910 tmp |= LATENCY_WATERMARK_MASK(1); 911 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 912 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 913 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 914 LATENCY_HIGH_WATERMARK(line_time))); 915 /* select wm B */ 916 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 917 tmp &= ~LATENCY_WATERMARK_MASK(3); 918 tmp |= LATENCY_WATERMARK_MASK(2); 919 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 920 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 921 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 922 LATENCY_HIGH_WATERMARK(line_time))); 923 /* restore original selection */ 924 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); 925 926 /* write the priority marks */ 927 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 928 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 929 930 } 931 932 void dce6_bandwidth_update(struct radeon_device *rdev) 933 { 934 struct drm_display_mode *mode0 = NULL; 935 struct drm_display_mode *mode1 = NULL; 936 u32 num_heads = 0, lb_size; 937 int i; 938 939 radeon_update_display_priority(rdev); 940 941 for (i = 0; i < rdev->num_crtc; i++) { 942 if (rdev->mode_info.crtcs[i]->base.enabled) 943 num_heads++; 944 } 945 for (i = 0; i < rdev->num_crtc; i += 2) { 946 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 947 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 948 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 949 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 950 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 951 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 952 } 953 } 954 955 /* 956 * Core functions 957 */ 958 static void si_tiling_mode_table_init(struct radeon_device *rdev) 959 { 960 const u32 num_tile_mode_states = 32; 961 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 962 963 switch (rdev->config.si.mem_row_size_in_kb) { 964 case 1: 965 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 966 break; 967 case 2: 968 default: 969 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 970 break; 971 case 4: 972 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 973 break; 974 } 975 976 if ((rdev->family == CHIP_TAHITI) || 977 (rdev->family == CHIP_PITCAIRN)) { 978 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 979 switch (reg_offset) { 980 case 0: /* non-AA compressed depth or any compressed stencil */ 981 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 982 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 983 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 984 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 985 NUM_BANKS(ADDR_SURF_16_BANK) | 986 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 987 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 988 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 989 break; 990 case 1: /* 2xAA/4xAA compressed depth only */ 991 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 992 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 993 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 995 NUM_BANKS(ADDR_SURF_16_BANK) | 996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 999 break; 1000 case 2: /* 8xAA compressed depth only */ 1001 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1002 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1003 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1005 NUM_BANKS(ADDR_SURF_16_BANK) | 1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1009 break; 1010 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1011 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1012 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1013 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1015 NUM_BANKS(ADDR_SURF_16_BANK) | 1016 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1019 break; 1020 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1021 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1022 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1025 NUM_BANKS(ADDR_SURF_16_BANK) | 1026 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1029 break; 1030 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1031 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1032 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1033 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1034 TILE_SPLIT(split_equal_to_row_size) | 1035 NUM_BANKS(ADDR_SURF_16_BANK) | 1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1039 break; 1040 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1041 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1042 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1043 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1044 TILE_SPLIT(split_equal_to_row_size) | 1045 NUM_BANKS(ADDR_SURF_16_BANK) | 1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1049 break; 1050 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1051 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1052 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1053 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1054 TILE_SPLIT(split_equal_to_row_size) | 1055 NUM_BANKS(ADDR_SURF_16_BANK) | 1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1059 break; 1060 case 8: /* 1D and 1D Array Surfaces */ 1061 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1062 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1063 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1065 NUM_BANKS(ADDR_SURF_16_BANK) | 1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1069 break; 1070 case 9: /* Displayable maps. */ 1071 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1072 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1073 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1074 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1075 NUM_BANKS(ADDR_SURF_16_BANK) | 1076 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1077 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1078 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1079 break; 1080 case 10: /* Display 8bpp. */ 1081 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1082 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1084 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1085 NUM_BANKS(ADDR_SURF_16_BANK) | 1086 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1089 break; 1090 case 11: /* Display 16bpp. */ 1091 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1092 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1093 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1095 NUM_BANKS(ADDR_SURF_16_BANK) | 1096 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1097 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1098 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1099 break; 1100 case 12: /* Display 32bpp. */ 1101 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1102 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1105 NUM_BANKS(ADDR_SURF_16_BANK) | 1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1109 break; 1110 case 13: /* Thin. */ 1111 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1112 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1113 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1115 NUM_BANKS(ADDR_SURF_16_BANK) | 1116 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1119 break; 1120 case 14: /* Thin 8 bpp. */ 1121 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1122 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1125 NUM_BANKS(ADDR_SURF_16_BANK) | 1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1129 break; 1130 case 15: /* Thin 16 bpp. */ 1131 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1132 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1135 NUM_BANKS(ADDR_SURF_16_BANK) | 1136 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1139 break; 1140 case 16: /* Thin 32 bpp. */ 1141 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1142 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1145 NUM_BANKS(ADDR_SURF_16_BANK) | 1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1149 break; 1150 case 17: /* Thin 64 bpp. */ 1151 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1152 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1154 TILE_SPLIT(split_equal_to_row_size) | 1155 NUM_BANKS(ADDR_SURF_16_BANK) | 1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1159 break; 1160 case 21: /* 8 bpp PRT. */ 1161 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1162 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1164 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1165 NUM_BANKS(ADDR_SURF_16_BANK) | 1166 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1169 break; 1170 case 22: /* 16 bpp PRT */ 1171 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1172 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1173 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1174 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1175 NUM_BANKS(ADDR_SURF_16_BANK) | 1176 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1179 break; 1180 case 23: /* 32 bpp PRT */ 1181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1182 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1184 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1185 NUM_BANKS(ADDR_SURF_16_BANK) | 1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1189 break; 1190 case 24: /* 64 bpp PRT */ 1191 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1192 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1195 NUM_BANKS(ADDR_SURF_16_BANK) | 1196 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1199 break; 1200 case 25: /* 128 bpp PRT */ 1201 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1202 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1205 NUM_BANKS(ADDR_SURF_8_BANK) | 1206 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1209 break; 1210 default: 1211 gb_tile_moden = 0; 1212 break; 1213 } 1214 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1215 } 1216 } else if ((rdev->family == CHIP_VERDE) || 1217 (rdev->family == CHIP_OLAND)) { 1218 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1219 switch (reg_offset) { 1220 case 0: /* non-AA compressed depth or any compressed stencil */ 1221 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1222 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1223 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1224 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1225 NUM_BANKS(ADDR_SURF_16_BANK) | 1226 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1227 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1228 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1229 break; 1230 case 1: /* 2xAA/4xAA compressed depth only */ 1231 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1232 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1233 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1235 NUM_BANKS(ADDR_SURF_16_BANK) | 1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1239 break; 1240 case 2: /* 8xAA compressed depth only */ 1241 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1242 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1245 NUM_BANKS(ADDR_SURF_16_BANK) | 1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1249 break; 1250 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1251 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1252 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1253 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1254 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1255 NUM_BANKS(ADDR_SURF_16_BANK) | 1256 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1259 break; 1260 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1261 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1262 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1263 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1264 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1265 NUM_BANKS(ADDR_SURF_16_BANK) | 1266 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1269 break; 1270 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1271 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1272 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1273 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1274 TILE_SPLIT(split_equal_to_row_size) | 1275 NUM_BANKS(ADDR_SURF_16_BANK) | 1276 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1277 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1278 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1279 break; 1280 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1281 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1282 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1283 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1284 TILE_SPLIT(split_equal_to_row_size) | 1285 NUM_BANKS(ADDR_SURF_16_BANK) | 1286 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1289 break; 1290 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1291 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1292 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1293 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1294 TILE_SPLIT(split_equal_to_row_size) | 1295 NUM_BANKS(ADDR_SURF_16_BANK) | 1296 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1297 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1298 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1299 break; 1300 case 8: /* 1D and 1D Array Surfaces */ 1301 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1302 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1303 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1305 NUM_BANKS(ADDR_SURF_16_BANK) | 1306 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1307 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1308 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1309 break; 1310 case 9: /* Displayable maps. */ 1311 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1312 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1313 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1314 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1315 NUM_BANKS(ADDR_SURF_16_BANK) | 1316 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1319 break; 1320 case 10: /* Display 8bpp. */ 1321 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1322 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1323 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1325 NUM_BANKS(ADDR_SURF_16_BANK) | 1326 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1329 break; 1330 case 11: /* Display 16bpp. */ 1331 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1332 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1333 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1334 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1335 NUM_BANKS(ADDR_SURF_16_BANK) | 1336 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1337 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1338 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1339 break; 1340 case 12: /* Display 32bpp. */ 1341 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1342 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1343 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1345 NUM_BANKS(ADDR_SURF_16_BANK) | 1346 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1349 break; 1350 case 13: /* Thin. */ 1351 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1352 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1353 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1354 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1355 NUM_BANKS(ADDR_SURF_16_BANK) | 1356 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1359 break; 1360 case 14: /* Thin 8 bpp. */ 1361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1362 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1363 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1365 NUM_BANKS(ADDR_SURF_16_BANK) | 1366 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1369 break; 1370 case 15: /* Thin 16 bpp. */ 1371 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1372 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1373 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1375 NUM_BANKS(ADDR_SURF_16_BANK) | 1376 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1379 break; 1380 case 16: /* Thin 32 bpp. */ 1381 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1382 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1383 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1385 NUM_BANKS(ADDR_SURF_16_BANK) | 1386 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1389 break; 1390 case 17: /* Thin 64 bpp. */ 1391 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1392 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1393 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1394 TILE_SPLIT(split_equal_to_row_size) | 1395 NUM_BANKS(ADDR_SURF_16_BANK) | 1396 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1399 break; 1400 case 21: /* 8 bpp PRT. */ 1401 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1402 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1403 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1405 NUM_BANKS(ADDR_SURF_16_BANK) | 1406 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1409 break; 1410 case 22: /* 16 bpp PRT */ 1411 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1412 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1413 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1414 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1415 NUM_BANKS(ADDR_SURF_16_BANK) | 1416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1419 break; 1420 case 23: /* 32 bpp PRT */ 1421 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1422 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1423 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1425 NUM_BANKS(ADDR_SURF_16_BANK) | 1426 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1429 break; 1430 case 24: /* 64 bpp PRT */ 1431 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1432 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1433 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1435 NUM_BANKS(ADDR_SURF_16_BANK) | 1436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1439 break; 1440 case 25: /* 128 bpp PRT */ 1441 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1442 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1443 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1444 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1445 NUM_BANKS(ADDR_SURF_8_BANK) | 1446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1449 break; 1450 default: 1451 gb_tile_moden = 0; 1452 break; 1453 } 1454 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1455 } 1456 } else 1457 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1458 } 1459 1460 static void si_select_se_sh(struct radeon_device *rdev, 1461 u32 se_num, u32 sh_num) 1462 { 1463 u32 data = INSTANCE_BROADCAST_WRITES; 1464 1465 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1466 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 1467 else if (se_num == 0xffffffff) 1468 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 1469 else if (sh_num == 0xffffffff) 1470 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 1471 else 1472 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 1473 WREG32(GRBM_GFX_INDEX, data); 1474 } 1475 1476 static u32 si_create_bitmask(u32 bit_width) 1477 { 1478 u32 i, mask = 0; 1479 1480 for (i = 0; i < bit_width; i++) { 1481 mask <<= 1; 1482 mask |= 1; 1483 } 1484 return mask; 1485 } 1486 1487 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh) 1488 { 1489 u32 data, mask; 1490 1491 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1492 if (data & 1) 1493 data &= INACTIVE_CUS_MASK; 1494 else 1495 data = 0; 1496 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1497 1498 data >>= INACTIVE_CUS_SHIFT; 1499 1500 mask = si_create_bitmask(cu_per_sh); 1501 1502 return ~data & mask; 1503 } 1504 1505 static void si_setup_spi(struct radeon_device *rdev, 1506 u32 se_num, u32 sh_per_se, 1507 u32 cu_per_sh) 1508 { 1509 int i, j, k; 1510 u32 data, mask, active_cu; 1511 1512 for (i = 0; i < se_num; i++) { 1513 for (j = 0; j < sh_per_se; j++) { 1514 si_select_se_sh(rdev, i, j); 1515 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1516 active_cu = si_get_cu_enabled(rdev, cu_per_sh); 1517 1518 mask = 1; 1519 for (k = 0; k < 16; k++) { 1520 mask <<= k; 1521 if (active_cu & mask) { 1522 data &= ~mask; 1523 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1524 break; 1525 } 1526 } 1527 } 1528 } 1529 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1530 } 1531 1532 static u32 si_get_rb_disabled(struct radeon_device *rdev, 1533 u32 max_rb_num, u32 se_num, 1534 u32 sh_per_se) 1535 { 1536 u32 data, mask; 1537 1538 data = RREG32(CC_RB_BACKEND_DISABLE); 1539 if (data & 1) 1540 data &= BACKEND_DISABLE_MASK; 1541 else 1542 data = 0; 1543 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 1544 1545 data >>= BACKEND_DISABLE_SHIFT; 1546 1547 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se); 1548 1549 return data & mask; 1550 } 1551 1552 static void si_setup_rb(struct radeon_device *rdev, 1553 u32 se_num, u32 sh_per_se, 1554 u32 max_rb_num) 1555 { 1556 int i, j; 1557 u32 data, mask; 1558 u32 disabled_rbs = 0; 1559 u32 enabled_rbs = 0; 1560 1561 for (i = 0; i < se_num; i++) { 1562 for (j = 0; j < sh_per_se; j++) { 1563 si_select_se_sh(rdev, i, j); 1564 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 1565 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1566 } 1567 } 1568 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1569 1570 mask = 1; 1571 for (i = 0; i < max_rb_num; i++) { 1572 if (!(disabled_rbs & mask)) 1573 enabled_rbs |= mask; 1574 mask <<= 1; 1575 } 1576 1577 for (i = 0; i < se_num; i++) { 1578 si_select_se_sh(rdev, i, 0xffffffff); 1579 data = 0; 1580 for (j = 0; j < sh_per_se; j++) { 1581 switch (enabled_rbs & 3) { 1582 case 1: 1583 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 1584 break; 1585 case 2: 1586 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); 1587 break; 1588 case 3: 1589 default: 1590 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); 1591 break; 1592 } 1593 enabled_rbs >>= 2; 1594 } 1595 WREG32(PA_SC_RASTER_CONFIG, data); 1596 } 1597 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1598 } 1599 1600 static void si_gpu_init(struct radeon_device *rdev) 1601 { 1602 u32 gb_addr_config = 0; 1603 u32 mc_shared_chmap, mc_arb_ramcfg; 1604 u32 sx_debug_1; 1605 u32 hdp_host_path_cntl; 1606 u32 tmp; 1607 int i, j; 1608 1609 switch (rdev->family) { 1610 case CHIP_TAHITI: 1611 rdev->config.si.max_shader_engines = 2; 1612 rdev->config.si.max_tile_pipes = 12; 1613 rdev->config.si.max_cu_per_sh = 8; 1614 rdev->config.si.max_sh_per_se = 2; 1615 rdev->config.si.max_backends_per_se = 4; 1616 rdev->config.si.max_texture_channel_caches = 12; 1617 rdev->config.si.max_gprs = 256; 1618 rdev->config.si.max_gs_threads = 32; 1619 rdev->config.si.max_hw_contexts = 8; 1620 1621 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1622 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1623 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1624 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1625 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1626 break; 1627 case CHIP_PITCAIRN: 1628 rdev->config.si.max_shader_engines = 2; 1629 rdev->config.si.max_tile_pipes = 8; 1630 rdev->config.si.max_cu_per_sh = 5; 1631 rdev->config.si.max_sh_per_se = 2; 1632 rdev->config.si.max_backends_per_se = 4; 1633 rdev->config.si.max_texture_channel_caches = 8; 1634 rdev->config.si.max_gprs = 256; 1635 rdev->config.si.max_gs_threads = 32; 1636 rdev->config.si.max_hw_contexts = 8; 1637 1638 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1639 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1640 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1641 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1642 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1643 break; 1644 case CHIP_VERDE: 1645 default: 1646 rdev->config.si.max_shader_engines = 1; 1647 rdev->config.si.max_tile_pipes = 4; 1648 rdev->config.si.max_cu_per_sh = 2; 1649 rdev->config.si.max_sh_per_se = 2; 1650 rdev->config.si.max_backends_per_se = 4; 1651 rdev->config.si.max_texture_channel_caches = 4; 1652 rdev->config.si.max_gprs = 256; 1653 rdev->config.si.max_gs_threads = 32; 1654 rdev->config.si.max_hw_contexts = 8; 1655 1656 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1657 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1658 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1659 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1660 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1661 break; 1662 case CHIP_OLAND: 1663 rdev->config.si.max_shader_engines = 1; 1664 rdev->config.si.max_tile_pipes = 4; 1665 rdev->config.si.max_cu_per_sh = 6; 1666 rdev->config.si.max_sh_per_se = 1; 1667 rdev->config.si.max_backends_per_se = 2; 1668 rdev->config.si.max_texture_channel_caches = 4; 1669 rdev->config.si.max_gprs = 256; 1670 rdev->config.si.max_gs_threads = 16; 1671 rdev->config.si.max_hw_contexts = 8; 1672 1673 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1674 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1675 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1676 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1677 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1678 break; 1679 } 1680 1681 /* Initialize HDP */ 1682 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1683 WREG32((0x2c14 + j), 0x00000000); 1684 WREG32((0x2c18 + j), 0x00000000); 1685 WREG32((0x2c1c + j), 0x00000000); 1686 WREG32((0x2c20 + j), 0x00000000); 1687 WREG32((0x2c24 + j), 0x00000000); 1688 } 1689 1690 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1691 1692 evergreen_fix_pci_max_read_req_size(rdev); 1693 1694 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1695 1696 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1697 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1698 1699 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1700 rdev->config.si.mem_max_burst_length_bytes = 256; 1701 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1702 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1703 if (rdev->config.si.mem_row_size_in_kb > 4) 1704 rdev->config.si.mem_row_size_in_kb = 4; 1705 /* XXX use MC settings? */ 1706 rdev->config.si.shader_engine_tile_size = 32; 1707 rdev->config.si.num_gpus = 1; 1708 rdev->config.si.multi_gpu_tile_size = 64; 1709 1710 /* fix up row size */ 1711 gb_addr_config &= ~ROW_SIZE_MASK; 1712 switch (rdev->config.si.mem_row_size_in_kb) { 1713 case 1: 1714 default: 1715 gb_addr_config |= ROW_SIZE(0); 1716 break; 1717 case 2: 1718 gb_addr_config |= ROW_SIZE(1); 1719 break; 1720 case 4: 1721 gb_addr_config |= ROW_SIZE(2); 1722 break; 1723 } 1724 1725 /* setup tiling info dword. gb_addr_config is not adequate since it does 1726 * not have bank info, so create a custom tiling dword. 1727 * bits 3:0 num_pipes 1728 * bits 7:4 num_banks 1729 * bits 11:8 group_size 1730 * bits 15:12 row_size 1731 */ 1732 rdev->config.si.tile_config = 0; 1733 switch (rdev->config.si.num_tile_pipes) { 1734 case 1: 1735 rdev->config.si.tile_config |= (0 << 0); 1736 break; 1737 case 2: 1738 rdev->config.si.tile_config |= (1 << 0); 1739 break; 1740 case 4: 1741 rdev->config.si.tile_config |= (2 << 0); 1742 break; 1743 case 8: 1744 default: 1745 /* XXX what about 12? */ 1746 rdev->config.si.tile_config |= (3 << 0); 1747 break; 1748 } 1749 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1750 case 0: /* four banks */ 1751 rdev->config.si.tile_config |= 0 << 4; 1752 break; 1753 case 1: /* eight banks */ 1754 rdev->config.si.tile_config |= 1 << 4; 1755 break; 1756 case 2: /* sixteen banks */ 1757 default: 1758 rdev->config.si.tile_config |= 2 << 4; 1759 break; 1760 } 1761 rdev->config.si.tile_config |= 1762 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1763 rdev->config.si.tile_config |= 1764 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1765 1766 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1767 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1768 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1769 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1770 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1771 1772 si_tiling_mode_table_init(rdev); 1773 1774 si_setup_rb(rdev, rdev->config.si.max_shader_engines, 1775 rdev->config.si.max_sh_per_se, 1776 rdev->config.si.max_backends_per_se); 1777 1778 si_setup_spi(rdev, rdev->config.si.max_shader_engines, 1779 rdev->config.si.max_sh_per_se, 1780 rdev->config.si.max_cu_per_sh); 1781 1782 1783 /* set HW defaults for 3D engine */ 1784 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1785 ROQ_IB2_START(0x2b))); 1786 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1787 1788 sx_debug_1 = RREG32(SX_DEBUG_1); 1789 WREG32(SX_DEBUG_1, sx_debug_1); 1790 1791 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1792 1793 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | 1794 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | 1795 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | 1796 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); 1797 1798 WREG32(VGT_NUM_INSTANCES, 1); 1799 1800 WREG32(CP_PERFMON_CNTL, 0); 1801 1802 WREG32(SQ_CONFIG, 0); 1803 1804 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1805 FORCE_EOV_MAX_REZ_CNT(255))); 1806 1807 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1808 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1809 1810 WREG32(VGT_GS_VERTEX_REUSE, 16); 1811 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1812 1813 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1814 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1815 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1816 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1817 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1818 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1819 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1820 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1821 1822 tmp = RREG32(HDP_MISC_CNTL); 1823 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1824 WREG32(HDP_MISC_CNTL, tmp); 1825 1826 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1827 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1828 1829 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1830 1831 udelay(50); 1832 } 1833 1834 /* 1835 * GPU scratch registers helpers function. 1836 */ 1837 static void si_scratch_init(struct radeon_device *rdev) 1838 { 1839 int i; 1840 1841 rdev->scratch.num_reg = 7; 1842 rdev->scratch.reg_base = SCRATCH_REG0; 1843 for (i = 0; i < rdev->scratch.num_reg; i++) { 1844 rdev->scratch.free[i] = true; 1845 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 1846 } 1847 } 1848 1849 void si_fence_ring_emit(struct radeon_device *rdev, 1850 struct radeon_fence *fence) 1851 { 1852 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1853 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1854 1855 /* flush read cache over gart */ 1856 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1857 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1858 radeon_ring_write(ring, 0); 1859 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1860 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1861 PACKET3_TC_ACTION_ENA | 1862 PACKET3_SH_KCACHE_ACTION_ENA | 1863 PACKET3_SH_ICACHE_ACTION_ENA); 1864 radeon_ring_write(ring, 0xFFFFFFFF); 1865 radeon_ring_write(ring, 0); 1866 radeon_ring_write(ring, 10); /* poll interval */ 1867 /* EVENT_WRITE_EOP - flush caches, send int */ 1868 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1869 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1870 radeon_ring_write(ring, addr & 0xffffffff); 1871 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1872 radeon_ring_write(ring, fence->seq); 1873 radeon_ring_write(ring, 0); 1874 } 1875 1876 /* 1877 * IB stuff 1878 */ 1879 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1880 { 1881 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1882 u32 header; 1883 1884 if (ib->is_const_ib) { 1885 /* set switch buffer packet before const IB */ 1886 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1887 radeon_ring_write(ring, 0); 1888 1889 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1890 } else { 1891 u32 next_rptr; 1892 if (ring->rptr_save_reg) { 1893 next_rptr = ring->wptr + 3 + 4 + 8; 1894 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1895 radeon_ring_write(ring, ((ring->rptr_save_reg - 1896 PACKET3_SET_CONFIG_REG_START) >> 2)); 1897 radeon_ring_write(ring, next_rptr); 1898 } else if (rdev->wb.enabled) { 1899 next_rptr = ring->wptr + 5 + 4 + 8; 1900 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1901 radeon_ring_write(ring, (1 << 8)); 1902 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1903 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 1904 radeon_ring_write(ring, next_rptr); 1905 } 1906 1907 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1908 } 1909 1910 radeon_ring_write(ring, header); 1911 radeon_ring_write(ring, 1912 #ifdef __BIG_ENDIAN 1913 (2 << 0) | 1914 #endif 1915 (ib->gpu_addr & 0xFFFFFFFC)); 1916 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1917 radeon_ring_write(ring, ib->length_dw | 1918 (ib->vm ? (ib->vm->id << 24) : 0)); 1919 1920 if (!ib->is_const_ib) { 1921 /* flush read cache over gart for this vmid */ 1922 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1923 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1924 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); 1925 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1926 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1927 PACKET3_TC_ACTION_ENA | 1928 PACKET3_SH_KCACHE_ACTION_ENA | 1929 PACKET3_SH_ICACHE_ACTION_ENA); 1930 radeon_ring_write(ring, 0xFFFFFFFF); 1931 radeon_ring_write(ring, 0); 1932 radeon_ring_write(ring, 10); /* poll interval */ 1933 } 1934 } 1935 1936 /* 1937 * CP. 1938 */ 1939 static void si_cp_enable(struct radeon_device *rdev, bool enable) 1940 { 1941 if (enable) 1942 WREG32(CP_ME_CNTL, 0); 1943 else { 1944 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1945 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1946 WREG32(SCRATCH_UMSK, 0); 1947 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1948 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1949 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1950 } 1951 udelay(50); 1952 } 1953 1954 static int si_cp_load_microcode(struct radeon_device *rdev) 1955 { 1956 const __be32 *fw_data; 1957 int i; 1958 1959 if (!rdev->me_fw || !rdev->pfp_fw) 1960 return -EINVAL; 1961 1962 si_cp_enable(rdev, false); 1963 1964 /* PFP */ 1965 fw_data = (const __be32 *)rdev->pfp_fw->data; 1966 WREG32(CP_PFP_UCODE_ADDR, 0); 1967 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) 1968 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1969 WREG32(CP_PFP_UCODE_ADDR, 0); 1970 1971 /* CE */ 1972 fw_data = (const __be32 *)rdev->ce_fw->data; 1973 WREG32(CP_CE_UCODE_ADDR, 0); 1974 for (i = 0; i < SI_CE_UCODE_SIZE; i++) 1975 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); 1976 WREG32(CP_CE_UCODE_ADDR, 0); 1977 1978 /* ME */ 1979 fw_data = (const __be32 *)rdev->me_fw->data; 1980 WREG32(CP_ME_RAM_WADDR, 0); 1981 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) 1982 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1983 WREG32(CP_ME_RAM_WADDR, 0); 1984 1985 WREG32(CP_PFP_UCODE_ADDR, 0); 1986 WREG32(CP_CE_UCODE_ADDR, 0); 1987 WREG32(CP_ME_RAM_WADDR, 0); 1988 WREG32(CP_ME_RAM_RADDR, 0); 1989 return 0; 1990 } 1991 1992 static int si_cp_start(struct radeon_device *rdev) 1993 { 1994 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1995 int r, i; 1996 1997 r = radeon_ring_lock(rdev, ring, 7 + 4); 1998 if (r) { 1999 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2000 return r; 2001 } 2002 /* init the CP */ 2003 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2004 radeon_ring_write(ring, 0x1); 2005 radeon_ring_write(ring, 0x0); 2006 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); 2007 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2008 radeon_ring_write(ring, 0); 2009 radeon_ring_write(ring, 0); 2010 2011 /* init the CE partitions */ 2012 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2013 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2014 radeon_ring_write(ring, 0xc000); 2015 radeon_ring_write(ring, 0xe000); 2016 radeon_ring_unlock_commit(rdev, ring); 2017 2018 si_cp_enable(rdev, true); 2019 2020 r = radeon_ring_lock(rdev, ring, si_default_size + 10); 2021 if (r) { 2022 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2023 return r; 2024 } 2025 2026 /* setup clear context state */ 2027 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2028 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2029 2030 for (i = 0; i < si_default_size; i++) 2031 radeon_ring_write(ring, si_default_state[i]); 2032 2033 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2034 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2035 2036 /* set clear context state */ 2037 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2038 radeon_ring_write(ring, 0); 2039 2040 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2041 radeon_ring_write(ring, 0x00000316); 2042 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2043 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2044 2045 radeon_ring_unlock_commit(rdev, ring); 2046 2047 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { 2048 ring = &rdev->ring[i]; 2049 r = radeon_ring_lock(rdev, ring, 2); 2050 2051 /* clear the compute context state */ 2052 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 2053 radeon_ring_write(ring, 0); 2054 2055 radeon_ring_unlock_commit(rdev, ring); 2056 } 2057 2058 return 0; 2059 } 2060 2061 static void si_cp_fini(struct radeon_device *rdev) 2062 { 2063 struct radeon_ring *ring; 2064 si_cp_enable(rdev, false); 2065 2066 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2067 radeon_ring_fini(rdev, ring); 2068 radeon_scratch_free(rdev, ring->rptr_save_reg); 2069 2070 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2071 radeon_ring_fini(rdev, ring); 2072 radeon_scratch_free(rdev, ring->rptr_save_reg); 2073 2074 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2075 radeon_ring_fini(rdev, ring); 2076 radeon_scratch_free(rdev, ring->rptr_save_reg); 2077 } 2078 2079 static int si_cp_resume(struct radeon_device *rdev) 2080 { 2081 struct radeon_ring *ring; 2082 u32 tmp; 2083 u32 rb_bufsz; 2084 int r; 2085 2086 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 2087 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 2088 SOFT_RESET_PA | 2089 SOFT_RESET_VGT | 2090 SOFT_RESET_SPI | 2091 SOFT_RESET_SX)); 2092 RREG32(GRBM_SOFT_RESET); 2093 mdelay(15); 2094 WREG32(GRBM_SOFT_RESET, 0); 2095 RREG32(GRBM_SOFT_RESET); 2096 2097 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2098 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2099 2100 /* Set the write pointer delay */ 2101 WREG32(CP_RB_WPTR_DELAY, 0); 2102 2103 WREG32(CP_DEBUG, 0); 2104 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2105 2106 /* ring 0 - compute and gfx */ 2107 /* Set ring buffer size */ 2108 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2109 rb_bufsz = drm_order(ring->ring_size / 8); 2110 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2111 #ifdef __BIG_ENDIAN 2112 tmp |= BUF_SWAP_32BIT; 2113 #endif 2114 WREG32(CP_RB0_CNTL, tmp); 2115 2116 /* Initialize the ring buffer's read and write pointers */ 2117 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 2118 ring->wptr = 0; 2119 WREG32(CP_RB0_WPTR, ring->wptr); 2120 2121 /* set the wb address whether it's enabled or not */ 2122 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 2123 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2124 2125 if (rdev->wb.enabled) 2126 WREG32(SCRATCH_UMSK, 0xff); 2127 else { 2128 tmp |= RB_NO_UPDATE; 2129 WREG32(SCRATCH_UMSK, 0); 2130 } 2131 2132 mdelay(1); 2133 WREG32(CP_RB0_CNTL, tmp); 2134 2135 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 2136 2137 ring->rptr = RREG32(CP_RB0_RPTR); 2138 2139 /* ring1 - compute only */ 2140 /* Set ring buffer size */ 2141 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2142 rb_bufsz = drm_order(ring->ring_size / 8); 2143 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2144 #ifdef __BIG_ENDIAN 2145 tmp |= BUF_SWAP_32BIT; 2146 #endif 2147 WREG32(CP_RB1_CNTL, tmp); 2148 2149 /* Initialize the ring buffer's read and write pointers */ 2150 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 2151 ring->wptr = 0; 2152 WREG32(CP_RB1_WPTR, ring->wptr); 2153 2154 /* set the wb address whether it's enabled or not */ 2155 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 2156 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 2157 2158 mdelay(1); 2159 WREG32(CP_RB1_CNTL, tmp); 2160 2161 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 2162 2163 ring->rptr = RREG32(CP_RB1_RPTR); 2164 2165 /* ring2 - compute only */ 2166 /* Set ring buffer size */ 2167 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2168 rb_bufsz = drm_order(ring->ring_size / 8); 2169 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2170 #ifdef __BIG_ENDIAN 2171 tmp |= BUF_SWAP_32BIT; 2172 #endif 2173 WREG32(CP_RB2_CNTL, tmp); 2174 2175 /* Initialize the ring buffer's read and write pointers */ 2176 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 2177 ring->wptr = 0; 2178 WREG32(CP_RB2_WPTR, ring->wptr); 2179 2180 /* set the wb address whether it's enabled or not */ 2181 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 2182 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 2183 2184 mdelay(1); 2185 WREG32(CP_RB2_CNTL, tmp); 2186 2187 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 2188 2189 ring->rptr = RREG32(CP_RB2_RPTR); 2190 2191 /* start the rings */ 2192 si_cp_start(rdev); 2193 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 2194 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; 2195 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; 2196 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 2197 if (r) { 2198 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2199 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2200 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2201 return r; 2202 } 2203 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); 2204 if (r) { 2205 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2206 } 2207 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); 2208 if (r) { 2209 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2210 } 2211 2212 return 0; 2213 } 2214 2215 static u32 si_gpu_check_soft_reset(struct radeon_device *rdev) 2216 { 2217 u32 reset_mask = 0; 2218 u32 tmp; 2219 2220 /* GRBM_STATUS */ 2221 tmp = RREG32(GRBM_STATUS); 2222 if (tmp & (PA_BUSY | SC_BUSY | 2223 BCI_BUSY | SX_BUSY | 2224 TA_BUSY | VGT_BUSY | 2225 DB_BUSY | CB_BUSY | 2226 GDS_BUSY | SPI_BUSY | 2227 IA_BUSY | IA_BUSY_NO_DMA)) 2228 reset_mask |= RADEON_RESET_GFX; 2229 2230 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | 2231 CP_BUSY | CP_COHERENCY_BUSY)) 2232 reset_mask |= RADEON_RESET_CP; 2233 2234 if (tmp & GRBM_EE_BUSY) 2235 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 2236 2237 /* GRBM_STATUS2 */ 2238 tmp = RREG32(GRBM_STATUS2); 2239 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) 2240 reset_mask |= RADEON_RESET_RLC; 2241 2242 /* DMA_STATUS_REG 0 */ 2243 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 2244 if (!(tmp & DMA_IDLE)) 2245 reset_mask |= RADEON_RESET_DMA; 2246 2247 /* DMA_STATUS_REG 1 */ 2248 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 2249 if (!(tmp & DMA_IDLE)) 2250 reset_mask |= RADEON_RESET_DMA1; 2251 2252 /* SRBM_STATUS2 */ 2253 tmp = RREG32(SRBM_STATUS2); 2254 if (tmp & DMA_BUSY) 2255 reset_mask |= RADEON_RESET_DMA; 2256 2257 if (tmp & DMA1_BUSY) 2258 reset_mask |= RADEON_RESET_DMA1; 2259 2260 /* SRBM_STATUS */ 2261 tmp = RREG32(SRBM_STATUS); 2262 2263 if (tmp & IH_BUSY) 2264 reset_mask |= RADEON_RESET_IH; 2265 2266 if (tmp & SEM_BUSY) 2267 reset_mask |= RADEON_RESET_SEM; 2268 2269 if (tmp & GRBM_RQ_PENDING) 2270 reset_mask |= RADEON_RESET_GRBM; 2271 2272 if (tmp & VMC_BUSY) 2273 reset_mask |= RADEON_RESET_VMC; 2274 2275 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | 2276 MCC_BUSY | MCD_BUSY)) 2277 reset_mask |= RADEON_RESET_MC; 2278 2279 if (evergreen_is_display_hung(rdev)) 2280 reset_mask |= RADEON_RESET_DISPLAY; 2281 2282 /* VM_L2_STATUS */ 2283 tmp = RREG32(VM_L2_STATUS); 2284 if (tmp & L2_BUSY) 2285 reset_mask |= RADEON_RESET_VMC; 2286 2287 return reset_mask; 2288 } 2289 2290 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2291 { 2292 struct evergreen_mc_save save; 2293 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 2294 u32 tmp; 2295 2296 if (reset_mask == 0) 2297 return; 2298 2299 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2300 2301 evergreen_print_gpu_status_regs(rdev); 2302 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 2303 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 2304 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 2305 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 2306 2307 /* Disable CP parsing/prefetching */ 2308 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2309 2310 if (reset_mask & RADEON_RESET_DMA) { 2311 /* dma0 */ 2312 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 2313 tmp &= ~DMA_RB_ENABLE; 2314 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 2315 } 2316 if (reset_mask & RADEON_RESET_DMA1) { 2317 /* dma1 */ 2318 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 2319 tmp &= ~DMA_RB_ENABLE; 2320 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 2321 } 2322 2323 udelay(50); 2324 2325 evergreen_mc_stop(rdev, &save); 2326 if (evergreen_mc_wait_for_idle(rdev)) { 2327 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2328 } 2329 2330 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) { 2331 grbm_soft_reset = SOFT_RESET_CB | 2332 SOFT_RESET_DB | 2333 SOFT_RESET_GDS | 2334 SOFT_RESET_PA | 2335 SOFT_RESET_SC | 2336 SOFT_RESET_BCI | 2337 SOFT_RESET_SPI | 2338 SOFT_RESET_SX | 2339 SOFT_RESET_TC | 2340 SOFT_RESET_TA | 2341 SOFT_RESET_VGT | 2342 SOFT_RESET_IA; 2343 } 2344 2345 if (reset_mask & RADEON_RESET_CP) { 2346 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; 2347 2348 srbm_soft_reset |= SOFT_RESET_GRBM; 2349 } 2350 2351 if (reset_mask & RADEON_RESET_DMA) 2352 srbm_soft_reset |= SOFT_RESET_DMA; 2353 2354 if (reset_mask & RADEON_RESET_DMA1) 2355 srbm_soft_reset |= SOFT_RESET_DMA1; 2356 2357 if (reset_mask & RADEON_RESET_DISPLAY) 2358 srbm_soft_reset |= SOFT_RESET_DC; 2359 2360 if (reset_mask & RADEON_RESET_RLC) 2361 grbm_soft_reset |= SOFT_RESET_RLC; 2362 2363 if (reset_mask & RADEON_RESET_SEM) 2364 srbm_soft_reset |= SOFT_RESET_SEM; 2365 2366 if (reset_mask & RADEON_RESET_IH) 2367 srbm_soft_reset |= SOFT_RESET_IH; 2368 2369 if (reset_mask & RADEON_RESET_GRBM) 2370 srbm_soft_reset |= SOFT_RESET_GRBM; 2371 2372 if (reset_mask & RADEON_RESET_VMC) 2373 srbm_soft_reset |= SOFT_RESET_VMC; 2374 2375 if (reset_mask & RADEON_RESET_MC) 2376 srbm_soft_reset |= SOFT_RESET_MC; 2377 2378 if (grbm_soft_reset) { 2379 tmp = RREG32(GRBM_SOFT_RESET); 2380 tmp |= grbm_soft_reset; 2381 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2382 WREG32(GRBM_SOFT_RESET, tmp); 2383 tmp = RREG32(GRBM_SOFT_RESET); 2384 2385 udelay(50); 2386 2387 tmp &= ~grbm_soft_reset; 2388 WREG32(GRBM_SOFT_RESET, tmp); 2389 tmp = RREG32(GRBM_SOFT_RESET); 2390 } 2391 2392 if (srbm_soft_reset) { 2393 tmp = RREG32(SRBM_SOFT_RESET); 2394 tmp |= srbm_soft_reset; 2395 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2396 WREG32(SRBM_SOFT_RESET, tmp); 2397 tmp = RREG32(SRBM_SOFT_RESET); 2398 2399 udelay(50); 2400 2401 tmp &= ~srbm_soft_reset; 2402 WREG32(SRBM_SOFT_RESET, tmp); 2403 tmp = RREG32(SRBM_SOFT_RESET); 2404 } 2405 2406 /* Wait a little for things to settle down */ 2407 udelay(50); 2408 2409 evergreen_mc_resume(rdev, &save); 2410 udelay(50); 2411 2412 evergreen_print_gpu_status_regs(rdev); 2413 } 2414 2415 int si_asic_reset(struct radeon_device *rdev) 2416 { 2417 u32 reset_mask; 2418 2419 reset_mask = si_gpu_check_soft_reset(rdev); 2420 2421 if (reset_mask) 2422 r600_set_bios_scratch_engine_hung(rdev, true); 2423 2424 si_gpu_soft_reset(rdev, reset_mask); 2425 2426 reset_mask = si_gpu_check_soft_reset(rdev); 2427 2428 if (!reset_mask) 2429 r600_set_bios_scratch_engine_hung(rdev, false); 2430 2431 return 0; 2432 } 2433 2434 /** 2435 * si_gfx_is_lockup - Check if the GFX engine is locked up 2436 * 2437 * @rdev: radeon_device pointer 2438 * @ring: radeon_ring structure holding ring information 2439 * 2440 * Check if the GFX engine is locked up. 2441 * Returns true if the engine appears to be locked up, false if not. 2442 */ 2443 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2444 { 2445 u32 reset_mask = si_gpu_check_soft_reset(rdev); 2446 2447 if (!(reset_mask & (RADEON_RESET_GFX | 2448 RADEON_RESET_COMPUTE | 2449 RADEON_RESET_CP))) { 2450 radeon_ring_lockup_update(ring); 2451 return false; 2452 } 2453 /* force CP activities */ 2454 radeon_ring_force_activity(rdev, ring); 2455 return radeon_ring_test_lockup(rdev, ring); 2456 } 2457 2458 /** 2459 * si_dma_is_lockup - Check if the DMA engine is locked up 2460 * 2461 * @rdev: radeon_device pointer 2462 * @ring: radeon_ring structure holding ring information 2463 * 2464 * Check if the async DMA engine is locked up. 2465 * Returns true if the engine appears to be locked up, false if not. 2466 */ 2467 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2468 { 2469 u32 reset_mask = si_gpu_check_soft_reset(rdev); 2470 u32 mask; 2471 2472 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 2473 mask = RADEON_RESET_DMA; 2474 else 2475 mask = RADEON_RESET_DMA1; 2476 2477 if (!(reset_mask & mask)) { 2478 radeon_ring_lockup_update(ring); 2479 return false; 2480 } 2481 /* force ring activities */ 2482 radeon_ring_force_activity(rdev, ring); 2483 return radeon_ring_test_lockup(rdev, ring); 2484 } 2485 2486 /* MC */ 2487 static void si_mc_program(struct radeon_device *rdev) 2488 { 2489 struct evergreen_mc_save save; 2490 u32 tmp; 2491 int i, j; 2492 2493 /* Initialize HDP */ 2494 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2495 WREG32((0x2c14 + j), 0x00000000); 2496 WREG32((0x2c18 + j), 0x00000000); 2497 WREG32((0x2c1c + j), 0x00000000); 2498 WREG32((0x2c20 + j), 0x00000000); 2499 WREG32((0x2c24 + j), 0x00000000); 2500 } 2501 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 2502 2503 evergreen_mc_stop(rdev, &save); 2504 if (radeon_mc_wait_for_idle(rdev)) { 2505 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2506 } 2507 /* Lockout access through VGA aperture*/ 2508 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 2509 /* Update configuration */ 2510 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 2511 rdev->mc.vram_start >> 12); 2512 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 2513 rdev->mc.vram_end >> 12); 2514 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 2515 rdev->vram_scratch.gpu_addr >> 12); 2516 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 2517 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 2518 WREG32(MC_VM_FB_LOCATION, tmp); 2519 /* XXX double check these! */ 2520 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 2521 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 2522 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 2523 WREG32(MC_VM_AGP_BASE, 0); 2524 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 2525 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 2526 if (radeon_mc_wait_for_idle(rdev)) { 2527 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2528 } 2529 evergreen_mc_resume(rdev, &save); 2530 /* we need to own VRAM, so turn off the VGA renderer here 2531 * to stop it overwriting our objects */ 2532 rv515_vga_render_disable(rdev); 2533 } 2534 2535 /* SI MC address space is 40 bits */ 2536 static void si_vram_location(struct radeon_device *rdev, 2537 struct radeon_mc *mc, u64 base) 2538 { 2539 mc->vram_start = base; 2540 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) { 2541 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 2542 mc->real_vram_size = mc->aper_size; 2543 mc->mc_vram_size = mc->aper_size; 2544 } 2545 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 2546 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 2547 mc->mc_vram_size >> 20, mc->vram_start, 2548 mc->vram_end, mc->real_vram_size >> 20); 2549 } 2550 2551 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 2552 { 2553 u64 size_af, size_bf; 2554 2555 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 2556 size_bf = mc->vram_start & ~mc->gtt_base_align; 2557 if (size_bf > size_af) { 2558 if (mc->gtt_size > size_bf) { 2559 dev_warn(rdev->dev, "limiting GTT\n"); 2560 mc->gtt_size = size_bf; 2561 } 2562 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 2563 } else { 2564 if (mc->gtt_size > size_af) { 2565 dev_warn(rdev->dev, "limiting GTT\n"); 2566 mc->gtt_size = size_af; 2567 } 2568 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 2569 } 2570 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 2571 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 2572 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 2573 } 2574 2575 static void si_vram_gtt_location(struct radeon_device *rdev, 2576 struct radeon_mc *mc) 2577 { 2578 if (mc->mc_vram_size > 0xFFC0000000ULL) { 2579 /* leave room for at least 1024M GTT */ 2580 dev_warn(rdev->dev, "limiting VRAM\n"); 2581 mc->real_vram_size = 0xFFC0000000ULL; 2582 mc->mc_vram_size = 0xFFC0000000ULL; 2583 } 2584 si_vram_location(rdev, &rdev->mc, 0); 2585 rdev->mc.gtt_base_align = 0; 2586 si_gtt_location(rdev, mc); 2587 } 2588 2589 static int si_mc_init(struct radeon_device *rdev) 2590 { 2591 u32 tmp; 2592 int chansize, numchan; 2593 2594 /* Get VRAM informations */ 2595 rdev->mc.vram_is_ddr = true; 2596 tmp = RREG32(MC_ARB_RAMCFG); 2597 if (tmp & CHANSIZE_OVERRIDE) { 2598 chansize = 16; 2599 } else if (tmp & CHANSIZE_MASK) { 2600 chansize = 64; 2601 } else { 2602 chansize = 32; 2603 } 2604 tmp = RREG32(MC_SHARED_CHMAP); 2605 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2606 case 0: 2607 default: 2608 numchan = 1; 2609 break; 2610 case 1: 2611 numchan = 2; 2612 break; 2613 case 2: 2614 numchan = 4; 2615 break; 2616 case 3: 2617 numchan = 8; 2618 break; 2619 case 4: 2620 numchan = 3; 2621 break; 2622 case 5: 2623 numchan = 6; 2624 break; 2625 case 6: 2626 numchan = 10; 2627 break; 2628 case 7: 2629 numchan = 12; 2630 break; 2631 case 8: 2632 numchan = 16; 2633 break; 2634 } 2635 rdev->mc.vram_width = numchan * chansize; 2636 /* Could aper size report 0 ? */ 2637 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2638 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2639 /* size in MB on si */ 2640 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2641 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2642 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2643 si_vram_gtt_location(rdev, &rdev->mc); 2644 radeon_update_bandwidth_info(rdev); 2645 2646 return 0; 2647 } 2648 2649 /* 2650 * GART 2651 */ 2652 void si_pcie_gart_tlb_flush(struct radeon_device *rdev) 2653 { 2654 /* flush hdp cache */ 2655 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 2656 2657 /* bits 0-15 are the VM contexts0-15 */ 2658 WREG32(VM_INVALIDATE_REQUEST, 1); 2659 } 2660 2661 static int si_pcie_gart_enable(struct radeon_device *rdev) 2662 { 2663 int r, i; 2664 2665 if (rdev->gart.robj == NULL) { 2666 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 2667 return -EINVAL; 2668 } 2669 r = radeon_gart_table_vram_pin(rdev); 2670 if (r) 2671 return r; 2672 radeon_gart_restore(rdev); 2673 /* Setup TLB control */ 2674 WREG32(MC_VM_MX_L1_TLB_CNTL, 2675 (0xA << 7) | 2676 ENABLE_L1_TLB | 2677 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2678 ENABLE_ADVANCED_DRIVER_MODEL | 2679 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2680 /* Setup L2 cache */ 2681 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 2682 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2683 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2684 EFFECTIVE_L2_QUEUE_SIZE(7) | 2685 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2686 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 2687 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2688 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2689 /* setup context0 */ 2690 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 2691 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 2692 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 2693 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 2694 (u32)(rdev->dummy_page.addr >> 12)); 2695 WREG32(VM_CONTEXT0_CNTL2, 0); 2696 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 2697 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 2698 2699 WREG32(0x15D4, 0); 2700 WREG32(0x15D8, 0); 2701 WREG32(0x15DC, 0); 2702 2703 /* empty context1-15 */ 2704 /* set vm size, must be a multiple of 4 */ 2705 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2706 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2707 /* Assign the pt base to something valid for now; the pts used for 2708 * the VMs are determined by the application and setup and assigned 2709 * on the fly in the vm part of radeon_gart.c 2710 */ 2711 for (i = 1; i < 16; i++) { 2712 if (i < 8) 2713 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2714 rdev->gart.table_addr >> 12); 2715 else 2716 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), 2717 rdev->gart.table_addr >> 12); 2718 } 2719 2720 /* enable context1-15 */ 2721 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2722 (u32)(rdev->dummy_page.addr >> 12)); 2723 WREG32(VM_CONTEXT1_CNTL2, 4); 2724 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 2725 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2726 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2727 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2728 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2729 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 2730 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 2731 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 2732 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 2733 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 2734 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 2735 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2736 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 2737 2738 si_pcie_gart_tlb_flush(rdev); 2739 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 2740 (unsigned)(rdev->mc.gtt_size >> 20), 2741 (unsigned long long)rdev->gart.table_addr); 2742 rdev->gart.ready = true; 2743 return 0; 2744 } 2745 2746 static void si_pcie_gart_disable(struct radeon_device *rdev) 2747 { 2748 /* Disable all tables */ 2749 WREG32(VM_CONTEXT0_CNTL, 0); 2750 WREG32(VM_CONTEXT1_CNTL, 0); 2751 /* Setup TLB control */ 2752 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2753 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2754 /* Setup L2 cache */ 2755 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2756 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2757 EFFECTIVE_L2_QUEUE_SIZE(7) | 2758 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2759 WREG32(VM_L2_CNTL2, 0); 2760 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2761 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2762 radeon_gart_table_vram_unpin(rdev); 2763 } 2764 2765 static void si_pcie_gart_fini(struct radeon_device *rdev) 2766 { 2767 si_pcie_gart_disable(rdev); 2768 radeon_gart_table_vram_free(rdev); 2769 radeon_gart_fini(rdev); 2770 } 2771 2772 /* vm parser */ 2773 static bool si_vm_reg_valid(u32 reg) 2774 { 2775 /* context regs are fine */ 2776 if (reg >= 0x28000) 2777 return true; 2778 2779 /* check config regs */ 2780 switch (reg) { 2781 case GRBM_GFX_INDEX: 2782 case CP_STRMOUT_CNTL: 2783 case VGT_VTX_VECT_EJECT_REG: 2784 case VGT_CACHE_INVALIDATION: 2785 case VGT_ESGS_RING_SIZE: 2786 case VGT_GSVS_RING_SIZE: 2787 case VGT_GS_VERTEX_REUSE: 2788 case VGT_PRIMITIVE_TYPE: 2789 case VGT_INDEX_TYPE: 2790 case VGT_NUM_INDICES: 2791 case VGT_NUM_INSTANCES: 2792 case VGT_TF_RING_SIZE: 2793 case VGT_HS_OFFCHIP_PARAM: 2794 case VGT_TF_MEMORY_BASE: 2795 case PA_CL_ENHANCE: 2796 case PA_SU_LINE_STIPPLE_VALUE: 2797 case PA_SC_LINE_STIPPLE_STATE: 2798 case PA_SC_ENHANCE: 2799 case SQC_CACHES: 2800 case SPI_STATIC_THREAD_MGMT_1: 2801 case SPI_STATIC_THREAD_MGMT_2: 2802 case SPI_STATIC_THREAD_MGMT_3: 2803 case SPI_PS_MAX_WAVE_ID: 2804 case SPI_CONFIG_CNTL: 2805 case SPI_CONFIG_CNTL_1: 2806 case TA_CNTL_AUX: 2807 return true; 2808 default: 2809 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 2810 return false; 2811 } 2812 } 2813 2814 static int si_vm_packet3_ce_check(struct radeon_device *rdev, 2815 u32 *ib, struct radeon_cs_packet *pkt) 2816 { 2817 switch (pkt->opcode) { 2818 case PACKET3_NOP: 2819 case PACKET3_SET_BASE: 2820 case PACKET3_SET_CE_DE_COUNTERS: 2821 case PACKET3_LOAD_CONST_RAM: 2822 case PACKET3_WRITE_CONST_RAM: 2823 case PACKET3_WRITE_CONST_RAM_OFFSET: 2824 case PACKET3_DUMP_CONST_RAM: 2825 case PACKET3_INCREMENT_CE_COUNTER: 2826 case PACKET3_WAIT_ON_DE_COUNTER: 2827 case PACKET3_CE_WRITE: 2828 break; 2829 default: 2830 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); 2831 return -EINVAL; 2832 } 2833 return 0; 2834 } 2835 2836 static int si_vm_packet3_gfx_check(struct radeon_device *rdev, 2837 u32 *ib, struct radeon_cs_packet *pkt) 2838 { 2839 u32 idx = pkt->idx + 1; 2840 u32 idx_value = ib[idx]; 2841 u32 start_reg, end_reg, reg, i; 2842 u32 command, info; 2843 2844 switch (pkt->opcode) { 2845 case PACKET3_NOP: 2846 case PACKET3_SET_BASE: 2847 case PACKET3_CLEAR_STATE: 2848 case PACKET3_INDEX_BUFFER_SIZE: 2849 case PACKET3_DISPATCH_DIRECT: 2850 case PACKET3_DISPATCH_INDIRECT: 2851 case PACKET3_ALLOC_GDS: 2852 case PACKET3_WRITE_GDS_RAM: 2853 case PACKET3_ATOMIC_GDS: 2854 case PACKET3_ATOMIC: 2855 case PACKET3_OCCLUSION_QUERY: 2856 case PACKET3_SET_PREDICATION: 2857 case PACKET3_COND_EXEC: 2858 case PACKET3_PRED_EXEC: 2859 case PACKET3_DRAW_INDIRECT: 2860 case PACKET3_DRAW_INDEX_INDIRECT: 2861 case PACKET3_INDEX_BASE: 2862 case PACKET3_DRAW_INDEX_2: 2863 case PACKET3_CONTEXT_CONTROL: 2864 case PACKET3_INDEX_TYPE: 2865 case PACKET3_DRAW_INDIRECT_MULTI: 2866 case PACKET3_DRAW_INDEX_AUTO: 2867 case PACKET3_DRAW_INDEX_IMMD: 2868 case PACKET3_NUM_INSTANCES: 2869 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2870 case PACKET3_STRMOUT_BUFFER_UPDATE: 2871 case PACKET3_DRAW_INDEX_OFFSET_2: 2872 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 2873 case PACKET3_DRAW_INDEX_INDIRECT_MULTI: 2874 case PACKET3_MPEG_INDEX: 2875 case PACKET3_WAIT_REG_MEM: 2876 case PACKET3_MEM_WRITE: 2877 case PACKET3_PFP_SYNC_ME: 2878 case PACKET3_SURFACE_SYNC: 2879 case PACKET3_EVENT_WRITE: 2880 case PACKET3_EVENT_WRITE_EOP: 2881 case PACKET3_EVENT_WRITE_EOS: 2882 case PACKET3_SET_CONTEXT_REG: 2883 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2884 case PACKET3_SET_SH_REG: 2885 case PACKET3_SET_SH_REG_OFFSET: 2886 case PACKET3_INCREMENT_DE_COUNTER: 2887 case PACKET3_WAIT_ON_CE_COUNTER: 2888 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2889 case PACKET3_ME_WRITE: 2890 break; 2891 case PACKET3_COPY_DATA: 2892 if ((idx_value & 0xf00) == 0) { 2893 reg = ib[idx + 3] * 4; 2894 if (!si_vm_reg_valid(reg)) 2895 return -EINVAL; 2896 } 2897 break; 2898 case PACKET3_WRITE_DATA: 2899 if ((idx_value & 0xf00) == 0) { 2900 start_reg = ib[idx + 1] * 4; 2901 if (idx_value & 0x10000) { 2902 if (!si_vm_reg_valid(start_reg)) 2903 return -EINVAL; 2904 } else { 2905 for (i = 0; i < (pkt->count - 2); i++) { 2906 reg = start_reg + (4 * i); 2907 if (!si_vm_reg_valid(reg)) 2908 return -EINVAL; 2909 } 2910 } 2911 } 2912 break; 2913 case PACKET3_COND_WRITE: 2914 if (idx_value & 0x100) { 2915 reg = ib[idx + 5] * 4; 2916 if (!si_vm_reg_valid(reg)) 2917 return -EINVAL; 2918 } 2919 break; 2920 case PACKET3_COPY_DW: 2921 if (idx_value & 0x2) { 2922 reg = ib[idx + 3] * 4; 2923 if (!si_vm_reg_valid(reg)) 2924 return -EINVAL; 2925 } 2926 break; 2927 case PACKET3_SET_CONFIG_REG: 2928 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2929 end_reg = 4 * pkt->count + start_reg - 4; 2930 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2931 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2932 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2933 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2934 return -EINVAL; 2935 } 2936 for (i = 0; i < pkt->count; i++) { 2937 reg = start_reg + (4 * i); 2938 if (!si_vm_reg_valid(reg)) 2939 return -EINVAL; 2940 } 2941 break; 2942 case PACKET3_CP_DMA: 2943 command = ib[idx + 4]; 2944 info = ib[idx + 1]; 2945 if (command & PACKET3_CP_DMA_CMD_SAS) { 2946 /* src address space is register */ 2947 if (((info & 0x60000000) >> 29) == 0) { 2948 start_reg = idx_value << 2; 2949 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2950 reg = start_reg; 2951 if (!si_vm_reg_valid(reg)) { 2952 DRM_ERROR("CP DMA Bad SRC register\n"); 2953 return -EINVAL; 2954 } 2955 } else { 2956 for (i = 0; i < (command & 0x1fffff); i++) { 2957 reg = start_reg + (4 * i); 2958 if (!si_vm_reg_valid(reg)) { 2959 DRM_ERROR("CP DMA Bad SRC register\n"); 2960 return -EINVAL; 2961 } 2962 } 2963 } 2964 } 2965 } 2966 if (command & PACKET3_CP_DMA_CMD_DAS) { 2967 /* dst address space is register */ 2968 if (((info & 0x00300000) >> 20) == 0) { 2969 start_reg = ib[idx + 2]; 2970 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2971 reg = start_reg; 2972 if (!si_vm_reg_valid(reg)) { 2973 DRM_ERROR("CP DMA Bad DST register\n"); 2974 return -EINVAL; 2975 } 2976 } else { 2977 for (i = 0; i < (command & 0x1fffff); i++) { 2978 reg = start_reg + (4 * i); 2979 if (!si_vm_reg_valid(reg)) { 2980 DRM_ERROR("CP DMA Bad DST register\n"); 2981 return -EINVAL; 2982 } 2983 } 2984 } 2985 } 2986 } 2987 break; 2988 default: 2989 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); 2990 return -EINVAL; 2991 } 2992 return 0; 2993 } 2994 2995 static int si_vm_packet3_compute_check(struct radeon_device *rdev, 2996 u32 *ib, struct radeon_cs_packet *pkt) 2997 { 2998 u32 idx = pkt->idx + 1; 2999 u32 idx_value = ib[idx]; 3000 u32 start_reg, reg, i; 3001 3002 switch (pkt->opcode) { 3003 case PACKET3_NOP: 3004 case PACKET3_SET_BASE: 3005 case PACKET3_CLEAR_STATE: 3006 case PACKET3_DISPATCH_DIRECT: 3007 case PACKET3_DISPATCH_INDIRECT: 3008 case PACKET3_ALLOC_GDS: 3009 case PACKET3_WRITE_GDS_RAM: 3010 case PACKET3_ATOMIC_GDS: 3011 case PACKET3_ATOMIC: 3012 case PACKET3_OCCLUSION_QUERY: 3013 case PACKET3_SET_PREDICATION: 3014 case PACKET3_COND_EXEC: 3015 case PACKET3_PRED_EXEC: 3016 case PACKET3_CONTEXT_CONTROL: 3017 case PACKET3_STRMOUT_BUFFER_UPDATE: 3018 case PACKET3_WAIT_REG_MEM: 3019 case PACKET3_MEM_WRITE: 3020 case PACKET3_PFP_SYNC_ME: 3021 case PACKET3_SURFACE_SYNC: 3022 case PACKET3_EVENT_WRITE: 3023 case PACKET3_EVENT_WRITE_EOP: 3024 case PACKET3_EVENT_WRITE_EOS: 3025 case PACKET3_SET_CONTEXT_REG: 3026 case PACKET3_SET_CONTEXT_REG_INDIRECT: 3027 case PACKET3_SET_SH_REG: 3028 case PACKET3_SET_SH_REG_OFFSET: 3029 case PACKET3_INCREMENT_DE_COUNTER: 3030 case PACKET3_WAIT_ON_CE_COUNTER: 3031 case PACKET3_WAIT_ON_AVAIL_BUFFER: 3032 case PACKET3_ME_WRITE: 3033 break; 3034 case PACKET3_COPY_DATA: 3035 if ((idx_value & 0xf00) == 0) { 3036 reg = ib[idx + 3] * 4; 3037 if (!si_vm_reg_valid(reg)) 3038 return -EINVAL; 3039 } 3040 break; 3041 case PACKET3_WRITE_DATA: 3042 if ((idx_value & 0xf00) == 0) { 3043 start_reg = ib[idx + 1] * 4; 3044 if (idx_value & 0x10000) { 3045 if (!si_vm_reg_valid(start_reg)) 3046 return -EINVAL; 3047 } else { 3048 for (i = 0; i < (pkt->count - 2); i++) { 3049 reg = start_reg + (4 * i); 3050 if (!si_vm_reg_valid(reg)) 3051 return -EINVAL; 3052 } 3053 } 3054 } 3055 break; 3056 case PACKET3_COND_WRITE: 3057 if (idx_value & 0x100) { 3058 reg = ib[idx + 5] * 4; 3059 if (!si_vm_reg_valid(reg)) 3060 return -EINVAL; 3061 } 3062 break; 3063 case PACKET3_COPY_DW: 3064 if (idx_value & 0x2) { 3065 reg = ib[idx + 3] * 4; 3066 if (!si_vm_reg_valid(reg)) 3067 return -EINVAL; 3068 } 3069 break; 3070 default: 3071 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); 3072 return -EINVAL; 3073 } 3074 return 0; 3075 } 3076 3077 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 3078 { 3079 int ret = 0; 3080 u32 idx = 0; 3081 struct radeon_cs_packet pkt; 3082 3083 do { 3084 pkt.idx = idx; 3085 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); 3086 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); 3087 pkt.one_reg_wr = 0; 3088 switch (pkt.type) { 3089 case RADEON_PACKET_TYPE0: 3090 dev_err(rdev->dev, "Packet0 not allowed!\n"); 3091 ret = -EINVAL; 3092 break; 3093 case RADEON_PACKET_TYPE2: 3094 idx += 1; 3095 break; 3096 case RADEON_PACKET_TYPE3: 3097 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3098 if (ib->is_const_ib) 3099 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 3100 else { 3101 switch (ib->ring) { 3102 case RADEON_RING_TYPE_GFX_INDEX: 3103 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); 3104 break; 3105 case CAYMAN_RING_TYPE_CP1_INDEX: 3106 case CAYMAN_RING_TYPE_CP2_INDEX: 3107 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); 3108 break; 3109 default: 3110 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); 3111 ret = -EINVAL; 3112 break; 3113 } 3114 } 3115 idx += pkt.count + 2; 3116 break; 3117 default: 3118 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 3119 ret = -EINVAL; 3120 break; 3121 } 3122 if (ret) 3123 break; 3124 } while (idx < ib->length_dw); 3125 3126 return ret; 3127 } 3128 3129 /* 3130 * vm 3131 */ 3132 int si_vm_init(struct radeon_device *rdev) 3133 { 3134 /* number of VMs */ 3135 rdev->vm_manager.nvm = 16; 3136 /* base offset of vram pages */ 3137 rdev->vm_manager.vram_base_offset = 0; 3138 3139 return 0; 3140 } 3141 3142 void si_vm_fini(struct radeon_device *rdev) 3143 { 3144 } 3145 3146 /** 3147 * si_vm_set_page - update the page tables using the CP 3148 * 3149 * @rdev: radeon_device pointer 3150 * @ib: indirect buffer to fill with commands 3151 * @pe: addr of the page entry 3152 * @addr: dst addr to write into pe 3153 * @count: number of page entries to update 3154 * @incr: increase next addr by incr bytes 3155 * @flags: access flags 3156 * 3157 * Update the page tables using the CP (SI). 3158 */ 3159 void si_vm_set_page(struct radeon_device *rdev, 3160 struct radeon_ib *ib, 3161 uint64_t pe, 3162 uint64_t addr, unsigned count, 3163 uint32_t incr, uint32_t flags) 3164 { 3165 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 3166 uint64_t value; 3167 unsigned ndw; 3168 3169 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { 3170 while (count) { 3171 ndw = 2 + count * 2; 3172 if (ndw > 0x3FFE) 3173 ndw = 0x3FFE; 3174 3175 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw); 3176 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) | 3177 WRITE_DATA_DST_SEL(1)); 3178 ib->ptr[ib->length_dw++] = pe; 3179 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 3180 for (; ndw > 2; ndw -= 2, --count, pe += 8) { 3181 if (flags & RADEON_VM_PAGE_SYSTEM) { 3182 value = radeon_vm_map_gart(rdev, addr); 3183 value &= 0xFFFFFFFFFFFFF000ULL; 3184 } else if (flags & RADEON_VM_PAGE_VALID) { 3185 value = addr; 3186 } else { 3187 value = 0; 3188 } 3189 addr += incr; 3190 value |= r600_flags; 3191 ib->ptr[ib->length_dw++] = value; 3192 ib->ptr[ib->length_dw++] = upper_32_bits(value); 3193 } 3194 } 3195 } else { 3196 /* DMA */ 3197 if (flags & RADEON_VM_PAGE_SYSTEM) { 3198 while (count) { 3199 ndw = count * 2; 3200 if (ndw > 0xFFFFE) 3201 ndw = 0xFFFFE; 3202 3203 /* for non-physically contiguous pages (system) */ 3204 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); 3205 ib->ptr[ib->length_dw++] = pe; 3206 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 3207 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 3208 if (flags & RADEON_VM_PAGE_SYSTEM) { 3209 value = radeon_vm_map_gart(rdev, addr); 3210 value &= 0xFFFFFFFFFFFFF000ULL; 3211 } else if (flags & RADEON_VM_PAGE_VALID) { 3212 value = addr; 3213 } else { 3214 value = 0; 3215 } 3216 addr += incr; 3217 value |= r600_flags; 3218 ib->ptr[ib->length_dw++] = value; 3219 ib->ptr[ib->length_dw++] = upper_32_bits(value); 3220 } 3221 } 3222 } else { 3223 while (count) { 3224 ndw = count * 2; 3225 if (ndw > 0xFFFFE) 3226 ndw = 0xFFFFE; 3227 3228 if (flags & RADEON_VM_PAGE_VALID) 3229 value = addr; 3230 else 3231 value = 0; 3232 /* for physically contiguous pages (vram) */ 3233 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); 3234 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 3235 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 3236 ib->ptr[ib->length_dw++] = r600_flags; /* mask */ 3237 ib->ptr[ib->length_dw++] = 0; 3238 ib->ptr[ib->length_dw++] = value; /* value */ 3239 ib->ptr[ib->length_dw++] = upper_32_bits(value); 3240 ib->ptr[ib->length_dw++] = incr; /* increment size */ 3241 ib->ptr[ib->length_dw++] = 0; 3242 pe += ndw * 4; 3243 addr += (ndw / 2) * incr; 3244 count -= ndw / 2; 3245 } 3246 } 3247 while (ib->length_dw & 0x7) 3248 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); 3249 } 3250 } 3251 3252 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3253 { 3254 struct radeon_ring *ring = &rdev->ring[ridx]; 3255 3256 if (vm == NULL) 3257 return; 3258 3259 /* write new base address */ 3260 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3261 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3262 WRITE_DATA_DST_SEL(0))); 3263 3264 if (vm->id < 8) { 3265 radeon_ring_write(ring, 3266 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 3267 } else { 3268 radeon_ring_write(ring, 3269 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 3270 } 3271 radeon_ring_write(ring, 0); 3272 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3273 3274 /* flush hdp cache */ 3275 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3276 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3277 WRITE_DATA_DST_SEL(0))); 3278 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 3279 radeon_ring_write(ring, 0); 3280 radeon_ring_write(ring, 0x1); 3281 3282 /* bits 0-15 are the VM contexts0-15 */ 3283 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3284 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3285 WRITE_DATA_DST_SEL(0))); 3286 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 3287 radeon_ring_write(ring, 0); 3288 radeon_ring_write(ring, 1 << vm->id); 3289 3290 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3291 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3292 radeon_ring_write(ring, 0x0); 3293 } 3294 3295 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3296 { 3297 struct radeon_ring *ring = &rdev->ring[ridx]; 3298 3299 if (vm == NULL) 3300 return; 3301 3302 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3303 if (vm->id < 8) { 3304 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); 3305 } else { 3306 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2)); 3307 } 3308 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3309 3310 /* flush hdp cache */ 3311 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3312 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3313 radeon_ring_write(ring, 1); 3314 3315 /* bits 0-7 are the VM contexts0-7 */ 3316 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3317 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); 3318 radeon_ring_write(ring, 1 << vm->id); 3319 } 3320 3321 /* 3322 * RLC 3323 */ 3324 void si_rlc_fini(struct radeon_device *rdev) 3325 { 3326 int r; 3327 3328 /* save restore block */ 3329 if (rdev->rlc.save_restore_obj) { 3330 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3331 if (unlikely(r != 0)) 3332 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); 3333 radeon_bo_unpin(rdev->rlc.save_restore_obj); 3334 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3335 3336 radeon_bo_unref(&rdev->rlc.save_restore_obj); 3337 rdev->rlc.save_restore_obj = NULL; 3338 } 3339 3340 /* clear state block */ 3341 if (rdev->rlc.clear_state_obj) { 3342 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3343 if (unlikely(r != 0)) 3344 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); 3345 radeon_bo_unpin(rdev->rlc.clear_state_obj); 3346 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3347 3348 radeon_bo_unref(&rdev->rlc.clear_state_obj); 3349 rdev->rlc.clear_state_obj = NULL; 3350 } 3351 } 3352 3353 int si_rlc_init(struct radeon_device *rdev) 3354 { 3355 int r; 3356 3357 /* save restore block */ 3358 if (rdev->rlc.save_restore_obj == NULL) { 3359 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3360 RADEON_GEM_DOMAIN_VRAM, NULL, 3361 &rdev->rlc.save_restore_obj); 3362 if (r) { 3363 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 3364 return r; 3365 } 3366 } 3367 3368 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3369 if (unlikely(r != 0)) { 3370 si_rlc_fini(rdev); 3371 return r; 3372 } 3373 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, 3374 &rdev->rlc.save_restore_gpu_addr); 3375 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3376 if (r) { 3377 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); 3378 si_rlc_fini(rdev); 3379 return r; 3380 } 3381 3382 /* clear state block */ 3383 if (rdev->rlc.clear_state_obj == NULL) { 3384 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3385 RADEON_GEM_DOMAIN_VRAM, NULL, 3386 &rdev->rlc.clear_state_obj); 3387 if (r) { 3388 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 3389 si_rlc_fini(rdev); 3390 return r; 3391 } 3392 } 3393 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3394 if (unlikely(r != 0)) { 3395 si_rlc_fini(rdev); 3396 return r; 3397 } 3398 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, 3399 &rdev->rlc.clear_state_gpu_addr); 3400 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3401 if (r) { 3402 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); 3403 si_rlc_fini(rdev); 3404 return r; 3405 } 3406 3407 return 0; 3408 } 3409 3410 static void si_rlc_stop(struct radeon_device *rdev) 3411 { 3412 WREG32(RLC_CNTL, 0); 3413 } 3414 3415 static void si_rlc_start(struct radeon_device *rdev) 3416 { 3417 WREG32(RLC_CNTL, RLC_ENABLE); 3418 } 3419 3420 static int si_rlc_resume(struct radeon_device *rdev) 3421 { 3422 u32 i; 3423 const __be32 *fw_data; 3424 3425 if (!rdev->rlc_fw) 3426 return -EINVAL; 3427 3428 si_rlc_stop(rdev); 3429 3430 WREG32(RLC_RL_BASE, 0); 3431 WREG32(RLC_RL_SIZE, 0); 3432 WREG32(RLC_LB_CNTL, 0); 3433 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 3434 WREG32(RLC_LB_CNTR_INIT, 0); 3435 3436 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3437 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3438 3439 WREG32(RLC_MC_CNTL, 0); 3440 WREG32(RLC_UCODE_CNTL, 0); 3441 3442 fw_data = (const __be32 *)rdev->rlc_fw->data; 3443 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { 3444 WREG32(RLC_UCODE_ADDR, i); 3445 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3446 } 3447 WREG32(RLC_UCODE_ADDR, 0); 3448 3449 si_rlc_start(rdev); 3450 3451 return 0; 3452 } 3453 3454 static void si_enable_interrupts(struct radeon_device *rdev) 3455 { 3456 u32 ih_cntl = RREG32(IH_CNTL); 3457 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3458 3459 ih_cntl |= ENABLE_INTR; 3460 ih_rb_cntl |= IH_RB_ENABLE; 3461 WREG32(IH_CNTL, ih_cntl); 3462 WREG32(IH_RB_CNTL, ih_rb_cntl); 3463 rdev->ih.enabled = true; 3464 } 3465 3466 static void si_disable_interrupts(struct radeon_device *rdev) 3467 { 3468 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3469 u32 ih_cntl = RREG32(IH_CNTL); 3470 3471 ih_rb_cntl &= ~IH_RB_ENABLE; 3472 ih_cntl &= ~ENABLE_INTR; 3473 WREG32(IH_RB_CNTL, ih_rb_cntl); 3474 WREG32(IH_CNTL, ih_cntl); 3475 /* set rptr, wptr to 0 */ 3476 WREG32(IH_RB_RPTR, 0); 3477 WREG32(IH_RB_WPTR, 0); 3478 rdev->ih.enabled = false; 3479 rdev->ih.rptr = 0; 3480 } 3481 3482 static void si_disable_interrupt_state(struct radeon_device *rdev) 3483 { 3484 u32 tmp; 3485 3486 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3487 WREG32(CP_INT_CNTL_RING1, 0); 3488 WREG32(CP_INT_CNTL_RING2, 0); 3489 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3490 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); 3491 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3492 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 3493 WREG32(GRBM_INT_CNTL, 0); 3494 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3495 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3496 if (rdev->num_crtc >= 4) { 3497 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3498 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3499 } 3500 if (rdev->num_crtc >= 6) { 3501 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3502 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3503 } 3504 3505 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3506 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3507 if (rdev->num_crtc >= 4) { 3508 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3509 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3510 } 3511 if (rdev->num_crtc >= 6) { 3512 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3513 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3514 } 3515 3516 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3517 3518 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3519 WREG32(DC_HPD1_INT_CONTROL, tmp); 3520 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3521 WREG32(DC_HPD2_INT_CONTROL, tmp); 3522 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3523 WREG32(DC_HPD3_INT_CONTROL, tmp); 3524 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3525 WREG32(DC_HPD4_INT_CONTROL, tmp); 3526 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3527 WREG32(DC_HPD5_INT_CONTROL, tmp); 3528 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3529 WREG32(DC_HPD6_INT_CONTROL, tmp); 3530 3531 } 3532 3533 static int si_irq_init(struct radeon_device *rdev) 3534 { 3535 int ret = 0; 3536 int rb_bufsz; 3537 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3538 3539 /* allocate ring */ 3540 ret = r600_ih_ring_alloc(rdev); 3541 if (ret) 3542 return ret; 3543 3544 /* disable irqs */ 3545 si_disable_interrupts(rdev); 3546 3547 /* init rlc */ 3548 ret = si_rlc_resume(rdev); 3549 if (ret) { 3550 r600_ih_ring_fini(rdev); 3551 return ret; 3552 } 3553 3554 /* setup interrupt control */ 3555 /* set dummy read address to ring address */ 3556 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3557 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3558 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3559 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3560 */ 3561 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3562 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3563 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3564 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3565 3566 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3567 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3568 3569 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3570 IH_WPTR_OVERFLOW_CLEAR | 3571 (rb_bufsz << 1)); 3572 3573 if (rdev->wb.enabled) 3574 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3575 3576 /* set the writeback address whether it's enabled or not */ 3577 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3578 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3579 3580 WREG32(IH_RB_CNTL, ih_rb_cntl); 3581 3582 /* set rptr, wptr to 0 */ 3583 WREG32(IH_RB_RPTR, 0); 3584 WREG32(IH_RB_WPTR, 0); 3585 3586 /* Default settings for IH_CNTL (disabled at first) */ 3587 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 3588 /* RPTR_REARM only works if msi's are enabled */ 3589 if (rdev->msi_enabled) 3590 ih_cntl |= RPTR_REARM; 3591 WREG32(IH_CNTL, ih_cntl); 3592 3593 /* force the active interrupt state to all disabled */ 3594 si_disable_interrupt_state(rdev); 3595 3596 pci_set_master(rdev->pdev); 3597 3598 /* enable irqs */ 3599 si_enable_interrupts(rdev); 3600 3601 return ret; 3602 } 3603 3604 int si_irq_set(struct radeon_device *rdev) 3605 { 3606 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3607 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 3608 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 3609 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 3610 u32 grbm_int_cntl = 0; 3611 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 3612 u32 dma_cntl, dma_cntl1; 3613 3614 if (!rdev->irq.installed) { 3615 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3616 return -EINVAL; 3617 } 3618 /* don't enable anything if the ih is disabled */ 3619 if (!rdev->ih.enabled) { 3620 si_disable_interrupts(rdev); 3621 /* force the active interrupt state to all disabled */ 3622 si_disable_interrupt_state(rdev); 3623 return 0; 3624 } 3625 3626 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3627 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3628 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3629 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3630 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3631 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3632 3633 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3634 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3635 3636 /* enable CP interrupts on all rings */ 3637 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3638 DRM_DEBUG("si_irq_set: sw int gfx\n"); 3639 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3640 } 3641 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { 3642 DRM_DEBUG("si_irq_set: sw int cp1\n"); 3643 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 3644 } 3645 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { 3646 DRM_DEBUG("si_irq_set: sw int cp2\n"); 3647 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 3648 } 3649 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3650 DRM_DEBUG("si_irq_set: sw int dma\n"); 3651 dma_cntl |= TRAP_ENABLE; 3652 } 3653 3654 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { 3655 DRM_DEBUG("si_irq_set: sw int dma1\n"); 3656 dma_cntl1 |= TRAP_ENABLE; 3657 } 3658 if (rdev->irq.crtc_vblank_int[0] || 3659 atomic_read(&rdev->irq.pflip[0])) { 3660 DRM_DEBUG("si_irq_set: vblank 0\n"); 3661 crtc1 |= VBLANK_INT_MASK; 3662 } 3663 if (rdev->irq.crtc_vblank_int[1] || 3664 atomic_read(&rdev->irq.pflip[1])) { 3665 DRM_DEBUG("si_irq_set: vblank 1\n"); 3666 crtc2 |= VBLANK_INT_MASK; 3667 } 3668 if (rdev->irq.crtc_vblank_int[2] || 3669 atomic_read(&rdev->irq.pflip[2])) { 3670 DRM_DEBUG("si_irq_set: vblank 2\n"); 3671 crtc3 |= VBLANK_INT_MASK; 3672 } 3673 if (rdev->irq.crtc_vblank_int[3] || 3674 atomic_read(&rdev->irq.pflip[3])) { 3675 DRM_DEBUG("si_irq_set: vblank 3\n"); 3676 crtc4 |= VBLANK_INT_MASK; 3677 } 3678 if (rdev->irq.crtc_vblank_int[4] || 3679 atomic_read(&rdev->irq.pflip[4])) { 3680 DRM_DEBUG("si_irq_set: vblank 4\n"); 3681 crtc5 |= VBLANK_INT_MASK; 3682 } 3683 if (rdev->irq.crtc_vblank_int[5] || 3684 atomic_read(&rdev->irq.pflip[5])) { 3685 DRM_DEBUG("si_irq_set: vblank 5\n"); 3686 crtc6 |= VBLANK_INT_MASK; 3687 } 3688 if (rdev->irq.hpd[0]) { 3689 DRM_DEBUG("si_irq_set: hpd 1\n"); 3690 hpd1 |= DC_HPDx_INT_EN; 3691 } 3692 if (rdev->irq.hpd[1]) { 3693 DRM_DEBUG("si_irq_set: hpd 2\n"); 3694 hpd2 |= DC_HPDx_INT_EN; 3695 } 3696 if (rdev->irq.hpd[2]) { 3697 DRM_DEBUG("si_irq_set: hpd 3\n"); 3698 hpd3 |= DC_HPDx_INT_EN; 3699 } 3700 if (rdev->irq.hpd[3]) { 3701 DRM_DEBUG("si_irq_set: hpd 4\n"); 3702 hpd4 |= DC_HPDx_INT_EN; 3703 } 3704 if (rdev->irq.hpd[4]) { 3705 DRM_DEBUG("si_irq_set: hpd 5\n"); 3706 hpd5 |= DC_HPDx_INT_EN; 3707 } 3708 if (rdev->irq.hpd[5]) { 3709 DRM_DEBUG("si_irq_set: hpd 6\n"); 3710 hpd6 |= DC_HPDx_INT_EN; 3711 } 3712 3713 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3714 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); 3715 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); 3716 3717 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); 3718 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); 3719 3720 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3721 3722 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 3723 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 3724 if (rdev->num_crtc >= 4) { 3725 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 3726 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 3727 } 3728 if (rdev->num_crtc >= 6) { 3729 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 3730 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 3731 } 3732 3733 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 3734 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 3735 if (rdev->num_crtc >= 4) { 3736 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 3737 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 3738 } 3739 if (rdev->num_crtc >= 6) { 3740 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 3741 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 3742 } 3743 3744 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3745 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3746 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3747 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3748 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3749 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3750 3751 return 0; 3752 } 3753 3754 static inline void si_irq_ack(struct radeon_device *rdev) 3755 { 3756 u32 tmp; 3757 3758 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3759 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3760 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 3761 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 3762 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 3763 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 3764 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 3765 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 3766 if (rdev->num_crtc >= 4) { 3767 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 3768 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 3769 } 3770 if (rdev->num_crtc >= 6) { 3771 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 3772 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 3773 } 3774 3775 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 3776 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3777 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 3778 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3779 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 3780 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 3781 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 3782 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 3783 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 3784 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 3785 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 3786 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 3787 3788 if (rdev->num_crtc >= 4) { 3789 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 3790 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3791 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 3792 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3793 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 3794 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 3795 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 3796 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 3797 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 3798 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 3799 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 3800 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 3801 } 3802 3803 if (rdev->num_crtc >= 6) { 3804 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 3805 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3806 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 3807 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3808 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 3809 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 3810 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 3811 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 3812 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 3813 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 3814 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 3815 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 3816 } 3817 3818 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3819 tmp = RREG32(DC_HPD1_INT_CONTROL); 3820 tmp |= DC_HPDx_INT_ACK; 3821 WREG32(DC_HPD1_INT_CONTROL, tmp); 3822 } 3823 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3824 tmp = RREG32(DC_HPD2_INT_CONTROL); 3825 tmp |= DC_HPDx_INT_ACK; 3826 WREG32(DC_HPD2_INT_CONTROL, tmp); 3827 } 3828 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3829 tmp = RREG32(DC_HPD3_INT_CONTROL); 3830 tmp |= DC_HPDx_INT_ACK; 3831 WREG32(DC_HPD3_INT_CONTROL, tmp); 3832 } 3833 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3834 tmp = RREG32(DC_HPD4_INT_CONTROL); 3835 tmp |= DC_HPDx_INT_ACK; 3836 WREG32(DC_HPD4_INT_CONTROL, tmp); 3837 } 3838 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3839 tmp = RREG32(DC_HPD5_INT_CONTROL); 3840 tmp |= DC_HPDx_INT_ACK; 3841 WREG32(DC_HPD5_INT_CONTROL, tmp); 3842 } 3843 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3844 tmp = RREG32(DC_HPD5_INT_CONTROL); 3845 tmp |= DC_HPDx_INT_ACK; 3846 WREG32(DC_HPD6_INT_CONTROL, tmp); 3847 } 3848 } 3849 3850 static void si_irq_disable(struct radeon_device *rdev) 3851 { 3852 si_disable_interrupts(rdev); 3853 /* Wait and acknowledge irq */ 3854 mdelay(1); 3855 si_irq_ack(rdev); 3856 si_disable_interrupt_state(rdev); 3857 } 3858 3859 static void si_irq_suspend(struct radeon_device *rdev) 3860 { 3861 si_irq_disable(rdev); 3862 si_rlc_stop(rdev); 3863 } 3864 3865 static void si_irq_fini(struct radeon_device *rdev) 3866 { 3867 si_irq_suspend(rdev); 3868 r600_ih_ring_fini(rdev); 3869 } 3870 3871 static inline u32 si_get_ih_wptr(struct radeon_device *rdev) 3872 { 3873 u32 wptr, tmp; 3874 3875 if (rdev->wb.enabled) 3876 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3877 else 3878 wptr = RREG32(IH_RB_WPTR); 3879 3880 if (wptr & RB_OVERFLOW) { 3881 /* When a ring buffer overflow happen start parsing interrupt 3882 * from the last not overwritten vector (wptr + 16). Hopefully 3883 * this should allow us to catchup. 3884 */ 3885 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3886 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3887 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3888 tmp = RREG32(IH_RB_CNTL); 3889 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3890 WREG32(IH_RB_CNTL, tmp); 3891 } 3892 return (wptr & rdev->ih.ptr_mask); 3893 } 3894 3895 /* SI IV Ring 3896 * Each IV ring entry is 128 bits: 3897 * [7:0] - interrupt source id 3898 * [31:8] - reserved 3899 * [59:32] - interrupt source data 3900 * [63:60] - reserved 3901 * [71:64] - RINGID 3902 * [79:72] - VMID 3903 * [127:80] - reserved 3904 */ 3905 int si_irq_process(struct radeon_device *rdev) 3906 { 3907 u32 wptr; 3908 u32 rptr; 3909 u32 src_id, src_data, ring_id; 3910 u32 ring_index; 3911 bool queue_hotplug = false; 3912 3913 if (!rdev->ih.enabled || rdev->shutdown) 3914 return IRQ_NONE; 3915 3916 wptr = si_get_ih_wptr(rdev); 3917 3918 restart_ih: 3919 /* is somebody else already processing irqs? */ 3920 if (atomic_xchg(&rdev->ih.lock, 1)) 3921 return IRQ_NONE; 3922 3923 rptr = rdev->ih.rptr; 3924 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3925 3926 /* Order reading of wptr vs. reading of IH ring data */ 3927 rmb(); 3928 3929 /* display interrupts */ 3930 si_irq_ack(rdev); 3931 3932 while (rptr != wptr) { 3933 /* wptr/rptr are in bytes! */ 3934 ring_index = rptr / 4; 3935 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3936 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3937 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; 3938 3939 switch (src_id) { 3940 case 1: /* D1 vblank/vline */ 3941 switch (src_data) { 3942 case 0: /* D1 vblank */ 3943 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 3944 if (rdev->irq.crtc_vblank_int[0]) { 3945 drm_handle_vblank(rdev->ddev, 0); 3946 rdev->pm.vblank_sync = true; 3947 wake_up(&rdev->irq.vblank_queue); 3948 } 3949 if (atomic_read(&rdev->irq.pflip[0])) 3950 radeon_crtc_handle_flip(rdev, 0); 3951 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3952 DRM_DEBUG("IH: D1 vblank\n"); 3953 } 3954 break; 3955 case 1: /* D1 vline */ 3956 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 3957 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3958 DRM_DEBUG("IH: D1 vline\n"); 3959 } 3960 break; 3961 default: 3962 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3963 break; 3964 } 3965 break; 3966 case 2: /* D2 vblank/vline */ 3967 switch (src_data) { 3968 case 0: /* D2 vblank */ 3969 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 3970 if (rdev->irq.crtc_vblank_int[1]) { 3971 drm_handle_vblank(rdev->ddev, 1); 3972 rdev->pm.vblank_sync = true; 3973 wake_up(&rdev->irq.vblank_queue); 3974 } 3975 if (atomic_read(&rdev->irq.pflip[1])) 3976 radeon_crtc_handle_flip(rdev, 1); 3977 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 3978 DRM_DEBUG("IH: D2 vblank\n"); 3979 } 3980 break; 3981 case 1: /* D2 vline */ 3982 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 3983 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 3984 DRM_DEBUG("IH: D2 vline\n"); 3985 } 3986 break; 3987 default: 3988 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3989 break; 3990 } 3991 break; 3992 case 3: /* D3 vblank/vline */ 3993 switch (src_data) { 3994 case 0: /* D3 vblank */ 3995 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 3996 if (rdev->irq.crtc_vblank_int[2]) { 3997 drm_handle_vblank(rdev->ddev, 2); 3998 rdev->pm.vblank_sync = true; 3999 wake_up(&rdev->irq.vblank_queue); 4000 } 4001 if (atomic_read(&rdev->irq.pflip[2])) 4002 radeon_crtc_handle_flip(rdev, 2); 4003 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 4004 DRM_DEBUG("IH: D3 vblank\n"); 4005 } 4006 break; 4007 case 1: /* D3 vline */ 4008 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 4009 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 4010 DRM_DEBUG("IH: D3 vline\n"); 4011 } 4012 break; 4013 default: 4014 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4015 break; 4016 } 4017 break; 4018 case 4: /* D4 vblank/vline */ 4019 switch (src_data) { 4020 case 0: /* D4 vblank */ 4021 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 4022 if (rdev->irq.crtc_vblank_int[3]) { 4023 drm_handle_vblank(rdev->ddev, 3); 4024 rdev->pm.vblank_sync = true; 4025 wake_up(&rdev->irq.vblank_queue); 4026 } 4027 if (atomic_read(&rdev->irq.pflip[3])) 4028 radeon_crtc_handle_flip(rdev, 3); 4029 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 4030 DRM_DEBUG("IH: D4 vblank\n"); 4031 } 4032 break; 4033 case 1: /* D4 vline */ 4034 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 4035 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 4036 DRM_DEBUG("IH: D4 vline\n"); 4037 } 4038 break; 4039 default: 4040 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4041 break; 4042 } 4043 break; 4044 case 5: /* D5 vblank/vline */ 4045 switch (src_data) { 4046 case 0: /* D5 vblank */ 4047 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 4048 if (rdev->irq.crtc_vblank_int[4]) { 4049 drm_handle_vblank(rdev->ddev, 4); 4050 rdev->pm.vblank_sync = true; 4051 wake_up(&rdev->irq.vblank_queue); 4052 } 4053 if (atomic_read(&rdev->irq.pflip[4])) 4054 radeon_crtc_handle_flip(rdev, 4); 4055 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 4056 DRM_DEBUG("IH: D5 vblank\n"); 4057 } 4058 break; 4059 case 1: /* D5 vline */ 4060 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 4061 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 4062 DRM_DEBUG("IH: D5 vline\n"); 4063 } 4064 break; 4065 default: 4066 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4067 break; 4068 } 4069 break; 4070 case 6: /* D6 vblank/vline */ 4071 switch (src_data) { 4072 case 0: /* D6 vblank */ 4073 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 4074 if (rdev->irq.crtc_vblank_int[5]) { 4075 drm_handle_vblank(rdev->ddev, 5); 4076 rdev->pm.vblank_sync = true; 4077 wake_up(&rdev->irq.vblank_queue); 4078 } 4079 if (atomic_read(&rdev->irq.pflip[5])) 4080 radeon_crtc_handle_flip(rdev, 5); 4081 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 4082 DRM_DEBUG("IH: D6 vblank\n"); 4083 } 4084 break; 4085 case 1: /* D6 vline */ 4086 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 4087 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 4088 DRM_DEBUG("IH: D6 vline\n"); 4089 } 4090 break; 4091 default: 4092 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4093 break; 4094 } 4095 break; 4096 case 42: /* HPD hotplug */ 4097 switch (src_data) { 4098 case 0: 4099 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 4100 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 4101 queue_hotplug = true; 4102 DRM_DEBUG("IH: HPD1\n"); 4103 } 4104 break; 4105 case 1: 4106 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 4107 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 4108 queue_hotplug = true; 4109 DRM_DEBUG("IH: HPD2\n"); 4110 } 4111 break; 4112 case 2: 4113 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 4114 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 4115 queue_hotplug = true; 4116 DRM_DEBUG("IH: HPD3\n"); 4117 } 4118 break; 4119 case 3: 4120 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 4121 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 4122 queue_hotplug = true; 4123 DRM_DEBUG("IH: HPD4\n"); 4124 } 4125 break; 4126 case 4: 4127 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 4128 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 4129 queue_hotplug = true; 4130 DRM_DEBUG("IH: HPD5\n"); 4131 } 4132 break; 4133 case 5: 4134 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 4135 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 4136 queue_hotplug = true; 4137 DRM_DEBUG("IH: HPD6\n"); 4138 } 4139 break; 4140 default: 4141 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4142 break; 4143 } 4144 break; 4145 case 146: 4146 case 147: 4147 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 4148 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 4149 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 4150 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 4151 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 4152 /* reset addr and status */ 4153 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 4154 break; 4155 case 176: /* RINGID0 CP_INT */ 4156 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4157 break; 4158 case 177: /* RINGID1 CP_INT */ 4159 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4160 break; 4161 case 178: /* RINGID2 CP_INT */ 4162 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4163 break; 4164 case 181: /* CP EOP event */ 4165 DRM_DEBUG("IH: CP EOP\n"); 4166 switch (ring_id) { 4167 case 0: 4168 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4169 break; 4170 case 1: 4171 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4172 break; 4173 case 2: 4174 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4175 break; 4176 } 4177 break; 4178 case 224: /* DMA trap event */ 4179 DRM_DEBUG("IH: DMA trap\n"); 4180 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4181 break; 4182 case 233: /* GUI IDLE */ 4183 DRM_DEBUG("IH: GUI idle\n"); 4184 break; 4185 case 244: /* DMA trap event */ 4186 DRM_DEBUG("IH: DMA1 trap\n"); 4187 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4188 break; 4189 default: 4190 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4191 break; 4192 } 4193 4194 /* wptr/rptr are in bytes! */ 4195 rptr += 16; 4196 rptr &= rdev->ih.ptr_mask; 4197 } 4198 if (queue_hotplug) 4199 schedule_work(&rdev->hotplug_work); 4200 rdev->ih.rptr = rptr; 4201 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4202 atomic_set(&rdev->ih.lock, 0); 4203 4204 /* make sure wptr hasn't changed while processing */ 4205 wptr = si_get_ih_wptr(rdev); 4206 if (wptr != rptr) 4207 goto restart_ih; 4208 4209 return IRQ_HANDLED; 4210 } 4211 4212 /** 4213 * si_copy_dma - copy pages using the DMA engine 4214 * 4215 * @rdev: radeon_device pointer 4216 * @src_offset: src GPU address 4217 * @dst_offset: dst GPU address 4218 * @num_gpu_pages: number of GPU pages to xfer 4219 * @fence: radeon fence object 4220 * 4221 * Copy GPU paging using the DMA engine (SI). 4222 * Used by the radeon ttm implementation to move pages if 4223 * registered as the asic copy callback. 4224 */ 4225 int si_copy_dma(struct radeon_device *rdev, 4226 uint64_t src_offset, uint64_t dst_offset, 4227 unsigned num_gpu_pages, 4228 struct radeon_fence **fence) 4229 { 4230 struct radeon_semaphore *sem = NULL; 4231 int ring_index = rdev->asic->copy.dma_ring_index; 4232 struct radeon_ring *ring = &rdev->ring[ring_index]; 4233 u32 size_in_bytes, cur_size_in_bytes; 4234 int i, num_loops; 4235 int r = 0; 4236 4237 r = radeon_semaphore_create(rdev, &sem); 4238 if (r) { 4239 DRM_ERROR("radeon: moving bo (%d).\n", r); 4240 return r; 4241 } 4242 4243 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 4244 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff); 4245 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); 4246 if (r) { 4247 DRM_ERROR("radeon: moving bo (%d).\n", r); 4248 radeon_semaphore_free(rdev, &sem, NULL); 4249 return r; 4250 } 4251 4252 if (radeon_fence_need_sync(*fence, ring->idx)) { 4253 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 4254 ring->idx); 4255 radeon_fence_note_sync(*fence, ring->idx); 4256 } else { 4257 radeon_semaphore_free(rdev, &sem, NULL); 4258 } 4259 4260 for (i = 0; i < num_loops; i++) { 4261 cur_size_in_bytes = size_in_bytes; 4262 if (cur_size_in_bytes > 0xFFFFF) 4263 cur_size_in_bytes = 0xFFFFF; 4264 size_in_bytes -= cur_size_in_bytes; 4265 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); 4266 radeon_ring_write(ring, dst_offset & 0xffffffff); 4267 radeon_ring_write(ring, src_offset & 0xffffffff); 4268 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 4269 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 4270 src_offset += cur_size_in_bytes; 4271 dst_offset += cur_size_in_bytes; 4272 } 4273 4274 r = radeon_fence_emit(rdev, fence, ring->idx); 4275 if (r) { 4276 radeon_ring_unlock_undo(rdev, ring); 4277 return r; 4278 } 4279 4280 radeon_ring_unlock_commit(rdev, ring); 4281 radeon_semaphore_free(rdev, &sem, *fence); 4282 4283 return r; 4284 } 4285 4286 /* 4287 * startup/shutdown callbacks 4288 */ 4289 static int si_startup(struct radeon_device *rdev) 4290 { 4291 struct radeon_ring *ring; 4292 int r; 4293 4294 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 4295 !rdev->rlc_fw || !rdev->mc_fw) { 4296 r = si_init_microcode(rdev); 4297 if (r) { 4298 DRM_ERROR("Failed to load firmware!\n"); 4299 return r; 4300 } 4301 } 4302 4303 r = si_mc_load_microcode(rdev); 4304 if (r) { 4305 DRM_ERROR("Failed to load MC firmware!\n"); 4306 return r; 4307 } 4308 4309 r = r600_vram_scratch_init(rdev); 4310 if (r) 4311 return r; 4312 4313 si_mc_program(rdev); 4314 r = si_pcie_gart_enable(rdev); 4315 if (r) 4316 return r; 4317 si_gpu_init(rdev); 4318 4319 #if 0 4320 r = evergreen_blit_init(rdev); 4321 if (r) { 4322 r600_blit_fini(rdev); 4323 rdev->asic->copy = NULL; 4324 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 4325 } 4326 #endif 4327 /* allocate rlc buffers */ 4328 r = si_rlc_init(rdev); 4329 if (r) { 4330 DRM_ERROR("Failed to init rlc BOs!\n"); 4331 return r; 4332 } 4333 4334 /* allocate wb buffer */ 4335 r = radeon_wb_init(rdev); 4336 if (r) 4337 return r; 4338 4339 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 4340 if (r) { 4341 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4342 return r; 4343 } 4344 4345 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4346 if (r) { 4347 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4348 return r; 4349 } 4350 4351 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4352 if (r) { 4353 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4354 return r; 4355 } 4356 4357 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 4358 if (r) { 4359 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4360 return r; 4361 } 4362 4363 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4364 if (r) { 4365 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4366 return r; 4367 } 4368 4369 /* Enable IRQ */ 4370 r = si_irq_init(rdev); 4371 if (r) { 4372 DRM_ERROR("radeon: IH init failed (%d).\n", r); 4373 radeon_irq_kms_fini(rdev); 4374 return r; 4375 } 4376 si_irq_set(rdev); 4377 4378 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4379 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 4380 CP_RB0_RPTR, CP_RB0_WPTR, 4381 0, 0xfffff, RADEON_CP_PACKET2); 4382 if (r) 4383 return r; 4384 4385 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4386 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 4387 CP_RB1_RPTR, CP_RB1_WPTR, 4388 0, 0xfffff, RADEON_CP_PACKET2); 4389 if (r) 4390 return r; 4391 4392 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4393 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 4394 CP_RB2_RPTR, CP_RB2_WPTR, 4395 0, 0xfffff, RADEON_CP_PACKET2); 4396 if (r) 4397 return r; 4398 4399 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4400 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 4401 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, 4402 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, 4403 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4404 if (r) 4405 return r; 4406 4407 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4408 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 4409 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, 4410 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, 4411 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4412 if (r) 4413 return r; 4414 4415 r = si_cp_load_microcode(rdev); 4416 if (r) 4417 return r; 4418 r = si_cp_resume(rdev); 4419 if (r) 4420 return r; 4421 4422 r = cayman_dma_resume(rdev); 4423 if (r) 4424 return r; 4425 4426 r = radeon_ib_pool_init(rdev); 4427 if (r) { 4428 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4429 return r; 4430 } 4431 4432 r = radeon_vm_manager_init(rdev); 4433 if (r) { 4434 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 4435 return r; 4436 } 4437 4438 return 0; 4439 } 4440 4441 int si_resume(struct radeon_device *rdev) 4442 { 4443 int r; 4444 4445 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 4446 * posting will perform necessary task to bring back GPU into good 4447 * shape. 4448 */ 4449 /* post card */ 4450 atom_asic_init(rdev->mode_info.atom_context); 4451 4452 rdev->accel_working = true; 4453 r = si_startup(rdev); 4454 if (r) { 4455 DRM_ERROR("si startup failed on resume\n"); 4456 rdev->accel_working = false; 4457 return r; 4458 } 4459 4460 return r; 4461 4462 } 4463 4464 int si_suspend(struct radeon_device *rdev) 4465 { 4466 si_cp_enable(rdev, false); 4467 cayman_dma_stop(rdev); 4468 si_irq_suspend(rdev); 4469 radeon_wb_disable(rdev); 4470 si_pcie_gart_disable(rdev); 4471 return 0; 4472 } 4473 4474 /* Plan is to move initialization in that function and use 4475 * helper function so that radeon_device_init pretty much 4476 * do nothing more than calling asic specific function. This 4477 * should also allow to remove a bunch of callback function 4478 * like vram_info. 4479 */ 4480 int si_init(struct radeon_device *rdev) 4481 { 4482 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4483 int r; 4484 4485 /* Read BIOS */ 4486 if (!radeon_get_bios(rdev)) { 4487 if (ASIC_IS_AVIVO(rdev)) 4488 return -EINVAL; 4489 } 4490 /* Must be an ATOMBIOS */ 4491 if (!rdev->is_atom_bios) { 4492 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 4493 return -EINVAL; 4494 } 4495 r = radeon_atombios_init(rdev); 4496 if (r) 4497 return r; 4498 4499 /* Post card if necessary */ 4500 if (!radeon_card_posted(rdev)) { 4501 if (!rdev->bios) { 4502 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 4503 return -EINVAL; 4504 } 4505 DRM_INFO("GPU not posted. posting now...\n"); 4506 atom_asic_init(rdev->mode_info.atom_context); 4507 } 4508 /* Initialize scratch registers */ 4509 si_scratch_init(rdev); 4510 /* Initialize surface registers */ 4511 radeon_surface_init(rdev); 4512 /* Initialize clocks */ 4513 radeon_get_clock_info(rdev->ddev); 4514 4515 /* Fence driver */ 4516 r = radeon_fence_driver_init(rdev); 4517 if (r) 4518 return r; 4519 4520 /* initialize memory controller */ 4521 r = si_mc_init(rdev); 4522 if (r) 4523 return r; 4524 /* Memory manager */ 4525 r = radeon_bo_init(rdev); 4526 if (r) 4527 return r; 4528 4529 r = radeon_irq_kms_init(rdev); 4530 if (r) 4531 return r; 4532 4533 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4534 ring->ring_obj = NULL; 4535 r600_ring_init(rdev, ring, 1024 * 1024); 4536 4537 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4538 ring->ring_obj = NULL; 4539 r600_ring_init(rdev, ring, 1024 * 1024); 4540 4541 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4542 ring->ring_obj = NULL; 4543 r600_ring_init(rdev, ring, 1024 * 1024); 4544 4545 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4546 ring->ring_obj = NULL; 4547 r600_ring_init(rdev, ring, 64 * 1024); 4548 4549 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4550 ring->ring_obj = NULL; 4551 r600_ring_init(rdev, ring, 64 * 1024); 4552 4553 rdev->ih.ring_obj = NULL; 4554 r600_ih_ring_init(rdev, 64 * 1024); 4555 4556 r = r600_pcie_gart_init(rdev); 4557 if (r) 4558 return r; 4559 4560 rdev->accel_working = true; 4561 r = si_startup(rdev); 4562 if (r) { 4563 dev_err(rdev->dev, "disabling GPU acceleration\n"); 4564 si_cp_fini(rdev); 4565 cayman_dma_fini(rdev); 4566 si_irq_fini(rdev); 4567 si_rlc_fini(rdev); 4568 radeon_wb_fini(rdev); 4569 radeon_ib_pool_fini(rdev); 4570 radeon_vm_manager_fini(rdev); 4571 radeon_irq_kms_fini(rdev); 4572 si_pcie_gart_fini(rdev); 4573 rdev->accel_working = false; 4574 } 4575 4576 /* Don't start up if the MC ucode is missing. 4577 * The default clocks and voltages before the MC ucode 4578 * is loaded are not suffient for advanced operations. 4579 */ 4580 if (!rdev->mc_fw) { 4581 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 4582 return -EINVAL; 4583 } 4584 4585 return 0; 4586 } 4587 4588 void si_fini(struct radeon_device *rdev) 4589 { 4590 #if 0 4591 r600_blit_fini(rdev); 4592 #endif 4593 si_cp_fini(rdev); 4594 cayman_dma_fini(rdev); 4595 si_irq_fini(rdev); 4596 si_rlc_fini(rdev); 4597 radeon_wb_fini(rdev); 4598 radeon_vm_manager_fini(rdev); 4599 radeon_ib_pool_fini(rdev); 4600 radeon_irq_kms_fini(rdev); 4601 si_pcie_gart_fini(rdev); 4602 r600_vram_scratch_fini(rdev); 4603 radeon_gem_fini(rdev); 4604 radeon_fence_driver_fini(rdev); 4605 radeon_bo_fini(rdev); 4606 radeon_atombios_fini(rdev); 4607 kfree(rdev->bios); 4608 rdev->bios = NULL; 4609 } 4610 4611 /** 4612 * si_get_gpu_clock_counter - return GPU clock counter snapshot 4613 * 4614 * @rdev: radeon_device pointer 4615 * 4616 * Fetches a GPU clock counter snapshot (SI). 4617 * Returns the 64 bit clock counter snapshot. 4618 */ 4619 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev) 4620 { 4621 uint64_t clock; 4622 4623 mutex_lock(&rdev->gpu_clock_mutex); 4624 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4625 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4626 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4627 mutex_unlock(&rdev->gpu_clock_mutex); 4628 return clock; 4629 } 4630