1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef RV770_H 28 #define RV770_H 29 30 #define R7XX_MAX_SH_GPRS 256 31 #define R7XX_MAX_TEMP_GPRS 16 32 #define R7XX_MAX_SH_THREADS 256 33 #define R7XX_MAX_SH_STACK_ENTRIES 4096 34 #define R7XX_MAX_BACKENDS 8 35 #define R7XX_MAX_BACKENDS_MASK 0xff 36 #define R7XX_MAX_SIMDS 16 37 #define R7XX_MAX_SIMDS_MASK 0xffff 38 #define R7XX_MAX_PIPES 8 39 #define R7XX_MAX_PIPES_MASK 0xff 40 41 /* discrete uvd clocks */ 42 #define CG_UPLL_FUNC_CNTL 0x718 43 # define UPLL_RESET_MASK 0x00000001 44 # define UPLL_SLEEP_MASK 0x00000002 45 # define UPLL_BYPASS_EN_MASK 0x00000004 46 # define UPLL_CTLREQ_MASK 0x00000008 47 # define UPLL_REF_DIV(x) ((x) << 16) 48 # define UPLL_REF_DIV_MASK 0x003F0000 49 # define UPLL_CTLACK_MASK 0x40000000 50 # define UPLL_CTLACK2_MASK 0x80000000 51 #define CG_UPLL_FUNC_CNTL_2 0x71c 52 # define UPLL_SW_HILEN(x) ((x) << 0) 53 # define UPLL_SW_LOLEN(x) ((x) << 4) 54 # define UPLL_SW_HILEN2(x) ((x) << 8) 55 # define UPLL_SW_LOLEN2(x) ((x) << 12) 56 # define UPLL_SW_MASK 0x0000FFFF 57 # define VCLK_SRC_SEL(x) ((x) << 20) 58 # define VCLK_SRC_SEL_MASK 0x01F00000 59 # define DCLK_SRC_SEL(x) ((x) << 25) 60 # define DCLK_SRC_SEL_MASK 0x3E000000 61 #define CG_UPLL_FUNC_CNTL_3 0x720 62 # define UPLL_FB_DIV(x) ((x) << 0) 63 # define UPLL_FB_DIV_MASK 0x01FFFFFF 64 65 /* pm registers */ 66 #define SMC_SRAM_ADDR 0x200 67 #define SMC_SRAM_AUTO_INC_DIS (1 << 16) 68 #define SMC_SRAM_DATA 0x204 69 #define SMC_IO 0x208 70 #define SMC_RST_N (1 << 0) 71 #define SMC_STOP_MODE (1 << 2) 72 #define SMC_CLK_EN (1 << 11) 73 #define SMC_MSG 0x20c 74 #define HOST_SMC_MSG(x) ((x) << 0) 75 #define HOST_SMC_MSG_MASK (0xff << 0) 76 #define HOST_SMC_MSG_SHIFT 0 77 #define HOST_SMC_RESP(x) ((x) << 8) 78 #define HOST_SMC_RESP_MASK (0xff << 8) 79 #define HOST_SMC_RESP_SHIFT 8 80 #define SMC_HOST_MSG(x) ((x) << 16) 81 #define SMC_HOST_MSG_MASK (0xff << 16) 82 #define SMC_HOST_MSG_SHIFT 16 83 #define SMC_HOST_RESP(x) ((x) << 24) 84 #define SMC_HOST_RESP_MASK (0xff << 24) 85 #define SMC_HOST_RESP_SHIFT 24 86 87 #define SMC_ISR_FFD8_FFDB 0x218 88 89 #define CG_SPLL_FUNC_CNTL 0x600 90 #define SPLL_RESET (1 << 0) 91 #define SPLL_SLEEP (1 << 1) 92 #define SPLL_DIVEN (1 << 2) 93 #define SPLL_BYPASS_EN (1 << 3) 94 #define SPLL_REF_DIV(x) ((x) << 4) 95 #define SPLL_REF_DIV_MASK (0x3f << 4) 96 #define SPLL_HILEN(x) ((x) << 12) 97 #define SPLL_HILEN_MASK (0xf << 12) 98 #define SPLL_LOLEN(x) ((x) << 16) 99 #define SPLL_LOLEN_MASK (0xf << 16) 100 #define CG_SPLL_FUNC_CNTL_2 0x604 101 #define SCLK_MUX_SEL(x) ((x) << 0) 102 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 103 #define CG_SPLL_FUNC_CNTL_3 0x608 104 #define SPLL_FB_DIV(x) ((x) << 0) 105 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 106 #define SPLL_DITHEN (1 << 28) 107 108 #define SPLL_CNTL_MODE 0x610 109 #define SPLL_DIV_SYNC (1 << 5) 110 111 #define MPLL_AD_FUNC_CNTL 0x624 112 #define CLKF(x) ((x) << 0) 113 #define CLKF_MASK (0x7f << 0) 114 #define CLKR(x) ((x) << 7) 115 #define CLKR_MASK (0x1f << 7) 116 #define CLKFRAC(x) ((x) << 12) 117 #define CLKFRAC_MASK (0x1f << 12) 118 #define YCLK_POST_DIV(x) ((x) << 17) 119 #define YCLK_POST_DIV_MASK (3 << 17) 120 #define IBIAS(x) ((x) << 20) 121 #define IBIAS_MASK (0x3ff << 20) 122 #define RESET (1 << 30) 123 #define PDNB (1 << 31) 124 #define MPLL_AD_FUNC_CNTL_2 0x628 125 #define BYPASS (1 << 19) 126 #define BIAS_GEN_PDNB (1 << 24) 127 #define RESET_EN (1 << 25) 128 #define VCO_MODE (1 << 29) 129 #define MPLL_DQ_FUNC_CNTL 0x62c 130 #define MPLL_DQ_FUNC_CNTL_2 0x630 131 132 #define GENERAL_PWRMGT 0x63c 133 # define GLOBAL_PWRMGT_EN (1 << 0) 134 # define STATIC_PM_EN (1 << 1) 135 # define THERMAL_PROTECTION_DIS (1 << 2) 136 # define THERMAL_PROTECTION_TYPE (1 << 3) 137 # define ENABLE_GEN2PCIE (1 << 4) 138 # define ENABLE_GEN2XSP (1 << 5) 139 # define SW_SMIO_INDEX(x) ((x) << 6) 140 # define SW_SMIO_INDEX_MASK (3 << 6) 141 # define SW_SMIO_INDEX_SHIFT 6 142 # define LOW_VOLT_D2_ACPI (1 << 8) 143 # define LOW_VOLT_D3_ACPI (1 << 9) 144 # define VOLT_PWRMGT_EN (1 << 10) 145 # define BACKBIAS_PAD_EN (1 << 18) 146 # define BACKBIAS_VALUE (1 << 19) 147 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 148 # define AC_DC_SW (1 << 24) 149 150 #define CG_TPC 0x640 151 #define SCLK_PWRMGT_CNTL 0x644 152 # define SCLK_PWRMGT_OFF (1 << 0) 153 # define SCLK_LOW_D1 (1 << 1) 154 # define FIR_RESET (1 << 4) 155 # define FIR_FORCE_TREND_SEL (1 << 5) 156 # define FIR_TREND_MODE (1 << 6) 157 # define DYN_GFX_CLK_OFF_EN (1 << 7) 158 # define GFX_CLK_FORCE_ON (1 << 8) 159 # define GFX_CLK_REQUEST_OFF (1 << 9) 160 # define GFX_CLK_FORCE_OFF (1 << 10) 161 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 162 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 163 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 164 #define MCLK_PWRMGT_CNTL 0x648 165 # define DLL_SPEED(x) ((x) << 0) 166 # define DLL_SPEED_MASK (0x1f << 0) 167 # define MPLL_PWRMGT_OFF (1 << 5) 168 # define DLL_READY (1 << 6) 169 # define MC_INT_CNTL (1 << 7) 170 # define MRDCKA0_SLEEP (1 << 8) 171 # define MRDCKA1_SLEEP (1 << 9) 172 # define MRDCKB0_SLEEP (1 << 10) 173 # define MRDCKB1_SLEEP (1 << 11) 174 # define MRDCKC0_SLEEP (1 << 12) 175 # define MRDCKC1_SLEEP (1 << 13) 176 # define MRDCKD0_SLEEP (1 << 14) 177 # define MRDCKD1_SLEEP (1 << 15) 178 # define MRDCKA0_RESET (1 << 16) 179 # define MRDCKA1_RESET (1 << 17) 180 # define MRDCKB0_RESET (1 << 18) 181 # define MRDCKB1_RESET (1 << 19) 182 # define MRDCKC0_RESET (1 << 20) 183 # define MRDCKC1_RESET (1 << 21) 184 # define MRDCKD0_RESET (1 << 22) 185 # define MRDCKD1_RESET (1 << 23) 186 # define DLL_READY_READ (1 << 24) 187 # define USE_DISPLAY_GAP (1 << 25) 188 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 189 # define MPLL_TURNOFF_D2 (1 << 28) 190 #define DLL_CNTL 0x64c 191 # define MRDCKA0_BYPASS (1 << 24) 192 # define MRDCKA1_BYPASS (1 << 25) 193 # define MRDCKB0_BYPASS (1 << 26) 194 # define MRDCKB1_BYPASS (1 << 27) 195 # define MRDCKC0_BYPASS (1 << 28) 196 # define MRDCKC1_BYPASS (1 << 29) 197 # define MRDCKD0_BYPASS (1 << 30) 198 # define MRDCKD1_BYPASS (1 << 31) 199 200 #define MPLL_TIME 0x654 201 # define MPLL_LOCK_TIME(x) ((x) << 0) 202 # define MPLL_LOCK_TIME_MASK (0xffff << 0) 203 # define MPLL_RESET_TIME(x) ((x) << 16) 204 # define MPLL_RESET_TIME_MASK (0xffff << 16) 205 206 #define CG_CLKPIN_CNTL 0x660 207 # define MUX_TCLK_TO_XCLK (1 << 8) 208 # define XTALIN_DIVIDE (1 << 9) 209 210 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 211 # define CURRENT_PROFILE_INDEX_MASK (0xf << 4) 212 # define CURRENT_PROFILE_INDEX_SHIFT 4 213 214 #define S0_VID_LOWER_SMIO_CNTL 0x678 215 #define S1_VID_LOWER_SMIO_CNTL 0x67c 216 #define S2_VID_LOWER_SMIO_CNTL 0x680 217 #define S3_VID_LOWER_SMIO_CNTL 0x684 218 219 #define CG_FTV 0x690 220 #define CG_FFCT_0 0x694 221 # define UTC_0(x) ((x) << 0) 222 # define UTC_0_MASK (0x3ff << 0) 223 # define DTC_0(x) ((x) << 10) 224 # define DTC_0_MASK (0x3ff << 10) 225 226 #define CG_BSP 0x6d0 227 # define BSP(x) ((x) << 0) 228 # define BSP_MASK (0xffff << 0) 229 # define BSU(x) ((x) << 16) 230 # define BSU_MASK (0xf << 16) 231 #define CG_AT 0x6d4 232 # define CG_R(x) ((x) << 0) 233 # define CG_R_MASK (0xffff << 0) 234 # define CG_L(x) ((x) << 16) 235 # define CG_L_MASK (0xffff << 16) 236 #define CG_GIT 0x6d8 237 # define CG_GICST(x) ((x) << 0) 238 # define CG_GICST_MASK (0xffff << 0) 239 # define CG_GIPOT(x) ((x) << 16) 240 # define CG_GIPOT_MASK (0xffff << 16) 241 242 #define CG_SSP 0x6e8 243 # define SST(x) ((x) << 0) 244 # define SST_MASK (0xffff << 0) 245 # define SSTU(x) ((x) << 16) 246 # define SSTU_MASK (0xf << 16) 247 248 #define CG_DISPLAY_GAP_CNTL 0x714 249 # define DISP1_GAP(x) ((x) << 0) 250 # define DISP1_GAP_MASK (3 << 0) 251 # define DISP2_GAP(x) ((x) << 2) 252 # define DISP2_GAP_MASK (3 << 2) 253 # define VBI_TIMER_COUNT(x) ((x) << 4) 254 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 255 # define VBI_TIMER_UNIT(x) ((x) << 20) 256 # define VBI_TIMER_UNIT_MASK (7 << 20) 257 # define DISP1_GAP_MCHG(x) ((x) << 24) 258 # define DISP1_GAP_MCHG_MASK (3 << 24) 259 # define DISP2_GAP_MCHG(x) ((x) << 26) 260 # define DISP2_GAP_MCHG_MASK (3 << 26) 261 262 #define CG_SPLL_SPREAD_SPECTRUM 0x790 263 #define SSEN (1 << 0) 264 #define CLKS(x) ((x) << 4) 265 #define CLKS_MASK (0xfff << 4) 266 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 267 #define CLKV(x) ((x) << 0) 268 #define CLKV_MASK (0x3ffffff << 0) 269 #define CG_MPLL_SPREAD_SPECTRUM 0x798 270 #define CG_UPLL_SPREAD_SPECTRUM 0x79c 271 # define SSEN_MASK 0x00000001 272 273 #define CG_CGTT_LOCAL_0 0x7d0 274 #define CG_CGTT_LOCAL_1 0x7d4 275 276 #define BIOS_SCRATCH_4 0x1734 277 278 #define MC_SEQ_MISC0 0x2a00 279 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 280 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 281 #define MC_SEQ_MISC0_GDDR5_VALUE 5 282 283 #define MC_ARB_SQM_RATIO 0x2770 284 #define STATE0(x) ((x) << 0) 285 #define STATE0_MASK (0xff << 0) 286 #define STATE1(x) ((x) << 8) 287 #define STATE1_MASK (0xff << 8) 288 #define STATE2(x) ((x) << 16) 289 #define STATE2_MASK (0xff << 16) 290 #define STATE3(x) ((x) << 24) 291 #define STATE3_MASK (0xff << 24) 292 293 #define MC_ARB_RFSH_RATE 0x27b0 294 #define POWERMODE0(x) ((x) << 0) 295 #define POWERMODE0_MASK (0xff << 0) 296 #define POWERMODE1(x) ((x) << 8) 297 #define POWERMODE1_MASK (0xff << 8) 298 #define POWERMODE2(x) ((x) << 16) 299 #define POWERMODE2_MASK (0xff << 16) 300 #define POWERMODE3(x) ((x) << 24) 301 #define POWERMODE3_MASK (0xff << 24) 302 303 #define CGTS_SM_CTRL_REG 0x9150 304 305 /* Registers */ 306 #define CB_COLOR0_BASE 0x28040 307 #define CB_COLOR1_BASE 0x28044 308 #define CB_COLOR2_BASE 0x28048 309 #define CB_COLOR3_BASE 0x2804C 310 #define CB_COLOR4_BASE 0x28050 311 #define CB_COLOR5_BASE 0x28054 312 #define CB_COLOR6_BASE 0x28058 313 #define CB_COLOR7_BASE 0x2805C 314 #define CB_COLOR7_FRAG 0x280FC 315 316 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 317 #define CC_RB_BACKEND_DISABLE 0x98F4 318 #define BACKEND_DISABLE(x) ((x) << 16) 319 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 320 321 #define CGTS_SYS_TCC_DISABLE 0x3F90 322 #define CGTS_TCC_DISABLE 0x9148 323 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 324 #define CGTS_USER_TCC_DISABLE 0x914C 325 326 #define CONFIG_MEMSIZE 0x5428 327 328 #define CP_ME_CNTL 0x86D8 329 #define CP_ME_HALT (1 << 28) 330 #define CP_PFP_HALT (1 << 26) 331 #define CP_ME_RAM_DATA 0xC160 332 #define CP_ME_RAM_RADDR 0xC158 333 #define CP_ME_RAM_WADDR 0xC15C 334 #define CP_MEQ_THRESHOLDS 0x8764 335 #define STQ_SPLIT(x) ((x) << 0) 336 #define CP_PERFMON_CNTL 0x87FC 337 #define CP_PFP_UCODE_ADDR 0xC150 338 #define CP_PFP_UCODE_DATA 0xC154 339 #define CP_QUEUE_THRESHOLDS 0x8760 340 #define ROQ_IB1_START(x) ((x) << 0) 341 #define ROQ_IB2_START(x) ((x) << 8) 342 #define CP_RB_CNTL 0xC104 343 #define RB_BUFSZ(x) ((x) << 0) 344 #define RB_BLKSZ(x) ((x) << 8) 345 #define RB_NO_UPDATE (1 << 27) 346 #define RB_RPTR_WR_ENA (1 << 31) 347 #define BUF_SWAP_32BIT (2 << 16) 348 #define CP_RB_RPTR 0x8700 349 #define CP_RB_RPTR_ADDR 0xC10C 350 #define CP_RB_RPTR_ADDR_HI 0xC110 351 #define CP_RB_RPTR_WR 0xC108 352 #define CP_RB_WPTR 0xC114 353 #define CP_RB_WPTR_ADDR 0xC118 354 #define CP_RB_WPTR_ADDR_HI 0xC11C 355 #define CP_RB_WPTR_DELAY 0x8704 356 #define CP_SEM_WAIT_TIMER 0x85BC 357 358 #define DB_DEBUG3 0x98B0 359 #define DB_CLK_OFF_DELAY(x) ((x) << 11) 360 #define DB_DEBUG4 0x9B8C 361 #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 362 363 #define DCP_TILING_CONFIG 0x6CA0 364 #define PIPE_TILING(x) ((x) << 1) 365 #define BANK_TILING(x) ((x) << 4) 366 #define GROUP_SIZE(x) ((x) << 6) 367 #define ROW_TILING(x) ((x) << 8) 368 #define BANK_SWAPS(x) ((x) << 11) 369 #define SAMPLE_SPLIT(x) ((x) << 14) 370 #define BACKEND_MAP(x) ((x) << 16) 371 372 #define GB_TILING_CONFIG 0x98F0 373 #define PIPE_TILING__SHIFT 1 374 #define PIPE_TILING__MASK 0x0000000e 375 376 #define DMA_TILING_CONFIG 0x3ec8 377 #define DMA_TILING_CONFIG2 0xd0b8 378 379 /* RV730 only */ 380 #define UVD_UDEC_TILING_CONFIG 0xef40 381 #define UVD_UDEC_DB_TILING_CONFIG 0xef44 382 #define UVD_UDEC_DBW_TILING_CONFIG 0xef48 383 384 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 385 #define INACTIVE_QD_PIPES(x) ((x) << 8) 386 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 387 #define INACTIVE_QD_PIPES_SHIFT 8 388 #define INACTIVE_SIMDS(x) ((x) << 16) 389 #define INACTIVE_SIMDS_MASK 0x00FF0000 390 391 #define GRBM_CNTL 0x8000 392 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 393 #define GRBM_SOFT_RESET 0x8020 394 #define SOFT_RESET_CP (1<<0) 395 #define GRBM_STATUS 0x8010 396 #define CMDFIFO_AVAIL_MASK 0x0000000F 397 #define GUI_ACTIVE (1<<31) 398 #define GRBM_STATUS2 0x8014 399 400 #define CG_THERMAL_CTRL 0x72C 401 #define DPM_EVENT_SRC(x) ((x) << 0) 402 #define DPM_EVENT_SRC_MASK (7 << 0) 403 #define DIG_THERM_DPM(x) ((x) << 14) 404 #define DIG_THERM_DPM_MASK 0x003FC000 405 #define DIG_THERM_DPM_SHIFT 14 406 407 #define CG_THERMAL_INT 0x734 408 #define DIG_THERM_INTH(x) ((x) << 8) 409 #define DIG_THERM_INTH_MASK 0x0000FF00 410 #define DIG_THERM_INTH_SHIFT 8 411 #define DIG_THERM_INTL(x) ((x) << 16) 412 #define DIG_THERM_INTL_MASK 0x00FF0000 413 #define DIG_THERM_INTL_SHIFT 16 414 #define THERM_INT_MASK_HIGH (1 << 24) 415 #define THERM_INT_MASK_LOW (1 << 25) 416 417 #define CG_MULT_THERMAL_STATUS 0x740 418 #define ASIC_T(x) ((x) << 16) 419 #define ASIC_T_MASK 0x3FF0000 420 #define ASIC_T_SHIFT 16 421 422 #define HDP_HOST_PATH_CNTL 0x2C00 423 #define HDP_NONSURFACE_BASE 0x2C04 424 #define HDP_NONSURFACE_INFO 0x2C08 425 #define HDP_NONSURFACE_SIZE 0x2C0C 426 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 427 #define HDP_TILING_CONFIG 0x2F3C 428 #define HDP_DEBUG1 0x2F34 429 430 #define MC_SHARED_CHMAP 0x2004 431 #define NOOFCHAN_SHIFT 12 432 #define NOOFCHAN_MASK 0x00003000 433 #define MC_SHARED_CHREMAP 0x2008 434 435 #define MC_ARB_RAMCFG 0x2760 436 #define NOOFBANK_SHIFT 0 437 #define NOOFBANK_MASK 0x00000003 438 #define NOOFRANK_SHIFT 2 439 #define NOOFRANK_MASK 0x00000004 440 #define NOOFROWS_SHIFT 3 441 #define NOOFROWS_MASK 0x00000038 442 #define NOOFCOLS_SHIFT 6 443 #define NOOFCOLS_MASK 0x000000C0 444 #define CHANSIZE_SHIFT 8 445 #define CHANSIZE_MASK 0x00000100 446 #define BURSTLENGTH_SHIFT 9 447 #define BURSTLENGTH_MASK 0x00000200 448 #define CHANSIZE_OVERRIDE (1 << 11) 449 #define MC_VM_AGP_TOP 0x2028 450 #define MC_VM_AGP_BOT 0x202C 451 #define MC_VM_AGP_BASE 0x2030 452 #define MC_VM_FB_LOCATION 0x2024 453 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 454 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 455 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 456 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 457 #define ENABLE_L1_TLB (1 << 0) 458 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 459 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 460 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 461 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 462 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 463 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 464 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 465 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 466 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 467 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 468 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 469 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 470 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 471 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 472 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 473 474 #define PA_CL_ENHANCE 0x8A14 475 #define CLIP_VTX_REORDER_ENA (1 << 0) 476 #define NUM_CLIP_SEQ(x) ((x) << 1) 477 #define PA_SC_AA_CONFIG 0x28C04 478 #define PA_SC_CLIPRECT_RULE 0x2820C 479 #define PA_SC_EDGERULE 0x28230 480 #define PA_SC_FIFO_SIZE 0x8BCC 481 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 482 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 483 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 484 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 485 #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 486 #define PA_SC_LINE_STIPPLE 0x28A0C 487 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 488 #define PA_SC_MODE_CNTL 0x28A4C 489 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 490 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 491 492 #define SCRATCH_REG0 0x8500 493 #define SCRATCH_REG1 0x8504 494 #define SCRATCH_REG2 0x8508 495 #define SCRATCH_REG3 0x850C 496 #define SCRATCH_REG4 0x8510 497 #define SCRATCH_REG5 0x8514 498 #define SCRATCH_REG6 0x8518 499 #define SCRATCH_REG7 0x851C 500 #define SCRATCH_UMSK 0x8540 501 #define SCRATCH_ADDR 0x8544 502 503 #define SMX_SAR_CTL0 0xA008 504 #define SMX_DC_CTL0 0xA020 505 #define USE_HASH_FUNCTION (1 << 0) 506 #define CACHE_DEPTH(x) ((x) << 1) 507 #define FLUSH_ALL_ON_EVENT (1 << 10) 508 #define STALL_ON_EVENT (1 << 11) 509 #define SMX_EVENT_CTL 0xA02C 510 #define ES_FLUSH_CTL(x) ((x) << 0) 511 #define GS_FLUSH_CTL(x) ((x) << 3) 512 #define ACK_FLUSH_CTL(x) ((x) << 6) 513 #define SYNC_FLUSH_CTL (1 << 8) 514 515 #define SPI_CONFIG_CNTL 0x9100 516 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 517 #define DISABLE_INTERP_1 (1 << 5) 518 #define SPI_CONFIG_CNTL_1 0x913C 519 #define VTX_DONE_DELAY(x) ((x) << 0) 520 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 521 #define SPI_INPUT_Z 0x286D8 522 #define SPI_PS_IN_CONTROL_0 0x286CC 523 #define NUM_INTERP(x) ((x)<<0) 524 #define POSITION_ENA (1<<8) 525 #define POSITION_CENTROID (1<<9) 526 #define POSITION_ADDR(x) ((x)<<10) 527 #define PARAM_GEN(x) ((x)<<15) 528 #define PARAM_GEN_ADDR(x) ((x)<<19) 529 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 530 #define PERSP_GRADIENT_ENA (1<<28) 531 #define LINEAR_GRADIENT_ENA (1<<29) 532 #define POSITION_SAMPLE (1<<30) 533 #define BARYC_AT_SAMPLE_ENA (1<<31) 534 535 #define SQ_CONFIG 0x8C00 536 #define VC_ENABLE (1 << 0) 537 #define EXPORT_SRC_C (1 << 1) 538 #define DX9_CONSTS (1 << 2) 539 #define ALU_INST_PREFER_VECTOR (1 << 3) 540 #define DX10_CLAMP (1 << 4) 541 #define CLAUSE_SEQ_PRIO(x) ((x) << 8) 542 #define PS_PRIO(x) ((x) << 24) 543 #define VS_PRIO(x) ((x) << 26) 544 #define GS_PRIO(x) ((x) << 28) 545 #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 546 #define SIMDA_RING0(x) ((x)<<0) 547 #define SIMDA_RING1(x) ((x)<<8) 548 #define SIMDB_RING0(x) ((x)<<16) 549 #define SIMDB_RING1(x) ((x)<<24) 550 #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 551 #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 552 #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 553 #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 554 #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 555 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 556 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 557 #define ES_PRIO(x) ((x) << 30) 558 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 559 #define NUM_PS_GPRS(x) ((x) << 0) 560 #define NUM_VS_GPRS(x) ((x) << 16) 561 #define DYN_GPR_ENABLE (1 << 27) 562 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 563 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 564 #define NUM_GS_GPRS(x) ((x) << 0) 565 #define NUM_ES_GPRS(x) ((x) << 16) 566 #define SQ_MS_FIFO_SIZES 0x8CF0 567 #define CACHE_FIFO_SIZE(x) ((x) << 0) 568 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 569 #define DONE_FIFO_HIWATER(x) ((x) << 16) 570 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 571 #define SQ_STACK_RESOURCE_MGMT_1 0x8C10 572 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 573 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 574 #define SQ_STACK_RESOURCE_MGMT_2 0x8C14 575 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 576 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 577 #define SQ_THREAD_RESOURCE_MGMT 0x8C0C 578 #define NUM_PS_THREADS(x) ((x) << 0) 579 #define NUM_VS_THREADS(x) ((x) << 8) 580 #define NUM_GS_THREADS(x) ((x) << 16) 581 #define NUM_ES_THREADS(x) ((x) << 24) 582 583 #define SX_DEBUG_1 0x9058 584 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 585 #define SX_EXPORT_BUFFER_SIZES 0x900C 586 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 587 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 588 #define SMX_BUFFER_SIZE(x) ((x) << 16) 589 #define SX_MISC 0x28350 590 591 #define TA_CNTL_AUX 0x9508 592 #define DISABLE_CUBE_WRAP (1 << 0) 593 #define DISABLE_CUBE_ANISO (1 << 1) 594 #define SYNC_GRADIENT (1 << 24) 595 #define SYNC_WALKER (1 << 25) 596 #define SYNC_ALIGNER (1 << 26) 597 #define BILINEAR_PRECISION_6_BIT (0 << 31) 598 #define BILINEAR_PRECISION_8_BIT (1 << 31) 599 600 #define TCP_CNTL 0x9610 601 #define TCP_CHAN_STEER 0x9614 602 603 #define VC_ENHANCE 0x9714 604 605 #define VGT_CACHE_INVALIDATION 0x88C4 606 #define CACHE_INVALIDATION(x) ((x)<<0) 607 #define VC_ONLY 0 608 #define TC_ONLY 1 609 #define VC_AND_TC 2 610 #define AUTO_INVLD_EN(x) ((x) << 6) 611 #define NO_AUTO 0 612 #define ES_AUTO 1 613 #define GS_AUTO 2 614 #define ES_AND_GS_AUTO 3 615 #define VGT_ES_PER_GS 0x88CC 616 #define VGT_GS_PER_ES 0x88C8 617 #define VGT_GS_PER_VS 0x88E8 618 #define VGT_GS_VERTEX_REUSE 0x88D4 619 #define VGT_NUM_INSTANCES 0x8974 620 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 621 #define DEALLOC_DIST_MASK 0x0000007F 622 #define VGT_STRMOUT_EN 0x28AB0 623 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 624 #define VTX_REUSE_DEPTH_MASK 0x000000FF 625 626 #define VM_CONTEXT0_CNTL 0x1410 627 #define ENABLE_CONTEXT (1 << 0) 628 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 629 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 630 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 631 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 632 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 633 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 634 #define VM_L2_CNTL 0x1400 635 #define ENABLE_L2_CACHE (1 << 0) 636 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 637 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 638 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 639 #define VM_L2_CNTL2 0x1404 640 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 641 #define INVALIDATE_L2_CACHE (1 << 1) 642 #define VM_L2_CNTL3 0x1408 643 #define BANK_SELECT(x) ((x) << 0) 644 #define CACHE_UPDATE_MODE(x) ((x) << 6) 645 #define VM_L2_STATUS 0x140C 646 #define L2_BUSY (1 << 0) 647 648 #define WAIT_UNTIL 0x8040 649 650 /* async DMA */ 651 #define DMA_RB_RPTR 0xd008 652 #define DMA_RB_WPTR 0xd00c 653 654 /* async DMA packets */ 655 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 656 (((t) & 0x1) << 23) | \ 657 (((s) & 0x1) << 22) | \ 658 (((n) & 0xFFFF) << 0)) 659 /* async DMA Packet types */ 660 #define DMA_PACKET_WRITE 0x2 661 #define DMA_PACKET_COPY 0x3 662 #define DMA_PACKET_INDIRECT_BUFFER 0x4 663 #define DMA_PACKET_SEMAPHORE 0x5 664 #define DMA_PACKET_FENCE 0x6 665 #define DMA_PACKET_TRAP 0x7 666 #define DMA_PACKET_CONSTANT_FILL 0xd 667 #define DMA_PACKET_NOP 0xf 668 669 670 #define SRBM_STATUS 0x0E50 671 672 /* DCE 3.2 HDMI */ 673 #define HDMI_CONTROL 0x7400 674 # define HDMI_KEEPOUT_MODE (1 << 0) 675 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 676 # define HDMI_ERROR_ACK (1 << 8) 677 # define HDMI_ERROR_MASK (1 << 9) 678 #define HDMI_STATUS 0x7404 679 # define HDMI_ACTIVE_AVMUTE (1 << 0) 680 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 681 # define HDMI_VBI_PACKET_ERROR (1 << 20) 682 #define HDMI_AUDIO_PACKET_CONTROL 0x7408 683 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 684 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 685 #define HDMI_ACR_PACKET_CONTROL 0x740c 686 # define HDMI_ACR_SEND (1 << 0) 687 # define HDMI_ACR_CONT (1 << 1) 688 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 689 # define HDMI_ACR_HW 0 690 # define HDMI_ACR_32 1 691 # define HDMI_ACR_44 2 692 # define HDMI_ACR_48 3 693 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 694 # define HDMI_ACR_AUTO_SEND (1 << 12) 695 #define HDMI_VBI_PACKET_CONTROL 0x7410 696 # define HDMI_NULL_SEND (1 << 0) 697 # define HDMI_GC_SEND (1 << 4) 698 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 699 #define HDMI_INFOFRAME_CONTROL0 0x7414 700 # define HDMI_AVI_INFO_SEND (1 << 0) 701 # define HDMI_AVI_INFO_CONT (1 << 1) 702 # define HDMI_AUDIO_INFO_SEND (1 << 4) 703 # define HDMI_AUDIO_INFO_CONT (1 << 5) 704 # define HDMI_MPEG_INFO_SEND (1 << 8) 705 # define HDMI_MPEG_INFO_CONT (1 << 9) 706 #define HDMI_INFOFRAME_CONTROL1 0x7418 707 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 708 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 709 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 710 #define HDMI_GENERIC_PACKET_CONTROL 0x741c 711 # define HDMI_GENERIC0_SEND (1 << 0) 712 # define HDMI_GENERIC0_CONT (1 << 1) 713 # define HDMI_GENERIC1_SEND (1 << 4) 714 # define HDMI_GENERIC1_CONT (1 << 5) 715 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 716 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 717 #define HDMI_GC 0x7428 718 # define HDMI_GC_AVMUTE (1 << 0) 719 #define AFMT_AUDIO_PACKET_CONTROL2 0x742c 720 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 721 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 722 # define AFMT_60958_CS_SOURCE (1 << 4) 723 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 724 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 725 #define AFMT_AVI_INFO0 0x7454 726 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 727 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 728 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 729 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 730 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 731 # define AFMT_AVI_INFO_Y_RGB 0 732 # define AFMT_AVI_INFO_Y_YCBCR422 1 733 # define AFMT_AVI_INFO_Y_YCBCR444 2 734 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 735 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 736 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 737 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 738 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 739 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 740 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 741 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 742 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 743 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 744 #define AFMT_AVI_INFO1 0x7458 745 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 746 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 747 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 748 #define AFMT_AVI_INFO2 0x745c 749 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 750 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 751 #define AFMT_AVI_INFO3 0x7460 752 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 753 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 754 #define AFMT_MPEG_INFO0 0x7464 755 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 756 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 757 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 758 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 759 #define AFMT_MPEG_INFO1 0x7468 760 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 761 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 762 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 763 #define AFMT_GENERIC0_HDR 0x746c 764 #define AFMT_GENERIC0_0 0x7470 765 #define AFMT_GENERIC0_1 0x7474 766 #define AFMT_GENERIC0_2 0x7478 767 #define AFMT_GENERIC0_3 0x747c 768 #define AFMT_GENERIC0_4 0x7480 769 #define AFMT_GENERIC0_5 0x7484 770 #define AFMT_GENERIC0_6 0x7488 771 #define AFMT_GENERIC1_HDR 0x748c 772 #define AFMT_GENERIC1_0 0x7490 773 #define AFMT_GENERIC1_1 0x7494 774 #define AFMT_GENERIC1_2 0x7498 775 #define AFMT_GENERIC1_3 0x749c 776 #define AFMT_GENERIC1_4 0x74a0 777 #define AFMT_GENERIC1_5 0x74a4 778 #define AFMT_GENERIC1_6 0x74a8 779 #define HDMI_ACR_32_0 0x74ac 780 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 781 #define HDMI_ACR_32_1 0x74b0 782 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 783 #define HDMI_ACR_44_0 0x74b4 784 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 785 #define HDMI_ACR_44_1 0x74b8 786 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 787 #define HDMI_ACR_48_0 0x74bc 788 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 789 #define HDMI_ACR_48_1 0x74c0 790 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 791 #define HDMI_ACR_STATUS_0 0x74c4 792 #define HDMI_ACR_STATUS_1 0x74c8 793 #define AFMT_AUDIO_INFO0 0x74cc 794 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 795 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 796 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 797 #define AFMT_AUDIO_INFO1 0x74d0 798 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 799 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 800 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 801 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 802 #define AFMT_60958_0 0x74d4 803 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 804 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 805 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 806 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 807 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 808 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 809 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 810 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 811 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 812 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 813 #define AFMT_60958_1 0x74d8 814 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 815 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 816 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 817 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 818 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 819 #define AFMT_AUDIO_CRC_CONTROL 0x74dc 820 # define AFMT_AUDIO_CRC_EN (1 << 0) 821 #define AFMT_RAMP_CONTROL0 0x74e0 822 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 823 # define AFMT_RAMP_DATA_SIGN (1 << 31) 824 #define AFMT_RAMP_CONTROL1 0x74e4 825 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 826 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 827 #define AFMT_RAMP_CONTROL2 0x74e8 828 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 829 #define AFMT_RAMP_CONTROL3 0x74ec 830 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 831 #define AFMT_60958_2 0x74f0 832 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 833 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 834 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 835 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 836 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 837 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 838 #define AFMT_STATUS 0x7600 839 # define AFMT_AUDIO_ENABLE (1 << 4) 840 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 841 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 842 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 843 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 844 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 845 # define AFMT_AUDIO_TEST_EN (1 << 12) 846 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 847 # define AFMT_60958_CS_UPDATE (1 << 26) 848 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 849 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 850 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 851 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 852 #define AFMT_VBI_PACKET_CONTROL 0x7608 853 # define AFMT_GENERIC0_UPDATE (1 << 2) 854 #define AFMT_INFOFRAME_CONTROL0 0x760c 855 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ 856 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 857 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 858 #define AFMT_GENERIC0_7 0x7610 859 /* second instance starts at 0x7800 */ 860 #define HDMI_OFFSET0 (0x7400 - 0x7400) 861 #define HDMI_OFFSET1 (0x7800 - 0x7400) 862 863 /* DCE3.2 ELD audio interface */ 864 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 865 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 866 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 867 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 868 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 869 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 870 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 871 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 872 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 873 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 874 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 875 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 876 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 877 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 878 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 879 /* max channels minus one. 7 = 8 channels */ 880 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 881 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 882 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 883 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 884 * bit0 = 32 kHz 885 * bit1 = 44.1 kHz 886 * bit2 = 48 kHz 887 * bit3 = 88.2 kHz 888 * bit4 = 96 kHz 889 * bit5 = 176.4 kHz 890 * bit6 = 192 kHz 891 */ 892 893 #define AZ_HOT_PLUG_CONTROL 0x7300 894 # define AZ_FORCE_CODEC_WAKE (1 << 0) 895 # define PIN0_JACK_DETECTION_ENABLE (1 << 4) 896 # define PIN1_JACK_DETECTION_ENABLE (1 << 5) 897 # define PIN2_JACK_DETECTION_ENABLE (1 << 6) 898 # define PIN3_JACK_DETECTION_ENABLE (1 << 7) 899 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 900 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 901 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 902 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 903 # define CODEC_HOT_PLUG_ENABLE (1 << 12) 904 # define PIN0_AUDIO_ENABLED (1 << 24) 905 # define PIN1_AUDIO_ENABLED (1 << 25) 906 # define PIN2_AUDIO_ENABLED (1 << 26) 907 # define PIN3_AUDIO_ENABLED (1 << 27) 908 # define AUDIO_ENABLED (1 << 31) 909 910 911 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 912 #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 913 #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 914 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 915 #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 916 #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 917 918 /* PCIE indirect regs */ 919 #define PCIE_P_CNTL 0x40 920 # define P_PLL_PWRDN_IN_L1L23 (1 << 3) 921 # define P_PLL_BUF_PDNB (1 << 4) 922 # define P_PLL_PDNB (1 << 9) 923 # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) 924 /* PCIE PORT regs */ 925 #define PCIE_LC_CNTL 0xa0 926 # define LC_L0S_INACTIVITY(x) ((x) << 8) 927 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 928 # define LC_L0S_INACTIVITY_SHIFT 8 929 # define LC_L1_INACTIVITY(x) ((x) << 12) 930 # define LC_L1_INACTIVITY_MASK (0xf << 12) 931 # define LC_L1_INACTIVITY_SHIFT 12 932 # define LC_PMI_TO_L1_DIS (1 << 16) 933 # define LC_ASPM_TO_L1_DIS (1 << 24) 934 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 935 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 936 # define LC_LINK_WIDTH_SHIFT 0 937 # define LC_LINK_WIDTH_MASK 0x7 938 # define LC_LINK_WIDTH_X0 0 939 # define LC_LINK_WIDTH_X1 1 940 # define LC_LINK_WIDTH_X2 2 941 # define LC_LINK_WIDTH_X4 3 942 # define LC_LINK_WIDTH_X8 4 943 # define LC_LINK_WIDTH_X16 6 944 # define LC_LINK_WIDTH_RD_SHIFT 4 945 # define LC_LINK_WIDTH_RD_MASK 0x70 946 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 947 # define LC_RECONFIG_NOW (1 << 8) 948 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 949 # define LC_RENEGOTIATE_EN (1 << 10) 950 # define LC_SHORT_RECONFIG_EN (1 << 11) 951 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 952 # define LC_UPCONFIGURE_DIS (1 << 13) 953 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 954 # define LC_GEN2_EN_STRAP (1 << 0) 955 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 956 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 957 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 958 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 959 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 960 # define LC_CURRENT_DATA_RATE (1 << 11) 961 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 962 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 963 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 964 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 965 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 966 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 967 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 968 #define MM_CFGREGS_CNTL 0x544c 969 # define MM_WR_TO_CFG_EN (1 << 3) 970 #define LINK_CNTL2 0x88 /* F0 */ 971 # define TARGET_LINK_SPEED_MASK (0xf << 0) 972 # define SELECTABLE_DEEMPHASIS (1 << 6) 973 974 /* 975 * PM4 976 */ 977 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 978 (((reg) >> 2) & 0xFFFF) | \ 979 ((n) & 0x3FFF) << 16) 980 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 981 (((op) & 0xFF) << 8) | \ 982 ((n) & 0x3FFF) << 16) 983 984 /* UVD */ 985 #define UVD_GPCOM_VCPU_CMD 0xef0c 986 #define UVD_GPCOM_VCPU_DATA0 0xef10 987 #define UVD_GPCOM_VCPU_DATA1 0xef14 988 989 #define UVD_LMI_EXT40_ADDR 0xf498 990 #define UVD_VCPU_CHIP_ID 0xf4d4 991 #define UVD_VCPU_CACHE_OFFSET0 0xf4d8 992 #define UVD_VCPU_CACHE_SIZE0 0xf4dc 993 #define UVD_VCPU_CACHE_OFFSET1 0xf4e0 994 #define UVD_VCPU_CACHE_SIZE1 0xf4e4 995 #define UVD_VCPU_CACHE_OFFSET2 0xf4e8 996 #define UVD_VCPU_CACHE_SIZE2 0xf4ec 997 #define UVD_LMI_ADDR_EXT 0xf594 998 999 #define UVD_RBC_RB_RPTR 0xf690 1000 #define UVD_RBC_RB_WPTR 0xf694 1001 1002 #define UVD_CONTEXT_ID 0xf6f4 1003 1004 #endif 1005