1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef RV770_H 28 #define RV770_H 29 30 #define R7XX_MAX_SH_GPRS 256 31 #define R7XX_MAX_TEMP_GPRS 16 32 #define R7XX_MAX_SH_THREADS 256 33 #define R7XX_MAX_SH_STACK_ENTRIES 4096 34 #define R7XX_MAX_BACKENDS 8 35 #define R7XX_MAX_BACKENDS_MASK 0xff 36 #define R7XX_MAX_SIMDS 16 37 #define R7XX_MAX_SIMDS_MASK 0xffff 38 #define R7XX_MAX_PIPES 8 39 #define R7XX_MAX_PIPES_MASK 0xff 40 41 /* Registers */ 42 #define CB_COLOR0_BASE 0x28040 43 #define CB_COLOR1_BASE 0x28044 44 #define CB_COLOR2_BASE 0x28048 45 #define CB_COLOR3_BASE 0x2804C 46 #define CB_COLOR4_BASE 0x28050 47 #define CB_COLOR5_BASE 0x28054 48 #define CB_COLOR6_BASE 0x28058 49 #define CB_COLOR7_BASE 0x2805C 50 #define CB_COLOR7_FRAG 0x280FC 51 52 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 53 #define CC_RB_BACKEND_DISABLE 0x98F4 54 #define BACKEND_DISABLE(x) ((x) << 16) 55 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 56 57 #define CGTS_SYS_TCC_DISABLE 0x3F90 58 #define CGTS_TCC_DISABLE 0x9148 59 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 60 #define CGTS_USER_TCC_DISABLE 0x914C 61 62 #define CONFIG_MEMSIZE 0x5428 63 64 #define CP_ME_CNTL 0x86D8 65 #define CP_ME_HALT (1<<28) 66 #define CP_PFP_HALT (1<<26) 67 #define CP_ME_RAM_DATA 0xC160 68 #define CP_ME_RAM_RADDR 0xC158 69 #define CP_ME_RAM_WADDR 0xC15C 70 #define CP_MEQ_THRESHOLDS 0x8764 71 #define STQ_SPLIT(x) ((x) << 0) 72 #define CP_PERFMON_CNTL 0x87FC 73 #define CP_PFP_UCODE_ADDR 0xC150 74 #define CP_PFP_UCODE_DATA 0xC154 75 #define CP_QUEUE_THRESHOLDS 0x8760 76 #define ROQ_IB1_START(x) ((x) << 0) 77 #define ROQ_IB2_START(x) ((x) << 8) 78 #define CP_RB_CNTL 0xC104 79 #define RB_BUFSZ(x) ((x) << 0) 80 #define RB_BLKSZ(x) ((x) << 8) 81 #define RB_NO_UPDATE (1 << 27) 82 #define RB_RPTR_WR_ENA (1 << 31) 83 #define BUF_SWAP_32BIT (2 << 16) 84 #define CP_RB_RPTR 0x8700 85 #define CP_RB_RPTR_ADDR 0xC10C 86 #define CP_RB_RPTR_ADDR_HI 0xC110 87 #define CP_RB_RPTR_WR 0xC108 88 #define CP_RB_WPTR 0xC114 89 #define CP_RB_WPTR_ADDR 0xC118 90 #define CP_RB_WPTR_ADDR_HI 0xC11C 91 #define CP_RB_WPTR_DELAY 0x8704 92 #define CP_SEM_WAIT_TIMER 0x85BC 93 94 #define DB_DEBUG3 0x98B0 95 #define DB_CLK_OFF_DELAY(x) ((x) << 11) 96 #define DB_DEBUG4 0x9B8C 97 #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 98 99 #define DCP_TILING_CONFIG 0x6CA0 100 #define PIPE_TILING(x) ((x) << 1) 101 #define BANK_TILING(x) ((x) << 4) 102 #define GROUP_SIZE(x) ((x) << 6) 103 #define ROW_TILING(x) ((x) << 8) 104 #define BANK_SWAPS(x) ((x) << 11) 105 #define SAMPLE_SPLIT(x) ((x) << 14) 106 #define BACKEND_MAP(x) ((x) << 16) 107 108 #define GB_TILING_CONFIG 0x98F0 109 #define PIPE_TILING__SHIFT 1 110 #define PIPE_TILING__MASK 0x0000000e 111 112 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 113 #define INACTIVE_QD_PIPES(x) ((x) << 8) 114 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 115 #define INACTIVE_QD_PIPES_SHIFT 8 116 #define INACTIVE_SIMDS(x) ((x) << 16) 117 #define INACTIVE_SIMDS_MASK 0x00FF0000 118 119 #define GRBM_CNTL 0x8000 120 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 121 #define GRBM_SOFT_RESET 0x8020 122 #define SOFT_RESET_CP (1<<0) 123 #define GRBM_STATUS 0x8010 124 #define CMDFIFO_AVAIL_MASK 0x0000000F 125 #define GUI_ACTIVE (1<<31) 126 #define GRBM_STATUS2 0x8014 127 128 #define CG_MULT_THERMAL_STATUS 0x740 129 #define ASIC_T(x) ((x) << 16) 130 #define ASIC_T_MASK 0x3FF0000 131 #define ASIC_T_SHIFT 16 132 133 #define HDP_HOST_PATH_CNTL 0x2C00 134 #define HDP_NONSURFACE_BASE 0x2C04 135 #define HDP_NONSURFACE_INFO 0x2C08 136 #define HDP_NONSURFACE_SIZE 0x2C0C 137 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 138 #define HDP_TILING_CONFIG 0x2F3C 139 #define HDP_DEBUG1 0x2F34 140 141 #define MC_SHARED_CHMAP 0x2004 142 #define NOOFCHAN_SHIFT 12 143 #define NOOFCHAN_MASK 0x00003000 144 #define MC_SHARED_CHREMAP 0x2008 145 146 #define MC_ARB_RAMCFG 0x2760 147 #define NOOFBANK_SHIFT 0 148 #define NOOFBANK_MASK 0x00000003 149 #define NOOFRANK_SHIFT 2 150 #define NOOFRANK_MASK 0x00000004 151 #define NOOFROWS_SHIFT 3 152 #define NOOFROWS_MASK 0x00000038 153 #define NOOFCOLS_SHIFT 6 154 #define NOOFCOLS_MASK 0x000000C0 155 #define CHANSIZE_SHIFT 8 156 #define CHANSIZE_MASK 0x00000100 157 #define BURSTLENGTH_SHIFT 9 158 #define BURSTLENGTH_MASK 0x00000200 159 #define CHANSIZE_OVERRIDE (1 << 11) 160 #define MC_VM_AGP_TOP 0x2028 161 #define MC_VM_AGP_BOT 0x202C 162 #define MC_VM_AGP_BASE 0x2030 163 #define MC_VM_FB_LOCATION 0x2024 164 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 165 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 166 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 167 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 168 #define ENABLE_L1_TLB (1 << 0) 169 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 170 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 171 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 172 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 173 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 174 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 175 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 176 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 177 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 178 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 179 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 180 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 181 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 182 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 183 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 184 185 #define PA_CL_ENHANCE 0x8A14 186 #define CLIP_VTX_REORDER_ENA (1 << 0) 187 #define NUM_CLIP_SEQ(x) ((x) << 1) 188 #define PA_SC_AA_CONFIG 0x28C04 189 #define PA_SC_CLIPRECT_RULE 0x2820C 190 #define PA_SC_EDGERULE 0x28230 191 #define PA_SC_FIFO_SIZE 0x8BCC 192 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 193 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 194 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 195 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 196 #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 197 #define PA_SC_LINE_STIPPLE 0x28A0C 198 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 199 #define PA_SC_MODE_CNTL 0x28A4C 200 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 201 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 202 203 #define SCRATCH_REG0 0x8500 204 #define SCRATCH_REG1 0x8504 205 #define SCRATCH_REG2 0x8508 206 #define SCRATCH_REG3 0x850C 207 #define SCRATCH_REG4 0x8510 208 #define SCRATCH_REG5 0x8514 209 #define SCRATCH_REG6 0x8518 210 #define SCRATCH_REG7 0x851C 211 #define SCRATCH_UMSK 0x8540 212 #define SCRATCH_ADDR 0x8544 213 214 #define SMX_SAR_CTL0 0xA008 215 #define SMX_DC_CTL0 0xA020 216 #define USE_HASH_FUNCTION (1 << 0) 217 #define CACHE_DEPTH(x) ((x) << 1) 218 #define FLUSH_ALL_ON_EVENT (1 << 10) 219 #define STALL_ON_EVENT (1 << 11) 220 #define SMX_EVENT_CTL 0xA02C 221 #define ES_FLUSH_CTL(x) ((x) << 0) 222 #define GS_FLUSH_CTL(x) ((x) << 3) 223 #define ACK_FLUSH_CTL(x) ((x) << 6) 224 #define SYNC_FLUSH_CTL (1 << 8) 225 226 #define SPI_CONFIG_CNTL 0x9100 227 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 228 #define DISABLE_INTERP_1 (1 << 5) 229 #define SPI_CONFIG_CNTL_1 0x913C 230 #define VTX_DONE_DELAY(x) ((x) << 0) 231 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 232 #define SPI_INPUT_Z 0x286D8 233 #define SPI_PS_IN_CONTROL_0 0x286CC 234 #define NUM_INTERP(x) ((x)<<0) 235 #define POSITION_ENA (1<<8) 236 #define POSITION_CENTROID (1<<9) 237 #define POSITION_ADDR(x) ((x)<<10) 238 #define PARAM_GEN(x) ((x)<<15) 239 #define PARAM_GEN_ADDR(x) ((x)<<19) 240 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 241 #define PERSP_GRADIENT_ENA (1<<28) 242 #define LINEAR_GRADIENT_ENA (1<<29) 243 #define POSITION_SAMPLE (1<<30) 244 #define BARYC_AT_SAMPLE_ENA (1<<31) 245 246 #define SQ_CONFIG 0x8C00 247 #define VC_ENABLE (1 << 0) 248 #define EXPORT_SRC_C (1 << 1) 249 #define DX9_CONSTS (1 << 2) 250 #define ALU_INST_PREFER_VECTOR (1 << 3) 251 #define DX10_CLAMP (1 << 4) 252 #define CLAUSE_SEQ_PRIO(x) ((x) << 8) 253 #define PS_PRIO(x) ((x) << 24) 254 #define VS_PRIO(x) ((x) << 26) 255 #define GS_PRIO(x) ((x) << 28) 256 #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 257 #define SIMDA_RING0(x) ((x)<<0) 258 #define SIMDA_RING1(x) ((x)<<8) 259 #define SIMDB_RING0(x) ((x)<<16) 260 #define SIMDB_RING1(x) ((x)<<24) 261 #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 262 #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 263 #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 264 #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 265 #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 266 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 267 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 268 #define ES_PRIO(x) ((x) << 30) 269 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 270 #define NUM_PS_GPRS(x) ((x) << 0) 271 #define NUM_VS_GPRS(x) ((x) << 16) 272 #define DYN_GPR_ENABLE (1 << 27) 273 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 274 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 275 #define NUM_GS_GPRS(x) ((x) << 0) 276 #define NUM_ES_GPRS(x) ((x) << 16) 277 #define SQ_MS_FIFO_SIZES 0x8CF0 278 #define CACHE_FIFO_SIZE(x) ((x) << 0) 279 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 280 #define DONE_FIFO_HIWATER(x) ((x) << 16) 281 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 282 #define SQ_STACK_RESOURCE_MGMT_1 0x8C10 283 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 284 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 285 #define SQ_STACK_RESOURCE_MGMT_2 0x8C14 286 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 287 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 288 #define SQ_THREAD_RESOURCE_MGMT 0x8C0C 289 #define NUM_PS_THREADS(x) ((x) << 0) 290 #define NUM_VS_THREADS(x) ((x) << 8) 291 #define NUM_GS_THREADS(x) ((x) << 16) 292 #define NUM_ES_THREADS(x) ((x) << 24) 293 294 #define SX_DEBUG_1 0x9058 295 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 296 #define SX_EXPORT_BUFFER_SIZES 0x900C 297 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 298 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 299 #define SMX_BUFFER_SIZE(x) ((x) << 16) 300 #define SX_MISC 0x28350 301 302 #define TA_CNTL_AUX 0x9508 303 #define DISABLE_CUBE_WRAP (1 << 0) 304 #define DISABLE_CUBE_ANISO (1 << 1) 305 #define SYNC_GRADIENT (1 << 24) 306 #define SYNC_WALKER (1 << 25) 307 #define SYNC_ALIGNER (1 << 26) 308 #define BILINEAR_PRECISION_6_BIT (0 << 31) 309 #define BILINEAR_PRECISION_8_BIT (1 << 31) 310 311 #define TCP_CNTL 0x9610 312 #define TCP_CHAN_STEER 0x9614 313 314 #define VC_ENHANCE 0x9714 315 316 #define VGT_CACHE_INVALIDATION 0x88C4 317 #define CACHE_INVALIDATION(x) ((x)<<0) 318 #define VC_ONLY 0 319 #define TC_ONLY 1 320 #define VC_AND_TC 2 321 #define AUTO_INVLD_EN(x) ((x) << 6) 322 #define NO_AUTO 0 323 #define ES_AUTO 1 324 #define GS_AUTO 2 325 #define ES_AND_GS_AUTO 3 326 #define VGT_ES_PER_GS 0x88CC 327 #define VGT_GS_PER_ES 0x88C8 328 #define VGT_GS_PER_VS 0x88E8 329 #define VGT_GS_VERTEX_REUSE 0x88D4 330 #define VGT_NUM_INSTANCES 0x8974 331 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 332 #define DEALLOC_DIST_MASK 0x0000007F 333 #define VGT_STRMOUT_EN 0x28AB0 334 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 335 #define VTX_REUSE_DEPTH_MASK 0x000000FF 336 337 #define VM_CONTEXT0_CNTL 0x1410 338 #define ENABLE_CONTEXT (1 << 0) 339 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 340 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 341 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 342 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 343 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 344 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 345 #define VM_L2_CNTL 0x1400 346 #define ENABLE_L2_CACHE (1 << 0) 347 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 348 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 349 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 350 #define VM_L2_CNTL2 0x1404 351 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 352 #define INVALIDATE_L2_CACHE (1 << 1) 353 #define VM_L2_CNTL3 0x1408 354 #define BANK_SELECT(x) ((x) << 0) 355 #define CACHE_UPDATE_MODE(x) ((x) << 6) 356 #define VM_L2_STATUS 0x140C 357 #define L2_BUSY (1 << 0) 358 359 #define WAIT_UNTIL 0x8040 360 361 #define SRBM_STATUS 0x0E50 362 363 /* DCE 3.2 HDMI */ 364 #define HDMI_CONTROL 0x7400 365 # define HDMI_KEEPOUT_MODE (1 << 0) 366 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 367 # define HDMI_ERROR_ACK (1 << 8) 368 # define HDMI_ERROR_MASK (1 << 9) 369 #define HDMI_STATUS 0x7404 370 # define HDMI_ACTIVE_AVMUTE (1 << 0) 371 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 372 # define HDMI_VBI_PACKET_ERROR (1 << 20) 373 #define HDMI_AUDIO_PACKET_CONTROL 0x7408 374 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 375 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 376 #define HDMI_ACR_PACKET_CONTROL 0x740c 377 # define HDMI_ACR_SEND (1 << 0) 378 # define HDMI_ACR_CONT (1 << 1) 379 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 380 # define HDMI_ACR_HW 0 381 # define HDMI_ACR_32 1 382 # define HDMI_ACR_44 2 383 # define HDMI_ACR_48 3 384 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 385 # define HDMI_ACR_AUTO_SEND (1 << 12) 386 #define HDMI_VBI_PACKET_CONTROL 0x7410 387 # define HDMI_NULL_SEND (1 << 0) 388 # define HDMI_GC_SEND (1 << 4) 389 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 390 #define HDMI_INFOFRAME_CONTROL0 0x7414 391 # define HDMI_AVI_INFO_SEND (1 << 0) 392 # define HDMI_AVI_INFO_CONT (1 << 1) 393 # define HDMI_AUDIO_INFO_SEND (1 << 4) 394 # define HDMI_AUDIO_INFO_CONT (1 << 5) 395 # define HDMI_MPEG_INFO_SEND (1 << 8) 396 # define HDMI_MPEG_INFO_CONT (1 << 9) 397 #define HDMI_INFOFRAME_CONTROL1 0x7418 398 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 399 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 400 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 401 #define HDMI_GENERIC_PACKET_CONTROL 0x741c 402 # define HDMI_GENERIC0_SEND (1 << 0) 403 # define HDMI_GENERIC0_CONT (1 << 1) 404 # define HDMI_GENERIC1_SEND (1 << 4) 405 # define HDMI_GENERIC1_CONT (1 << 5) 406 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 407 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 408 #define HDMI_GC 0x7428 409 # define HDMI_GC_AVMUTE (1 << 0) 410 #define AFMT_AUDIO_PACKET_CONTROL2 0x742c 411 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 412 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 413 # define AFMT_60958_CS_SOURCE (1 << 4) 414 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 415 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 416 #define AFMT_AVI_INFO0 0x7454 417 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 418 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 419 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 420 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 421 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 422 # define AFMT_AVI_INFO_Y_RGB 0 423 # define AFMT_AVI_INFO_Y_YCBCR422 1 424 # define AFMT_AVI_INFO_Y_YCBCR444 2 425 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 426 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 427 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 428 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 429 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 430 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 431 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 432 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 433 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 434 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 435 #define AFMT_AVI_INFO1 0x7458 436 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 437 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 438 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 439 #define AFMT_AVI_INFO2 0x745c 440 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 441 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 442 #define AFMT_AVI_INFO3 0x7460 443 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 444 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 445 #define AFMT_MPEG_INFO0 0x7464 446 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 447 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 448 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 449 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 450 #define AFMT_MPEG_INFO1 0x7468 451 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 452 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 453 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 454 #define AFMT_GENERIC0_HDR 0x746c 455 #define AFMT_GENERIC0_0 0x7470 456 #define AFMT_GENERIC0_1 0x7474 457 #define AFMT_GENERIC0_2 0x7478 458 #define AFMT_GENERIC0_3 0x747c 459 #define AFMT_GENERIC0_4 0x7480 460 #define AFMT_GENERIC0_5 0x7484 461 #define AFMT_GENERIC0_6 0x7488 462 #define AFMT_GENERIC1_HDR 0x748c 463 #define AFMT_GENERIC1_0 0x7490 464 #define AFMT_GENERIC1_1 0x7494 465 #define AFMT_GENERIC1_2 0x7498 466 #define AFMT_GENERIC1_3 0x749c 467 #define AFMT_GENERIC1_4 0x74a0 468 #define AFMT_GENERIC1_5 0x74a4 469 #define AFMT_GENERIC1_6 0x74a8 470 #define HDMI_ACR_32_0 0x74ac 471 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 472 #define HDMI_ACR_32_1 0x74b0 473 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 474 #define HDMI_ACR_44_0 0x74b4 475 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 476 #define HDMI_ACR_44_1 0x74b8 477 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 478 #define HDMI_ACR_48_0 0x74bc 479 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 480 #define HDMI_ACR_48_1 0x74c0 481 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 482 #define HDMI_ACR_STATUS_0 0x74c4 483 #define HDMI_ACR_STATUS_1 0x74c8 484 #define AFMT_AUDIO_INFO0 0x74cc 485 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 486 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 487 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 488 #define AFMT_AUDIO_INFO1 0x74d0 489 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 490 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 491 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 492 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 493 #define AFMT_60958_0 0x74d4 494 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 495 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 496 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 497 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 498 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 499 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 500 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 501 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 502 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 503 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 504 #define AFMT_60958_1 0x74d8 505 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 506 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 507 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 508 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 509 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 510 #define AFMT_AUDIO_CRC_CONTROL 0x74dc 511 # define AFMT_AUDIO_CRC_EN (1 << 0) 512 #define AFMT_RAMP_CONTROL0 0x74e0 513 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 514 # define AFMT_RAMP_DATA_SIGN (1 << 31) 515 #define AFMT_RAMP_CONTROL1 0x74e4 516 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 517 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 518 #define AFMT_RAMP_CONTROL2 0x74e8 519 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 520 #define AFMT_RAMP_CONTROL3 0x74ec 521 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 522 #define AFMT_60958_2 0x74f0 523 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 524 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 525 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 526 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 527 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 528 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 529 #define AFMT_STATUS 0x7600 530 # define AFMT_AUDIO_ENABLE (1 << 4) 531 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 532 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 533 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 534 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 535 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 536 # define AFMT_AUDIO_TEST_EN (1 << 12) 537 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 538 # define AFMT_60958_CS_UPDATE (1 << 26) 539 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 540 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 541 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 542 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 543 #define AFMT_VBI_PACKET_CONTROL 0x7608 544 # define AFMT_GENERIC0_UPDATE (1 << 2) 545 #define AFMT_INFOFRAME_CONTROL0 0x760c 546 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 547 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 548 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 549 #define AFMT_GENERIC0_7 0x7610 550 /* second instance starts at 0x7800 */ 551 #define HDMI_OFFSET0 (0x7400 - 0x7400) 552 #define HDMI_OFFSET1 (0x7800 - 0x7400) 553 554 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 555 #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 556 #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 557 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 558 #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 559 #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 560 561 /* PCIE link stuff */ 562 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 563 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 564 # define LC_LINK_WIDTH_SHIFT 0 565 # define LC_LINK_WIDTH_MASK 0x7 566 # define LC_LINK_WIDTH_X0 0 567 # define LC_LINK_WIDTH_X1 1 568 # define LC_LINK_WIDTH_X2 2 569 # define LC_LINK_WIDTH_X4 3 570 # define LC_LINK_WIDTH_X8 4 571 # define LC_LINK_WIDTH_X16 6 572 # define LC_LINK_WIDTH_RD_SHIFT 4 573 # define LC_LINK_WIDTH_RD_MASK 0x70 574 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 575 # define LC_RECONFIG_NOW (1 << 8) 576 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 577 # define LC_RENEGOTIATE_EN (1 << 10) 578 # define LC_SHORT_RECONFIG_EN (1 << 11) 579 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 580 # define LC_UPCONFIGURE_DIS (1 << 13) 581 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 582 # define LC_GEN2_EN_STRAP (1 << 0) 583 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 584 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 585 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 586 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 587 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 588 # define LC_CURRENT_DATA_RATE (1 << 11) 589 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 590 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 591 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 592 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 593 #define MM_CFGREGS_CNTL 0x544c 594 # define MM_WR_TO_CFG_EN (1 << 3) 595 #define LINK_CNTL2 0x88 /* F0 */ 596 # define TARGET_LINK_SPEED_MASK (0xf << 0) 597 # define SELECTABLE_DEEMPHASIS (1 << 6) 598 599 #endif 600