1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <linux/platform_device.h> 30 #include "drmP.h" 31 #include "radeon.h" 32 #include "radeon_drm.h" 33 #include "rv770d.h" 34 #include "atom.h" 35 #include "avivod.h" 36 37 #define R700_PFP_UCODE_SIZE 848 38 #define R700_PM4_UCODE_SIZE 1360 39 40 static void rv770_gpu_init(struct radeon_device *rdev); 41 void rv770_fini(struct radeon_device *rdev); 42 43 44 /* 45 * GART 46 */ 47 int rv770_pcie_gart_enable(struct radeon_device *rdev) 48 { 49 u32 tmp; 50 int r, i; 51 52 if (rdev->gart.table.vram.robj == NULL) { 53 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 54 return -EINVAL; 55 } 56 r = radeon_gart_table_vram_pin(rdev); 57 if (r) 58 return r; 59 /* Setup L2 cache */ 60 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 61 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 62 EFFECTIVE_L2_QUEUE_SIZE(7)); 63 WREG32(VM_L2_CNTL2, 0); 64 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 65 /* Setup TLB control */ 66 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 67 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 68 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 69 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 70 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 71 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 72 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 73 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 74 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 75 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 76 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 77 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 78 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 79 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 80 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 81 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 82 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 83 (u32)(rdev->dummy_page.addr >> 12)); 84 for (i = 1; i < 7; i++) 85 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 86 87 r600_pcie_gart_tlb_flush(rdev); 88 rdev->gart.ready = true; 89 return 0; 90 } 91 92 void rv770_pcie_gart_disable(struct radeon_device *rdev) 93 { 94 u32 tmp; 95 int i, r; 96 97 /* Disable all tables */ 98 for (i = 0; i < 7; i++) 99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 100 101 /* Setup L2 cache */ 102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 103 EFFECTIVE_L2_QUEUE_SIZE(7)); 104 WREG32(VM_L2_CNTL2, 0); 105 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 106 /* Setup TLB control */ 107 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 115 if (rdev->gart.table.vram.robj) { 116 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 117 if (likely(r == 0)) { 118 radeon_bo_kunmap(rdev->gart.table.vram.robj); 119 radeon_bo_unpin(rdev->gart.table.vram.robj); 120 radeon_bo_unreserve(rdev->gart.table.vram.robj); 121 } 122 } 123 } 124 125 void rv770_pcie_gart_fini(struct radeon_device *rdev) 126 { 127 rv770_pcie_gart_disable(rdev); 128 radeon_gart_table_vram_free(rdev); 129 radeon_gart_fini(rdev); 130 } 131 132 133 void rv770_agp_enable(struct radeon_device *rdev) 134 { 135 u32 tmp; 136 int i; 137 138 /* Setup L2 cache */ 139 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 140 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 141 EFFECTIVE_L2_QUEUE_SIZE(7)); 142 WREG32(VM_L2_CNTL2, 0); 143 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 144 /* Setup TLB control */ 145 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 146 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 147 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 148 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 149 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 150 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 151 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 152 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 153 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 154 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 155 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 156 for (i = 0; i < 7; i++) 157 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 158 } 159 160 static void rv770_mc_program(struct radeon_device *rdev) 161 { 162 struct rv515_mc_save save; 163 u32 tmp; 164 int i, j; 165 166 /* Initialize HDP */ 167 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 168 WREG32((0x2c14 + j), 0x00000000); 169 WREG32((0x2c18 + j), 0x00000000); 170 WREG32((0x2c1c + j), 0x00000000); 171 WREG32((0x2c20 + j), 0x00000000); 172 WREG32((0x2c24 + j), 0x00000000); 173 } 174 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 175 176 rv515_mc_stop(rdev, &save); 177 if (r600_mc_wait_for_idle(rdev)) { 178 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 179 } 180 /* Lockout access through VGA aperture*/ 181 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 182 /* Update configuration */ 183 if (rdev->flags & RADEON_IS_AGP) { 184 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 185 /* VRAM before AGP */ 186 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 187 rdev->mc.vram_start >> 12); 188 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 189 rdev->mc.gtt_end >> 12); 190 } else { 191 /* VRAM after AGP */ 192 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 193 rdev->mc.gtt_start >> 12); 194 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 195 rdev->mc.vram_end >> 12); 196 } 197 } else { 198 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 199 rdev->mc.vram_start >> 12); 200 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 201 rdev->mc.vram_end >> 12); 202 } 203 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 204 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 205 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 206 WREG32(MC_VM_FB_LOCATION, tmp); 207 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 208 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 209 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); 210 if (rdev->flags & RADEON_IS_AGP) { 211 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 212 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 213 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 214 } else { 215 WREG32(MC_VM_AGP_BASE, 0); 216 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 217 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 218 } 219 if (r600_mc_wait_for_idle(rdev)) { 220 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 221 } 222 rv515_mc_resume(rdev, &save); 223 /* we need to own VRAM, so turn off the VGA renderer here 224 * to stop it overwriting our objects */ 225 rv515_vga_render_disable(rdev); 226 } 227 228 229 /* 230 * CP. 231 */ 232 void r700_cp_stop(struct radeon_device *rdev) 233 { 234 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 235 } 236 237 238 static int rv770_cp_load_microcode(struct radeon_device *rdev) 239 { 240 const __be32 *fw_data; 241 int i; 242 243 if (!rdev->me_fw || !rdev->pfp_fw) 244 return -EINVAL; 245 246 r700_cp_stop(rdev); 247 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 248 249 /* Reset cp */ 250 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 251 RREG32(GRBM_SOFT_RESET); 252 mdelay(15); 253 WREG32(GRBM_SOFT_RESET, 0); 254 255 fw_data = (const __be32 *)rdev->pfp_fw->data; 256 WREG32(CP_PFP_UCODE_ADDR, 0); 257 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 258 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 259 WREG32(CP_PFP_UCODE_ADDR, 0); 260 261 fw_data = (const __be32 *)rdev->me_fw->data; 262 WREG32(CP_ME_RAM_WADDR, 0); 263 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 264 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 265 266 WREG32(CP_PFP_UCODE_ADDR, 0); 267 WREG32(CP_ME_RAM_WADDR, 0); 268 WREG32(CP_ME_RAM_RADDR, 0); 269 return 0; 270 } 271 272 273 /* 274 * Core functions 275 */ 276 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 277 u32 num_backends, 278 u32 backend_disable_mask) 279 { 280 u32 backend_map = 0; 281 u32 enabled_backends_mask; 282 u32 enabled_backends_count; 283 u32 cur_pipe; 284 u32 swizzle_pipe[R7XX_MAX_PIPES]; 285 u32 cur_backend; 286 u32 i; 287 288 if (num_tile_pipes > R7XX_MAX_PIPES) 289 num_tile_pipes = R7XX_MAX_PIPES; 290 if (num_tile_pipes < 1) 291 num_tile_pipes = 1; 292 if (num_backends > R7XX_MAX_BACKENDS) 293 num_backends = R7XX_MAX_BACKENDS; 294 if (num_backends < 1) 295 num_backends = 1; 296 297 enabled_backends_mask = 0; 298 enabled_backends_count = 0; 299 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 300 if (((backend_disable_mask >> i) & 1) == 0) { 301 enabled_backends_mask |= (1 << i); 302 ++enabled_backends_count; 303 } 304 if (enabled_backends_count == num_backends) 305 break; 306 } 307 308 if (enabled_backends_count == 0) { 309 enabled_backends_mask = 1; 310 enabled_backends_count = 1; 311 } 312 313 if (enabled_backends_count != num_backends) 314 num_backends = enabled_backends_count; 315 316 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 317 switch (num_tile_pipes) { 318 case 1: 319 swizzle_pipe[0] = 0; 320 break; 321 case 2: 322 swizzle_pipe[0] = 0; 323 swizzle_pipe[1] = 1; 324 break; 325 case 3: 326 swizzle_pipe[0] = 0; 327 swizzle_pipe[1] = 2; 328 swizzle_pipe[2] = 1; 329 break; 330 case 4: 331 swizzle_pipe[0] = 0; 332 swizzle_pipe[1] = 2; 333 swizzle_pipe[2] = 3; 334 swizzle_pipe[3] = 1; 335 break; 336 case 5: 337 swizzle_pipe[0] = 0; 338 swizzle_pipe[1] = 2; 339 swizzle_pipe[2] = 4; 340 swizzle_pipe[3] = 1; 341 swizzle_pipe[4] = 3; 342 break; 343 case 6: 344 swizzle_pipe[0] = 0; 345 swizzle_pipe[1] = 2; 346 swizzle_pipe[2] = 4; 347 swizzle_pipe[3] = 5; 348 swizzle_pipe[4] = 3; 349 swizzle_pipe[5] = 1; 350 break; 351 case 7: 352 swizzle_pipe[0] = 0; 353 swizzle_pipe[1] = 2; 354 swizzle_pipe[2] = 4; 355 swizzle_pipe[3] = 6; 356 swizzle_pipe[4] = 3; 357 swizzle_pipe[5] = 1; 358 swizzle_pipe[6] = 5; 359 break; 360 case 8: 361 swizzle_pipe[0] = 0; 362 swizzle_pipe[1] = 2; 363 swizzle_pipe[2] = 4; 364 swizzle_pipe[3] = 6; 365 swizzle_pipe[4] = 3; 366 swizzle_pipe[5] = 1; 367 swizzle_pipe[6] = 7; 368 swizzle_pipe[7] = 5; 369 break; 370 } 371 372 cur_backend = 0; 373 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 374 while (((1 << cur_backend) & enabled_backends_mask) == 0) 375 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 376 377 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 378 379 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 380 } 381 382 return backend_map; 383 } 384 385 static void rv770_gpu_init(struct radeon_device *rdev) 386 { 387 int i, j, num_qd_pipes; 388 u32 sx_debug_1; 389 u32 smx_dc_ctl0; 390 u32 num_gs_verts_per_thread; 391 u32 vgt_gs_per_es; 392 u32 gs_prim_buffer_depth = 0; 393 u32 sq_ms_fifo_sizes; 394 u32 sq_config; 395 u32 sq_thread_resource_mgmt; 396 u32 hdp_host_path_cntl; 397 u32 sq_dyn_gpr_size_simd_ab_0; 398 u32 backend_map; 399 u32 gb_tiling_config = 0; 400 u32 cc_rb_backend_disable = 0; 401 u32 cc_gc_shader_pipe_config = 0; 402 u32 mc_arb_ramcfg; 403 u32 db_debug4; 404 405 /* setup chip specs */ 406 switch (rdev->family) { 407 case CHIP_RV770: 408 rdev->config.rv770.max_pipes = 4; 409 rdev->config.rv770.max_tile_pipes = 8; 410 rdev->config.rv770.max_simds = 10; 411 rdev->config.rv770.max_backends = 4; 412 rdev->config.rv770.max_gprs = 256; 413 rdev->config.rv770.max_threads = 248; 414 rdev->config.rv770.max_stack_entries = 512; 415 rdev->config.rv770.max_hw_contexts = 8; 416 rdev->config.rv770.max_gs_threads = 16 * 2; 417 rdev->config.rv770.sx_max_export_size = 128; 418 rdev->config.rv770.sx_max_export_pos_size = 16; 419 rdev->config.rv770.sx_max_export_smx_size = 112; 420 rdev->config.rv770.sq_num_cf_insts = 2; 421 422 rdev->config.rv770.sx_num_of_sets = 7; 423 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 424 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 425 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 426 break; 427 case CHIP_RV730: 428 rdev->config.rv770.max_pipes = 2; 429 rdev->config.rv770.max_tile_pipes = 4; 430 rdev->config.rv770.max_simds = 8; 431 rdev->config.rv770.max_backends = 2; 432 rdev->config.rv770.max_gprs = 128; 433 rdev->config.rv770.max_threads = 248; 434 rdev->config.rv770.max_stack_entries = 256; 435 rdev->config.rv770.max_hw_contexts = 8; 436 rdev->config.rv770.max_gs_threads = 16 * 2; 437 rdev->config.rv770.sx_max_export_size = 256; 438 rdev->config.rv770.sx_max_export_pos_size = 32; 439 rdev->config.rv770.sx_max_export_smx_size = 224; 440 rdev->config.rv770.sq_num_cf_insts = 2; 441 442 rdev->config.rv770.sx_num_of_sets = 7; 443 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 444 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 445 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 446 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 447 rdev->config.rv770.sx_max_export_pos_size -= 16; 448 rdev->config.rv770.sx_max_export_smx_size += 16; 449 } 450 break; 451 case CHIP_RV710: 452 rdev->config.rv770.max_pipes = 2; 453 rdev->config.rv770.max_tile_pipes = 2; 454 rdev->config.rv770.max_simds = 2; 455 rdev->config.rv770.max_backends = 1; 456 rdev->config.rv770.max_gprs = 256; 457 rdev->config.rv770.max_threads = 192; 458 rdev->config.rv770.max_stack_entries = 256; 459 rdev->config.rv770.max_hw_contexts = 4; 460 rdev->config.rv770.max_gs_threads = 8 * 2; 461 rdev->config.rv770.sx_max_export_size = 128; 462 rdev->config.rv770.sx_max_export_pos_size = 16; 463 rdev->config.rv770.sx_max_export_smx_size = 112; 464 rdev->config.rv770.sq_num_cf_insts = 1; 465 466 rdev->config.rv770.sx_num_of_sets = 7; 467 rdev->config.rv770.sc_prim_fifo_size = 0x40; 468 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 469 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 470 break; 471 case CHIP_RV740: 472 rdev->config.rv770.max_pipes = 4; 473 rdev->config.rv770.max_tile_pipes = 4; 474 rdev->config.rv770.max_simds = 8; 475 rdev->config.rv770.max_backends = 4; 476 rdev->config.rv770.max_gprs = 256; 477 rdev->config.rv770.max_threads = 248; 478 rdev->config.rv770.max_stack_entries = 512; 479 rdev->config.rv770.max_hw_contexts = 8; 480 rdev->config.rv770.max_gs_threads = 16 * 2; 481 rdev->config.rv770.sx_max_export_size = 256; 482 rdev->config.rv770.sx_max_export_pos_size = 32; 483 rdev->config.rv770.sx_max_export_smx_size = 224; 484 rdev->config.rv770.sq_num_cf_insts = 2; 485 486 rdev->config.rv770.sx_num_of_sets = 7; 487 rdev->config.rv770.sc_prim_fifo_size = 0x100; 488 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 489 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 490 491 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 492 rdev->config.rv770.sx_max_export_pos_size -= 16; 493 rdev->config.rv770.sx_max_export_smx_size += 16; 494 } 495 break; 496 default: 497 break; 498 } 499 500 /* Initialize HDP */ 501 j = 0; 502 for (i = 0; i < 32; i++) { 503 WREG32((0x2c14 + j), 0x00000000); 504 WREG32((0x2c18 + j), 0x00000000); 505 WREG32((0x2c1c + j), 0x00000000); 506 WREG32((0x2c20 + j), 0x00000000); 507 WREG32((0x2c24 + j), 0x00000000); 508 j += 0x18; 509 } 510 511 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 512 513 /* setup tiling, simd, pipe config */ 514 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 515 516 switch (rdev->config.rv770.max_tile_pipes) { 517 case 1: 518 gb_tiling_config |= PIPE_TILING(0); 519 break; 520 case 2: 521 gb_tiling_config |= PIPE_TILING(1); 522 break; 523 case 4: 524 gb_tiling_config |= PIPE_TILING(2); 525 break; 526 case 8: 527 gb_tiling_config |= PIPE_TILING(3); 528 break; 529 default: 530 break; 531 } 532 533 if (rdev->family == CHIP_RV770) 534 gb_tiling_config |= BANK_TILING(1); 535 else 536 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 537 538 gb_tiling_config |= GROUP_SIZE(0); 539 540 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 541 gb_tiling_config |= ROW_TILING(3); 542 gb_tiling_config |= SAMPLE_SPLIT(3); 543 } else { 544 gb_tiling_config |= 545 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 546 gb_tiling_config |= 547 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 548 } 549 550 gb_tiling_config |= BANK_SWAPS(1); 551 552 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, 553 rdev->config.rv770.max_backends, 554 (0xff << rdev->config.rv770.max_backends) & 0xff); 555 gb_tiling_config |= BACKEND_MAP(backend_map); 556 557 cc_gc_shader_pipe_config = 558 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 559 cc_gc_shader_pipe_config |= 560 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 561 562 cc_rb_backend_disable = 563 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 564 565 WREG32(GB_TILING_CONFIG, gb_tiling_config); 566 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 567 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 568 569 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 570 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 571 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 572 573 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 574 WREG32(CGTS_SYS_TCC_DISABLE, 0); 575 WREG32(CGTS_TCC_DISABLE, 0); 576 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 577 WREG32(CGTS_USER_TCC_DISABLE, 0); 578 579 num_qd_pipes = 580 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); 581 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 582 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 583 584 /* set HW defaults for 3D engine */ 585 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 586 ROQ_IB2_START(0x2b))); 587 588 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 589 590 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 591 SYNC_GRADIENT | 592 SYNC_WALKER | 593 SYNC_ALIGNER)); 594 595 sx_debug_1 = RREG32(SX_DEBUG_1); 596 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 597 WREG32(SX_DEBUG_1, sx_debug_1); 598 599 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 600 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 601 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 602 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 603 604 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 605 GS_FLUSH_CTL(4) | 606 ACK_FLUSH_CTL(3) | 607 SYNC_FLUSH_CTL)); 608 609 if (rdev->family == CHIP_RV770) 610 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); 611 else { 612 db_debug4 = RREG32(DB_DEBUG4); 613 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 614 WREG32(DB_DEBUG4, db_debug4); 615 } 616 617 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 618 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 619 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 620 621 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 622 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 623 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 624 625 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 626 627 WREG32(VGT_NUM_INSTANCES, 1); 628 629 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 630 631 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 632 633 WREG32(CP_PERFMON_CNTL, 0); 634 635 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 636 DONE_FIFO_HIWATER(0xe0) | 637 ALU_UPDATE_FIFO_HIWATER(0x8)); 638 switch (rdev->family) { 639 case CHIP_RV770: 640 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 641 break; 642 case CHIP_RV730: 643 case CHIP_RV710: 644 case CHIP_RV740: 645 default: 646 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 647 break; 648 } 649 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 650 651 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 652 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 653 */ 654 sq_config = RREG32(SQ_CONFIG); 655 sq_config &= ~(PS_PRIO(3) | 656 VS_PRIO(3) | 657 GS_PRIO(3) | 658 ES_PRIO(3)); 659 sq_config |= (DX9_CONSTS | 660 VC_ENABLE | 661 EXPORT_SRC_C | 662 PS_PRIO(0) | 663 VS_PRIO(1) | 664 GS_PRIO(2) | 665 ES_PRIO(3)); 666 if (rdev->family == CHIP_RV710) 667 /* no vertex cache */ 668 sq_config &= ~VC_ENABLE; 669 670 WREG32(SQ_CONFIG, sq_config); 671 672 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 673 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 674 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 675 676 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 677 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 678 679 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 680 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 681 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 682 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 683 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 684 else 685 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 686 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 687 688 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 689 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 690 691 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 692 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 693 694 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 695 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 696 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 697 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 698 699 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 700 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 701 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 702 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 703 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 704 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 705 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 706 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 707 708 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 709 FORCE_EOV_MAX_REZ_CNT(255))); 710 711 if (rdev->family == CHIP_RV710) 712 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 713 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 714 else 715 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 716 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 717 718 switch (rdev->family) { 719 case CHIP_RV770: 720 case CHIP_RV730: 721 case CHIP_RV740: 722 gs_prim_buffer_depth = 384; 723 break; 724 case CHIP_RV710: 725 gs_prim_buffer_depth = 128; 726 break; 727 default: 728 break; 729 } 730 731 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 732 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 733 /* Max value for this is 256 */ 734 if (vgt_gs_per_es > 256) 735 vgt_gs_per_es = 256; 736 737 WREG32(VGT_ES_PER_GS, 128); 738 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 739 WREG32(VGT_GS_PER_VS, 2); 740 741 /* more default values. 2D/3D driver should adjust as needed */ 742 WREG32(VGT_GS_VERTEX_REUSE, 16); 743 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 744 WREG32(VGT_STRMOUT_EN, 0); 745 WREG32(SX_MISC, 0); 746 WREG32(PA_SC_MODE_CNTL, 0); 747 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 748 WREG32(PA_SC_AA_CONFIG, 0); 749 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 750 WREG32(PA_SC_LINE_STIPPLE, 0); 751 WREG32(SPI_INPUT_Z, 0); 752 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 753 WREG32(CB_COLOR7_FRAG, 0); 754 755 /* clear render buffer base addresses */ 756 WREG32(CB_COLOR0_BASE, 0); 757 WREG32(CB_COLOR1_BASE, 0); 758 WREG32(CB_COLOR2_BASE, 0); 759 WREG32(CB_COLOR3_BASE, 0); 760 WREG32(CB_COLOR4_BASE, 0); 761 WREG32(CB_COLOR5_BASE, 0); 762 WREG32(CB_COLOR6_BASE, 0); 763 WREG32(CB_COLOR7_BASE, 0); 764 765 WREG32(TCP_CNTL, 0); 766 767 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 768 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 769 770 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 771 772 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 773 NUM_CLIP_SEQ(3))); 774 775 } 776 777 int rv770_mc_init(struct radeon_device *rdev) 778 { 779 fixed20_12 a; 780 u32 tmp; 781 int chansize, numchan; 782 int r; 783 784 /* Get VRAM informations */ 785 rdev->mc.vram_is_ddr = true; 786 tmp = RREG32(MC_ARB_RAMCFG); 787 if (tmp & CHANSIZE_OVERRIDE) { 788 chansize = 16; 789 } else if (tmp & CHANSIZE_MASK) { 790 chansize = 64; 791 } else { 792 chansize = 32; 793 } 794 tmp = RREG32(MC_SHARED_CHMAP); 795 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 796 case 0: 797 default: 798 numchan = 1; 799 break; 800 case 1: 801 numchan = 2; 802 break; 803 case 2: 804 numchan = 4; 805 break; 806 case 3: 807 numchan = 8; 808 break; 809 } 810 rdev->mc.vram_width = numchan * chansize; 811 /* Could aper size report 0 ? */ 812 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 813 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 814 /* Setup GPU memory space */ 815 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 816 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 817 818 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 819 rdev->mc.mc_vram_size = rdev->mc.aper_size; 820 821 if (rdev->mc.real_vram_size > rdev->mc.aper_size) 822 rdev->mc.real_vram_size = rdev->mc.aper_size; 823 824 if (rdev->flags & RADEON_IS_AGP) { 825 r = radeon_agp_init(rdev); 826 if (r) 827 return r; 828 /* gtt_size is setup by radeon_agp_init */ 829 rdev->mc.gtt_location = rdev->mc.agp_base; 830 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 831 /* Try to put vram before or after AGP because we 832 * we want SYSTEM_APERTURE to cover both VRAM and 833 * AGP so that GPU can catch out of VRAM/AGP access 834 */ 835 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { 836 /* Enough place before */ 837 rdev->mc.vram_location = rdev->mc.gtt_location - 838 rdev->mc.mc_vram_size; 839 } else if (tmp > rdev->mc.mc_vram_size) { 840 /* Enough place after */ 841 rdev->mc.vram_location = rdev->mc.gtt_location + 842 rdev->mc.gtt_size; 843 } else { 844 /* Try to setup VRAM then AGP might not 845 * not work on some card 846 */ 847 rdev->mc.vram_location = 0x00000000UL; 848 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 849 } 850 } else { 851 rdev->mc.vram_location = 0x00000000UL; 852 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 853 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 854 } 855 rdev->mc.vram_start = rdev->mc.vram_location; 856 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 857 rdev->mc.gtt_start = rdev->mc.gtt_location; 858 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 859 /* FIXME: we should enforce default clock in case GPU is not in 860 * default setup 861 */ 862 a.full = rfixed_const(100); 863 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 864 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 865 return 0; 866 } 867 int rv770_gpu_reset(struct radeon_device *rdev) 868 { 869 /* FIXME: implement any rv770 specific bits */ 870 return r600_gpu_reset(rdev); 871 } 872 873 static int rv770_startup(struct radeon_device *rdev) 874 { 875 int r; 876 877 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 878 r = r600_init_microcode(rdev); 879 if (r) { 880 DRM_ERROR("Failed to load firmware!\n"); 881 return r; 882 } 883 } 884 885 rv770_mc_program(rdev); 886 if (rdev->flags & RADEON_IS_AGP) { 887 rv770_agp_enable(rdev); 888 } else { 889 r = rv770_pcie_gart_enable(rdev); 890 if (r) 891 return r; 892 } 893 rv770_gpu_init(rdev); 894 895 if (!rdev->r600_blit.shader_obj) { 896 r = r600_blit_init(rdev); 897 if (r) { 898 DRM_ERROR("radeon: failed blitter (%d).\n", r); 899 return r; 900 } 901 } 902 903 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 904 if (unlikely(r != 0)) 905 return r; 906 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 907 &rdev->r600_blit.shader_gpu_addr); 908 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 909 if (r) { 910 DRM_ERROR("failed to pin blit object %d\n", r); 911 return r; 912 } 913 914 /* Enable IRQ */ 915 r = r600_irq_init(rdev); 916 if (r) { 917 DRM_ERROR("radeon: IH init failed (%d).\n", r); 918 radeon_irq_kms_fini(rdev); 919 return r; 920 } 921 r600_irq_set(rdev); 922 923 r = radeon_ring_init(rdev, rdev->cp.ring_size); 924 if (r) 925 return r; 926 r = rv770_cp_load_microcode(rdev); 927 if (r) 928 return r; 929 r = r600_cp_resume(rdev); 930 if (r) 931 return r; 932 /* write back buffer are not vital so don't worry about failure */ 933 r600_wb_enable(rdev); 934 return 0; 935 } 936 937 int rv770_resume(struct radeon_device *rdev) 938 { 939 int r; 940 941 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 942 * posting will perform necessary task to bring back GPU into good 943 * shape. 944 */ 945 /* post card */ 946 atom_asic_init(rdev->mode_info.atom_context); 947 /* Initialize clocks */ 948 r = radeon_clocks_init(rdev); 949 if (r) { 950 return r; 951 } 952 953 r = rv770_startup(rdev); 954 if (r) { 955 DRM_ERROR("r600 startup failed on resume\n"); 956 return r; 957 } 958 959 r = r600_ib_test(rdev); 960 if (r) { 961 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 962 return r; 963 } 964 return r; 965 966 } 967 968 int rv770_suspend(struct radeon_device *rdev) 969 { 970 int r; 971 972 /* FIXME: we should wait for ring to be empty */ 973 r700_cp_stop(rdev); 974 rdev->cp.ready = false; 975 r600_wb_disable(rdev); 976 rv770_pcie_gart_disable(rdev); 977 /* unpin shaders bo */ 978 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 979 if (likely(r == 0)) { 980 radeon_bo_unpin(rdev->r600_blit.shader_obj); 981 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 982 } 983 return 0; 984 } 985 986 /* Plan is to move initialization in that function and use 987 * helper function so that radeon_device_init pretty much 988 * do nothing more than calling asic specific function. This 989 * should also allow to remove a bunch of callback function 990 * like vram_info. 991 */ 992 int rv770_init(struct radeon_device *rdev) 993 { 994 int r; 995 996 r = radeon_dummy_page_init(rdev); 997 if (r) 998 return r; 999 /* This don't do much */ 1000 r = radeon_gem_init(rdev); 1001 if (r) 1002 return r; 1003 /* Read BIOS */ 1004 if (!radeon_get_bios(rdev)) { 1005 if (ASIC_IS_AVIVO(rdev)) 1006 return -EINVAL; 1007 } 1008 /* Must be an ATOMBIOS */ 1009 if (!rdev->is_atom_bios) { 1010 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1011 return -EINVAL; 1012 } 1013 r = radeon_atombios_init(rdev); 1014 if (r) 1015 return r; 1016 /* Post card if necessary */ 1017 if (!r600_card_posted(rdev)) { 1018 if (!rdev->bios) { 1019 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1020 return -EINVAL; 1021 } 1022 DRM_INFO("GPU not posted. posting now...\n"); 1023 atom_asic_init(rdev->mode_info.atom_context); 1024 } 1025 /* Initialize scratch registers */ 1026 r600_scratch_init(rdev); 1027 /* Initialize surface registers */ 1028 radeon_surface_init(rdev); 1029 /* Initialize clocks */ 1030 radeon_get_clock_info(rdev->ddev); 1031 r = radeon_clocks_init(rdev); 1032 if (r) 1033 return r; 1034 /* Initialize power management */ 1035 radeon_pm_init(rdev); 1036 /* Fence driver */ 1037 r = radeon_fence_driver_init(rdev); 1038 if (r) 1039 return r; 1040 r = rv770_mc_init(rdev); 1041 if (r) 1042 return r; 1043 /* Memory manager */ 1044 r = radeon_bo_init(rdev); 1045 if (r) 1046 return r; 1047 1048 r = radeon_irq_kms_init(rdev); 1049 if (r) 1050 return r; 1051 1052 rdev->cp.ring_obj = NULL; 1053 r600_ring_init(rdev, 1024 * 1024); 1054 1055 rdev->ih.ring_obj = NULL; 1056 r600_ih_ring_init(rdev, 64 * 1024); 1057 1058 r = r600_pcie_gart_init(rdev); 1059 if (r) 1060 return r; 1061 1062 rdev->accel_working = true; 1063 r = rv770_startup(rdev); 1064 if (r) { 1065 rv770_suspend(rdev); 1066 r600_wb_fini(rdev); 1067 radeon_ring_fini(rdev); 1068 rv770_pcie_gart_fini(rdev); 1069 rdev->accel_working = false; 1070 } 1071 if (rdev->accel_working) { 1072 r = radeon_ib_pool_init(rdev); 1073 if (r) { 1074 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 1075 rdev->accel_working = false; 1076 } 1077 r = r600_ib_test(rdev); 1078 if (r) { 1079 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 1080 rdev->accel_working = false; 1081 } 1082 } 1083 return 0; 1084 } 1085 1086 void rv770_fini(struct radeon_device *rdev) 1087 { 1088 rv770_suspend(rdev); 1089 1090 r600_blit_fini(rdev); 1091 r600_irq_fini(rdev); 1092 radeon_irq_kms_fini(rdev); 1093 radeon_ring_fini(rdev); 1094 r600_wb_fini(rdev); 1095 rv770_pcie_gart_fini(rdev); 1096 radeon_gem_fini(rdev); 1097 radeon_fence_driver_fini(rdev); 1098 radeon_clocks_fini(rdev); 1099 radeon_agp_fini(rdev); 1100 radeon_bo_fini(rdev); 1101 radeon_atombios_fini(rdev); 1102 kfree(rdev->bios); 1103 rdev->bios = NULL; 1104 radeon_dummy_page_fini(rdev); 1105 } 1106