1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "rv515d.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "rv515_reg_safe.h" 36 37 /* This files gather functions specifics to: rv515 */ 38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40 static void rv515_gpu_init(struct radeon_device *rdev); 41 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42 43 static const u32 crtc_offsets[2] = 44 { 45 0, 46 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 47 }; 48 49 void rv515_debugfs(struct radeon_device *rdev) 50 { 51 if (r100_debugfs_rbbm_init(rdev)) { 52 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 53 } 54 if (rv515_debugfs_pipes_info_init(rdev)) { 55 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 56 } 57 if (rv515_debugfs_ga_info_init(rdev)) { 58 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 59 } 60 } 61 62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 63 { 64 int r; 65 66 r = radeon_ring_lock(rdev, ring, 64); 67 if (r) { 68 return; 69 } 70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 71 radeon_ring_write(ring, 72 ISYNC_ANY2D_IDLE3D | 73 ISYNC_ANY3D_IDLE2D | 74 ISYNC_WAIT_IDLEGUI | 75 ISYNC_CPSCRATCH_IDLEGUI); 76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 81 radeon_ring_write(ring, 0); 82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 83 radeon_ring_write(ring, 0); 84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 87 radeon_ring_write(ring, 0); 88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 95 radeon_ring_write(ring, 0); 96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 101 radeon_ring_write(ring, 102 ((6 << MS_X0_SHIFT) | 103 (6 << MS_Y0_SHIFT) | 104 (6 << MS_X1_SHIFT) | 105 (6 << MS_Y1_SHIFT) | 106 (6 << MS_X2_SHIFT) | 107 (6 << MS_Y2_SHIFT) | 108 (6 << MSBD0_Y_SHIFT) | 109 (6 << MSBD0_X_SHIFT))); 110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 111 radeon_ring_write(ring, 112 ((6 << MS_X3_SHIFT) | 113 (6 << MS_Y3_SHIFT) | 114 (6 << MS_X4_SHIFT) | 115 (6 << MS_Y4_SHIFT) | 116 (6 << MS_X5_SHIFT) | 117 (6 << MS_Y5_SHIFT) | 118 (6 << MSBD1_SHIFT))); 119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 125 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 126 radeon_ring_write(ring, 0); 127 radeon_ring_unlock_commit(rdev, ring); 128 } 129 130 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 131 { 132 unsigned i; 133 uint32_t tmp; 134 135 for (i = 0; i < rdev->usec_timeout; i++) { 136 /* read MC_STATUS */ 137 tmp = RREG32_MC(MC_STATUS); 138 if (tmp & MC_STATUS_IDLE) { 139 return 0; 140 } 141 DRM_UDELAY(1); 142 } 143 return -1; 144 } 145 146 void rv515_vga_render_disable(struct radeon_device *rdev) 147 { 148 WREG32(R_000300_VGA_RENDER_CONTROL, 149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 150 } 151 152 static void rv515_gpu_init(struct radeon_device *rdev) 153 { 154 unsigned pipe_select_current, gb_pipe_select, tmp; 155 156 if (r100_gui_wait_for_idle(rdev)) { 157 printk(KERN_WARNING "Failed to wait GUI idle while " 158 "resetting GPU. Bad things might happen.\n"); 159 } 160 rv515_vga_render_disable(rdev); 161 r420_pipes_init(rdev); 162 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 163 tmp = RREG32(R300_DST_PIPE_CONFIG); 164 pipe_select_current = (tmp >> 2) & 3; 165 tmp = (1 << pipe_select_current) | 166 (((gb_pipe_select >> 8) & 0xF) << 4); 167 WREG32_PLL(0x000D, tmp); 168 if (r100_gui_wait_for_idle(rdev)) { 169 printk(KERN_WARNING "Failed to wait GUI idle while " 170 "resetting GPU. Bad things might happen.\n"); 171 } 172 if (rv515_mc_wait_for_idle(rdev)) { 173 printk(KERN_WARNING "Failed to wait MC idle while " 174 "programming pipes. Bad things might happen.\n"); 175 } 176 } 177 178 static void rv515_vram_get_type(struct radeon_device *rdev) 179 { 180 uint32_t tmp; 181 182 rdev->mc.vram_width = 128; 183 rdev->mc.vram_is_ddr = true; 184 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 185 switch (tmp) { 186 case 0: 187 rdev->mc.vram_width = 64; 188 break; 189 case 1: 190 rdev->mc.vram_width = 128; 191 break; 192 default: 193 rdev->mc.vram_width = 128; 194 break; 195 } 196 } 197 198 static void rv515_mc_init(struct radeon_device *rdev) 199 { 200 201 rv515_vram_get_type(rdev); 202 r100_vram_init_sizes(rdev); 203 radeon_vram_location(rdev, &rdev->mc, 0); 204 rdev->mc.gtt_base_align = 0; 205 if (!(rdev->flags & RADEON_IS_AGP)) 206 radeon_gtt_location(rdev, &rdev->mc); 207 radeon_update_bandwidth_info(rdev); 208 } 209 210 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 211 { 212 uint32_t r; 213 214 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 215 r = RREG32(MC_IND_DATA); 216 WREG32(MC_IND_INDEX, 0); 217 return r; 218 } 219 220 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 221 { 222 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 223 WREG32(MC_IND_DATA, (v)); 224 WREG32(MC_IND_INDEX, 0); 225 } 226 227 #if defined(CONFIG_DEBUG_FS) 228 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 229 { 230 struct drm_info_node *node = (struct drm_info_node *) m->private; 231 struct drm_device *dev = node->minor->dev; 232 struct radeon_device *rdev = dev->dev_private; 233 uint32_t tmp; 234 235 tmp = RREG32(GB_PIPE_SELECT); 236 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 237 tmp = RREG32(SU_REG_DEST); 238 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 239 tmp = RREG32(GB_TILE_CONFIG); 240 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 241 tmp = RREG32(DST_PIPE_CONFIG); 242 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 243 return 0; 244 } 245 246 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 247 { 248 struct drm_info_node *node = (struct drm_info_node *) m->private; 249 struct drm_device *dev = node->minor->dev; 250 struct radeon_device *rdev = dev->dev_private; 251 uint32_t tmp; 252 253 tmp = RREG32(0x2140); 254 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 255 radeon_asic_reset(rdev); 256 tmp = RREG32(0x425C); 257 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 258 return 0; 259 } 260 261 static struct drm_info_list rv515_pipes_info_list[] = { 262 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 263 }; 264 265 static struct drm_info_list rv515_ga_info_list[] = { 266 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 267 }; 268 #endif 269 270 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 271 { 272 #if defined(CONFIG_DEBUG_FS) 273 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 274 #else 275 return 0; 276 #endif 277 } 278 279 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 280 { 281 #if defined(CONFIG_DEBUG_FS) 282 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 283 #else 284 return 0; 285 #endif 286 } 287 288 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 289 { 290 u32 crtc_enabled, tmp, frame_count, blackout; 291 int i, j; 292 293 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 294 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 295 296 /* disable VGA render */ 297 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 298 /* blank the display controllers */ 299 for (i = 0; i < rdev->num_crtc; i++) { 300 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 301 if (crtc_enabled) { 302 save->crtc_enabled[i] = true; 303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 305 radeon_wait_for_vblank(rdev, i); 306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 307 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 308 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 309 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 310 } 311 /* wait for the next frame */ 312 frame_count = radeon_get_vblank_counter(rdev, i); 313 for (j = 0; j < rdev->usec_timeout; j++) { 314 if (radeon_get_vblank_counter(rdev, i) != frame_count) 315 break; 316 udelay(1); 317 } 318 319 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 320 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 322 tmp &= ~AVIVO_CRTC_EN; 323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 325 save->crtc_enabled[i] = false; 326 /* ***** */ 327 } else { 328 save->crtc_enabled[i] = false; 329 } 330 } 331 332 radeon_mc_wait_for_idle(rdev); 333 334 if (rdev->family >= CHIP_R600) { 335 if (rdev->family >= CHIP_RV770) 336 blackout = RREG32(R700_MC_CITF_CNTL); 337 else 338 blackout = RREG32(R600_CITF_CNTL); 339 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 340 /* Block CPU access */ 341 WREG32(R600_BIF_FB_EN, 0); 342 /* blackout the MC */ 343 blackout |= R600_BLACKOUT_MASK; 344 if (rdev->family >= CHIP_RV770) 345 WREG32(R700_MC_CITF_CNTL, blackout); 346 else 347 WREG32(R600_CITF_CNTL, blackout); 348 } 349 } 350 /* wait for the MC to settle */ 351 udelay(100); 352 353 /* lock double buffered regs */ 354 for (i = 0; i < rdev->num_crtc; i++) { 355 if (save->crtc_enabled[i]) { 356 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 357 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 358 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 359 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 360 } 361 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 362 if (!(tmp & 1)) { 363 tmp |= 1; 364 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 365 } 366 } 367 } 368 } 369 370 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 371 { 372 u32 tmp, frame_count; 373 int i, j; 374 375 /* update crtc base addresses */ 376 for (i = 0; i < rdev->num_crtc; i++) { 377 if (rdev->family >= CHIP_RV770) { 378 if (i == 0) { 379 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 380 upper_32_bits(rdev->mc.vram_start)); 381 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 382 upper_32_bits(rdev->mc.vram_start)); 383 } else { 384 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 385 upper_32_bits(rdev->mc.vram_start)); 386 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 387 upper_32_bits(rdev->mc.vram_start)); 388 } 389 } 390 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 391 (u32)rdev->mc.vram_start); 392 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 393 (u32)rdev->mc.vram_start); 394 } 395 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 396 397 /* unlock regs and wait for update */ 398 for (i = 0; i < rdev->num_crtc; i++) { 399 if (save->crtc_enabled[i]) { 400 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 401 if ((tmp & 0x3) != 0) { 402 tmp &= ~0x3; 403 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 404 } 405 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 406 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 407 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 408 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 409 } 410 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 411 if (tmp & 1) { 412 tmp &= ~1; 413 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 414 } 415 for (j = 0; j < rdev->usec_timeout; j++) { 416 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 417 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 418 break; 419 udelay(1); 420 } 421 } 422 } 423 424 if (rdev->family >= CHIP_R600) { 425 /* unblackout the MC */ 426 if (rdev->family >= CHIP_RV770) 427 tmp = RREG32(R700_MC_CITF_CNTL); 428 else 429 tmp = RREG32(R600_CITF_CNTL); 430 tmp &= ~R600_BLACKOUT_MASK; 431 if (rdev->family >= CHIP_RV770) 432 WREG32(R700_MC_CITF_CNTL, tmp); 433 else 434 WREG32(R600_CITF_CNTL, tmp); 435 /* allow CPU access */ 436 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 437 } 438 439 for (i = 0; i < rdev->num_crtc; i++) { 440 if (save->crtc_enabled[i]) { 441 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 442 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 443 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 444 /* wait for the next frame */ 445 frame_count = radeon_get_vblank_counter(rdev, i); 446 for (j = 0; j < rdev->usec_timeout; j++) { 447 if (radeon_get_vblank_counter(rdev, i) != frame_count) 448 break; 449 udelay(1); 450 } 451 } 452 } 453 /* Unlock vga access */ 454 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 455 mdelay(1); 456 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 457 } 458 459 static void rv515_mc_program(struct radeon_device *rdev) 460 { 461 struct rv515_mc_save save; 462 463 /* Stops all mc clients */ 464 rv515_mc_stop(rdev, &save); 465 466 /* Wait for mc idle */ 467 if (rv515_mc_wait_for_idle(rdev)) 468 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 469 /* Write VRAM size in case we are limiting it */ 470 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 471 /* Program MC, should be a 32bits limited address space */ 472 WREG32_MC(R_000001_MC_FB_LOCATION, 473 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 474 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 475 WREG32(R_000134_HDP_FB_LOCATION, 476 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 477 if (rdev->flags & RADEON_IS_AGP) { 478 WREG32_MC(R_000002_MC_AGP_LOCATION, 479 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 480 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 481 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 482 WREG32_MC(R_000004_MC_AGP_BASE_2, 483 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 484 } else { 485 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 486 WREG32_MC(R_000003_MC_AGP_BASE, 0); 487 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 488 } 489 490 rv515_mc_resume(rdev, &save); 491 } 492 493 void rv515_clock_startup(struct radeon_device *rdev) 494 { 495 if (radeon_dynclks != -1 && radeon_dynclks) 496 radeon_atom_set_clock_gating(rdev, 1); 497 /* We need to force on some of the block */ 498 WREG32_PLL(R_00000F_CP_DYN_CNTL, 499 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 500 WREG32_PLL(R_000011_E2_DYN_CNTL, 501 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 502 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 503 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 504 } 505 506 static int rv515_startup(struct radeon_device *rdev) 507 { 508 int r; 509 510 rv515_mc_program(rdev); 511 /* Resume clock */ 512 rv515_clock_startup(rdev); 513 /* Initialize GPU configuration (# pipes, ...) */ 514 rv515_gpu_init(rdev); 515 /* Initialize GART (initialize after TTM so we can allocate 516 * memory through TTM but finalize after TTM) */ 517 if (rdev->flags & RADEON_IS_PCIE) { 518 r = rv370_pcie_gart_enable(rdev); 519 if (r) 520 return r; 521 } 522 523 /* allocate wb buffer */ 524 r = radeon_wb_init(rdev); 525 if (r) 526 return r; 527 528 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 529 if (r) { 530 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 531 return r; 532 } 533 534 /* Enable IRQ */ 535 if (!rdev->irq.installed) { 536 r = radeon_irq_kms_init(rdev); 537 if (r) 538 return r; 539 } 540 541 rs600_irq_set(rdev); 542 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 543 /* 1M ring buffer */ 544 r = r100_cp_init(rdev, 1024 * 1024); 545 if (r) { 546 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 547 return r; 548 } 549 550 r = radeon_ib_pool_init(rdev); 551 if (r) { 552 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 553 return r; 554 } 555 556 return 0; 557 } 558 559 int rv515_resume(struct radeon_device *rdev) 560 { 561 int r; 562 563 /* Make sur GART are not working */ 564 if (rdev->flags & RADEON_IS_PCIE) 565 rv370_pcie_gart_disable(rdev); 566 /* Resume clock before doing reset */ 567 rv515_clock_startup(rdev); 568 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 569 if (radeon_asic_reset(rdev)) { 570 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 571 RREG32(R_000E40_RBBM_STATUS), 572 RREG32(R_0007C0_CP_STAT)); 573 } 574 /* post */ 575 atom_asic_init(rdev->mode_info.atom_context); 576 /* Resume clock after posting */ 577 rv515_clock_startup(rdev); 578 /* Initialize surface registers */ 579 radeon_surface_init(rdev); 580 581 rdev->accel_working = true; 582 r = rv515_startup(rdev); 583 if (r) { 584 rdev->accel_working = false; 585 } 586 return r; 587 } 588 589 int rv515_suspend(struct radeon_device *rdev) 590 { 591 r100_cp_disable(rdev); 592 radeon_wb_disable(rdev); 593 rs600_irq_disable(rdev); 594 if (rdev->flags & RADEON_IS_PCIE) 595 rv370_pcie_gart_disable(rdev); 596 return 0; 597 } 598 599 void rv515_set_safe_registers(struct radeon_device *rdev) 600 { 601 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 602 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 603 } 604 605 void rv515_fini(struct radeon_device *rdev) 606 { 607 r100_cp_fini(rdev); 608 radeon_wb_fini(rdev); 609 radeon_ib_pool_fini(rdev); 610 radeon_gem_fini(rdev); 611 rv370_pcie_gart_fini(rdev); 612 radeon_agp_fini(rdev); 613 radeon_irq_kms_fini(rdev); 614 radeon_fence_driver_fini(rdev); 615 radeon_bo_fini(rdev); 616 radeon_atombios_fini(rdev); 617 kfree(rdev->bios); 618 rdev->bios = NULL; 619 } 620 621 int rv515_init(struct radeon_device *rdev) 622 { 623 int r; 624 625 /* Initialize scratch registers */ 626 radeon_scratch_init(rdev); 627 /* Initialize surface registers */ 628 radeon_surface_init(rdev); 629 /* TODO: disable VGA need to use VGA request */ 630 /* restore some register to sane defaults */ 631 r100_restore_sanity(rdev); 632 /* BIOS*/ 633 if (!radeon_get_bios(rdev)) { 634 if (ASIC_IS_AVIVO(rdev)) 635 return -EINVAL; 636 } 637 if (rdev->is_atom_bios) { 638 r = radeon_atombios_init(rdev); 639 if (r) 640 return r; 641 } else { 642 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 643 return -EINVAL; 644 } 645 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 646 if (radeon_asic_reset(rdev)) { 647 dev_warn(rdev->dev, 648 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 649 RREG32(R_000E40_RBBM_STATUS), 650 RREG32(R_0007C0_CP_STAT)); 651 } 652 /* check if cards are posted or not */ 653 if (radeon_boot_test_post_card(rdev) == false) 654 return -EINVAL; 655 /* Initialize clocks */ 656 radeon_get_clock_info(rdev->ddev); 657 /* initialize AGP */ 658 if (rdev->flags & RADEON_IS_AGP) { 659 r = radeon_agp_init(rdev); 660 if (r) { 661 radeon_agp_disable(rdev); 662 } 663 } 664 /* initialize memory controller */ 665 rv515_mc_init(rdev); 666 rv515_debugfs(rdev); 667 /* Fence driver */ 668 r = radeon_fence_driver_init(rdev); 669 if (r) 670 return r; 671 /* Memory manager */ 672 r = radeon_bo_init(rdev); 673 if (r) 674 return r; 675 r = rv370_pcie_gart_init(rdev); 676 if (r) 677 return r; 678 rv515_set_safe_registers(rdev); 679 680 rdev->accel_working = true; 681 r = rv515_startup(rdev); 682 if (r) { 683 /* Somethings want wront with the accel init stop accel */ 684 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 685 r100_cp_fini(rdev); 686 radeon_wb_fini(rdev); 687 radeon_ib_pool_fini(rdev); 688 radeon_irq_kms_fini(rdev); 689 rv370_pcie_gart_fini(rdev); 690 radeon_agp_fini(rdev); 691 rdev->accel_working = false; 692 } 693 return 0; 694 } 695 696 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 697 { 698 int index_reg = 0x6578 + crtc->crtc_offset; 699 int data_reg = 0x657c + crtc->crtc_offset; 700 701 WREG32(0x659C + crtc->crtc_offset, 0x0); 702 WREG32(0x6594 + crtc->crtc_offset, 0x705); 703 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 704 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 705 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 706 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 707 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 708 WREG32(index_reg, 0x0); 709 WREG32(data_reg, 0x841880A8); 710 WREG32(index_reg, 0x1); 711 WREG32(data_reg, 0x84208680); 712 WREG32(index_reg, 0x2); 713 WREG32(data_reg, 0xBFF880B0); 714 WREG32(index_reg, 0x100); 715 WREG32(data_reg, 0x83D88088); 716 WREG32(index_reg, 0x101); 717 WREG32(data_reg, 0x84608680); 718 WREG32(index_reg, 0x102); 719 WREG32(data_reg, 0xBFF080D0); 720 WREG32(index_reg, 0x200); 721 WREG32(data_reg, 0x83988068); 722 WREG32(index_reg, 0x201); 723 WREG32(data_reg, 0x84A08680); 724 WREG32(index_reg, 0x202); 725 WREG32(data_reg, 0xBFF080F8); 726 WREG32(index_reg, 0x300); 727 WREG32(data_reg, 0x83588058); 728 WREG32(index_reg, 0x301); 729 WREG32(data_reg, 0x84E08660); 730 WREG32(index_reg, 0x302); 731 WREG32(data_reg, 0xBFF88120); 732 WREG32(index_reg, 0x400); 733 WREG32(data_reg, 0x83188040); 734 WREG32(index_reg, 0x401); 735 WREG32(data_reg, 0x85008660); 736 WREG32(index_reg, 0x402); 737 WREG32(data_reg, 0xBFF88150); 738 WREG32(index_reg, 0x500); 739 WREG32(data_reg, 0x82D88030); 740 WREG32(index_reg, 0x501); 741 WREG32(data_reg, 0x85408640); 742 WREG32(index_reg, 0x502); 743 WREG32(data_reg, 0xBFF88180); 744 WREG32(index_reg, 0x600); 745 WREG32(data_reg, 0x82A08018); 746 WREG32(index_reg, 0x601); 747 WREG32(data_reg, 0x85808620); 748 WREG32(index_reg, 0x602); 749 WREG32(data_reg, 0xBFF081B8); 750 WREG32(index_reg, 0x700); 751 WREG32(data_reg, 0x82608010); 752 WREG32(index_reg, 0x701); 753 WREG32(data_reg, 0x85A08600); 754 WREG32(index_reg, 0x702); 755 WREG32(data_reg, 0x800081F0); 756 WREG32(index_reg, 0x800); 757 WREG32(data_reg, 0x8228BFF8); 758 WREG32(index_reg, 0x801); 759 WREG32(data_reg, 0x85E085E0); 760 WREG32(index_reg, 0x802); 761 WREG32(data_reg, 0xBFF88228); 762 WREG32(index_reg, 0x10000); 763 WREG32(data_reg, 0x82A8BF00); 764 WREG32(index_reg, 0x10001); 765 WREG32(data_reg, 0x82A08CC0); 766 WREG32(index_reg, 0x10002); 767 WREG32(data_reg, 0x8008BEF8); 768 WREG32(index_reg, 0x10100); 769 WREG32(data_reg, 0x81F0BF28); 770 WREG32(index_reg, 0x10101); 771 WREG32(data_reg, 0x83608CA0); 772 WREG32(index_reg, 0x10102); 773 WREG32(data_reg, 0x8018BED0); 774 WREG32(index_reg, 0x10200); 775 WREG32(data_reg, 0x8148BF38); 776 WREG32(index_reg, 0x10201); 777 WREG32(data_reg, 0x84408C80); 778 WREG32(index_reg, 0x10202); 779 WREG32(data_reg, 0x8008BEB8); 780 WREG32(index_reg, 0x10300); 781 WREG32(data_reg, 0x80B0BF78); 782 WREG32(index_reg, 0x10301); 783 WREG32(data_reg, 0x85008C20); 784 WREG32(index_reg, 0x10302); 785 WREG32(data_reg, 0x8020BEA0); 786 WREG32(index_reg, 0x10400); 787 WREG32(data_reg, 0x8028BF90); 788 WREG32(index_reg, 0x10401); 789 WREG32(data_reg, 0x85E08BC0); 790 WREG32(index_reg, 0x10402); 791 WREG32(data_reg, 0x8018BE90); 792 WREG32(index_reg, 0x10500); 793 WREG32(data_reg, 0xBFB8BFB0); 794 WREG32(index_reg, 0x10501); 795 WREG32(data_reg, 0x86C08B40); 796 WREG32(index_reg, 0x10502); 797 WREG32(data_reg, 0x8010BE90); 798 WREG32(index_reg, 0x10600); 799 WREG32(data_reg, 0xBF58BFC8); 800 WREG32(index_reg, 0x10601); 801 WREG32(data_reg, 0x87A08AA0); 802 WREG32(index_reg, 0x10602); 803 WREG32(data_reg, 0x8010BE98); 804 WREG32(index_reg, 0x10700); 805 WREG32(data_reg, 0xBF10BFF0); 806 WREG32(index_reg, 0x10701); 807 WREG32(data_reg, 0x886089E0); 808 WREG32(index_reg, 0x10702); 809 WREG32(data_reg, 0x8018BEB0); 810 WREG32(index_reg, 0x10800); 811 WREG32(data_reg, 0xBED8BFE8); 812 WREG32(index_reg, 0x10801); 813 WREG32(data_reg, 0x89408940); 814 WREG32(index_reg, 0x10802); 815 WREG32(data_reg, 0xBFE8BED8); 816 WREG32(index_reg, 0x20000); 817 WREG32(data_reg, 0x80008000); 818 WREG32(index_reg, 0x20001); 819 WREG32(data_reg, 0x90008000); 820 WREG32(index_reg, 0x20002); 821 WREG32(data_reg, 0x80008000); 822 WREG32(index_reg, 0x20003); 823 WREG32(data_reg, 0x80008000); 824 WREG32(index_reg, 0x20100); 825 WREG32(data_reg, 0x80108000); 826 WREG32(index_reg, 0x20101); 827 WREG32(data_reg, 0x8FE0BF70); 828 WREG32(index_reg, 0x20102); 829 WREG32(data_reg, 0xBFE880C0); 830 WREG32(index_reg, 0x20103); 831 WREG32(data_reg, 0x80008000); 832 WREG32(index_reg, 0x20200); 833 WREG32(data_reg, 0x8018BFF8); 834 WREG32(index_reg, 0x20201); 835 WREG32(data_reg, 0x8F80BF08); 836 WREG32(index_reg, 0x20202); 837 WREG32(data_reg, 0xBFD081A0); 838 WREG32(index_reg, 0x20203); 839 WREG32(data_reg, 0xBFF88000); 840 WREG32(index_reg, 0x20300); 841 WREG32(data_reg, 0x80188000); 842 WREG32(index_reg, 0x20301); 843 WREG32(data_reg, 0x8EE0BEC0); 844 WREG32(index_reg, 0x20302); 845 WREG32(data_reg, 0xBFB082A0); 846 WREG32(index_reg, 0x20303); 847 WREG32(data_reg, 0x80008000); 848 WREG32(index_reg, 0x20400); 849 WREG32(data_reg, 0x80188000); 850 WREG32(index_reg, 0x20401); 851 WREG32(data_reg, 0x8E00BEA0); 852 WREG32(index_reg, 0x20402); 853 WREG32(data_reg, 0xBF8883C0); 854 WREG32(index_reg, 0x20403); 855 WREG32(data_reg, 0x80008000); 856 WREG32(index_reg, 0x20500); 857 WREG32(data_reg, 0x80188000); 858 WREG32(index_reg, 0x20501); 859 WREG32(data_reg, 0x8D00BE90); 860 WREG32(index_reg, 0x20502); 861 WREG32(data_reg, 0xBF588500); 862 WREG32(index_reg, 0x20503); 863 WREG32(data_reg, 0x80008008); 864 WREG32(index_reg, 0x20600); 865 WREG32(data_reg, 0x80188000); 866 WREG32(index_reg, 0x20601); 867 WREG32(data_reg, 0x8BC0BE98); 868 WREG32(index_reg, 0x20602); 869 WREG32(data_reg, 0xBF308660); 870 WREG32(index_reg, 0x20603); 871 WREG32(data_reg, 0x80008008); 872 WREG32(index_reg, 0x20700); 873 WREG32(data_reg, 0x80108000); 874 WREG32(index_reg, 0x20701); 875 WREG32(data_reg, 0x8A80BEB0); 876 WREG32(index_reg, 0x20702); 877 WREG32(data_reg, 0xBF0087C0); 878 WREG32(index_reg, 0x20703); 879 WREG32(data_reg, 0x80008008); 880 WREG32(index_reg, 0x20800); 881 WREG32(data_reg, 0x80108000); 882 WREG32(index_reg, 0x20801); 883 WREG32(data_reg, 0x8920BED0); 884 WREG32(index_reg, 0x20802); 885 WREG32(data_reg, 0xBED08920); 886 WREG32(index_reg, 0x20803); 887 WREG32(data_reg, 0x80008010); 888 WREG32(index_reg, 0x30000); 889 WREG32(data_reg, 0x90008000); 890 WREG32(index_reg, 0x30001); 891 WREG32(data_reg, 0x80008000); 892 WREG32(index_reg, 0x30100); 893 WREG32(data_reg, 0x8FE0BF90); 894 WREG32(index_reg, 0x30101); 895 WREG32(data_reg, 0xBFF880A0); 896 WREG32(index_reg, 0x30200); 897 WREG32(data_reg, 0x8F60BF40); 898 WREG32(index_reg, 0x30201); 899 WREG32(data_reg, 0xBFE88180); 900 WREG32(index_reg, 0x30300); 901 WREG32(data_reg, 0x8EC0BF00); 902 WREG32(index_reg, 0x30301); 903 WREG32(data_reg, 0xBFC88280); 904 WREG32(index_reg, 0x30400); 905 WREG32(data_reg, 0x8DE0BEE0); 906 WREG32(index_reg, 0x30401); 907 WREG32(data_reg, 0xBFA083A0); 908 WREG32(index_reg, 0x30500); 909 WREG32(data_reg, 0x8CE0BED0); 910 WREG32(index_reg, 0x30501); 911 WREG32(data_reg, 0xBF7884E0); 912 WREG32(index_reg, 0x30600); 913 WREG32(data_reg, 0x8BA0BED8); 914 WREG32(index_reg, 0x30601); 915 WREG32(data_reg, 0xBF508640); 916 WREG32(index_reg, 0x30700); 917 WREG32(data_reg, 0x8A60BEE8); 918 WREG32(index_reg, 0x30701); 919 WREG32(data_reg, 0xBF2087A0); 920 WREG32(index_reg, 0x30800); 921 WREG32(data_reg, 0x8900BF00); 922 WREG32(index_reg, 0x30801); 923 WREG32(data_reg, 0xBF008900); 924 } 925 926 struct rv515_watermark { 927 u32 lb_request_fifo_depth; 928 fixed20_12 num_line_pair; 929 fixed20_12 estimated_width; 930 fixed20_12 worst_case_latency; 931 fixed20_12 consumption_rate; 932 fixed20_12 active_time; 933 fixed20_12 dbpp; 934 fixed20_12 priority_mark_max; 935 fixed20_12 priority_mark; 936 fixed20_12 sclk; 937 }; 938 939 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 940 struct radeon_crtc *crtc, 941 struct rv515_watermark *wm, 942 bool low) 943 { 944 struct drm_display_mode *mode = &crtc->base.mode; 945 fixed20_12 a, b, c; 946 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 947 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 948 fixed20_12 sclk; 949 u32 selected_sclk; 950 951 if (!crtc->base.enabled) { 952 /* FIXME: wouldn't it better to set priority mark to maximum */ 953 wm->lb_request_fifo_depth = 4; 954 return; 955 } 956 957 /* rv6xx, rv7xx */ 958 if ((rdev->family >= CHIP_RV610) && 959 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 960 selected_sclk = radeon_dpm_get_sclk(rdev, low); 961 else 962 selected_sclk = rdev->pm.current_sclk; 963 964 /* sclk in Mhz */ 965 a.full = dfixed_const(100); 966 sclk.full = dfixed_const(selected_sclk); 967 sclk.full = dfixed_div(sclk, a); 968 969 if (crtc->vsc.full > dfixed_const(2)) 970 wm->num_line_pair.full = dfixed_const(2); 971 else 972 wm->num_line_pair.full = dfixed_const(1); 973 974 b.full = dfixed_const(mode->crtc_hdisplay); 975 c.full = dfixed_const(256); 976 a.full = dfixed_div(b, c); 977 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 978 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 979 if (a.full < dfixed_const(4)) { 980 wm->lb_request_fifo_depth = 4; 981 } else { 982 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 983 } 984 985 /* Determine consumption rate 986 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 987 * vtaps = number of vertical taps, 988 * vsc = vertical scaling ratio, defined as source/destination 989 * hsc = horizontal scaling ration, defined as source/destination 990 */ 991 a.full = dfixed_const(mode->clock); 992 b.full = dfixed_const(1000); 993 a.full = dfixed_div(a, b); 994 pclk.full = dfixed_div(b, a); 995 if (crtc->rmx_type != RMX_OFF) { 996 b.full = dfixed_const(2); 997 if (crtc->vsc.full > b.full) 998 b.full = crtc->vsc.full; 999 b.full = dfixed_mul(b, crtc->hsc); 1000 c.full = dfixed_const(2); 1001 b.full = dfixed_div(b, c); 1002 consumption_time.full = dfixed_div(pclk, b); 1003 } else { 1004 consumption_time.full = pclk.full; 1005 } 1006 a.full = dfixed_const(1); 1007 wm->consumption_rate.full = dfixed_div(a, consumption_time); 1008 1009 1010 /* Determine line time 1011 * LineTime = total time for one line of displayhtotal 1012 * LineTime = total number of horizontal pixels 1013 * pclk = pixel clock period(ns) 1014 */ 1015 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1016 line_time.full = dfixed_mul(a, pclk); 1017 1018 /* Determine active time 1019 * ActiveTime = time of active region of display within one line, 1020 * hactive = total number of horizontal active pixels 1021 * htotal = total number of horizontal pixels 1022 */ 1023 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1024 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1025 wm->active_time.full = dfixed_mul(line_time, b); 1026 wm->active_time.full = dfixed_div(wm->active_time, a); 1027 1028 /* Determine chunk time 1029 * ChunkTime = the time it takes the DCP to send one chunk of data 1030 * to the LB which consists of pipeline delay and inter chunk gap 1031 * sclk = system clock(Mhz) 1032 */ 1033 a.full = dfixed_const(600 * 1000); 1034 chunk_time.full = dfixed_div(a, sclk); 1035 read_delay_latency.full = dfixed_const(1000); 1036 1037 /* Determine the worst case latency 1038 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1039 * WorstCaseLatency = worst case time from urgent to when the MC starts 1040 * to return data 1041 * READ_DELAY_IDLE_MAX = constant of 1us 1042 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1043 * which consists of pipeline delay and inter chunk gap 1044 */ 1045 if (dfixed_trunc(wm->num_line_pair) > 1) { 1046 a.full = dfixed_const(3); 1047 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1048 wm->worst_case_latency.full += read_delay_latency.full; 1049 } else { 1050 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1051 } 1052 1053 /* Determine the tolerable latency 1054 * TolerableLatency = Any given request has only 1 line time 1055 * for the data to be returned 1056 * LBRequestFifoDepth = Number of chunk requests the LB can 1057 * put into the request FIFO for a display 1058 * LineTime = total time for one line of display 1059 * ChunkTime = the time it takes the DCP to send one chunk 1060 * of data to the LB which consists of 1061 * pipeline delay and inter chunk gap 1062 */ 1063 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1064 tolerable_latency.full = line_time.full; 1065 } else { 1066 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1067 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 1068 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1069 tolerable_latency.full = line_time.full - tolerable_latency.full; 1070 } 1071 /* We assume worst case 32bits (4 bytes) */ 1072 wm->dbpp.full = dfixed_const(2 * 16); 1073 1074 /* Determine the maximum priority mark 1075 * width = viewport width in pixels 1076 */ 1077 a.full = dfixed_const(16); 1078 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1079 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1080 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1081 1082 /* Determine estimated width */ 1083 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1084 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1085 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1086 wm->priority_mark.full = wm->priority_mark_max.full; 1087 } else { 1088 a.full = dfixed_const(16); 1089 wm->priority_mark.full = dfixed_div(estimated_width, a); 1090 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1091 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1092 } 1093 } 1094 1095 static void rv515_compute_mode_priority(struct radeon_device *rdev, 1096 struct rv515_watermark *wm0, 1097 struct rv515_watermark *wm1, 1098 struct drm_display_mode *mode0, 1099 struct drm_display_mode *mode1, 1100 u32 *d1mode_priority_a_cnt, 1101 u32 *d2mode_priority_a_cnt) 1102 { 1103 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1104 fixed20_12 a, b; 1105 1106 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1107 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1108 1109 if (mode0 && mode1) { 1110 if (dfixed_trunc(wm0->dbpp) > 64) 1111 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1112 else 1113 a.full = wm0->num_line_pair.full; 1114 if (dfixed_trunc(wm1->dbpp) > 64) 1115 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1116 else 1117 b.full = wm1->num_line_pair.full; 1118 a.full += b.full; 1119 fill_rate.full = dfixed_div(wm0->sclk, a); 1120 if (wm0->consumption_rate.full > fill_rate.full) { 1121 b.full = wm0->consumption_rate.full - fill_rate.full; 1122 b.full = dfixed_mul(b, wm0->active_time); 1123 a.full = dfixed_const(16); 1124 b.full = dfixed_div(b, a); 1125 a.full = dfixed_mul(wm0->worst_case_latency, 1126 wm0->consumption_rate); 1127 priority_mark02.full = a.full + b.full; 1128 } else { 1129 a.full = dfixed_mul(wm0->worst_case_latency, 1130 wm0->consumption_rate); 1131 b.full = dfixed_const(16 * 1000); 1132 priority_mark02.full = dfixed_div(a, b); 1133 } 1134 if (wm1->consumption_rate.full > fill_rate.full) { 1135 b.full = wm1->consumption_rate.full - fill_rate.full; 1136 b.full = dfixed_mul(b, wm1->active_time); 1137 a.full = dfixed_const(16); 1138 b.full = dfixed_div(b, a); 1139 a.full = dfixed_mul(wm1->worst_case_latency, 1140 wm1->consumption_rate); 1141 priority_mark12.full = a.full + b.full; 1142 } else { 1143 a.full = dfixed_mul(wm1->worst_case_latency, 1144 wm1->consumption_rate); 1145 b.full = dfixed_const(16 * 1000); 1146 priority_mark12.full = dfixed_div(a, b); 1147 } 1148 if (wm0->priority_mark.full > priority_mark02.full) 1149 priority_mark02.full = wm0->priority_mark.full; 1150 if (dfixed_trunc(priority_mark02) < 0) 1151 priority_mark02.full = 0; 1152 if (wm0->priority_mark_max.full > priority_mark02.full) 1153 priority_mark02.full = wm0->priority_mark_max.full; 1154 if (wm1->priority_mark.full > priority_mark12.full) 1155 priority_mark12.full = wm1->priority_mark.full; 1156 if (dfixed_trunc(priority_mark12) < 0) 1157 priority_mark12.full = 0; 1158 if (wm1->priority_mark_max.full > priority_mark12.full) 1159 priority_mark12.full = wm1->priority_mark_max.full; 1160 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1161 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1162 if (rdev->disp_priority == 2) { 1163 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1164 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1165 } 1166 } else if (mode0) { 1167 if (dfixed_trunc(wm0->dbpp) > 64) 1168 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1169 else 1170 a.full = wm0->num_line_pair.full; 1171 fill_rate.full = dfixed_div(wm0->sclk, a); 1172 if (wm0->consumption_rate.full > fill_rate.full) { 1173 b.full = wm0->consumption_rate.full - fill_rate.full; 1174 b.full = dfixed_mul(b, wm0->active_time); 1175 a.full = dfixed_const(16); 1176 b.full = dfixed_div(b, a); 1177 a.full = dfixed_mul(wm0->worst_case_latency, 1178 wm0->consumption_rate); 1179 priority_mark02.full = a.full + b.full; 1180 } else { 1181 a.full = dfixed_mul(wm0->worst_case_latency, 1182 wm0->consumption_rate); 1183 b.full = dfixed_const(16); 1184 priority_mark02.full = dfixed_div(a, b); 1185 } 1186 if (wm0->priority_mark.full > priority_mark02.full) 1187 priority_mark02.full = wm0->priority_mark.full; 1188 if (dfixed_trunc(priority_mark02) < 0) 1189 priority_mark02.full = 0; 1190 if (wm0->priority_mark_max.full > priority_mark02.full) 1191 priority_mark02.full = wm0->priority_mark_max.full; 1192 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1193 if (rdev->disp_priority == 2) 1194 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1195 } else if (mode1) { 1196 if (dfixed_trunc(wm1->dbpp) > 64) 1197 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1198 else 1199 a.full = wm1->num_line_pair.full; 1200 fill_rate.full = dfixed_div(wm1->sclk, a); 1201 if (wm1->consumption_rate.full > fill_rate.full) { 1202 b.full = wm1->consumption_rate.full - fill_rate.full; 1203 b.full = dfixed_mul(b, wm1->active_time); 1204 a.full = dfixed_const(16); 1205 b.full = dfixed_div(b, a); 1206 a.full = dfixed_mul(wm1->worst_case_latency, 1207 wm1->consumption_rate); 1208 priority_mark12.full = a.full + b.full; 1209 } else { 1210 a.full = dfixed_mul(wm1->worst_case_latency, 1211 wm1->consumption_rate); 1212 b.full = dfixed_const(16 * 1000); 1213 priority_mark12.full = dfixed_div(a, b); 1214 } 1215 if (wm1->priority_mark.full > priority_mark12.full) 1216 priority_mark12.full = wm1->priority_mark.full; 1217 if (dfixed_trunc(priority_mark12) < 0) 1218 priority_mark12.full = 0; 1219 if (wm1->priority_mark_max.full > priority_mark12.full) 1220 priority_mark12.full = wm1->priority_mark_max.full; 1221 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1222 if (rdev->disp_priority == 2) 1223 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1224 } 1225 } 1226 1227 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1228 { 1229 struct drm_display_mode *mode0 = NULL; 1230 struct drm_display_mode *mode1 = NULL; 1231 struct rv515_watermark wm0_high, wm0_low; 1232 struct rv515_watermark wm1_high, wm1_low; 1233 u32 tmp; 1234 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 1235 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1236 1237 if (rdev->mode_info.crtcs[0]->base.enabled) 1238 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1239 if (rdev->mode_info.crtcs[1]->base.enabled) 1240 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1241 rs690_line_buffer_adjust(rdev, mode0, mode1); 1242 1243 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 1244 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1245 1246 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 1247 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 1248 1249 tmp = wm0_high.lb_request_fifo_depth; 1250 tmp |= wm1_high.lb_request_fifo_depth << 16; 1251 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1252 1253 rv515_compute_mode_priority(rdev, 1254 &wm0_high, &wm1_high, 1255 mode0, mode1, 1256 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 1257 rv515_compute_mode_priority(rdev, 1258 &wm0_low, &wm1_low, 1259 mode0, mode1, 1260 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1261 1262 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1263 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1264 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1265 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1266 } 1267 1268 void rv515_bandwidth_update(struct radeon_device *rdev) 1269 { 1270 uint32_t tmp; 1271 struct drm_display_mode *mode0 = NULL; 1272 struct drm_display_mode *mode1 = NULL; 1273 1274 radeon_update_display_priority(rdev); 1275 1276 if (rdev->mode_info.crtcs[0]->base.enabled) 1277 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1278 if (rdev->mode_info.crtcs[1]->base.enabled) 1279 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1280 /* 1281 * Set display0/1 priority up in the memory controller for 1282 * modes if the user specifies HIGH for displaypriority 1283 * option. 1284 */ 1285 if ((rdev->disp_priority == 2) && 1286 (rdev->family == CHIP_RV515)) { 1287 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1288 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1289 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1290 if (mode1) 1291 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1292 if (mode0) 1293 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1294 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1295 } 1296 rv515_bandwidth_avivo_update(rdev); 1297 } 1298