1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include "drmP.h" 31 #include "rv515d.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "rv515_reg_safe.h" 36 37 /* This files gather functions specifics to: rv515 */ 38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40 void rv515_gpu_init(struct radeon_device *rdev); 41 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42 43 void rv515_debugfs(struct radeon_device *rdev) 44 { 45 if (r100_debugfs_rbbm_init(rdev)) { 46 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 47 } 48 if (rv515_debugfs_pipes_info_init(rdev)) { 49 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 50 } 51 if (rv515_debugfs_ga_info_init(rdev)) { 52 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 53 } 54 } 55 56 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 57 { 58 int r; 59 60 r = radeon_ring_lock(rdev, ring, 64); 61 if (r) { 62 return; 63 } 64 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 65 radeon_ring_write(ring, 66 ISYNC_ANY2D_IDLE3D | 67 ISYNC_ANY3D_IDLE2D | 68 ISYNC_WAIT_IDLEGUI | 69 ISYNC_CPSCRATCH_IDLEGUI); 70 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 71 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 72 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 73 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 74 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 75 radeon_ring_write(ring, 0); 76 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 77 radeon_ring_write(ring, 0); 78 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 79 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 80 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 81 radeon_ring_write(ring, 0); 82 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 83 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 84 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 85 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 86 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 87 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 88 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 89 radeon_ring_write(ring, 0); 90 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 91 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 92 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 93 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 94 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 95 radeon_ring_write(ring, 96 ((6 << MS_X0_SHIFT) | 97 (6 << MS_Y0_SHIFT) | 98 (6 << MS_X1_SHIFT) | 99 (6 << MS_Y1_SHIFT) | 100 (6 << MS_X2_SHIFT) | 101 (6 << MS_Y2_SHIFT) | 102 (6 << MSBD0_Y_SHIFT) | 103 (6 << MSBD0_X_SHIFT))); 104 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 105 radeon_ring_write(ring, 106 ((6 << MS_X3_SHIFT) | 107 (6 << MS_Y3_SHIFT) | 108 (6 << MS_X4_SHIFT) | 109 (6 << MS_Y4_SHIFT) | 110 (6 << MS_X5_SHIFT) | 111 (6 << MS_Y5_SHIFT) | 112 (6 << MSBD1_SHIFT))); 113 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 114 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 115 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 116 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 117 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 118 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 119 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 120 radeon_ring_write(ring, 0); 121 radeon_ring_unlock_commit(rdev, ring); 122 } 123 124 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 125 { 126 unsigned i; 127 uint32_t tmp; 128 129 for (i = 0; i < rdev->usec_timeout; i++) { 130 /* read MC_STATUS */ 131 tmp = RREG32_MC(MC_STATUS); 132 if (tmp & MC_STATUS_IDLE) { 133 return 0; 134 } 135 DRM_UDELAY(1); 136 } 137 return -1; 138 } 139 140 void rv515_vga_render_disable(struct radeon_device *rdev) 141 { 142 WREG32(R_000300_VGA_RENDER_CONTROL, 143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 144 } 145 146 void rv515_gpu_init(struct radeon_device *rdev) 147 { 148 unsigned pipe_select_current, gb_pipe_select, tmp; 149 150 if (r100_gui_wait_for_idle(rdev)) { 151 printk(KERN_WARNING "Failed to wait GUI idle while " 152 "resetting GPU. Bad things might happen.\n"); 153 } 154 rv515_vga_render_disable(rdev); 155 r420_pipes_init(rdev); 156 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 157 tmp = RREG32(R300_DST_PIPE_CONFIG); 158 pipe_select_current = (tmp >> 2) & 3; 159 tmp = (1 << pipe_select_current) | 160 (((gb_pipe_select >> 8) & 0xF) << 4); 161 WREG32_PLL(0x000D, tmp); 162 if (r100_gui_wait_for_idle(rdev)) { 163 printk(KERN_WARNING "Failed to wait GUI idle while " 164 "resetting GPU. Bad things might happen.\n"); 165 } 166 if (rv515_mc_wait_for_idle(rdev)) { 167 printk(KERN_WARNING "Failed to wait MC idle while " 168 "programming pipes. Bad things might happen.\n"); 169 } 170 } 171 172 static void rv515_vram_get_type(struct radeon_device *rdev) 173 { 174 uint32_t tmp; 175 176 rdev->mc.vram_width = 128; 177 rdev->mc.vram_is_ddr = true; 178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 179 switch (tmp) { 180 case 0: 181 rdev->mc.vram_width = 64; 182 break; 183 case 1: 184 rdev->mc.vram_width = 128; 185 break; 186 default: 187 rdev->mc.vram_width = 128; 188 break; 189 } 190 } 191 192 void rv515_mc_init(struct radeon_device *rdev) 193 { 194 195 rv515_vram_get_type(rdev); 196 r100_vram_init_sizes(rdev); 197 radeon_vram_location(rdev, &rdev->mc, 0); 198 rdev->mc.gtt_base_align = 0; 199 if (!(rdev->flags & RADEON_IS_AGP)) 200 radeon_gtt_location(rdev, &rdev->mc); 201 radeon_update_bandwidth_info(rdev); 202 } 203 204 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 205 { 206 uint32_t r; 207 208 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 209 r = RREG32(MC_IND_DATA); 210 WREG32(MC_IND_INDEX, 0); 211 return r; 212 } 213 214 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 215 { 216 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 217 WREG32(MC_IND_DATA, (v)); 218 WREG32(MC_IND_INDEX, 0); 219 } 220 221 #if defined(CONFIG_DEBUG_FS) 222 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 223 { 224 struct drm_info_node *node = (struct drm_info_node *) m->private; 225 struct drm_device *dev = node->minor->dev; 226 struct radeon_device *rdev = dev->dev_private; 227 uint32_t tmp; 228 229 tmp = RREG32(GB_PIPE_SELECT); 230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 231 tmp = RREG32(SU_REG_DEST); 232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 233 tmp = RREG32(GB_TILE_CONFIG); 234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 235 tmp = RREG32(DST_PIPE_CONFIG); 236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 237 return 0; 238 } 239 240 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 241 { 242 struct drm_info_node *node = (struct drm_info_node *) m->private; 243 struct drm_device *dev = node->minor->dev; 244 struct radeon_device *rdev = dev->dev_private; 245 uint32_t tmp; 246 247 tmp = RREG32(0x2140); 248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 249 radeon_asic_reset(rdev); 250 tmp = RREG32(0x425C); 251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 252 return 0; 253 } 254 255 static struct drm_info_list rv515_pipes_info_list[] = { 256 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 257 }; 258 259 static struct drm_info_list rv515_ga_info_list[] = { 260 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 261 }; 262 #endif 263 264 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 265 { 266 #if defined(CONFIG_DEBUG_FS) 267 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 268 #else 269 return 0; 270 #endif 271 } 272 273 int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 274 { 275 #if defined(CONFIG_DEBUG_FS) 276 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 277 #else 278 return 0; 279 #endif 280 } 281 282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 283 { 284 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); 285 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); 286 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 287 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 288 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); 289 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 290 291 /* Stop all video */ 292 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 293 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 296 WREG32(R_006080_D1CRTC_CONTROL, 0); 297 WREG32(R_006880_D2CRTC_CONTROL, 0); 298 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 299 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 300 WREG32(R_000330_D1VGA_CONTROL, 0); 301 WREG32(R_000338_D2VGA_CONTROL, 0); 302 } 303 304 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 305 { 306 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 307 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 308 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 309 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 310 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 311 /* Unlock host access */ 312 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 313 mdelay(1); 314 /* Restore video state */ 315 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); 316 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); 317 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 318 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 319 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 320 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 321 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 322 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 323 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 324 } 325 326 void rv515_mc_program(struct radeon_device *rdev) 327 { 328 struct rv515_mc_save save; 329 330 /* Stops all mc clients */ 331 rv515_mc_stop(rdev, &save); 332 333 /* Wait for mc idle */ 334 if (rv515_mc_wait_for_idle(rdev)) 335 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 336 /* Write VRAM size in case we are limiting it */ 337 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 338 /* Program MC, should be a 32bits limited address space */ 339 WREG32_MC(R_000001_MC_FB_LOCATION, 340 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 341 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 342 WREG32(R_000134_HDP_FB_LOCATION, 343 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 344 if (rdev->flags & RADEON_IS_AGP) { 345 WREG32_MC(R_000002_MC_AGP_LOCATION, 346 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 347 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 348 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 349 WREG32_MC(R_000004_MC_AGP_BASE_2, 350 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 351 } else { 352 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 353 WREG32_MC(R_000003_MC_AGP_BASE, 0); 354 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 355 } 356 357 rv515_mc_resume(rdev, &save); 358 } 359 360 void rv515_clock_startup(struct radeon_device *rdev) 361 { 362 if (radeon_dynclks != -1 && radeon_dynclks) 363 radeon_atom_set_clock_gating(rdev, 1); 364 /* We need to force on some of the block */ 365 WREG32_PLL(R_00000F_CP_DYN_CNTL, 366 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 367 WREG32_PLL(R_000011_E2_DYN_CNTL, 368 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 369 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 370 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 371 } 372 373 static int rv515_startup(struct radeon_device *rdev) 374 { 375 int r; 376 377 rv515_mc_program(rdev); 378 /* Resume clock */ 379 rv515_clock_startup(rdev); 380 /* Initialize GPU configuration (# pipes, ...) */ 381 rv515_gpu_init(rdev); 382 /* Initialize GART (initialize after TTM so we can allocate 383 * memory through TTM but finalize after TTM) */ 384 if (rdev->flags & RADEON_IS_PCIE) { 385 r = rv370_pcie_gart_enable(rdev); 386 if (r) 387 return r; 388 } 389 390 /* allocate wb buffer */ 391 r = radeon_wb_init(rdev); 392 if (r) 393 return r; 394 395 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 396 if (r) { 397 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 398 return r; 399 } 400 401 /* Enable IRQ */ 402 rs600_irq_set(rdev); 403 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 404 /* 1M ring buffer */ 405 r = r100_cp_init(rdev, 1024 * 1024); 406 if (r) { 407 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 408 return r; 409 } 410 411 r = radeon_ib_pool_start(rdev); 412 if (r) 413 return r; 414 415 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 416 if (r) { 417 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 418 rdev->accel_working = false; 419 return r; 420 } 421 return 0; 422 } 423 424 int rv515_resume(struct radeon_device *rdev) 425 { 426 int r; 427 428 /* Make sur GART are not working */ 429 if (rdev->flags & RADEON_IS_PCIE) 430 rv370_pcie_gart_disable(rdev); 431 /* Resume clock before doing reset */ 432 rv515_clock_startup(rdev); 433 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 434 if (radeon_asic_reset(rdev)) { 435 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 436 RREG32(R_000E40_RBBM_STATUS), 437 RREG32(R_0007C0_CP_STAT)); 438 } 439 /* post */ 440 atom_asic_init(rdev->mode_info.atom_context); 441 /* Resume clock after posting */ 442 rv515_clock_startup(rdev); 443 /* Initialize surface registers */ 444 radeon_surface_init(rdev); 445 446 rdev->accel_working = true; 447 r = rv515_startup(rdev); 448 if (r) { 449 rdev->accel_working = false; 450 } 451 return r; 452 } 453 454 int rv515_suspend(struct radeon_device *rdev) 455 { 456 r100_cp_disable(rdev); 457 radeon_wb_disable(rdev); 458 rs600_irq_disable(rdev); 459 if (rdev->flags & RADEON_IS_PCIE) 460 rv370_pcie_gart_disable(rdev); 461 return 0; 462 } 463 464 void rv515_set_safe_registers(struct radeon_device *rdev) 465 { 466 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 467 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 468 } 469 470 void rv515_fini(struct radeon_device *rdev) 471 { 472 r100_cp_fini(rdev); 473 radeon_wb_fini(rdev); 474 r100_ib_fini(rdev); 475 radeon_gem_fini(rdev); 476 rv370_pcie_gart_fini(rdev); 477 radeon_agp_fini(rdev); 478 radeon_irq_kms_fini(rdev); 479 radeon_fence_driver_fini(rdev); 480 radeon_bo_fini(rdev); 481 radeon_atombios_fini(rdev); 482 kfree(rdev->bios); 483 rdev->bios = NULL; 484 } 485 486 int rv515_init(struct radeon_device *rdev) 487 { 488 int r; 489 490 /* Initialize scratch registers */ 491 radeon_scratch_init(rdev); 492 /* Initialize surface registers */ 493 radeon_surface_init(rdev); 494 /* TODO: disable VGA need to use VGA request */ 495 /* restore some register to sane defaults */ 496 r100_restore_sanity(rdev); 497 /* BIOS*/ 498 if (!radeon_get_bios(rdev)) { 499 if (ASIC_IS_AVIVO(rdev)) 500 return -EINVAL; 501 } 502 if (rdev->is_atom_bios) { 503 r = radeon_atombios_init(rdev); 504 if (r) 505 return r; 506 } else { 507 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 508 return -EINVAL; 509 } 510 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 511 if (radeon_asic_reset(rdev)) { 512 dev_warn(rdev->dev, 513 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 514 RREG32(R_000E40_RBBM_STATUS), 515 RREG32(R_0007C0_CP_STAT)); 516 } 517 /* check if cards are posted or not */ 518 if (radeon_boot_test_post_card(rdev) == false) 519 return -EINVAL; 520 /* Initialize clocks */ 521 radeon_get_clock_info(rdev->ddev); 522 /* initialize AGP */ 523 if (rdev->flags & RADEON_IS_AGP) { 524 r = radeon_agp_init(rdev); 525 if (r) { 526 radeon_agp_disable(rdev); 527 } 528 } 529 /* initialize memory controller */ 530 rv515_mc_init(rdev); 531 rv515_debugfs(rdev); 532 /* Fence driver */ 533 r = radeon_fence_driver_init(rdev); 534 if (r) 535 return r; 536 r = radeon_irq_kms_init(rdev); 537 if (r) 538 return r; 539 /* Memory manager */ 540 r = radeon_bo_init(rdev); 541 if (r) 542 return r; 543 r = rv370_pcie_gart_init(rdev); 544 if (r) 545 return r; 546 rv515_set_safe_registers(rdev); 547 548 r = radeon_ib_pool_init(rdev); 549 rdev->accel_working = true; 550 if (r) { 551 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 552 rdev->accel_working = false; 553 } 554 555 r = rv515_startup(rdev); 556 if (r) { 557 /* Somethings want wront with the accel init stop accel */ 558 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 559 r100_cp_fini(rdev); 560 radeon_wb_fini(rdev); 561 r100_ib_fini(rdev); 562 radeon_irq_kms_fini(rdev); 563 rv370_pcie_gart_fini(rdev); 564 radeon_agp_fini(rdev); 565 rdev->accel_working = false; 566 } 567 return 0; 568 } 569 570 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 571 { 572 int index_reg = 0x6578 + crtc->crtc_offset; 573 int data_reg = 0x657c + crtc->crtc_offset; 574 575 WREG32(0x659C + crtc->crtc_offset, 0x0); 576 WREG32(0x6594 + crtc->crtc_offset, 0x705); 577 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 578 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 579 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 580 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 581 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 582 WREG32(index_reg, 0x0); 583 WREG32(data_reg, 0x841880A8); 584 WREG32(index_reg, 0x1); 585 WREG32(data_reg, 0x84208680); 586 WREG32(index_reg, 0x2); 587 WREG32(data_reg, 0xBFF880B0); 588 WREG32(index_reg, 0x100); 589 WREG32(data_reg, 0x83D88088); 590 WREG32(index_reg, 0x101); 591 WREG32(data_reg, 0x84608680); 592 WREG32(index_reg, 0x102); 593 WREG32(data_reg, 0xBFF080D0); 594 WREG32(index_reg, 0x200); 595 WREG32(data_reg, 0x83988068); 596 WREG32(index_reg, 0x201); 597 WREG32(data_reg, 0x84A08680); 598 WREG32(index_reg, 0x202); 599 WREG32(data_reg, 0xBFF080F8); 600 WREG32(index_reg, 0x300); 601 WREG32(data_reg, 0x83588058); 602 WREG32(index_reg, 0x301); 603 WREG32(data_reg, 0x84E08660); 604 WREG32(index_reg, 0x302); 605 WREG32(data_reg, 0xBFF88120); 606 WREG32(index_reg, 0x400); 607 WREG32(data_reg, 0x83188040); 608 WREG32(index_reg, 0x401); 609 WREG32(data_reg, 0x85008660); 610 WREG32(index_reg, 0x402); 611 WREG32(data_reg, 0xBFF88150); 612 WREG32(index_reg, 0x500); 613 WREG32(data_reg, 0x82D88030); 614 WREG32(index_reg, 0x501); 615 WREG32(data_reg, 0x85408640); 616 WREG32(index_reg, 0x502); 617 WREG32(data_reg, 0xBFF88180); 618 WREG32(index_reg, 0x600); 619 WREG32(data_reg, 0x82A08018); 620 WREG32(index_reg, 0x601); 621 WREG32(data_reg, 0x85808620); 622 WREG32(index_reg, 0x602); 623 WREG32(data_reg, 0xBFF081B8); 624 WREG32(index_reg, 0x700); 625 WREG32(data_reg, 0x82608010); 626 WREG32(index_reg, 0x701); 627 WREG32(data_reg, 0x85A08600); 628 WREG32(index_reg, 0x702); 629 WREG32(data_reg, 0x800081F0); 630 WREG32(index_reg, 0x800); 631 WREG32(data_reg, 0x8228BFF8); 632 WREG32(index_reg, 0x801); 633 WREG32(data_reg, 0x85E085E0); 634 WREG32(index_reg, 0x802); 635 WREG32(data_reg, 0xBFF88228); 636 WREG32(index_reg, 0x10000); 637 WREG32(data_reg, 0x82A8BF00); 638 WREG32(index_reg, 0x10001); 639 WREG32(data_reg, 0x82A08CC0); 640 WREG32(index_reg, 0x10002); 641 WREG32(data_reg, 0x8008BEF8); 642 WREG32(index_reg, 0x10100); 643 WREG32(data_reg, 0x81F0BF28); 644 WREG32(index_reg, 0x10101); 645 WREG32(data_reg, 0x83608CA0); 646 WREG32(index_reg, 0x10102); 647 WREG32(data_reg, 0x8018BED0); 648 WREG32(index_reg, 0x10200); 649 WREG32(data_reg, 0x8148BF38); 650 WREG32(index_reg, 0x10201); 651 WREG32(data_reg, 0x84408C80); 652 WREG32(index_reg, 0x10202); 653 WREG32(data_reg, 0x8008BEB8); 654 WREG32(index_reg, 0x10300); 655 WREG32(data_reg, 0x80B0BF78); 656 WREG32(index_reg, 0x10301); 657 WREG32(data_reg, 0x85008C20); 658 WREG32(index_reg, 0x10302); 659 WREG32(data_reg, 0x8020BEA0); 660 WREG32(index_reg, 0x10400); 661 WREG32(data_reg, 0x8028BF90); 662 WREG32(index_reg, 0x10401); 663 WREG32(data_reg, 0x85E08BC0); 664 WREG32(index_reg, 0x10402); 665 WREG32(data_reg, 0x8018BE90); 666 WREG32(index_reg, 0x10500); 667 WREG32(data_reg, 0xBFB8BFB0); 668 WREG32(index_reg, 0x10501); 669 WREG32(data_reg, 0x86C08B40); 670 WREG32(index_reg, 0x10502); 671 WREG32(data_reg, 0x8010BE90); 672 WREG32(index_reg, 0x10600); 673 WREG32(data_reg, 0xBF58BFC8); 674 WREG32(index_reg, 0x10601); 675 WREG32(data_reg, 0x87A08AA0); 676 WREG32(index_reg, 0x10602); 677 WREG32(data_reg, 0x8010BE98); 678 WREG32(index_reg, 0x10700); 679 WREG32(data_reg, 0xBF10BFF0); 680 WREG32(index_reg, 0x10701); 681 WREG32(data_reg, 0x886089E0); 682 WREG32(index_reg, 0x10702); 683 WREG32(data_reg, 0x8018BEB0); 684 WREG32(index_reg, 0x10800); 685 WREG32(data_reg, 0xBED8BFE8); 686 WREG32(index_reg, 0x10801); 687 WREG32(data_reg, 0x89408940); 688 WREG32(index_reg, 0x10802); 689 WREG32(data_reg, 0xBFE8BED8); 690 WREG32(index_reg, 0x20000); 691 WREG32(data_reg, 0x80008000); 692 WREG32(index_reg, 0x20001); 693 WREG32(data_reg, 0x90008000); 694 WREG32(index_reg, 0x20002); 695 WREG32(data_reg, 0x80008000); 696 WREG32(index_reg, 0x20003); 697 WREG32(data_reg, 0x80008000); 698 WREG32(index_reg, 0x20100); 699 WREG32(data_reg, 0x80108000); 700 WREG32(index_reg, 0x20101); 701 WREG32(data_reg, 0x8FE0BF70); 702 WREG32(index_reg, 0x20102); 703 WREG32(data_reg, 0xBFE880C0); 704 WREG32(index_reg, 0x20103); 705 WREG32(data_reg, 0x80008000); 706 WREG32(index_reg, 0x20200); 707 WREG32(data_reg, 0x8018BFF8); 708 WREG32(index_reg, 0x20201); 709 WREG32(data_reg, 0x8F80BF08); 710 WREG32(index_reg, 0x20202); 711 WREG32(data_reg, 0xBFD081A0); 712 WREG32(index_reg, 0x20203); 713 WREG32(data_reg, 0xBFF88000); 714 WREG32(index_reg, 0x20300); 715 WREG32(data_reg, 0x80188000); 716 WREG32(index_reg, 0x20301); 717 WREG32(data_reg, 0x8EE0BEC0); 718 WREG32(index_reg, 0x20302); 719 WREG32(data_reg, 0xBFB082A0); 720 WREG32(index_reg, 0x20303); 721 WREG32(data_reg, 0x80008000); 722 WREG32(index_reg, 0x20400); 723 WREG32(data_reg, 0x80188000); 724 WREG32(index_reg, 0x20401); 725 WREG32(data_reg, 0x8E00BEA0); 726 WREG32(index_reg, 0x20402); 727 WREG32(data_reg, 0xBF8883C0); 728 WREG32(index_reg, 0x20403); 729 WREG32(data_reg, 0x80008000); 730 WREG32(index_reg, 0x20500); 731 WREG32(data_reg, 0x80188000); 732 WREG32(index_reg, 0x20501); 733 WREG32(data_reg, 0x8D00BE90); 734 WREG32(index_reg, 0x20502); 735 WREG32(data_reg, 0xBF588500); 736 WREG32(index_reg, 0x20503); 737 WREG32(data_reg, 0x80008008); 738 WREG32(index_reg, 0x20600); 739 WREG32(data_reg, 0x80188000); 740 WREG32(index_reg, 0x20601); 741 WREG32(data_reg, 0x8BC0BE98); 742 WREG32(index_reg, 0x20602); 743 WREG32(data_reg, 0xBF308660); 744 WREG32(index_reg, 0x20603); 745 WREG32(data_reg, 0x80008008); 746 WREG32(index_reg, 0x20700); 747 WREG32(data_reg, 0x80108000); 748 WREG32(index_reg, 0x20701); 749 WREG32(data_reg, 0x8A80BEB0); 750 WREG32(index_reg, 0x20702); 751 WREG32(data_reg, 0xBF0087C0); 752 WREG32(index_reg, 0x20703); 753 WREG32(data_reg, 0x80008008); 754 WREG32(index_reg, 0x20800); 755 WREG32(data_reg, 0x80108000); 756 WREG32(index_reg, 0x20801); 757 WREG32(data_reg, 0x8920BED0); 758 WREG32(index_reg, 0x20802); 759 WREG32(data_reg, 0xBED08920); 760 WREG32(index_reg, 0x20803); 761 WREG32(data_reg, 0x80008010); 762 WREG32(index_reg, 0x30000); 763 WREG32(data_reg, 0x90008000); 764 WREG32(index_reg, 0x30001); 765 WREG32(data_reg, 0x80008000); 766 WREG32(index_reg, 0x30100); 767 WREG32(data_reg, 0x8FE0BF90); 768 WREG32(index_reg, 0x30101); 769 WREG32(data_reg, 0xBFF880A0); 770 WREG32(index_reg, 0x30200); 771 WREG32(data_reg, 0x8F60BF40); 772 WREG32(index_reg, 0x30201); 773 WREG32(data_reg, 0xBFE88180); 774 WREG32(index_reg, 0x30300); 775 WREG32(data_reg, 0x8EC0BF00); 776 WREG32(index_reg, 0x30301); 777 WREG32(data_reg, 0xBFC88280); 778 WREG32(index_reg, 0x30400); 779 WREG32(data_reg, 0x8DE0BEE0); 780 WREG32(index_reg, 0x30401); 781 WREG32(data_reg, 0xBFA083A0); 782 WREG32(index_reg, 0x30500); 783 WREG32(data_reg, 0x8CE0BED0); 784 WREG32(index_reg, 0x30501); 785 WREG32(data_reg, 0xBF7884E0); 786 WREG32(index_reg, 0x30600); 787 WREG32(data_reg, 0x8BA0BED8); 788 WREG32(index_reg, 0x30601); 789 WREG32(data_reg, 0xBF508640); 790 WREG32(index_reg, 0x30700); 791 WREG32(data_reg, 0x8A60BEE8); 792 WREG32(index_reg, 0x30701); 793 WREG32(data_reg, 0xBF2087A0); 794 WREG32(index_reg, 0x30800); 795 WREG32(data_reg, 0x8900BF00); 796 WREG32(index_reg, 0x30801); 797 WREG32(data_reg, 0xBF008900); 798 } 799 800 struct rv515_watermark { 801 u32 lb_request_fifo_depth; 802 fixed20_12 num_line_pair; 803 fixed20_12 estimated_width; 804 fixed20_12 worst_case_latency; 805 fixed20_12 consumption_rate; 806 fixed20_12 active_time; 807 fixed20_12 dbpp; 808 fixed20_12 priority_mark_max; 809 fixed20_12 priority_mark; 810 fixed20_12 sclk; 811 }; 812 813 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 814 struct radeon_crtc *crtc, 815 struct rv515_watermark *wm) 816 { 817 struct drm_display_mode *mode = &crtc->base.mode; 818 fixed20_12 a, b, c; 819 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 820 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 821 822 if (!crtc->base.enabled) { 823 /* FIXME: wouldn't it better to set priority mark to maximum */ 824 wm->lb_request_fifo_depth = 4; 825 return; 826 } 827 828 if (crtc->vsc.full > dfixed_const(2)) 829 wm->num_line_pair.full = dfixed_const(2); 830 else 831 wm->num_line_pair.full = dfixed_const(1); 832 833 b.full = dfixed_const(mode->crtc_hdisplay); 834 c.full = dfixed_const(256); 835 a.full = dfixed_div(b, c); 836 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 837 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 838 if (a.full < dfixed_const(4)) { 839 wm->lb_request_fifo_depth = 4; 840 } else { 841 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 842 } 843 844 /* Determine consumption rate 845 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 846 * vtaps = number of vertical taps, 847 * vsc = vertical scaling ratio, defined as source/destination 848 * hsc = horizontal scaling ration, defined as source/destination 849 */ 850 a.full = dfixed_const(mode->clock); 851 b.full = dfixed_const(1000); 852 a.full = dfixed_div(a, b); 853 pclk.full = dfixed_div(b, a); 854 if (crtc->rmx_type != RMX_OFF) { 855 b.full = dfixed_const(2); 856 if (crtc->vsc.full > b.full) 857 b.full = crtc->vsc.full; 858 b.full = dfixed_mul(b, crtc->hsc); 859 c.full = dfixed_const(2); 860 b.full = dfixed_div(b, c); 861 consumption_time.full = dfixed_div(pclk, b); 862 } else { 863 consumption_time.full = pclk.full; 864 } 865 a.full = dfixed_const(1); 866 wm->consumption_rate.full = dfixed_div(a, consumption_time); 867 868 869 /* Determine line time 870 * LineTime = total time for one line of displayhtotal 871 * LineTime = total number of horizontal pixels 872 * pclk = pixel clock period(ns) 873 */ 874 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 875 line_time.full = dfixed_mul(a, pclk); 876 877 /* Determine active time 878 * ActiveTime = time of active region of display within one line, 879 * hactive = total number of horizontal active pixels 880 * htotal = total number of horizontal pixels 881 */ 882 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 883 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 884 wm->active_time.full = dfixed_mul(line_time, b); 885 wm->active_time.full = dfixed_div(wm->active_time, a); 886 887 /* Determine chunk time 888 * ChunkTime = the time it takes the DCP to send one chunk of data 889 * to the LB which consists of pipeline delay and inter chunk gap 890 * sclk = system clock(Mhz) 891 */ 892 a.full = dfixed_const(600 * 1000); 893 chunk_time.full = dfixed_div(a, rdev->pm.sclk); 894 read_delay_latency.full = dfixed_const(1000); 895 896 /* Determine the worst case latency 897 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 898 * WorstCaseLatency = worst case time from urgent to when the MC starts 899 * to return data 900 * READ_DELAY_IDLE_MAX = constant of 1us 901 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 902 * which consists of pipeline delay and inter chunk gap 903 */ 904 if (dfixed_trunc(wm->num_line_pair) > 1) { 905 a.full = dfixed_const(3); 906 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 907 wm->worst_case_latency.full += read_delay_latency.full; 908 } else { 909 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 910 } 911 912 /* Determine the tolerable latency 913 * TolerableLatency = Any given request has only 1 line time 914 * for the data to be returned 915 * LBRequestFifoDepth = Number of chunk requests the LB can 916 * put into the request FIFO for a display 917 * LineTime = total time for one line of display 918 * ChunkTime = the time it takes the DCP to send one chunk 919 * of data to the LB which consists of 920 * pipeline delay and inter chunk gap 921 */ 922 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 923 tolerable_latency.full = line_time.full; 924 } else { 925 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 926 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 927 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 928 tolerable_latency.full = line_time.full - tolerable_latency.full; 929 } 930 /* We assume worst case 32bits (4 bytes) */ 931 wm->dbpp.full = dfixed_const(2 * 16); 932 933 /* Determine the maximum priority mark 934 * width = viewport width in pixels 935 */ 936 a.full = dfixed_const(16); 937 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 938 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 939 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 940 941 /* Determine estimated width */ 942 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 943 estimated_width.full = dfixed_div(estimated_width, consumption_time); 944 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 945 wm->priority_mark.full = wm->priority_mark_max.full; 946 } else { 947 a.full = dfixed_const(16); 948 wm->priority_mark.full = dfixed_div(estimated_width, a); 949 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 950 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 951 } 952 } 953 954 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 955 { 956 struct drm_display_mode *mode0 = NULL; 957 struct drm_display_mode *mode1 = NULL; 958 struct rv515_watermark wm0; 959 struct rv515_watermark wm1; 960 u32 tmp; 961 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 962 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 963 fixed20_12 priority_mark02, priority_mark12, fill_rate; 964 fixed20_12 a, b; 965 966 if (rdev->mode_info.crtcs[0]->base.enabled) 967 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 968 if (rdev->mode_info.crtcs[1]->base.enabled) 969 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 970 rs690_line_buffer_adjust(rdev, mode0, mode1); 971 972 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 973 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 974 975 tmp = wm0.lb_request_fifo_depth; 976 tmp |= wm1.lb_request_fifo_depth << 16; 977 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 978 979 if (mode0 && mode1) { 980 if (dfixed_trunc(wm0.dbpp) > 64) 981 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 982 else 983 a.full = wm0.num_line_pair.full; 984 if (dfixed_trunc(wm1.dbpp) > 64) 985 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 986 else 987 b.full = wm1.num_line_pair.full; 988 a.full += b.full; 989 fill_rate.full = dfixed_div(wm0.sclk, a); 990 if (wm0.consumption_rate.full > fill_rate.full) { 991 b.full = wm0.consumption_rate.full - fill_rate.full; 992 b.full = dfixed_mul(b, wm0.active_time); 993 a.full = dfixed_const(16); 994 b.full = dfixed_div(b, a); 995 a.full = dfixed_mul(wm0.worst_case_latency, 996 wm0.consumption_rate); 997 priority_mark02.full = a.full + b.full; 998 } else { 999 a.full = dfixed_mul(wm0.worst_case_latency, 1000 wm0.consumption_rate); 1001 b.full = dfixed_const(16 * 1000); 1002 priority_mark02.full = dfixed_div(a, b); 1003 } 1004 if (wm1.consumption_rate.full > fill_rate.full) { 1005 b.full = wm1.consumption_rate.full - fill_rate.full; 1006 b.full = dfixed_mul(b, wm1.active_time); 1007 a.full = dfixed_const(16); 1008 b.full = dfixed_div(b, a); 1009 a.full = dfixed_mul(wm1.worst_case_latency, 1010 wm1.consumption_rate); 1011 priority_mark12.full = a.full + b.full; 1012 } else { 1013 a.full = dfixed_mul(wm1.worst_case_latency, 1014 wm1.consumption_rate); 1015 b.full = dfixed_const(16 * 1000); 1016 priority_mark12.full = dfixed_div(a, b); 1017 } 1018 if (wm0.priority_mark.full > priority_mark02.full) 1019 priority_mark02.full = wm0.priority_mark.full; 1020 if (dfixed_trunc(priority_mark02) < 0) 1021 priority_mark02.full = 0; 1022 if (wm0.priority_mark_max.full > priority_mark02.full) 1023 priority_mark02.full = wm0.priority_mark_max.full; 1024 if (wm1.priority_mark.full > priority_mark12.full) 1025 priority_mark12.full = wm1.priority_mark.full; 1026 if (dfixed_trunc(priority_mark12) < 0) 1027 priority_mark12.full = 0; 1028 if (wm1.priority_mark_max.full > priority_mark12.full) 1029 priority_mark12.full = wm1.priority_mark_max.full; 1030 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1031 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1032 if (rdev->disp_priority == 2) { 1033 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1034 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1035 } 1036 } else if (mode0) { 1037 if (dfixed_trunc(wm0.dbpp) > 64) 1038 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1039 else 1040 a.full = wm0.num_line_pair.full; 1041 fill_rate.full = dfixed_div(wm0.sclk, a); 1042 if (wm0.consumption_rate.full > fill_rate.full) { 1043 b.full = wm0.consumption_rate.full - fill_rate.full; 1044 b.full = dfixed_mul(b, wm0.active_time); 1045 a.full = dfixed_const(16); 1046 b.full = dfixed_div(b, a); 1047 a.full = dfixed_mul(wm0.worst_case_latency, 1048 wm0.consumption_rate); 1049 priority_mark02.full = a.full + b.full; 1050 } else { 1051 a.full = dfixed_mul(wm0.worst_case_latency, 1052 wm0.consumption_rate); 1053 b.full = dfixed_const(16); 1054 priority_mark02.full = dfixed_div(a, b); 1055 } 1056 if (wm0.priority_mark.full > priority_mark02.full) 1057 priority_mark02.full = wm0.priority_mark.full; 1058 if (dfixed_trunc(priority_mark02) < 0) 1059 priority_mark02.full = 0; 1060 if (wm0.priority_mark_max.full > priority_mark02.full) 1061 priority_mark02.full = wm0.priority_mark_max.full; 1062 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1063 if (rdev->disp_priority == 2) 1064 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1065 } else if (mode1) { 1066 if (dfixed_trunc(wm1.dbpp) > 64) 1067 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1068 else 1069 a.full = wm1.num_line_pair.full; 1070 fill_rate.full = dfixed_div(wm1.sclk, a); 1071 if (wm1.consumption_rate.full > fill_rate.full) { 1072 b.full = wm1.consumption_rate.full - fill_rate.full; 1073 b.full = dfixed_mul(b, wm1.active_time); 1074 a.full = dfixed_const(16); 1075 b.full = dfixed_div(b, a); 1076 a.full = dfixed_mul(wm1.worst_case_latency, 1077 wm1.consumption_rate); 1078 priority_mark12.full = a.full + b.full; 1079 } else { 1080 a.full = dfixed_mul(wm1.worst_case_latency, 1081 wm1.consumption_rate); 1082 b.full = dfixed_const(16 * 1000); 1083 priority_mark12.full = dfixed_div(a, b); 1084 } 1085 if (wm1.priority_mark.full > priority_mark12.full) 1086 priority_mark12.full = wm1.priority_mark.full; 1087 if (dfixed_trunc(priority_mark12) < 0) 1088 priority_mark12.full = 0; 1089 if (wm1.priority_mark_max.full > priority_mark12.full) 1090 priority_mark12.full = wm1.priority_mark_max.full; 1091 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1092 if (rdev->disp_priority == 2) 1093 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1094 } 1095 1096 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1097 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1098 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1099 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1100 } 1101 1102 void rv515_bandwidth_update(struct radeon_device *rdev) 1103 { 1104 uint32_t tmp; 1105 struct drm_display_mode *mode0 = NULL; 1106 struct drm_display_mode *mode1 = NULL; 1107 1108 radeon_update_display_priority(rdev); 1109 1110 if (rdev->mode_info.crtcs[0]->base.enabled) 1111 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1112 if (rdev->mode_info.crtcs[1]->base.enabled) 1113 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1114 /* 1115 * Set display0/1 priority up in the memory controller for 1116 * modes if the user specifies HIGH for displaypriority 1117 * option. 1118 */ 1119 if ((rdev->disp_priority == 2) && 1120 (rdev->family == CHIP_RV515)) { 1121 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1122 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1123 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1124 if (mode1) 1125 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1126 if (mode0) 1127 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1128 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1129 } 1130 rv515_bandwidth_avivo_update(rdev); 1131 } 1132