1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse #include <linux/seq_file.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 30760285e7SDavid Howells #include <drm/drmP.h> 313ce0a23dSJerome Glisse #include "rv515d.h" 32771fe6b9SJerome Glisse #include "radeon.h" 33e6990375SDaniel Vetter #include "radeon_asic.h" 34d39c3b89SJerome Glisse #include "atom.h" 3550f15303SDave Airlie #include "rv515_reg_safe.h" 36771fe6b9SJerome Glisse 37d39c3b89SJerome Glisse /* This files gather functions specifics to: rv515 */ 38771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev); 41771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42771fe6b9SJerome Glisse 43f0ed1f65SJerome Glisse void rv515_debugfs(struct radeon_device *rdev) 44771fe6b9SJerome Glisse { 45771fe6b9SJerome Glisse if (r100_debugfs_rbbm_init(rdev)) { 46771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 47771fe6b9SJerome Glisse } 48771fe6b9SJerome Glisse if (rv515_debugfs_pipes_info_init(rdev)) { 49771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 50771fe6b9SJerome Glisse } 51771fe6b9SJerome Glisse if (rv515_debugfs_ga_info_init(rdev)) { 52771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 53771fe6b9SJerome Glisse } 54771fe6b9SJerome Glisse } 55771fe6b9SJerome Glisse 56f712812eSAlex Deucher void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 57771fe6b9SJerome Glisse { 58771fe6b9SJerome Glisse int r; 59771fe6b9SJerome Glisse 60e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 64); 61771fe6b9SJerome Glisse if (r) { 62771fe6b9SJerome Glisse return; 63771fe6b9SJerome Glisse } 64e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 65e32eb50dSChristian König radeon_ring_write(ring, 66c93bb85bSJerome Glisse ISYNC_ANY2D_IDLE3D | 67c93bb85bSJerome Glisse ISYNC_ANY3D_IDLE2D | 68c93bb85bSJerome Glisse ISYNC_WAIT_IDLEGUI | 69c93bb85bSJerome Glisse ISYNC_CPSCRATCH_IDLEGUI); 70e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 71e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 72e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 73e32eb50dSChristian König radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 74e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 75e32eb50dSChristian König radeon_ring_write(ring, 0); 76e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 77e32eb50dSChristian König radeon_ring_write(ring, 0); 78e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 79e32eb50dSChristian König radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 80e32eb50dSChristian König radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 81e32eb50dSChristian König radeon_ring_write(ring, 0); 82e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 83e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 84e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 85e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 86e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 87e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 88e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 89e32eb50dSChristian König radeon_ring_write(ring, 0); 90e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 91e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 92e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 93e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 94e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 95e32eb50dSChristian König radeon_ring_write(ring, 96c93bb85bSJerome Glisse ((6 << MS_X0_SHIFT) | 97c93bb85bSJerome Glisse (6 << MS_Y0_SHIFT) | 98c93bb85bSJerome Glisse (6 << MS_X1_SHIFT) | 99c93bb85bSJerome Glisse (6 << MS_Y1_SHIFT) | 100c93bb85bSJerome Glisse (6 << MS_X2_SHIFT) | 101c93bb85bSJerome Glisse (6 << MS_Y2_SHIFT) | 102c93bb85bSJerome Glisse (6 << MSBD0_Y_SHIFT) | 103c93bb85bSJerome Glisse (6 << MSBD0_X_SHIFT))); 104e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 105e32eb50dSChristian König radeon_ring_write(ring, 106c93bb85bSJerome Glisse ((6 << MS_X3_SHIFT) | 107c93bb85bSJerome Glisse (6 << MS_Y3_SHIFT) | 108c93bb85bSJerome Glisse (6 << MS_X4_SHIFT) | 109c93bb85bSJerome Glisse (6 << MS_Y4_SHIFT) | 110c93bb85bSJerome Glisse (6 << MS_X5_SHIFT) | 111c93bb85bSJerome Glisse (6 << MS_Y5_SHIFT) | 112c93bb85bSJerome Glisse (6 << MSBD1_SHIFT))); 113e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 114e32eb50dSChristian König radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 115e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 116e32eb50dSChristian König radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 117e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 118e32eb50dSChristian König radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 119e32eb50dSChristian König radeon_ring_write(ring, PACKET0(0x20C8, 0)); 120e32eb50dSChristian König radeon_ring_write(ring, 0); 121e32eb50dSChristian König radeon_ring_unlock_commit(rdev, ring); 122771fe6b9SJerome Glisse } 123771fe6b9SJerome Glisse 124771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev) 125771fe6b9SJerome Glisse { 126771fe6b9SJerome Glisse unsigned i; 127771fe6b9SJerome Glisse uint32_t tmp; 128771fe6b9SJerome Glisse 129771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 130771fe6b9SJerome Glisse /* read MC_STATUS */ 131c93bb85bSJerome Glisse tmp = RREG32_MC(MC_STATUS); 132c93bb85bSJerome Glisse if (tmp & MC_STATUS_IDLE) { 133771fe6b9SJerome Glisse return 0; 134771fe6b9SJerome Glisse } 135771fe6b9SJerome Glisse DRM_UDELAY(1); 136771fe6b9SJerome Glisse } 137771fe6b9SJerome Glisse return -1; 138771fe6b9SJerome Glisse } 139771fe6b9SJerome Glisse 140d39c3b89SJerome Glisse void rv515_vga_render_disable(struct radeon_device *rdev) 141d39c3b89SJerome Glisse { 142d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 143d39c3b89SJerome Glisse RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 144d39c3b89SJerome Glisse } 145d39c3b89SJerome Glisse 146771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev) 147771fe6b9SJerome Glisse { 148771fe6b9SJerome Glisse unsigned pipe_select_current, gb_pipe_select, tmp; 149771fe6b9SJerome Glisse 150771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 151771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 152481e6283SMasanari Iida "resetting GPU. Bad things might happen.\n"); 153771fe6b9SJerome Glisse } 154d39c3b89SJerome Glisse rv515_vga_render_disable(rdev); 155771fe6b9SJerome Glisse r420_pipes_init(rdev); 156d75ee3beSAlex Deucher gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 157d75ee3beSAlex Deucher tmp = RREG32(R300_DST_PIPE_CONFIG); 158771fe6b9SJerome Glisse pipe_select_current = (tmp >> 2) & 3; 159771fe6b9SJerome Glisse tmp = (1 << pipe_select_current) | 160771fe6b9SJerome Glisse (((gb_pipe_select >> 8) & 0xF) << 4); 161771fe6b9SJerome Glisse WREG32_PLL(0x000D, tmp); 162771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 163771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 164481e6283SMasanari Iida "resetting GPU. Bad things might happen.\n"); 165771fe6b9SJerome Glisse } 166771fe6b9SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) { 167771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait MC idle while " 168771fe6b9SJerome Glisse "programming pipes. Bad things might happen.\n"); 169771fe6b9SJerome Glisse } 170771fe6b9SJerome Glisse } 171771fe6b9SJerome Glisse 172771fe6b9SJerome Glisse static void rv515_vram_get_type(struct radeon_device *rdev) 173771fe6b9SJerome Glisse { 174771fe6b9SJerome Glisse uint32_t tmp; 175771fe6b9SJerome Glisse 176771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 177771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 178c93bb85bSJerome Glisse tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 179771fe6b9SJerome Glisse switch (tmp) { 180771fe6b9SJerome Glisse case 0: 181771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 182771fe6b9SJerome Glisse break; 183771fe6b9SJerome Glisse case 1: 184771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 185771fe6b9SJerome Glisse break; 186771fe6b9SJerome Glisse default: 187771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 188771fe6b9SJerome Glisse break; 189771fe6b9SJerome Glisse } 190771fe6b9SJerome Glisse } 191771fe6b9SJerome Glisse 192d594e46aSJerome Glisse void rv515_mc_init(struct radeon_device *rdev) 193771fe6b9SJerome Glisse { 194771fe6b9SJerome Glisse 195c93bb85bSJerome Glisse rv515_vram_get_type(rdev); 1960924d942SDave Airlie r100_vram_init_sizes(rdev); 197d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, 0); 1988d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 199d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 200d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 201f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 202771fe6b9SJerome Glisse } 203771fe6b9SJerome Glisse 204771fe6b9SJerome Glisse uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 205771fe6b9SJerome Glisse { 206771fe6b9SJerome Glisse uint32_t r; 207771fe6b9SJerome Glisse 208c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 209c93bb85bSJerome Glisse r = RREG32(MC_IND_DATA); 210c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 211771fe6b9SJerome Glisse return r; 212771fe6b9SJerome Glisse } 213771fe6b9SJerome Glisse 214771fe6b9SJerome Glisse void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 215771fe6b9SJerome Glisse { 216c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 217c93bb85bSJerome Glisse WREG32(MC_IND_DATA, (v)); 218c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 219771fe6b9SJerome Glisse } 220771fe6b9SJerome Glisse 221771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 222771fe6b9SJerome Glisse static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 223771fe6b9SJerome Glisse { 224771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 225771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 226771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 227771fe6b9SJerome Glisse uint32_t tmp; 228771fe6b9SJerome Glisse 229c93bb85bSJerome Glisse tmp = RREG32(GB_PIPE_SELECT); 230771fe6b9SJerome Glisse seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 231c93bb85bSJerome Glisse tmp = RREG32(SU_REG_DEST); 232771fe6b9SJerome Glisse seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 233c93bb85bSJerome Glisse tmp = RREG32(GB_TILE_CONFIG); 234771fe6b9SJerome Glisse seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 235c93bb85bSJerome Glisse tmp = RREG32(DST_PIPE_CONFIG); 236771fe6b9SJerome Glisse seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 237771fe6b9SJerome Glisse return 0; 238771fe6b9SJerome Glisse } 239771fe6b9SJerome Glisse 240771fe6b9SJerome Glisse static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 241771fe6b9SJerome Glisse { 242771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 243771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 244771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 245771fe6b9SJerome Glisse uint32_t tmp; 246771fe6b9SJerome Glisse 247771fe6b9SJerome Glisse tmp = RREG32(0x2140); 248771fe6b9SJerome Glisse seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 249a2d07b74SJerome Glisse radeon_asic_reset(rdev); 250771fe6b9SJerome Glisse tmp = RREG32(0x425C); 251771fe6b9SJerome Glisse seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 252771fe6b9SJerome Glisse return 0; 253771fe6b9SJerome Glisse } 254771fe6b9SJerome Glisse 255771fe6b9SJerome Glisse static struct drm_info_list rv515_pipes_info_list[] = { 256771fe6b9SJerome Glisse {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 257771fe6b9SJerome Glisse }; 258771fe6b9SJerome Glisse 259771fe6b9SJerome Glisse static struct drm_info_list rv515_ga_info_list[] = { 260771fe6b9SJerome Glisse {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 261771fe6b9SJerome Glisse }; 262771fe6b9SJerome Glisse #endif 263771fe6b9SJerome Glisse 264771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 265771fe6b9SJerome Glisse { 266771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 267771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 268771fe6b9SJerome Glisse #else 269771fe6b9SJerome Glisse return 0; 270771fe6b9SJerome Glisse #endif 271771fe6b9SJerome Glisse } 272771fe6b9SJerome Glisse 273771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 274771fe6b9SJerome Glisse { 275771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 276771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 277771fe6b9SJerome Glisse #else 278771fe6b9SJerome Glisse return 0; 279771fe6b9SJerome Glisse #endif 280771fe6b9SJerome Glisse } 281068a117cSJerome Glisse 282d39c3b89SJerome Glisse void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 283d39c3b89SJerome Glisse { 284d39c3b89SJerome Glisse save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 285d39c3b89SJerome Glisse save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 286d39c3b89SJerome Glisse 287d39c3b89SJerome Glisse /* Stop all video */ 288d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 289d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 0); 290d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 291d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 292d39c3b89SJerome Glisse WREG32(R_006080_D1CRTC_CONTROL, 0); 293d39c3b89SJerome Glisse WREG32(R_006880_D2CRTC_CONTROL, 0); 294d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 295d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 296ef630627SDave Airlie WREG32(R_000330_D1VGA_CONTROL, 0); 297ef630627SDave Airlie WREG32(R_000338_D2VGA_CONTROL, 0); 298d39c3b89SJerome Glisse } 299d39c3b89SJerome Glisse 300d39c3b89SJerome Glisse void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 301d39c3b89SJerome Glisse { 302d39c3b89SJerome Glisse WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 303d39c3b89SJerome Glisse WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 304d39c3b89SJerome Glisse WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 305d39c3b89SJerome Glisse WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 306d39c3b89SJerome Glisse WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 307d39c3b89SJerome Glisse /* Unlock host access */ 308d39c3b89SJerome Glisse WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 309d39c3b89SJerome Glisse mdelay(1); 310d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 311d39c3b89SJerome Glisse } 312d39c3b89SJerome Glisse 313d39c3b89SJerome Glisse void rv515_mc_program(struct radeon_device *rdev) 314d39c3b89SJerome Glisse { 315d39c3b89SJerome Glisse struct rv515_mc_save save; 316d39c3b89SJerome Glisse 317d39c3b89SJerome Glisse /* Stops all mc clients */ 318d39c3b89SJerome Glisse rv515_mc_stop(rdev, &save); 319d39c3b89SJerome Glisse 320d39c3b89SJerome Glisse /* Wait for mc idle */ 321d39c3b89SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) 322d39c3b89SJerome Glisse dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 323d39c3b89SJerome Glisse /* Write VRAM size in case we are limiting it */ 324d39c3b89SJerome Glisse WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 325d39c3b89SJerome Glisse /* Program MC, should be a 32bits limited address space */ 326d39c3b89SJerome Glisse WREG32_MC(R_000001_MC_FB_LOCATION, 327d39c3b89SJerome Glisse S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 328d39c3b89SJerome Glisse S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 329d39c3b89SJerome Glisse WREG32(R_000134_HDP_FB_LOCATION, 330d39c3b89SJerome Glisse S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 331d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 332d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 333d39c3b89SJerome Glisse S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 334d39c3b89SJerome Glisse S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 335d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 336d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 337d39c3b89SJerome Glisse S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 338d39c3b89SJerome Glisse } else { 339d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 340d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, 0); 341d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 342d39c3b89SJerome Glisse } 343d39c3b89SJerome Glisse 344d39c3b89SJerome Glisse rv515_mc_resume(rdev, &save); 345d39c3b89SJerome Glisse } 346d39c3b89SJerome Glisse 347d39c3b89SJerome Glisse void rv515_clock_startup(struct radeon_device *rdev) 348d39c3b89SJerome Glisse { 349d39c3b89SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 350d39c3b89SJerome Glisse radeon_atom_set_clock_gating(rdev, 1); 351d39c3b89SJerome Glisse /* We need to force on some of the block */ 352d39c3b89SJerome Glisse WREG32_PLL(R_00000F_CP_DYN_CNTL, 353d39c3b89SJerome Glisse RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 354d39c3b89SJerome Glisse WREG32_PLL(R_000011_E2_DYN_CNTL, 355d39c3b89SJerome Glisse RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 356d39c3b89SJerome Glisse WREG32_PLL(R_000013_IDCT_DYN_CNTL, 357d39c3b89SJerome Glisse RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 358d39c3b89SJerome Glisse } 359d39c3b89SJerome Glisse 360d39c3b89SJerome Glisse static int rv515_startup(struct radeon_device *rdev) 361d39c3b89SJerome Glisse { 362d39c3b89SJerome Glisse int r; 363d39c3b89SJerome Glisse 364d39c3b89SJerome Glisse rv515_mc_program(rdev); 365d39c3b89SJerome Glisse /* Resume clock */ 366d39c3b89SJerome Glisse rv515_clock_startup(rdev); 367d39c3b89SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 368d39c3b89SJerome Glisse rv515_gpu_init(rdev); 369d39c3b89SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 370d39c3b89SJerome Glisse * memory through TTM but finalize after TTM) */ 371d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) { 372d39c3b89SJerome Glisse r = rv370_pcie_gart_enable(rdev); 373d39c3b89SJerome Glisse if (r) 374d39c3b89SJerome Glisse return r; 375d39c3b89SJerome Glisse } 376724c80e1SAlex Deucher 377724c80e1SAlex Deucher /* allocate wb buffer */ 378724c80e1SAlex Deucher r = radeon_wb_init(rdev); 379724c80e1SAlex Deucher if (r) 380724c80e1SAlex Deucher return r; 381724c80e1SAlex Deucher 38230eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 38330eb77f4SJerome Glisse if (r) { 38430eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 38530eb77f4SJerome Glisse return r; 38630eb77f4SJerome Glisse } 38730eb77f4SJerome Glisse 388d39c3b89SJerome Glisse /* Enable IRQ */ 389ac447df4SJerome Glisse rs600_irq_set(rdev); 390cafe6609SJerome Glisse rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 391d39c3b89SJerome Glisse /* 1M ring buffer */ 392d39c3b89SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 393d39c3b89SJerome Glisse if (r) { 394ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 395d39c3b89SJerome Glisse return r; 396d39c3b89SJerome Glisse } 397b15ba512SJerome Glisse 3982898c348SChristian König r = radeon_ib_pool_init(rdev); 3992898c348SChristian König if (r) { 4002898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 401b15ba512SJerome Glisse return r; 4022898c348SChristian König } 403b15ba512SJerome Glisse 404d39c3b89SJerome Glisse return 0; 405d39c3b89SJerome Glisse } 406d39c3b89SJerome Glisse 407d39c3b89SJerome Glisse int rv515_resume(struct radeon_device *rdev) 408d39c3b89SJerome Glisse { 4096b7746e8SJerome Glisse int r; 4106b7746e8SJerome Glisse 411d39c3b89SJerome Glisse /* Make sur GART are not working */ 412d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 413d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 414d39c3b89SJerome Glisse /* Resume clock before doing reset */ 415d39c3b89SJerome Glisse rv515_clock_startup(rdev); 416d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 417a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 418d39c3b89SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 419d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 420d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 421d39c3b89SJerome Glisse } 422d39c3b89SJerome Glisse /* post */ 423d39c3b89SJerome Glisse atom_asic_init(rdev->mode_info.atom_context); 424d39c3b89SJerome Glisse /* Resume clock after posting */ 425d39c3b89SJerome Glisse rv515_clock_startup(rdev); 426550e2d92SDave Airlie /* Initialize surface registers */ 427550e2d92SDave Airlie radeon_surface_init(rdev); 428b15ba512SJerome Glisse 429b15ba512SJerome Glisse rdev->accel_working = true; 4306b7746e8SJerome Glisse r = rv515_startup(rdev); 4316b7746e8SJerome Glisse if (r) { 4326b7746e8SJerome Glisse rdev->accel_working = false; 4336b7746e8SJerome Glisse } 4346b7746e8SJerome Glisse return r; 435d39c3b89SJerome Glisse } 436d39c3b89SJerome Glisse 437d39c3b89SJerome Glisse int rv515_suspend(struct radeon_device *rdev) 438d39c3b89SJerome Glisse { 439d39c3b89SJerome Glisse r100_cp_disable(rdev); 440724c80e1SAlex Deucher radeon_wb_disable(rdev); 441ac447df4SJerome Glisse rs600_irq_disable(rdev); 442d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 443d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 444d39c3b89SJerome Glisse return 0; 445d39c3b89SJerome Glisse } 446d39c3b89SJerome Glisse 447d39c3b89SJerome Glisse void rv515_set_safe_registers(struct radeon_device *rdev) 448068a117cSJerome Glisse { 44950f15303SDave Airlie rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 45050f15303SDave Airlie rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 451d39c3b89SJerome Glisse } 452d39c3b89SJerome Glisse 453d39c3b89SJerome Glisse void rv515_fini(struct radeon_device *rdev) 454d39c3b89SJerome Glisse { 455d39c3b89SJerome Glisse r100_cp_fini(rdev); 456724c80e1SAlex Deucher radeon_wb_fini(rdev); 4572898c348SChristian König radeon_ib_pool_fini(rdev); 458d39c3b89SJerome Glisse radeon_gem_fini(rdev); 459d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 460d39c3b89SJerome Glisse radeon_agp_fini(rdev); 461d39c3b89SJerome Glisse radeon_irq_kms_fini(rdev); 462d39c3b89SJerome Glisse radeon_fence_driver_fini(rdev); 4634c788679SJerome Glisse radeon_bo_fini(rdev); 464d39c3b89SJerome Glisse radeon_atombios_fini(rdev); 465d39c3b89SJerome Glisse kfree(rdev->bios); 466d39c3b89SJerome Glisse rdev->bios = NULL; 467d39c3b89SJerome Glisse } 468d39c3b89SJerome Glisse 469d39c3b89SJerome Glisse int rv515_init(struct radeon_device *rdev) 470d39c3b89SJerome Glisse { 471d39c3b89SJerome Glisse int r; 472d39c3b89SJerome Glisse 473d39c3b89SJerome Glisse /* Initialize scratch registers */ 474d39c3b89SJerome Glisse radeon_scratch_init(rdev); 475d39c3b89SJerome Glisse /* Initialize surface registers */ 476d39c3b89SJerome Glisse radeon_surface_init(rdev); 477d39c3b89SJerome Glisse /* TODO: disable VGA need to use VGA request */ 4784c712e6cSDave Airlie /* restore some register to sane defaults */ 4794c712e6cSDave Airlie r100_restore_sanity(rdev); 480d39c3b89SJerome Glisse /* BIOS*/ 481d39c3b89SJerome Glisse if (!radeon_get_bios(rdev)) { 482d39c3b89SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 483d39c3b89SJerome Glisse return -EINVAL; 484d39c3b89SJerome Glisse } 485d39c3b89SJerome Glisse if (rdev->is_atom_bios) { 486d39c3b89SJerome Glisse r = radeon_atombios_init(rdev); 487d39c3b89SJerome Glisse if (r) 488d39c3b89SJerome Glisse return r; 489d39c3b89SJerome Glisse } else { 490d39c3b89SJerome Glisse dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 491d39c3b89SJerome Glisse return -EINVAL; 492d39c3b89SJerome Glisse } 493d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 494a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 495d39c3b89SJerome Glisse dev_warn(rdev->dev, 496d39c3b89SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 497d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 498d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 499d39c3b89SJerome Glisse } 500d39c3b89SJerome Glisse /* check if cards are posted or not */ 50172542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 50272542d77SDave Airlie return -EINVAL; 503d39c3b89SJerome Glisse /* Initialize clocks */ 504d39c3b89SJerome Glisse radeon_get_clock_info(rdev->ddev); 505d594e46aSJerome Glisse /* initialize AGP */ 506d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 507d594e46aSJerome Glisse r = radeon_agp_init(rdev); 508d594e46aSJerome Glisse if (r) { 509d594e46aSJerome Glisse radeon_agp_disable(rdev); 510d594e46aSJerome Glisse } 511d594e46aSJerome Glisse } 512d594e46aSJerome Glisse /* initialize memory controller */ 513d594e46aSJerome Glisse rv515_mc_init(rdev); 514d39c3b89SJerome Glisse rv515_debugfs(rdev); 515d39c3b89SJerome Glisse /* Fence driver */ 51630eb77f4SJerome Glisse r = radeon_fence_driver_init(rdev); 517d39c3b89SJerome Glisse if (r) 518d39c3b89SJerome Glisse return r; 519d39c3b89SJerome Glisse r = radeon_irq_kms_init(rdev); 520d39c3b89SJerome Glisse if (r) 521d39c3b89SJerome Glisse return r; 522d39c3b89SJerome Glisse /* Memory manager */ 5234c788679SJerome Glisse r = radeon_bo_init(rdev); 524d39c3b89SJerome Glisse if (r) 525d39c3b89SJerome Glisse return r; 526d39c3b89SJerome Glisse r = rv370_pcie_gart_init(rdev); 527d39c3b89SJerome Glisse if (r) 528d39c3b89SJerome Glisse return r; 529d39c3b89SJerome Glisse rv515_set_safe_registers(rdev); 530b15ba512SJerome Glisse 531d39c3b89SJerome Glisse rdev->accel_working = true; 532d39c3b89SJerome Glisse r = rv515_startup(rdev); 533d39c3b89SJerome Glisse if (r) { 534d39c3b89SJerome Glisse /* Somethings want wront with the accel init stop accel */ 535d39c3b89SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 536d39c3b89SJerome Glisse r100_cp_fini(rdev); 537724c80e1SAlex Deucher radeon_wb_fini(rdev); 5382898c348SChristian König radeon_ib_pool_fini(rdev); 539655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 540d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 541d39c3b89SJerome Glisse radeon_agp_fini(rdev); 542d39c3b89SJerome Glisse rdev->accel_working = false; 543d39c3b89SJerome Glisse } 544068a117cSJerome Glisse return 0; 545068a117cSJerome Glisse } 546c93bb85bSJerome Glisse 5474ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 548c93bb85bSJerome Glisse { 5494ce001abSDave Airlie int index_reg = 0x6578 + crtc->crtc_offset; 5504ce001abSDave Airlie int data_reg = 0x657c + crtc->crtc_offset; 551c93bb85bSJerome Glisse 5524ce001abSDave Airlie WREG32(0x659C + crtc->crtc_offset, 0x0); 5534ce001abSDave Airlie WREG32(0x6594 + crtc->crtc_offset, 0x705); 5544ce001abSDave Airlie WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 5554ce001abSDave Airlie WREG32(0x65D8 + crtc->crtc_offset, 0x0); 5564ce001abSDave Airlie WREG32(0x65B0 + crtc->crtc_offset, 0x0); 5574ce001abSDave Airlie WREG32(0x65C0 + crtc->crtc_offset, 0x0); 5584ce001abSDave Airlie WREG32(0x65D4 + crtc->crtc_offset, 0x0); 5594ce001abSDave Airlie WREG32(index_reg, 0x0); 5604ce001abSDave Airlie WREG32(data_reg, 0x841880A8); 5614ce001abSDave Airlie WREG32(index_reg, 0x1); 5624ce001abSDave Airlie WREG32(data_reg, 0x84208680); 5634ce001abSDave Airlie WREG32(index_reg, 0x2); 5644ce001abSDave Airlie WREG32(data_reg, 0xBFF880B0); 5654ce001abSDave Airlie WREG32(index_reg, 0x100); 5664ce001abSDave Airlie WREG32(data_reg, 0x83D88088); 5674ce001abSDave Airlie WREG32(index_reg, 0x101); 5684ce001abSDave Airlie WREG32(data_reg, 0x84608680); 5694ce001abSDave Airlie WREG32(index_reg, 0x102); 5704ce001abSDave Airlie WREG32(data_reg, 0xBFF080D0); 5714ce001abSDave Airlie WREG32(index_reg, 0x200); 5724ce001abSDave Airlie WREG32(data_reg, 0x83988068); 5734ce001abSDave Airlie WREG32(index_reg, 0x201); 5744ce001abSDave Airlie WREG32(data_reg, 0x84A08680); 5754ce001abSDave Airlie WREG32(index_reg, 0x202); 5764ce001abSDave Airlie WREG32(data_reg, 0xBFF080F8); 5774ce001abSDave Airlie WREG32(index_reg, 0x300); 5784ce001abSDave Airlie WREG32(data_reg, 0x83588058); 5794ce001abSDave Airlie WREG32(index_reg, 0x301); 5804ce001abSDave Airlie WREG32(data_reg, 0x84E08660); 5814ce001abSDave Airlie WREG32(index_reg, 0x302); 5824ce001abSDave Airlie WREG32(data_reg, 0xBFF88120); 5834ce001abSDave Airlie WREG32(index_reg, 0x400); 5844ce001abSDave Airlie WREG32(data_reg, 0x83188040); 5854ce001abSDave Airlie WREG32(index_reg, 0x401); 5864ce001abSDave Airlie WREG32(data_reg, 0x85008660); 5874ce001abSDave Airlie WREG32(index_reg, 0x402); 5884ce001abSDave Airlie WREG32(data_reg, 0xBFF88150); 5894ce001abSDave Airlie WREG32(index_reg, 0x500); 5904ce001abSDave Airlie WREG32(data_reg, 0x82D88030); 5914ce001abSDave Airlie WREG32(index_reg, 0x501); 5924ce001abSDave Airlie WREG32(data_reg, 0x85408640); 5934ce001abSDave Airlie WREG32(index_reg, 0x502); 5944ce001abSDave Airlie WREG32(data_reg, 0xBFF88180); 5954ce001abSDave Airlie WREG32(index_reg, 0x600); 5964ce001abSDave Airlie WREG32(data_reg, 0x82A08018); 5974ce001abSDave Airlie WREG32(index_reg, 0x601); 5984ce001abSDave Airlie WREG32(data_reg, 0x85808620); 5994ce001abSDave Airlie WREG32(index_reg, 0x602); 6004ce001abSDave Airlie WREG32(data_reg, 0xBFF081B8); 6014ce001abSDave Airlie WREG32(index_reg, 0x700); 6024ce001abSDave Airlie WREG32(data_reg, 0x82608010); 6034ce001abSDave Airlie WREG32(index_reg, 0x701); 6044ce001abSDave Airlie WREG32(data_reg, 0x85A08600); 6054ce001abSDave Airlie WREG32(index_reg, 0x702); 6064ce001abSDave Airlie WREG32(data_reg, 0x800081F0); 6074ce001abSDave Airlie WREG32(index_reg, 0x800); 6084ce001abSDave Airlie WREG32(data_reg, 0x8228BFF8); 6094ce001abSDave Airlie WREG32(index_reg, 0x801); 6104ce001abSDave Airlie WREG32(data_reg, 0x85E085E0); 6114ce001abSDave Airlie WREG32(index_reg, 0x802); 6124ce001abSDave Airlie WREG32(data_reg, 0xBFF88228); 6134ce001abSDave Airlie WREG32(index_reg, 0x10000); 6144ce001abSDave Airlie WREG32(data_reg, 0x82A8BF00); 6154ce001abSDave Airlie WREG32(index_reg, 0x10001); 6164ce001abSDave Airlie WREG32(data_reg, 0x82A08CC0); 6174ce001abSDave Airlie WREG32(index_reg, 0x10002); 6184ce001abSDave Airlie WREG32(data_reg, 0x8008BEF8); 6194ce001abSDave Airlie WREG32(index_reg, 0x10100); 6204ce001abSDave Airlie WREG32(data_reg, 0x81F0BF28); 6214ce001abSDave Airlie WREG32(index_reg, 0x10101); 6224ce001abSDave Airlie WREG32(data_reg, 0x83608CA0); 6234ce001abSDave Airlie WREG32(index_reg, 0x10102); 6244ce001abSDave Airlie WREG32(data_reg, 0x8018BED0); 6254ce001abSDave Airlie WREG32(index_reg, 0x10200); 6264ce001abSDave Airlie WREG32(data_reg, 0x8148BF38); 6274ce001abSDave Airlie WREG32(index_reg, 0x10201); 6284ce001abSDave Airlie WREG32(data_reg, 0x84408C80); 6294ce001abSDave Airlie WREG32(index_reg, 0x10202); 6304ce001abSDave Airlie WREG32(data_reg, 0x8008BEB8); 6314ce001abSDave Airlie WREG32(index_reg, 0x10300); 6324ce001abSDave Airlie WREG32(data_reg, 0x80B0BF78); 6334ce001abSDave Airlie WREG32(index_reg, 0x10301); 6344ce001abSDave Airlie WREG32(data_reg, 0x85008C20); 6354ce001abSDave Airlie WREG32(index_reg, 0x10302); 6364ce001abSDave Airlie WREG32(data_reg, 0x8020BEA0); 6374ce001abSDave Airlie WREG32(index_reg, 0x10400); 6384ce001abSDave Airlie WREG32(data_reg, 0x8028BF90); 6394ce001abSDave Airlie WREG32(index_reg, 0x10401); 6404ce001abSDave Airlie WREG32(data_reg, 0x85E08BC0); 6414ce001abSDave Airlie WREG32(index_reg, 0x10402); 6424ce001abSDave Airlie WREG32(data_reg, 0x8018BE90); 6434ce001abSDave Airlie WREG32(index_reg, 0x10500); 6444ce001abSDave Airlie WREG32(data_reg, 0xBFB8BFB0); 6454ce001abSDave Airlie WREG32(index_reg, 0x10501); 6464ce001abSDave Airlie WREG32(data_reg, 0x86C08B40); 6474ce001abSDave Airlie WREG32(index_reg, 0x10502); 6484ce001abSDave Airlie WREG32(data_reg, 0x8010BE90); 6494ce001abSDave Airlie WREG32(index_reg, 0x10600); 6504ce001abSDave Airlie WREG32(data_reg, 0xBF58BFC8); 6514ce001abSDave Airlie WREG32(index_reg, 0x10601); 6524ce001abSDave Airlie WREG32(data_reg, 0x87A08AA0); 6534ce001abSDave Airlie WREG32(index_reg, 0x10602); 6544ce001abSDave Airlie WREG32(data_reg, 0x8010BE98); 6554ce001abSDave Airlie WREG32(index_reg, 0x10700); 6564ce001abSDave Airlie WREG32(data_reg, 0xBF10BFF0); 6574ce001abSDave Airlie WREG32(index_reg, 0x10701); 6584ce001abSDave Airlie WREG32(data_reg, 0x886089E0); 6594ce001abSDave Airlie WREG32(index_reg, 0x10702); 6604ce001abSDave Airlie WREG32(data_reg, 0x8018BEB0); 6614ce001abSDave Airlie WREG32(index_reg, 0x10800); 6624ce001abSDave Airlie WREG32(data_reg, 0xBED8BFE8); 6634ce001abSDave Airlie WREG32(index_reg, 0x10801); 6644ce001abSDave Airlie WREG32(data_reg, 0x89408940); 6654ce001abSDave Airlie WREG32(index_reg, 0x10802); 6664ce001abSDave Airlie WREG32(data_reg, 0xBFE8BED8); 6674ce001abSDave Airlie WREG32(index_reg, 0x20000); 6684ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6694ce001abSDave Airlie WREG32(index_reg, 0x20001); 6704ce001abSDave Airlie WREG32(data_reg, 0x90008000); 6714ce001abSDave Airlie WREG32(index_reg, 0x20002); 6724ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6734ce001abSDave Airlie WREG32(index_reg, 0x20003); 6744ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6754ce001abSDave Airlie WREG32(index_reg, 0x20100); 6764ce001abSDave Airlie WREG32(data_reg, 0x80108000); 6774ce001abSDave Airlie WREG32(index_reg, 0x20101); 6784ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF70); 6794ce001abSDave Airlie WREG32(index_reg, 0x20102); 6804ce001abSDave Airlie WREG32(data_reg, 0xBFE880C0); 6814ce001abSDave Airlie WREG32(index_reg, 0x20103); 6824ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6834ce001abSDave Airlie WREG32(index_reg, 0x20200); 6844ce001abSDave Airlie WREG32(data_reg, 0x8018BFF8); 6854ce001abSDave Airlie WREG32(index_reg, 0x20201); 6864ce001abSDave Airlie WREG32(data_reg, 0x8F80BF08); 6874ce001abSDave Airlie WREG32(index_reg, 0x20202); 6884ce001abSDave Airlie WREG32(data_reg, 0xBFD081A0); 6894ce001abSDave Airlie WREG32(index_reg, 0x20203); 6904ce001abSDave Airlie WREG32(data_reg, 0xBFF88000); 6914ce001abSDave Airlie WREG32(index_reg, 0x20300); 6924ce001abSDave Airlie WREG32(data_reg, 0x80188000); 6934ce001abSDave Airlie WREG32(index_reg, 0x20301); 6944ce001abSDave Airlie WREG32(data_reg, 0x8EE0BEC0); 6954ce001abSDave Airlie WREG32(index_reg, 0x20302); 6964ce001abSDave Airlie WREG32(data_reg, 0xBFB082A0); 6974ce001abSDave Airlie WREG32(index_reg, 0x20303); 6984ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6994ce001abSDave Airlie WREG32(index_reg, 0x20400); 7004ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7014ce001abSDave Airlie WREG32(index_reg, 0x20401); 7024ce001abSDave Airlie WREG32(data_reg, 0x8E00BEA0); 7034ce001abSDave Airlie WREG32(index_reg, 0x20402); 7044ce001abSDave Airlie WREG32(data_reg, 0xBF8883C0); 7054ce001abSDave Airlie WREG32(index_reg, 0x20403); 7064ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7074ce001abSDave Airlie WREG32(index_reg, 0x20500); 7084ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7094ce001abSDave Airlie WREG32(index_reg, 0x20501); 7104ce001abSDave Airlie WREG32(data_reg, 0x8D00BE90); 7114ce001abSDave Airlie WREG32(index_reg, 0x20502); 7124ce001abSDave Airlie WREG32(data_reg, 0xBF588500); 7134ce001abSDave Airlie WREG32(index_reg, 0x20503); 7144ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7154ce001abSDave Airlie WREG32(index_reg, 0x20600); 7164ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7174ce001abSDave Airlie WREG32(index_reg, 0x20601); 7184ce001abSDave Airlie WREG32(data_reg, 0x8BC0BE98); 7194ce001abSDave Airlie WREG32(index_reg, 0x20602); 7204ce001abSDave Airlie WREG32(data_reg, 0xBF308660); 7214ce001abSDave Airlie WREG32(index_reg, 0x20603); 7224ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7234ce001abSDave Airlie WREG32(index_reg, 0x20700); 7244ce001abSDave Airlie WREG32(data_reg, 0x80108000); 7254ce001abSDave Airlie WREG32(index_reg, 0x20701); 7264ce001abSDave Airlie WREG32(data_reg, 0x8A80BEB0); 7274ce001abSDave Airlie WREG32(index_reg, 0x20702); 7284ce001abSDave Airlie WREG32(data_reg, 0xBF0087C0); 7294ce001abSDave Airlie WREG32(index_reg, 0x20703); 7304ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7314ce001abSDave Airlie WREG32(index_reg, 0x20800); 7324ce001abSDave Airlie WREG32(data_reg, 0x80108000); 7334ce001abSDave Airlie WREG32(index_reg, 0x20801); 7344ce001abSDave Airlie WREG32(data_reg, 0x8920BED0); 7354ce001abSDave Airlie WREG32(index_reg, 0x20802); 7364ce001abSDave Airlie WREG32(data_reg, 0xBED08920); 7374ce001abSDave Airlie WREG32(index_reg, 0x20803); 7384ce001abSDave Airlie WREG32(data_reg, 0x80008010); 7394ce001abSDave Airlie WREG32(index_reg, 0x30000); 7404ce001abSDave Airlie WREG32(data_reg, 0x90008000); 7414ce001abSDave Airlie WREG32(index_reg, 0x30001); 7424ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7434ce001abSDave Airlie WREG32(index_reg, 0x30100); 7444ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF90); 7454ce001abSDave Airlie WREG32(index_reg, 0x30101); 7464ce001abSDave Airlie WREG32(data_reg, 0xBFF880A0); 7474ce001abSDave Airlie WREG32(index_reg, 0x30200); 7484ce001abSDave Airlie WREG32(data_reg, 0x8F60BF40); 7494ce001abSDave Airlie WREG32(index_reg, 0x30201); 7504ce001abSDave Airlie WREG32(data_reg, 0xBFE88180); 7514ce001abSDave Airlie WREG32(index_reg, 0x30300); 7524ce001abSDave Airlie WREG32(data_reg, 0x8EC0BF00); 7534ce001abSDave Airlie WREG32(index_reg, 0x30301); 7544ce001abSDave Airlie WREG32(data_reg, 0xBFC88280); 7554ce001abSDave Airlie WREG32(index_reg, 0x30400); 7564ce001abSDave Airlie WREG32(data_reg, 0x8DE0BEE0); 7574ce001abSDave Airlie WREG32(index_reg, 0x30401); 7584ce001abSDave Airlie WREG32(data_reg, 0xBFA083A0); 7594ce001abSDave Airlie WREG32(index_reg, 0x30500); 7604ce001abSDave Airlie WREG32(data_reg, 0x8CE0BED0); 7614ce001abSDave Airlie WREG32(index_reg, 0x30501); 7624ce001abSDave Airlie WREG32(data_reg, 0xBF7884E0); 7634ce001abSDave Airlie WREG32(index_reg, 0x30600); 7644ce001abSDave Airlie WREG32(data_reg, 0x8BA0BED8); 7654ce001abSDave Airlie WREG32(index_reg, 0x30601); 7664ce001abSDave Airlie WREG32(data_reg, 0xBF508640); 7674ce001abSDave Airlie WREG32(index_reg, 0x30700); 7684ce001abSDave Airlie WREG32(data_reg, 0x8A60BEE8); 7694ce001abSDave Airlie WREG32(index_reg, 0x30701); 7704ce001abSDave Airlie WREG32(data_reg, 0xBF2087A0); 7714ce001abSDave Airlie WREG32(index_reg, 0x30800); 7724ce001abSDave Airlie WREG32(data_reg, 0x8900BF00); 7734ce001abSDave Airlie WREG32(index_reg, 0x30801); 7744ce001abSDave Airlie WREG32(data_reg, 0xBF008900); 775c93bb85bSJerome Glisse } 776c93bb85bSJerome Glisse 777c93bb85bSJerome Glisse struct rv515_watermark { 778c93bb85bSJerome Glisse u32 lb_request_fifo_depth; 779c93bb85bSJerome Glisse fixed20_12 num_line_pair; 780c93bb85bSJerome Glisse fixed20_12 estimated_width; 781c93bb85bSJerome Glisse fixed20_12 worst_case_latency; 782c93bb85bSJerome Glisse fixed20_12 consumption_rate; 783c93bb85bSJerome Glisse fixed20_12 active_time; 784c93bb85bSJerome Glisse fixed20_12 dbpp; 785c93bb85bSJerome Glisse fixed20_12 priority_mark_max; 786c93bb85bSJerome Glisse fixed20_12 priority_mark; 787c93bb85bSJerome Glisse fixed20_12 sclk; 788c93bb85bSJerome Glisse }; 789c93bb85bSJerome Glisse 790c93bb85bSJerome Glisse void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 791c93bb85bSJerome Glisse struct radeon_crtc *crtc, 792c93bb85bSJerome Glisse struct rv515_watermark *wm) 793c93bb85bSJerome Glisse { 794c93bb85bSJerome Glisse struct drm_display_mode *mode = &crtc->base.mode; 795c93bb85bSJerome Glisse fixed20_12 a, b, c; 796c93bb85bSJerome Glisse fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 797c93bb85bSJerome Glisse fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 798c93bb85bSJerome Glisse 799c93bb85bSJerome Glisse if (!crtc->base.enabled) { 800c93bb85bSJerome Glisse /* FIXME: wouldn't it better to set priority mark to maximum */ 801c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 802c93bb85bSJerome Glisse return; 803c93bb85bSJerome Glisse } 804c93bb85bSJerome Glisse 80568adac5eSBen Skeggs if (crtc->vsc.full > dfixed_const(2)) 80668adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(2); 807c93bb85bSJerome Glisse else 80868adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(1); 809c93bb85bSJerome Glisse 81068adac5eSBen Skeggs b.full = dfixed_const(mode->crtc_hdisplay); 81168adac5eSBen Skeggs c.full = dfixed_const(256); 81268adac5eSBen Skeggs a.full = dfixed_div(b, c); 81368adac5eSBen Skeggs request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 81468adac5eSBen Skeggs request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 81568adac5eSBen Skeggs if (a.full < dfixed_const(4)) { 816c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 817c93bb85bSJerome Glisse } else { 81868adac5eSBen Skeggs wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 819c93bb85bSJerome Glisse } 820c93bb85bSJerome Glisse 821c93bb85bSJerome Glisse /* Determine consumption rate 822c93bb85bSJerome Glisse * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 823c93bb85bSJerome Glisse * vtaps = number of vertical taps, 824c93bb85bSJerome Glisse * vsc = vertical scaling ratio, defined as source/destination 825c93bb85bSJerome Glisse * hsc = horizontal scaling ration, defined as source/destination 826c93bb85bSJerome Glisse */ 82768adac5eSBen Skeggs a.full = dfixed_const(mode->clock); 82868adac5eSBen Skeggs b.full = dfixed_const(1000); 82968adac5eSBen Skeggs a.full = dfixed_div(a, b); 83068adac5eSBen Skeggs pclk.full = dfixed_div(b, a); 831c93bb85bSJerome Glisse if (crtc->rmx_type != RMX_OFF) { 83268adac5eSBen Skeggs b.full = dfixed_const(2); 833c93bb85bSJerome Glisse if (crtc->vsc.full > b.full) 834c93bb85bSJerome Glisse b.full = crtc->vsc.full; 83568adac5eSBen Skeggs b.full = dfixed_mul(b, crtc->hsc); 83668adac5eSBen Skeggs c.full = dfixed_const(2); 83768adac5eSBen Skeggs b.full = dfixed_div(b, c); 83868adac5eSBen Skeggs consumption_time.full = dfixed_div(pclk, b); 839c93bb85bSJerome Glisse } else { 840c93bb85bSJerome Glisse consumption_time.full = pclk.full; 841c93bb85bSJerome Glisse } 84268adac5eSBen Skeggs a.full = dfixed_const(1); 84368adac5eSBen Skeggs wm->consumption_rate.full = dfixed_div(a, consumption_time); 844c93bb85bSJerome Glisse 845c93bb85bSJerome Glisse 846c93bb85bSJerome Glisse /* Determine line time 847c93bb85bSJerome Glisse * LineTime = total time for one line of displayhtotal 848c93bb85bSJerome Glisse * LineTime = total number of horizontal pixels 849c93bb85bSJerome Glisse * pclk = pixel clock period(ns) 850c93bb85bSJerome Glisse */ 85168adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 85268adac5eSBen Skeggs line_time.full = dfixed_mul(a, pclk); 853c93bb85bSJerome Glisse 854c93bb85bSJerome Glisse /* Determine active time 855c93bb85bSJerome Glisse * ActiveTime = time of active region of display within one line, 856c93bb85bSJerome Glisse * hactive = total number of horizontal active pixels 857c93bb85bSJerome Glisse * htotal = total number of horizontal pixels 858c93bb85bSJerome Glisse */ 85968adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 86068adac5eSBen Skeggs b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 86168adac5eSBen Skeggs wm->active_time.full = dfixed_mul(line_time, b); 86268adac5eSBen Skeggs wm->active_time.full = dfixed_div(wm->active_time, a); 863c93bb85bSJerome Glisse 864c93bb85bSJerome Glisse /* Determine chunk time 865c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk of data 866c93bb85bSJerome Glisse * to the LB which consists of pipeline delay and inter chunk gap 867c93bb85bSJerome Glisse * sclk = system clock(Mhz) 868c93bb85bSJerome Glisse */ 86968adac5eSBen Skeggs a.full = dfixed_const(600 * 1000); 87068adac5eSBen Skeggs chunk_time.full = dfixed_div(a, rdev->pm.sclk); 87168adac5eSBen Skeggs read_delay_latency.full = dfixed_const(1000); 872c93bb85bSJerome Glisse 873c93bb85bSJerome Glisse /* Determine the worst case latency 874c93bb85bSJerome Glisse * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 875c93bb85bSJerome Glisse * WorstCaseLatency = worst case time from urgent to when the MC starts 876c93bb85bSJerome Glisse * to return data 877c93bb85bSJerome Glisse * READ_DELAY_IDLE_MAX = constant of 1us 878c93bb85bSJerome Glisse * ChunkTime = time it takes the DCP to send one chunk of data to the LB 879c93bb85bSJerome Glisse * which consists of pipeline delay and inter chunk gap 880c93bb85bSJerome Glisse */ 88168adac5eSBen Skeggs if (dfixed_trunc(wm->num_line_pair) > 1) { 88268adac5eSBen Skeggs a.full = dfixed_const(3); 88368adac5eSBen Skeggs wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 884c93bb85bSJerome Glisse wm->worst_case_latency.full += read_delay_latency.full; 885c93bb85bSJerome Glisse } else { 886c93bb85bSJerome Glisse wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 887c93bb85bSJerome Glisse } 888c93bb85bSJerome Glisse 889c93bb85bSJerome Glisse /* Determine the tolerable latency 890c93bb85bSJerome Glisse * TolerableLatency = Any given request has only 1 line time 891c93bb85bSJerome Glisse * for the data to be returned 892c93bb85bSJerome Glisse * LBRequestFifoDepth = Number of chunk requests the LB can 893c93bb85bSJerome Glisse * put into the request FIFO for a display 894c93bb85bSJerome Glisse * LineTime = total time for one line of display 895c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk 896c93bb85bSJerome Glisse * of data to the LB which consists of 897c93bb85bSJerome Glisse * pipeline delay and inter chunk gap 898c93bb85bSJerome Glisse */ 89968adac5eSBen Skeggs if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 900c93bb85bSJerome Glisse tolerable_latency.full = line_time.full; 901c93bb85bSJerome Glisse } else { 90268adac5eSBen Skeggs tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 903c93bb85bSJerome Glisse tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 90468adac5eSBen Skeggs tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 905c93bb85bSJerome Glisse tolerable_latency.full = line_time.full - tolerable_latency.full; 906c93bb85bSJerome Glisse } 907c93bb85bSJerome Glisse /* We assume worst case 32bits (4 bytes) */ 90868adac5eSBen Skeggs wm->dbpp.full = dfixed_const(2 * 16); 909c93bb85bSJerome Glisse 910c93bb85bSJerome Glisse /* Determine the maximum priority mark 911c93bb85bSJerome Glisse * width = viewport width in pixels 912c93bb85bSJerome Glisse */ 91368adac5eSBen Skeggs a.full = dfixed_const(16); 91468adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 91568adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 91668adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 917c93bb85bSJerome Glisse 918c93bb85bSJerome Glisse /* Determine estimated width */ 919c93bb85bSJerome Glisse estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 92068adac5eSBen Skeggs estimated_width.full = dfixed_div(estimated_width, consumption_time); 92168adac5eSBen Skeggs if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 92269b3b5e5SAlex Deucher wm->priority_mark.full = wm->priority_mark_max.full; 923c93bb85bSJerome Glisse } else { 92468adac5eSBen Skeggs a.full = dfixed_const(16); 92568adac5eSBen Skeggs wm->priority_mark.full = dfixed_div(estimated_width, a); 92668adac5eSBen Skeggs wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 927c93bb85bSJerome Glisse wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 928c93bb85bSJerome Glisse } 929c93bb85bSJerome Glisse } 930c93bb85bSJerome Glisse 931c93bb85bSJerome Glisse void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 932c93bb85bSJerome Glisse { 933c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 934c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 935c93bb85bSJerome Glisse struct rv515_watermark wm0; 936c93bb85bSJerome Glisse struct rv515_watermark wm1; 937e06b14eeSAlex Deucher u32 tmp; 938e06b14eeSAlex Deucher u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 939e06b14eeSAlex Deucher u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 940c93bb85bSJerome Glisse fixed20_12 priority_mark02, priority_mark12, fill_rate; 941c93bb85bSJerome Glisse fixed20_12 a, b; 942c93bb85bSJerome Glisse 943c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 944c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 945c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 946c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 947c93bb85bSJerome Glisse rs690_line_buffer_adjust(rdev, mode0, mode1); 948c93bb85bSJerome Glisse 949c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 950c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 951c93bb85bSJerome Glisse 952c93bb85bSJerome Glisse tmp = wm0.lb_request_fifo_depth; 953c93bb85bSJerome Glisse tmp |= wm1.lb_request_fifo_depth << 16; 954c93bb85bSJerome Glisse WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 955c93bb85bSJerome Glisse 956c93bb85bSJerome Glisse if (mode0 && mode1) { 95768adac5eSBen Skeggs if (dfixed_trunc(wm0.dbpp) > 64) 95868adac5eSBen Skeggs a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 959c93bb85bSJerome Glisse else 960c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 96168adac5eSBen Skeggs if (dfixed_trunc(wm1.dbpp) > 64) 96268adac5eSBen Skeggs b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 963c93bb85bSJerome Glisse else 964c93bb85bSJerome Glisse b.full = wm1.num_line_pair.full; 965c93bb85bSJerome Glisse a.full += b.full; 96668adac5eSBen Skeggs fill_rate.full = dfixed_div(wm0.sclk, a); 967c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 968c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 96968adac5eSBen Skeggs b.full = dfixed_mul(b, wm0.active_time); 97068adac5eSBen Skeggs a.full = dfixed_const(16); 97168adac5eSBen Skeggs b.full = dfixed_div(b, a); 97268adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 973c93bb85bSJerome Glisse wm0.consumption_rate); 974c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 975c93bb85bSJerome Glisse } else { 97668adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 977c93bb85bSJerome Glisse wm0.consumption_rate); 97868adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 97968adac5eSBen Skeggs priority_mark02.full = dfixed_div(a, b); 980c93bb85bSJerome Glisse } 981c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 982c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 98368adac5eSBen Skeggs b.full = dfixed_mul(b, wm1.active_time); 98468adac5eSBen Skeggs a.full = dfixed_const(16); 98568adac5eSBen Skeggs b.full = dfixed_div(b, a); 98668adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 987c93bb85bSJerome Glisse wm1.consumption_rate); 988c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 989c93bb85bSJerome Glisse } else { 99068adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 991c93bb85bSJerome Glisse wm1.consumption_rate); 99268adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 99368adac5eSBen Skeggs priority_mark12.full = dfixed_div(a, b); 994c93bb85bSJerome Glisse } 995c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 996c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 99768adac5eSBen Skeggs if (dfixed_trunc(priority_mark02) < 0) 998c93bb85bSJerome Glisse priority_mark02.full = 0; 999c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1000c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 1001c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1002c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 100368adac5eSBen Skeggs if (dfixed_trunc(priority_mark12) < 0) 1004c93bb85bSJerome Glisse priority_mark12.full = 0; 1005c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1006c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 100768adac5eSBen Skeggs d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 100868adac5eSBen Skeggs d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1009f46c0120SAlex Deucher if (rdev->disp_priority == 2) { 1010f46c0120SAlex Deucher d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1011f46c0120SAlex Deucher d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1012f46c0120SAlex Deucher } 1013c93bb85bSJerome Glisse } else if (mode0) { 101468adac5eSBen Skeggs if (dfixed_trunc(wm0.dbpp) > 64) 101568adac5eSBen Skeggs a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1016c93bb85bSJerome Glisse else 1017c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 101868adac5eSBen Skeggs fill_rate.full = dfixed_div(wm0.sclk, a); 1019c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 1020c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 102168adac5eSBen Skeggs b.full = dfixed_mul(b, wm0.active_time); 102268adac5eSBen Skeggs a.full = dfixed_const(16); 102368adac5eSBen Skeggs b.full = dfixed_div(b, a); 102468adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 1025c93bb85bSJerome Glisse wm0.consumption_rate); 1026c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 1027c93bb85bSJerome Glisse } else { 102868adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 1029c93bb85bSJerome Glisse wm0.consumption_rate); 103068adac5eSBen Skeggs b.full = dfixed_const(16); 103168adac5eSBen Skeggs priority_mark02.full = dfixed_div(a, b); 1032c93bb85bSJerome Glisse } 1033c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 1034c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 103568adac5eSBen Skeggs if (dfixed_trunc(priority_mark02) < 0) 1036c93bb85bSJerome Glisse priority_mark02.full = 0; 1037c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1038c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 103968adac5eSBen Skeggs d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1040f46c0120SAlex Deucher if (rdev->disp_priority == 2) 1041f46c0120SAlex Deucher d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1042e06b14eeSAlex Deucher } else if (mode1) { 104368adac5eSBen Skeggs if (dfixed_trunc(wm1.dbpp) > 64) 104468adac5eSBen Skeggs a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1045c93bb85bSJerome Glisse else 1046c93bb85bSJerome Glisse a.full = wm1.num_line_pair.full; 104768adac5eSBen Skeggs fill_rate.full = dfixed_div(wm1.sclk, a); 1048c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 1049c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 105068adac5eSBen Skeggs b.full = dfixed_mul(b, wm1.active_time); 105168adac5eSBen Skeggs a.full = dfixed_const(16); 105268adac5eSBen Skeggs b.full = dfixed_div(b, a); 105368adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1054c93bb85bSJerome Glisse wm1.consumption_rate); 1055c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 1056c93bb85bSJerome Glisse } else { 105768adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1058c93bb85bSJerome Glisse wm1.consumption_rate); 105968adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 106068adac5eSBen Skeggs priority_mark12.full = dfixed_div(a, b); 1061c93bb85bSJerome Glisse } 1062c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1063c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 106468adac5eSBen Skeggs if (dfixed_trunc(priority_mark12) < 0) 1065c93bb85bSJerome Glisse priority_mark12.full = 0; 1066c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1067c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 106868adac5eSBen Skeggs d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1069f46c0120SAlex Deucher if (rdev->disp_priority == 2) 1070f46c0120SAlex Deucher d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1071e06b14eeSAlex Deucher } 1072e06b14eeSAlex Deucher 1073e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1074e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1075f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1076f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1077c93bb85bSJerome Glisse } 1078c93bb85bSJerome Glisse 1079c93bb85bSJerome Glisse void rv515_bandwidth_update(struct radeon_device *rdev) 1080c93bb85bSJerome Glisse { 1081c93bb85bSJerome Glisse uint32_t tmp; 1082c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1083c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1084c93bb85bSJerome Glisse 1085f46c0120SAlex Deucher radeon_update_display_priority(rdev); 1086f46c0120SAlex Deucher 1087c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1088c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1089c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1090c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1091c93bb85bSJerome Glisse /* 1092c93bb85bSJerome Glisse * Set display0/1 priority up in the memory controller for 1093c93bb85bSJerome Glisse * modes if the user specifies HIGH for displaypriority 1094c93bb85bSJerome Glisse * option. 1095c93bb85bSJerome Glisse */ 1096f46c0120SAlex Deucher if ((rdev->disp_priority == 2) && 1097f46c0120SAlex Deucher (rdev->family == CHIP_RV515)) { 1098c93bb85bSJerome Glisse tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1099c93bb85bSJerome Glisse tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1100c93bb85bSJerome Glisse tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1101c93bb85bSJerome Glisse if (mode1) 1102c93bb85bSJerome Glisse tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1103c93bb85bSJerome Glisse if (mode0) 1104c93bb85bSJerome Glisse tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1105c93bb85bSJerome Glisse WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1106c93bb85bSJerome Glisse } 1107c93bb85bSJerome Glisse rv515_bandwidth_avivo_update(rdev); 1108c93bb85bSJerome Glisse } 1109