1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse #include <linux/seq_file.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 30771fe6b9SJerome Glisse #include "drmP.h" 313ce0a23dSJerome Glisse #include "rv515d.h" 32771fe6b9SJerome Glisse #include "radeon.h" 33d39c3b89SJerome Glisse #include "atom.h" 3450f15303SDave Airlie #include "rv515_reg_safe.h" 35771fe6b9SJerome Glisse 36d39c3b89SJerome Glisse /* This files gather functions specifics to: rv515 */ 37771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 38771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 39771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev); 40771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev); 41771fe6b9SJerome Glisse 42f0ed1f65SJerome Glisse void rv515_debugfs(struct radeon_device *rdev) 43771fe6b9SJerome Glisse { 44771fe6b9SJerome Glisse if (r100_debugfs_rbbm_init(rdev)) { 45771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 46771fe6b9SJerome Glisse } 47771fe6b9SJerome Glisse if (rv515_debugfs_pipes_info_init(rdev)) { 48771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 49771fe6b9SJerome Glisse } 50771fe6b9SJerome Glisse if (rv515_debugfs_ga_info_init(rdev)) { 51771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 52771fe6b9SJerome Glisse } 53771fe6b9SJerome Glisse } 54771fe6b9SJerome Glisse 55771fe6b9SJerome Glisse void rv515_ring_start(struct radeon_device *rdev) 56771fe6b9SJerome Glisse { 57771fe6b9SJerome Glisse int r; 58771fe6b9SJerome Glisse 59771fe6b9SJerome Glisse r = radeon_ring_lock(rdev, 64); 60771fe6b9SJerome Glisse if (r) { 61771fe6b9SJerome Glisse return; 62771fe6b9SJerome Glisse } 63c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); 64771fe6b9SJerome Glisse radeon_ring_write(rdev, 65c93bb85bSJerome Glisse ISYNC_ANY2D_IDLE3D | 66c93bb85bSJerome Glisse ISYNC_ANY3D_IDLE2D | 67c93bb85bSJerome Glisse ISYNC_WAIT_IDLEGUI | 68c93bb85bSJerome Glisse ISYNC_CPSCRATCH_IDLEGUI); 69c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 70c93bb85bSJerome Glisse radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 71771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(0x170C, 0)); 72771fe6b9SJerome Glisse radeon_ring_write(rdev, 1 << 31); 73c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); 74771fe6b9SJerome Glisse radeon_ring_write(rdev, 0); 75c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); 76771fe6b9SJerome Glisse radeon_ring_write(rdev, 0); 77771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(0x42C8, 0)); 78771fe6b9SJerome Glisse radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); 79c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); 80771fe6b9SJerome Glisse radeon_ring_write(rdev, 0); 81c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 82c93bb85bSJerome Glisse radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 83c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 84c93bb85bSJerome Glisse radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 85c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 86c93bb85bSJerome Glisse radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 87c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); 88771fe6b9SJerome Glisse radeon_ring_write(rdev, 0); 89c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 90c93bb85bSJerome Glisse radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 91c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 92c93bb85bSJerome Glisse radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 93c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); 94771fe6b9SJerome Glisse radeon_ring_write(rdev, 95c93bb85bSJerome Glisse ((6 << MS_X0_SHIFT) | 96c93bb85bSJerome Glisse (6 << MS_Y0_SHIFT) | 97c93bb85bSJerome Glisse (6 << MS_X1_SHIFT) | 98c93bb85bSJerome Glisse (6 << MS_Y1_SHIFT) | 99c93bb85bSJerome Glisse (6 << MS_X2_SHIFT) | 100c93bb85bSJerome Glisse (6 << MS_Y2_SHIFT) | 101c93bb85bSJerome Glisse (6 << MSBD0_Y_SHIFT) | 102c93bb85bSJerome Glisse (6 << MSBD0_X_SHIFT))); 103c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); 104771fe6b9SJerome Glisse radeon_ring_write(rdev, 105c93bb85bSJerome Glisse ((6 << MS_X3_SHIFT) | 106c93bb85bSJerome Glisse (6 << MS_Y3_SHIFT) | 107c93bb85bSJerome Glisse (6 << MS_X4_SHIFT) | 108c93bb85bSJerome Glisse (6 << MS_Y4_SHIFT) | 109c93bb85bSJerome Glisse (6 << MS_X5_SHIFT) | 110c93bb85bSJerome Glisse (6 << MS_Y5_SHIFT) | 111c93bb85bSJerome Glisse (6 << MSBD1_SHIFT))); 112c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); 113c93bb85bSJerome Glisse radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 114c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); 115c93bb85bSJerome Glisse radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 116c93bb85bSJerome Glisse radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); 117c93bb85bSJerome Glisse radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 118068a117cSJerome Glisse radeon_ring_write(rdev, PACKET0(0x20C8, 0)); 119068a117cSJerome Glisse radeon_ring_write(rdev, 0); 120771fe6b9SJerome Glisse radeon_ring_unlock_commit(rdev); 121771fe6b9SJerome Glisse } 122771fe6b9SJerome Glisse 123771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev) 124771fe6b9SJerome Glisse { 125771fe6b9SJerome Glisse unsigned i; 126771fe6b9SJerome Glisse uint32_t tmp; 127771fe6b9SJerome Glisse 128771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 129771fe6b9SJerome Glisse /* read MC_STATUS */ 130c93bb85bSJerome Glisse tmp = RREG32_MC(MC_STATUS); 131c93bb85bSJerome Glisse if (tmp & MC_STATUS_IDLE) { 132771fe6b9SJerome Glisse return 0; 133771fe6b9SJerome Glisse } 134771fe6b9SJerome Glisse DRM_UDELAY(1); 135771fe6b9SJerome Glisse } 136771fe6b9SJerome Glisse return -1; 137771fe6b9SJerome Glisse } 138771fe6b9SJerome Glisse 139d39c3b89SJerome Glisse void rv515_vga_render_disable(struct radeon_device *rdev) 140d39c3b89SJerome Glisse { 141d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 142d39c3b89SJerome Glisse RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 143d39c3b89SJerome Glisse } 144d39c3b89SJerome Glisse 145771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev) 146771fe6b9SJerome Glisse { 147771fe6b9SJerome Glisse unsigned pipe_select_current, gb_pipe_select, tmp; 148771fe6b9SJerome Glisse 149771fe6b9SJerome Glisse r100_hdp_reset(rdev); 150771fe6b9SJerome Glisse r100_rb2d_reset(rdev); 151771fe6b9SJerome Glisse 152771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 153771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 154771fe6b9SJerome Glisse "reseting GPU. Bad things might happen.\n"); 155771fe6b9SJerome Glisse } 156771fe6b9SJerome Glisse 157d39c3b89SJerome Glisse rv515_vga_render_disable(rdev); 158771fe6b9SJerome Glisse 159771fe6b9SJerome Glisse r420_pipes_init(rdev); 160771fe6b9SJerome Glisse gb_pipe_select = RREG32(0x402C); 161771fe6b9SJerome Glisse tmp = RREG32(0x170C); 162771fe6b9SJerome Glisse pipe_select_current = (tmp >> 2) & 3; 163771fe6b9SJerome Glisse tmp = (1 << pipe_select_current) | 164771fe6b9SJerome Glisse (((gb_pipe_select >> 8) & 0xF) << 4); 165771fe6b9SJerome Glisse WREG32_PLL(0x000D, tmp); 166771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 167771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 168771fe6b9SJerome Glisse "reseting GPU. Bad things might happen.\n"); 169771fe6b9SJerome Glisse } 170771fe6b9SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) { 171771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait MC idle while " 172771fe6b9SJerome Glisse "programming pipes. Bad things might happen.\n"); 173771fe6b9SJerome Glisse } 174771fe6b9SJerome Glisse } 175771fe6b9SJerome Glisse 176771fe6b9SJerome Glisse int rv515_ga_reset(struct radeon_device *rdev) 177771fe6b9SJerome Glisse { 178771fe6b9SJerome Glisse uint32_t tmp; 179771fe6b9SJerome Glisse bool reinit_cp; 180771fe6b9SJerome Glisse int i; 181771fe6b9SJerome Glisse 182771fe6b9SJerome Glisse reinit_cp = rdev->cp.ready; 183771fe6b9SJerome Glisse rdev->cp.ready = false; 184771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 185c93bb85bSJerome Glisse WREG32(CP_CSQ_MODE, 0); 186c93bb85bSJerome Glisse WREG32(CP_CSQ_CNTL, 0); 187c93bb85bSJerome Glisse WREG32(RBBM_SOFT_RESET, 0x32005); 188c93bb85bSJerome Glisse (void)RREG32(RBBM_SOFT_RESET); 189771fe6b9SJerome Glisse udelay(200); 190c93bb85bSJerome Glisse WREG32(RBBM_SOFT_RESET, 0); 191771fe6b9SJerome Glisse /* Wait to prevent race in RBBM_STATUS */ 192771fe6b9SJerome Glisse mdelay(1); 193c93bb85bSJerome Glisse tmp = RREG32(RBBM_STATUS); 194771fe6b9SJerome Glisse if (tmp & ((1 << 20) | (1 << 26))) { 195771fe6b9SJerome Glisse DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); 196771fe6b9SJerome Glisse /* GA still busy soft reset it */ 197771fe6b9SJerome Glisse WREG32(0x429C, 0x200); 198c93bb85bSJerome Glisse WREG32(VAP_PVS_STATE_FLUSH_REG, 0); 199771fe6b9SJerome Glisse WREG32(0x43E0, 0); 200771fe6b9SJerome Glisse WREG32(0x43E4, 0); 201771fe6b9SJerome Glisse WREG32(0x24AC, 0); 202771fe6b9SJerome Glisse } 203771fe6b9SJerome Glisse /* Wait to prevent race in RBBM_STATUS */ 204771fe6b9SJerome Glisse mdelay(1); 205c93bb85bSJerome Glisse tmp = RREG32(RBBM_STATUS); 206771fe6b9SJerome Glisse if (!(tmp & ((1 << 20) | (1 << 26)))) { 207771fe6b9SJerome Glisse break; 208771fe6b9SJerome Glisse } 209771fe6b9SJerome Glisse } 210771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 211c93bb85bSJerome Glisse tmp = RREG32(RBBM_STATUS); 212771fe6b9SJerome Glisse if (!(tmp & ((1 << 20) | (1 << 26)))) { 213771fe6b9SJerome Glisse DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", 214771fe6b9SJerome Glisse tmp); 215771fe6b9SJerome Glisse DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); 216771fe6b9SJerome Glisse DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); 217771fe6b9SJerome Glisse DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); 218771fe6b9SJerome Glisse if (reinit_cp) { 219771fe6b9SJerome Glisse return r100_cp_init(rdev, rdev->cp.ring_size); 220771fe6b9SJerome Glisse } 221771fe6b9SJerome Glisse return 0; 222771fe6b9SJerome Glisse } 223771fe6b9SJerome Glisse DRM_UDELAY(1); 224771fe6b9SJerome Glisse } 225c93bb85bSJerome Glisse tmp = RREG32(RBBM_STATUS); 226771fe6b9SJerome Glisse DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); 227771fe6b9SJerome Glisse return -1; 228771fe6b9SJerome Glisse } 229771fe6b9SJerome Glisse 230771fe6b9SJerome Glisse int rv515_gpu_reset(struct radeon_device *rdev) 231771fe6b9SJerome Glisse { 232771fe6b9SJerome Glisse uint32_t status; 233771fe6b9SJerome Glisse 234771fe6b9SJerome Glisse /* reset order likely matter */ 235c93bb85bSJerome Glisse status = RREG32(RBBM_STATUS); 236771fe6b9SJerome Glisse /* reset HDP */ 237771fe6b9SJerome Glisse r100_hdp_reset(rdev); 238771fe6b9SJerome Glisse /* reset rb2d */ 239771fe6b9SJerome Glisse if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { 240771fe6b9SJerome Glisse r100_rb2d_reset(rdev); 241771fe6b9SJerome Glisse } 242771fe6b9SJerome Glisse /* reset GA */ 243771fe6b9SJerome Glisse if (status & ((1 << 20) | (1 << 26))) { 244771fe6b9SJerome Glisse rv515_ga_reset(rdev); 245771fe6b9SJerome Glisse } 246771fe6b9SJerome Glisse /* reset CP */ 247c93bb85bSJerome Glisse status = RREG32(RBBM_STATUS); 248771fe6b9SJerome Glisse if (status & (1 << 16)) { 249771fe6b9SJerome Glisse r100_cp_reset(rdev); 250771fe6b9SJerome Glisse } 251771fe6b9SJerome Glisse /* Check if GPU is idle */ 252c93bb85bSJerome Glisse status = RREG32(RBBM_STATUS); 253771fe6b9SJerome Glisse if (status & (1 << 31)) { 254771fe6b9SJerome Glisse DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 255771fe6b9SJerome Glisse return -1; 256771fe6b9SJerome Glisse } 257771fe6b9SJerome Glisse DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); 258771fe6b9SJerome Glisse return 0; 259771fe6b9SJerome Glisse } 260771fe6b9SJerome Glisse 261771fe6b9SJerome Glisse static void rv515_vram_get_type(struct radeon_device *rdev) 262771fe6b9SJerome Glisse { 263771fe6b9SJerome Glisse uint32_t tmp; 264771fe6b9SJerome Glisse 265771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 266771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 267c93bb85bSJerome Glisse tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 268771fe6b9SJerome Glisse switch (tmp) { 269771fe6b9SJerome Glisse case 0: 270771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 271771fe6b9SJerome Glisse break; 272771fe6b9SJerome Glisse case 1: 273771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 274771fe6b9SJerome Glisse break; 275771fe6b9SJerome Glisse default: 276771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 277771fe6b9SJerome Glisse break; 278771fe6b9SJerome Glisse } 279771fe6b9SJerome Glisse } 280771fe6b9SJerome Glisse 281d594e46aSJerome Glisse void rv515_mc_init(struct radeon_device *rdev) 282771fe6b9SJerome Glisse { 283c93bb85bSJerome Glisse fixed20_12 a; 284771fe6b9SJerome Glisse 285c93bb85bSJerome Glisse rv515_vram_get_type(rdev); 2860924d942SDave Airlie r100_vram_init_sizes(rdev); 287d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, 0); 288d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 289d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 290c93bb85bSJerome Glisse /* FIXME: we should enforce default clock in case GPU is not in 291c93bb85bSJerome Glisse * default setup 292c93bb85bSJerome Glisse */ 293c93bb85bSJerome Glisse a.full = rfixed_const(100); 294c93bb85bSJerome Glisse rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 295c93bb85bSJerome Glisse rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 296771fe6b9SJerome Glisse } 297771fe6b9SJerome Glisse 298771fe6b9SJerome Glisse uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 299771fe6b9SJerome Glisse { 300771fe6b9SJerome Glisse uint32_t r; 301771fe6b9SJerome Glisse 302c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 303c93bb85bSJerome Glisse r = RREG32(MC_IND_DATA); 304c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 305771fe6b9SJerome Glisse return r; 306771fe6b9SJerome Glisse } 307771fe6b9SJerome Glisse 308771fe6b9SJerome Glisse void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 309771fe6b9SJerome Glisse { 310c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 311c93bb85bSJerome Glisse WREG32(MC_IND_DATA, (v)); 312c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 313771fe6b9SJerome Glisse } 314771fe6b9SJerome Glisse 315771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 316771fe6b9SJerome Glisse static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 317771fe6b9SJerome Glisse { 318771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 319771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 320771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 321771fe6b9SJerome Glisse uint32_t tmp; 322771fe6b9SJerome Glisse 323c93bb85bSJerome Glisse tmp = RREG32(GB_PIPE_SELECT); 324771fe6b9SJerome Glisse seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 325c93bb85bSJerome Glisse tmp = RREG32(SU_REG_DEST); 326771fe6b9SJerome Glisse seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 327c93bb85bSJerome Glisse tmp = RREG32(GB_TILE_CONFIG); 328771fe6b9SJerome Glisse seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 329c93bb85bSJerome Glisse tmp = RREG32(DST_PIPE_CONFIG); 330771fe6b9SJerome Glisse seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 331771fe6b9SJerome Glisse return 0; 332771fe6b9SJerome Glisse } 333771fe6b9SJerome Glisse 334771fe6b9SJerome Glisse static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 335771fe6b9SJerome Glisse { 336771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 337771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 338771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 339771fe6b9SJerome Glisse uint32_t tmp; 340771fe6b9SJerome Glisse 341771fe6b9SJerome Glisse tmp = RREG32(0x2140); 342771fe6b9SJerome Glisse seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 343771fe6b9SJerome Glisse radeon_gpu_reset(rdev); 344771fe6b9SJerome Glisse tmp = RREG32(0x425C); 345771fe6b9SJerome Glisse seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 346771fe6b9SJerome Glisse return 0; 347771fe6b9SJerome Glisse } 348771fe6b9SJerome Glisse 349771fe6b9SJerome Glisse static struct drm_info_list rv515_pipes_info_list[] = { 350771fe6b9SJerome Glisse {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 351771fe6b9SJerome Glisse }; 352771fe6b9SJerome Glisse 353771fe6b9SJerome Glisse static struct drm_info_list rv515_ga_info_list[] = { 354771fe6b9SJerome Glisse {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 355771fe6b9SJerome Glisse }; 356771fe6b9SJerome Glisse #endif 357771fe6b9SJerome Glisse 358771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 359771fe6b9SJerome Glisse { 360771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 361771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 362771fe6b9SJerome Glisse #else 363771fe6b9SJerome Glisse return 0; 364771fe6b9SJerome Glisse #endif 365771fe6b9SJerome Glisse } 366771fe6b9SJerome Glisse 367771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 368771fe6b9SJerome Glisse { 369771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 370771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 371771fe6b9SJerome Glisse #else 372771fe6b9SJerome Glisse return 0; 373771fe6b9SJerome Glisse #endif 374771fe6b9SJerome Glisse } 375068a117cSJerome Glisse 376d39c3b89SJerome Glisse void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 377d39c3b89SJerome Glisse { 378d39c3b89SJerome Glisse save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); 379d39c3b89SJerome Glisse save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); 380d39c3b89SJerome Glisse save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 381d39c3b89SJerome Glisse save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 382d39c3b89SJerome Glisse save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); 383d39c3b89SJerome Glisse save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 384d39c3b89SJerome Glisse 385d39c3b89SJerome Glisse /* Stop all video */ 386d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 387d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 0); 388d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 389d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 390d39c3b89SJerome Glisse WREG32(R_006080_D1CRTC_CONTROL, 0); 391d39c3b89SJerome Glisse WREG32(R_006880_D2CRTC_CONTROL, 0); 392d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 393d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 394ef630627SDave Airlie WREG32(R_000330_D1VGA_CONTROL, 0); 395ef630627SDave Airlie WREG32(R_000338_D2VGA_CONTROL, 0); 396d39c3b89SJerome Glisse } 397d39c3b89SJerome Glisse 398d39c3b89SJerome Glisse void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 399d39c3b89SJerome Glisse { 400d39c3b89SJerome Glisse WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 401d39c3b89SJerome Glisse WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 402d39c3b89SJerome Glisse WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 403d39c3b89SJerome Glisse WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 404d39c3b89SJerome Glisse WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 405d39c3b89SJerome Glisse /* Unlock host access */ 406d39c3b89SJerome Glisse WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 407d39c3b89SJerome Glisse mdelay(1); 408d39c3b89SJerome Glisse /* Restore video state */ 409ef630627SDave Airlie WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); 410ef630627SDave Airlie WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); 411d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 412d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 413d39c3b89SJerome Glisse WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 414d39c3b89SJerome Glisse WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 415d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 416d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 417d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 418d39c3b89SJerome Glisse } 419d39c3b89SJerome Glisse 420d39c3b89SJerome Glisse void rv515_mc_program(struct radeon_device *rdev) 421d39c3b89SJerome Glisse { 422d39c3b89SJerome Glisse struct rv515_mc_save save; 423d39c3b89SJerome Glisse 424d39c3b89SJerome Glisse /* Stops all mc clients */ 425d39c3b89SJerome Glisse rv515_mc_stop(rdev, &save); 426d39c3b89SJerome Glisse 427d39c3b89SJerome Glisse /* Wait for mc idle */ 428d39c3b89SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) 429d39c3b89SJerome Glisse dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 430d39c3b89SJerome Glisse /* Write VRAM size in case we are limiting it */ 431d39c3b89SJerome Glisse WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 432d39c3b89SJerome Glisse /* Program MC, should be a 32bits limited address space */ 433d39c3b89SJerome Glisse WREG32_MC(R_000001_MC_FB_LOCATION, 434d39c3b89SJerome Glisse S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 435d39c3b89SJerome Glisse S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 436d39c3b89SJerome Glisse WREG32(R_000134_HDP_FB_LOCATION, 437d39c3b89SJerome Glisse S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 438d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 439d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 440d39c3b89SJerome Glisse S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 441d39c3b89SJerome Glisse S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 442d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 443d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 444d39c3b89SJerome Glisse S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 445d39c3b89SJerome Glisse } else { 446d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 447d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, 0); 448d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 449d39c3b89SJerome Glisse } 450d39c3b89SJerome Glisse 451d39c3b89SJerome Glisse rv515_mc_resume(rdev, &save); 452d39c3b89SJerome Glisse } 453d39c3b89SJerome Glisse 454d39c3b89SJerome Glisse void rv515_clock_startup(struct radeon_device *rdev) 455d39c3b89SJerome Glisse { 456d39c3b89SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 457d39c3b89SJerome Glisse radeon_atom_set_clock_gating(rdev, 1); 458d39c3b89SJerome Glisse /* We need to force on some of the block */ 459d39c3b89SJerome Glisse WREG32_PLL(R_00000F_CP_DYN_CNTL, 460d39c3b89SJerome Glisse RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 461d39c3b89SJerome Glisse WREG32_PLL(R_000011_E2_DYN_CNTL, 462d39c3b89SJerome Glisse RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 463d39c3b89SJerome Glisse WREG32_PLL(R_000013_IDCT_DYN_CNTL, 464d39c3b89SJerome Glisse RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 465d39c3b89SJerome Glisse } 466d39c3b89SJerome Glisse 467d39c3b89SJerome Glisse static int rv515_startup(struct radeon_device *rdev) 468d39c3b89SJerome Glisse { 469d39c3b89SJerome Glisse int r; 470d39c3b89SJerome Glisse 471d39c3b89SJerome Glisse rv515_mc_program(rdev); 472d39c3b89SJerome Glisse /* Resume clock */ 473d39c3b89SJerome Glisse rv515_clock_startup(rdev); 474d39c3b89SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 475d39c3b89SJerome Glisse rv515_gpu_init(rdev); 476d39c3b89SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 477d39c3b89SJerome Glisse * memory through TTM but finalize after TTM) */ 478d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) { 479d39c3b89SJerome Glisse r = rv370_pcie_gart_enable(rdev); 480d39c3b89SJerome Glisse if (r) 481d39c3b89SJerome Glisse return r; 482d39c3b89SJerome Glisse } 483d39c3b89SJerome Glisse /* Enable IRQ */ 484ac447df4SJerome Glisse rs600_irq_set(rdev); 485cafe6609SJerome Glisse rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 486d39c3b89SJerome Glisse /* 1M ring buffer */ 487d39c3b89SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 488d39c3b89SJerome Glisse if (r) { 489d39c3b89SJerome Glisse dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 490d39c3b89SJerome Glisse return r; 491d39c3b89SJerome Glisse } 492d39c3b89SJerome Glisse r = r100_wb_init(rdev); 493d39c3b89SJerome Glisse if (r) 494d39c3b89SJerome Glisse dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 495d39c3b89SJerome Glisse r = r100_ib_init(rdev); 496d39c3b89SJerome Glisse if (r) { 497d39c3b89SJerome Glisse dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 498d39c3b89SJerome Glisse return r; 499d39c3b89SJerome Glisse } 500d39c3b89SJerome Glisse return 0; 501d39c3b89SJerome Glisse } 502d39c3b89SJerome Glisse 503d39c3b89SJerome Glisse int rv515_resume(struct radeon_device *rdev) 504d39c3b89SJerome Glisse { 505d39c3b89SJerome Glisse /* Make sur GART are not working */ 506d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 507d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 508d39c3b89SJerome Glisse /* Resume clock before doing reset */ 509d39c3b89SJerome Glisse rv515_clock_startup(rdev); 510d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 511d39c3b89SJerome Glisse if (radeon_gpu_reset(rdev)) { 512d39c3b89SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 513d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 514d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 515d39c3b89SJerome Glisse } 516d39c3b89SJerome Glisse /* post */ 517d39c3b89SJerome Glisse atom_asic_init(rdev->mode_info.atom_context); 518d39c3b89SJerome Glisse /* Resume clock after posting */ 519d39c3b89SJerome Glisse rv515_clock_startup(rdev); 520550e2d92SDave Airlie /* Initialize surface registers */ 521550e2d92SDave Airlie radeon_surface_init(rdev); 522d39c3b89SJerome Glisse return rv515_startup(rdev); 523d39c3b89SJerome Glisse } 524d39c3b89SJerome Glisse 525d39c3b89SJerome Glisse int rv515_suspend(struct radeon_device *rdev) 526d39c3b89SJerome Glisse { 527d39c3b89SJerome Glisse r100_cp_disable(rdev); 528d39c3b89SJerome Glisse r100_wb_disable(rdev); 529ac447df4SJerome Glisse rs600_irq_disable(rdev); 530d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 531d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 532d39c3b89SJerome Glisse return 0; 533d39c3b89SJerome Glisse } 534d39c3b89SJerome Glisse 535d39c3b89SJerome Glisse void rv515_set_safe_registers(struct radeon_device *rdev) 536068a117cSJerome Glisse { 53750f15303SDave Airlie rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 53850f15303SDave Airlie rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 539d39c3b89SJerome Glisse } 540d39c3b89SJerome Glisse 541d39c3b89SJerome Glisse void rv515_fini(struct radeon_device *rdev) 542d39c3b89SJerome Glisse { 543d39c3b89SJerome Glisse r100_cp_fini(rdev); 544d39c3b89SJerome Glisse r100_wb_fini(rdev); 545d39c3b89SJerome Glisse r100_ib_fini(rdev); 546d39c3b89SJerome Glisse radeon_gem_fini(rdev); 547d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 548d39c3b89SJerome Glisse radeon_agp_fini(rdev); 549d39c3b89SJerome Glisse radeon_irq_kms_fini(rdev); 550d39c3b89SJerome Glisse radeon_fence_driver_fini(rdev); 5514c788679SJerome Glisse radeon_bo_fini(rdev); 552d39c3b89SJerome Glisse radeon_atombios_fini(rdev); 553d39c3b89SJerome Glisse kfree(rdev->bios); 554d39c3b89SJerome Glisse rdev->bios = NULL; 555d39c3b89SJerome Glisse } 556d39c3b89SJerome Glisse 557d39c3b89SJerome Glisse int rv515_init(struct radeon_device *rdev) 558d39c3b89SJerome Glisse { 559d39c3b89SJerome Glisse int r; 560d39c3b89SJerome Glisse 561d39c3b89SJerome Glisse /* Initialize scratch registers */ 562d39c3b89SJerome Glisse radeon_scratch_init(rdev); 563d39c3b89SJerome Glisse /* Initialize surface registers */ 564d39c3b89SJerome Glisse radeon_surface_init(rdev); 565d39c3b89SJerome Glisse /* TODO: disable VGA need to use VGA request */ 566d39c3b89SJerome Glisse /* BIOS*/ 567d39c3b89SJerome Glisse if (!radeon_get_bios(rdev)) { 568d39c3b89SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 569d39c3b89SJerome Glisse return -EINVAL; 570d39c3b89SJerome Glisse } 571d39c3b89SJerome Glisse if (rdev->is_atom_bios) { 572d39c3b89SJerome Glisse r = radeon_atombios_init(rdev); 573d39c3b89SJerome Glisse if (r) 574d39c3b89SJerome Glisse return r; 575d39c3b89SJerome Glisse } else { 576d39c3b89SJerome Glisse dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 577d39c3b89SJerome Glisse return -EINVAL; 578d39c3b89SJerome Glisse } 579d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 580d39c3b89SJerome Glisse if (radeon_gpu_reset(rdev)) { 581d39c3b89SJerome Glisse dev_warn(rdev->dev, 582d39c3b89SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 583d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 584d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 585d39c3b89SJerome Glisse } 586d39c3b89SJerome Glisse /* check if cards are posted or not */ 58772542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 58872542d77SDave Airlie return -EINVAL; 589d39c3b89SJerome Glisse /* Initialize clocks */ 590d39c3b89SJerome Glisse radeon_get_clock_info(rdev->ddev); 5917433874eSRafał Miłecki /* Initialize power management */ 5927433874eSRafał Miłecki radeon_pm_init(rdev); 593d594e46aSJerome Glisse /* initialize AGP */ 594d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 595d594e46aSJerome Glisse r = radeon_agp_init(rdev); 596d594e46aSJerome Glisse if (r) { 597d594e46aSJerome Glisse radeon_agp_disable(rdev); 598d594e46aSJerome Glisse } 599d594e46aSJerome Glisse } 600d594e46aSJerome Glisse /* initialize memory controller */ 601d594e46aSJerome Glisse rv515_mc_init(rdev); 602d39c3b89SJerome Glisse rv515_debugfs(rdev); 603d39c3b89SJerome Glisse /* Fence driver */ 604d39c3b89SJerome Glisse r = radeon_fence_driver_init(rdev); 605d39c3b89SJerome Glisse if (r) 606d39c3b89SJerome Glisse return r; 607d39c3b89SJerome Glisse r = radeon_irq_kms_init(rdev); 608d39c3b89SJerome Glisse if (r) 609d39c3b89SJerome Glisse return r; 610d39c3b89SJerome Glisse /* Memory manager */ 6114c788679SJerome Glisse r = radeon_bo_init(rdev); 612d39c3b89SJerome Glisse if (r) 613d39c3b89SJerome Glisse return r; 614d39c3b89SJerome Glisse r = rv370_pcie_gart_init(rdev); 615d39c3b89SJerome Glisse if (r) 616d39c3b89SJerome Glisse return r; 617d39c3b89SJerome Glisse rv515_set_safe_registers(rdev); 618d39c3b89SJerome Glisse rdev->accel_working = true; 619d39c3b89SJerome Glisse r = rv515_startup(rdev); 620d39c3b89SJerome Glisse if (r) { 621d39c3b89SJerome Glisse /* Somethings want wront with the accel init stop accel */ 622d39c3b89SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 623d39c3b89SJerome Glisse r100_cp_fini(rdev); 624d39c3b89SJerome Glisse r100_wb_fini(rdev); 625d39c3b89SJerome Glisse r100_ib_fini(rdev); 626655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 627d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 628d39c3b89SJerome Glisse radeon_agp_fini(rdev); 629d39c3b89SJerome Glisse rdev->accel_working = false; 630d39c3b89SJerome Glisse } 631068a117cSJerome Glisse return 0; 632068a117cSJerome Glisse } 633c93bb85bSJerome Glisse 6344ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 635c93bb85bSJerome Glisse { 6364ce001abSDave Airlie int index_reg = 0x6578 + crtc->crtc_offset; 6374ce001abSDave Airlie int data_reg = 0x657c + crtc->crtc_offset; 638c93bb85bSJerome Glisse 6394ce001abSDave Airlie WREG32(0x659C + crtc->crtc_offset, 0x0); 6404ce001abSDave Airlie WREG32(0x6594 + crtc->crtc_offset, 0x705); 6414ce001abSDave Airlie WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 6424ce001abSDave Airlie WREG32(0x65D8 + crtc->crtc_offset, 0x0); 6434ce001abSDave Airlie WREG32(0x65B0 + crtc->crtc_offset, 0x0); 6444ce001abSDave Airlie WREG32(0x65C0 + crtc->crtc_offset, 0x0); 6454ce001abSDave Airlie WREG32(0x65D4 + crtc->crtc_offset, 0x0); 6464ce001abSDave Airlie WREG32(index_reg, 0x0); 6474ce001abSDave Airlie WREG32(data_reg, 0x841880A8); 6484ce001abSDave Airlie WREG32(index_reg, 0x1); 6494ce001abSDave Airlie WREG32(data_reg, 0x84208680); 6504ce001abSDave Airlie WREG32(index_reg, 0x2); 6514ce001abSDave Airlie WREG32(data_reg, 0xBFF880B0); 6524ce001abSDave Airlie WREG32(index_reg, 0x100); 6534ce001abSDave Airlie WREG32(data_reg, 0x83D88088); 6544ce001abSDave Airlie WREG32(index_reg, 0x101); 6554ce001abSDave Airlie WREG32(data_reg, 0x84608680); 6564ce001abSDave Airlie WREG32(index_reg, 0x102); 6574ce001abSDave Airlie WREG32(data_reg, 0xBFF080D0); 6584ce001abSDave Airlie WREG32(index_reg, 0x200); 6594ce001abSDave Airlie WREG32(data_reg, 0x83988068); 6604ce001abSDave Airlie WREG32(index_reg, 0x201); 6614ce001abSDave Airlie WREG32(data_reg, 0x84A08680); 6624ce001abSDave Airlie WREG32(index_reg, 0x202); 6634ce001abSDave Airlie WREG32(data_reg, 0xBFF080F8); 6644ce001abSDave Airlie WREG32(index_reg, 0x300); 6654ce001abSDave Airlie WREG32(data_reg, 0x83588058); 6664ce001abSDave Airlie WREG32(index_reg, 0x301); 6674ce001abSDave Airlie WREG32(data_reg, 0x84E08660); 6684ce001abSDave Airlie WREG32(index_reg, 0x302); 6694ce001abSDave Airlie WREG32(data_reg, 0xBFF88120); 6704ce001abSDave Airlie WREG32(index_reg, 0x400); 6714ce001abSDave Airlie WREG32(data_reg, 0x83188040); 6724ce001abSDave Airlie WREG32(index_reg, 0x401); 6734ce001abSDave Airlie WREG32(data_reg, 0x85008660); 6744ce001abSDave Airlie WREG32(index_reg, 0x402); 6754ce001abSDave Airlie WREG32(data_reg, 0xBFF88150); 6764ce001abSDave Airlie WREG32(index_reg, 0x500); 6774ce001abSDave Airlie WREG32(data_reg, 0x82D88030); 6784ce001abSDave Airlie WREG32(index_reg, 0x501); 6794ce001abSDave Airlie WREG32(data_reg, 0x85408640); 6804ce001abSDave Airlie WREG32(index_reg, 0x502); 6814ce001abSDave Airlie WREG32(data_reg, 0xBFF88180); 6824ce001abSDave Airlie WREG32(index_reg, 0x600); 6834ce001abSDave Airlie WREG32(data_reg, 0x82A08018); 6844ce001abSDave Airlie WREG32(index_reg, 0x601); 6854ce001abSDave Airlie WREG32(data_reg, 0x85808620); 6864ce001abSDave Airlie WREG32(index_reg, 0x602); 6874ce001abSDave Airlie WREG32(data_reg, 0xBFF081B8); 6884ce001abSDave Airlie WREG32(index_reg, 0x700); 6894ce001abSDave Airlie WREG32(data_reg, 0x82608010); 6904ce001abSDave Airlie WREG32(index_reg, 0x701); 6914ce001abSDave Airlie WREG32(data_reg, 0x85A08600); 6924ce001abSDave Airlie WREG32(index_reg, 0x702); 6934ce001abSDave Airlie WREG32(data_reg, 0x800081F0); 6944ce001abSDave Airlie WREG32(index_reg, 0x800); 6954ce001abSDave Airlie WREG32(data_reg, 0x8228BFF8); 6964ce001abSDave Airlie WREG32(index_reg, 0x801); 6974ce001abSDave Airlie WREG32(data_reg, 0x85E085E0); 6984ce001abSDave Airlie WREG32(index_reg, 0x802); 6994ce001abSDave Airlie WREG32(data_reg, 0xBFF88228); 7004ce001abSDave Airlie WREG32(index_reg, 0x10000); 7014ce001abSDave Airlie WREG32(data_reg, 0x82A8BF00); 7024ce001abSDave Airlie WREG32(index_reg, 0x10001); 7034ce001abSDave Airlie WREG32(data_reg, 0x82A08CC0); 7044ce001abSDave Airlie WREG32(index_reg, 0x10002); 7054ce001abSDave Airlie WREG32(data_reg, 0x8008BEF8); 7064ce001abSDave Airlie WREG32(index_reg, 0x10100); 7074ce001abSDave Airlie WREG32(data_reg, 0x81F0BF28); 7084ce001abSDave Airlie WREG32(index_reg, 0x10101); 7094ce001abSDave Airlie WREG32(data_reg, 0x83608CA0); 7104ce001abSDave Airlie WREG32(index_reg, 0x10102); 7114ce001abSDave Airlie WREG32(data_reg, 0x8018BED0); 7124ce001abSDave Airlie WREG32(index_reg, 0x10200); 7134ce001abSDave Airlie WREG32(data_reg, 0x8148BF38); 7144ce001abSDave Airlie WREG32(index_reg, 0x10201); 7154ce001abSDave Airlie WREG32(data_reg, 0x84408C80); 7164ce001abSDave Airlie WREG32(index_reg, 0x10202); 7174ce001abSDave Airlie WREG32(data_reg, 0x8008BEB8); 7184ce001abSDave Airlie WREG32(index_reg, 0x10300); 7194ce001abSDave Airlie WREG32(data_reg, 0x80B0BF78); 7204ce001abSDave Airlie WREG32(index_reg, 0x10301); 7214ce001abSDave Airlie WREG32(data_reg, 0x85008C20); 7224ce001abSDave Airlie WREG32(index_reg, 0x10302); 7234ce001abSDave Airlie WREG32(data_reg, 0x8020BEA0); 7244ce001abSDave Airlie WREG32(index_reg, 0x10400); 7254ce001abSDave Airlie WREG32(data_reg, 0x8028BF90); 7264ce001abSDave Airlie WREG32(index_reg, 0x10401); 7274ce001abSDave Airlie WREG32(data_reg, 0x85E08BC0); 7284ce001abSDave Airlie WREG32(index_reg, 0x10402); 7294ce001abSDave Airlie WREG32(data_reg, 0x8018BE90); 7304ce001abSDave Airlie WREG32(index_reg, 0x10500); 7314ce001abSDave Airlie WREG32(data_reg, 0xBFB8BFB0); 7324ce001abSDave Airlie WREG32(index_reg, 0x10501); 7334ce001abSDave Airlie WREG32(data_reg, 0x86C08B40); 7344ce001abSDave Airlie WREG32(index_reg, 0x10502); 7354ce001abSDave Airlie WREG32(data_reg, 0x8010BE90); 7364ce001abSDave Airlie WREG32(index_reg, 0x10600); 7374ce001abSDave Airlie WREG32(data_reg, 0xBF58BFC8); 7384ce001abSDave Airlie WREG32(index_reg, 0x10601); 7394ce001abSDave Airlie WREG32(data_reg, 0x87A08AA0); 7404ce001abSDave Airlie WREG32(index_reg, 0x10602); 7414ce001abSDave Airlie WREG32(data_reg, 0x8010BE98); 7424ce001abSDave Airlie WREG32(index_reg, 0x10700); 7434ce001abSDave Airlie WREG32(data_reg, 0xBF10BFF0); 7444ce001abSDave Airlie WREG32(index_reg, 0x10701); 7454ce001abSDave Airlie WREG32(data_reg, 0x886089E0); 7464ce001abSDave Airlie WREG32(index_reg, 0x10702); 7474ce001abSDave Airlie WREG32(data_reg, 0x8018BEB0); 7484ce001abSDave Airlie WREG32(index_reg, 0x10800); 7494ce001abSDave Airlie WREG32(data_reg, 0xBED8BFE8); 7504ce001abSDave Airlie WREG32(index_reg, 0x10801); 7514ce001abSDave Airlie WREG32(data_reg, 0x89408940); 7524ce001abSDave Airlie WREG32(index_reg, 0x10802); 7534ce001abSDave Airlie WREG32(data_reg, 0xBFE8BED8); 7544ce001abSDave Airlie WREG32(index_reg, 0x20000); 7554ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7564ce001abSDave Airlie WREG32(index_reg, 0x20001); 7574ce001abSDave Airlie WREG32(data_reg, 0x90008000); 7584ce001abSDave Airlie WREG32(index_reg, 0x20002); 7594ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7604ce001abSDave Airlie WREG32(index_reg, 0x20003); 7614ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7624ce001abSDave Airlie WREG32(index_reg, 0x20100); 7634ce001abSDave Airlie WREG32(data_reg, 0x80108000); 7644ce001abSDave Airlie WREG32(index_reg, 0x20101); 7654ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF70); 7664ce001abSDave Airlie WREG32(index_reg, 0x20102); 7674ce001abSDave Airlie WREG32(data_reg, 0xBFE880C0); 7684ce001abSDave Airlie WREG32(index_reg, 0x20103); 7694ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7704ce001abSDave Airlie WREG32(index_reg, 0x20200); 7714ce001abSDave Airlie WREG32(data_reg, 0x8018BFF8); 7724ce001abSDave Airlie WREG32(index_reg, 0x20201); 7734ce001abSDave Airlie WREG32(data_reg, 0x8F80BF08); 7744ce001abSDave Airlie WREG32(index_reg, 0x20202); 7754ce001abSDave Airlie WREG32(data_reg, 0xBFD081A0); 7764ce001abSDave Airlie WREG32(index_reg, 0x20203); 7774ce001abSDave Airlie WREG32(data_reg, 0xBFF88000); 7784ce001abSDave Airlie WREG32(index_reg, 0x20300); 7794ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7804ce001abSDave Airlie WREG32(index_reg, 0x20301); 7814ce001abSDave Airlie WREG32(data_reg, 0x8EE0BEC0); 7824ce001abSDave Airlie WREG32(index_reg, 0x20302); 7834ce001abSDave Airlie WREG32(data_reg, 0xBFB082A0); 7844ce001abSDave Airlie WREG32(index_reg, 0x20303); 7854ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7864ce001abSDave Airlie WREG32(index_reg, 0x20400); 7874ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7884ce001abSDave Airlie WREG32(index_reg, 0x20401); 7894ce001abSDave Airlie WREG32(data_reg, 0x8E00BEA0); 7904ce001abSDave Airlie WREG32(index_reg, 0x20402); 7914ce001abSDave Airlie WREG32(data_reg, 0xBF8883C0); 7924ce001abSDave Airlie WREG32(index_reg, 0x20403); 7934ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7944ce001abSDave Airlie WREG32(index_reg, 0x20500); 7954ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7964ce001abSDave Airlie WREG32(index_reg, 0x20501); 7974ce001abSDave Airlie WREG32(data_reg, 0x8D00BE90); 7984ce001abSDave Airlie WREG32(index_reg, 0x20502); 7994ce001abSDave Airlie WREG32(data_reg, 0xBF588500); 8004ce001abSDave Airlie WREG32(index_reg, 0x20503); 8014ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8024ce001abSDave Airlie WREG32(index_reg, 0x20600); 8034ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8044ce001abSDave Airlie WREG32(index_reg, 0x20601); 8054ce001abSDave Airlie WREG32(data_reg, 0x8BC0BE98); 8064ce001abSDave Airlie WREG32(index_reg, 0x20602); 8074ce001abSDave Airlie WREG32(data_reg, 0xBF308660); 8084ce001abSDave Airlie WREG32(index_reg, 0x20603); 8094ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8104ce001abSDave Airlie WREG32(index_reg, 0x20700); 8114ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8124ce001abSDave Airlie WREG32(index_reg, 0x20701); 8134ce001abSDave Airlie WREG32(data_reg, 0x8A80BEB0); 8144ce001abSDave Airlie WREG32(index_reg, 0x20702); 8154ce001abSDave Airlie WREG32(data_reg, 0xBF0087C0); 8164ce001abSDave Airlie WREG32(index_reg, 0x20703); 8174ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8184ce001abSDave Airlie WREG32(index_reg, 0x20800); 8194ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8204ce001abSDave Airlie WREG32(index_reg, 0x20801); 8214ce001abSDave Airlie WREG32(data_reg, 0x8920BED0); 8224ce001abSDave Airlie WREG32(index_reg, 0x20802); 8234ce001abSDave Airlie WREG32(data_reg, 0xBED08920); 8244ce001abSDave Airlie WREG32(index_reg, 0x20803); 8254ce001abSDave Airlie WREG32(data_reg, 0x80008010); 8264ce001abSDave Airlie WREG32(index_reg, 0x30000); 8274ce001abSDave Airlie WREG32(data_reg, 0x90008000); 8284ce001abSDave Airlie WREG32(index_reg, 0x30001); 8294ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8304ce001abSDave Airlie WREG32(index_reg, 0x30100); 8314ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF90); 8324ce001abSDave Airlie WREG32(index_reg, 0x30101); 8334ce001abSDave Airlie WREG32(data_reg, 0xBFF880A0); 8344ce001abSDave Airlie WREG32(index_reg, 0x30200); 8354ce001abSDave Airlie WREG32(data_reg, 0x8F60BF40); 8364ce001abSDave Airlie WREG32(index_reg, 0x30201); 8374ce001abSDave Airlie WREG32(data_reg, 0xBFE88180); 8384ce001abSDave Airlie WREG32(index_reg, 0x30300); 8394ce001abSDave Airlie WREG32(data_reg, 0x8EC0BF00); 8404ce001abSDave Airlie WREG32(index_reg, 0x30301); 8414ce001abSDave Airlie WREG32(data_reg, 0xBFC88280); 8424ce001abSDave Airlie WREG32(index_reg, 0x30400); 8434ce001abSDave Airlie WREG32(data_reg, 0x8DE0BEE0); 8444ce001abSDave Airlie WREG32(index_reg, 0x30401); 8454ce001abSDave Airlie WREG32(data_reg, 0xBFA083A0); 8464ce001abSDave Airlie WREG32(index_reg, 0x30500); 8474ce001abSDave Airlie WREG32(data_reg, 0x8CE0BED0); 8484ce001abSDave Airlie WREG32(index_reg, 0x30501); 8494ce001abSDave Airlie WREG32(data_reg, 0xBF7884E0); 8504ce001abSDave Airlie WREG32(index_reg, 0x30600); 8514ce001abSDave Airlie WREG32(data_reg, 0x8BA0BED8); 8524ce001abSDave Airlie WREG32(index_reg, 0x30601); 8534ce001abSDave Airlie WREG32(data_reg, 0xBF508640); 8544ce001abSDave Airlie WREG32(index_reg, 0x30700); 8554ce001abSDave Airlie WREG32(data_reg, 0x8A60BEE8); 8564ce001abSDave Airlie WREG32(index_reg, 0x30701); 8574ce001abSDave Airlie WREG32(data_reg, 0xBF2087A0); 8584ce001abSDave Airlie WREG32(index_reg, 0x30800); 8594ce001abSDave Airlie WREG32(data_reg, 0x8900BF00); 8604ce001abSDave Airlie WREG32(index_reg, 0x30801); 8614ce001abSDave Airlie WREG32(data_reg, 0xBF008900); 862c93bb85bSJerome Glisse } 863c93bb85bSJerome Glisse 864c93bb85bSJerome Glisse struct rv515_watermark { 865c93bb85bSJerome Glisse u32 lb_request_fifo_depth; 866c93bb85bSJerome Glisse fixed20_12 num_line_pair; 867c93bb85bSJerome Glisse fixed20_12 estimated_width; 868c93bb85bSJerome Glisse fixed20_12 worst_case_latency; 869c93bb85bSJerome Glisse fixed20_12 consumption_rate; 870c93bb85bSJerome Glisse fixed20_12 active_time; 871c93bb85bSJerome Glisse fixed20_12 dbpp; 872c93bb85bSJerome Glisse fixed20_12 priority_mark_max; 873c93bb85bSJerome Glisse fixed20_12 priority_mark; 874c93bb85bSJerome Glisse fixed20_12 sclk; 875c93bb85bSJerome Glisse }; 876c93bb85bSJerome Glisse 877c93bb85bSJerome Glisse void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 878c93bb85bSJerome Glisse struct radeon_crtc *crtc, 879c93bb85bSJerome Glisse struct rv515_watermark *wm) 880c93bb85bSJerome Glisse { 881c93bb85bSJerome Glisse struct drm_display_mode *mode = &crtc->base.mode; 882c93bb85bSJerome Glisse fixed20_12 a, b, c; 883c93bb85bSJerome Glisse fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 884c93bb85bSJerome Glisse fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 885c93bb85bSJerome Glisse 886c93bb85bSJerome Glisse if (!crtc->base.enabled) { 887c93bb85bSJerome Glisse /* FIXME: wouldn't it better to set priority mark to maximum */ 888c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 889c93bb85bSJerome Glisse return; 890c93bb85bSJerome Glisse } 891c93bb85bSJerome Glisse 892c93bb85bSJerome Glisse if (crtc->vsc.full > rfixed_const(2)) 893c93bb85bSJerome Glisse wm->num_line_pair.full = rfixed_const(2); 894c93bb85bSJerome Glisse else 895c93bb85bSJerome Glisse wm->num_line_pair.full = rfixed_const(1); 896c93bb85bSJerome Glisse 897c93bb85bSJerome Glisse b.full = rfixed_const(mode->crtc_hdisplay); 898c93bb85bSJerome Glisse c.full = rfixed_const(256); 89969b3b5e5SAlex Deucher a.full = rfixed_div(b, c); 90069b3b5e5SAlex Deucher request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); 90169b3b5e5SAlex Deucher request_fifo_depth.full = rfixed_ceil(request_fifo_depth); 902c93bb85bSJerome Glisse if (a.full < rfixed_const(4)) { 903c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 904c93bb85bSJerome Glisse } else { 905c93bb85bSJerome Glisse wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); 906c93bb85bSJerome Glisse } 907c93bb85bSJerome Glisse 908c93bb85bSJerome Glisse /* Determine consumption rate 909c93bb85bSJerome Glisse * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 910c93bb85bSJerome Glisse * vtaps = number of vertical taps, 911c93bb85bSJerome Glisse * vsc = vertical scaling ratio, defined as source/destination 912c93bb85bSJerome Glisse * hsc = horizontal scaling ration, defined as source/destination 913c93bb85bSJerome Glisse */ 914c93bb85bSJerome Glisse a.full = rfixed_const(mode->clock); 915c93bb85bSJerome Glisse b.full = rfixed_const(1000); 916c93bb85bSJerome Glisse a.full = rfixed_div(a, b); 917c93bb85bSJerome Glisse pclk.full = rfixed_div(b, a); 918c93bb85bSJerome Glisse if (crtc->rmx_type != RMX_OFF) { 919c93bb85bSJerome Glisse b.full = rfixed_const(2); 920c93bb85bSJerome Glisse if (crtc->vsc.full > b.full) 921c93bb85bSJerome Glisse b.full = crtc->vsc.full; 922c93bb85bSJerome Glisse b.full = rfixed_mul(b, crtc->hsc); 923c93bb85bSJerome Glisse c.full = rfixed_const(2); 924c93bb85bSJerome Glisse b.full = rfixed_div(b, c); 925c93bb85bSJerome Glisse consumption_time.full = rfixed_div(pclk, b); 926c93bb85bSJerome Glisse } else { 927c93bb85bSJerome Glisse consumption_time.full = pclk.full; 928c93bb85bSJerome Glisse } 929c93bb85bSJerome Glisse a.full = rfixed_const(1); 930c93bb85bSJerome Glisse wm->consumption_rate.full = rfixed_div(a, consumption_time); 931c93bb85bSJerome Glisse 932c93bb85bSJerome Glisse 933c93bb85bSJerome Glisse /* Determine line time 934c93bb85bSJerome Glisse * LineTime = total time for one line of displayhtotal 935c93bb85bSJerome Glisse * LineTime = total number of horizontal pixels 936c93bb85bSJerome Glisse * pclk = pixel clock period(ns) 937c93bb85bSJerome Glisse */ 938c93bb85bSJerome Glisse a.full = rfixed_const(crtc->base.mode.crtc_htotal); 939c93bb85bSJerome Glisse line_time.full = rfixed_mul(a, pclk); 940c93bb85bSJerome Glisse 941c93bb85bSJerome Glisse /* Determine active time 942c93bb85bSJerome Glisse * ActiveTime = time of active region of display within one line, 943c93bb85bSJerome Glisse * hactive = total number of horizontal active pixels 944c93bb85bSJerome Glisse * htotal = total number of horizontal pixels 945c93bb85bSJerome Glisse */ 946c93bb85bSJerome Glisse a.full = rfixed_const(crtc->base.mode.crtc_htotal); 947c93bb85bSJerome Glisse b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 948c93bb85bSJerome Glisse wm->active_time.full = rfixed_mul(line_time, b); 949c93bb85bSJerome Glisse wm->active_time.full = rfixed_div(wm->active_time, a); 950c93bb85bSJerome Glisse 951c93bb85bSJerome Glisse /* Determine chunk time 952c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk of data 953c93bb85bSJerome Glisse * to the LB which consists of pipeline delay and inter chunk gap 954c93bb85bSJerome Glisse * sclk = system clock(Mhz) 955c93bb85bSJerome Glisse */ 956c93bb85bSJerome Glisse a.full = rfixed_const(600 * 1000); 957c93bb85bSJerome Glisse chunk_time.full = rfixed_div(a, rdev->pm.sclk); 958c93bb85bSJerome Glisse read_delay_latency.full = rfixed_const(1000); 959c93bb85bSJerome Glisse 960c93bb85bSJerome Glisse /* Determine the worst case latency 961c93bb85bSJerome Glisse * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 962c93bb85bSJerome Glisse * WorstCaseLatency = worst case time from urgent to when the MC starts 963c93bb85bSJerome Glisse * to return data 964c93bb85bSJerome Glisse * READ_DELAY_IDLE_MAX = constant of 1us 965c93bb85bSJerome Glisse * ChunkTime = time it takes the DCP to send one chunk of data to the LB 966c93bb85bSJerome Glisse * which consists of pipeline delay and inter chunk gap 967c93bb85bSJerome Glisse */ 968c93bb85bSJerome Glisse if (rfixed_trunc(wm->num_line_pair) > 1) { 969c93bb85bSJerome Glisse a.full = rfixed_const(3); 970c93bb85bSJerome Glisse wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 971c93bb85bSJerome Glisse wm->worst_case_latency.full += read_delay_latency.full; 972c93bb85bSJerome Glisse } else { 973c93bb85bSJerome Glisse wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 974c93bb85bSJerome Glisse } 975c93bb85bSJerome Glisse 976c93bb85bSJerome Glisse /* Determine the tolerable latency 977c93bb85bSJerome Glisse * TolerableLatency = Any given request has only 1 line time 978c93bb85bSJerome Glisse * for the data to be returned 979c93bb85bSJerome Glisse * LBRequestFifoDepth = Number of chunk requests the LB can 980c93bb85bSJerome Glisse * put into the request FIFO for a display 981c93bb85bSJerome Glisse * LineTime = total time for one line of display 982c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk 983c93bb85bSJerome Glisse * of data to the LB which consists of 984c93bb85bSJerome Glisse * pipeline delay and inter chunk gap 985c93bb85bSJerome Glisse */ 986c93bb85bSJerome Glisse if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { 987c93bb85bSJerome Glisse tolerable_latency.full = line_time.full; 988c93bb85bSJerome Glisse } else { 989c93bb85bSJerome Glisse tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); 990c93bb85bSJerome Glisse tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 991c93bb85bSJerome Glisse tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); 992c93bb85bSJerome Glisse tolerable_latency.full = line_time.full - tolerable_latency.full; 993c93bb85bSJerome Glisse } 994c93bb85bSJerome Glisse /* We assume worst case 32bits (4 bytes) */ 995c93bb85bSJerome Glisse wm->dbpp.full = rfixed_const(2 * 16); 996c93bb85bSJerome Glisse 997c93bb85bSJerome Glisse /* Determine the maximum priority mark 998c93bb85bSJerome Glisse * width = viewport width in pixels 999c93bb85bSJerome Glisse */ 1000c93bb85bSJerome Glisse a.full = rfixed_const(16); 1001c93bb85bSJerome Glisse wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 1002c93bb85bSJerome Glisse wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); 100369b3b5e5SAlex Deucher wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); 1004c93bb85bSJerome Glisse 1005c93bb85bSJerome Glisse /* Determine estimated width */ 1006c93bb85bSJerome Glisse estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1007c93bb85bSJerome Glisse estimated_width.full = rfixed_div(estimated_width, consumption_time); 1008c93bb85bSJerome Glisse if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 100969b3b5e5SAlex Deucher wm->priority_mark.full = wm->priority_mark_max.full; 1010c93bb85bSJerome Glisse } else { 1011c93bb85bSJerome Glisse a.full = rfixed_const(16); 1012c93bb85bSJerome Glisse wm->priority_mark.full = rfixed_div(estimated_width, a); 101369b3b5e5SAlex Deucher wm->priority_mark.full = rfixed_ceil(wm->priority_mark); 1014c93bb85bSJerome Glisse wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1015c93bb85bSJerome Glisse } 1016c93bb85bSJerome Glisse } 1017c93bb85bSJerome Glisse 1018c93bb85bSJerome Glisse void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1019c93bb85bSJerome Glisse { 1020c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1021c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1022c93bb85bSJerome Glisse struct rv515_watermark wm0; 1023c93bb85bSJerome Glisse struct rv515_watermark wm1; 1024c93bb85bSJerome Glisse u32 tmp; 1025c93bb85bSJerome Glisse fixed20_12 priority_mark02, priority_mark12, fill_rate; 1026c93bb85bSJerome Glisse fixed20_12 a, b; 1027c93bb85bSJerome Glisse 1028c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1029c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1030c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1031c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1032c93bb85bSJerome Glisse rs690_line_buffer_adjust(rdev, mode0, mode1); 1033c93bb85bSJerome Glisse 1034c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 1035c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 1036c93bb85bSJerome Glisse 1037c93bb85bSJerome Glisse tmp = wm0.lb_request_fifo_depth; 1038c93bb85bSJerome Glisse tmp |= wm1.lb_request_fifo_depth << 16; 1039c93bb85bSJerome Glisse WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1040c93bb85bSJerome Glisse 1041c93bb85bSJerome Glisse if (mode0 && mode1) { 1042c93bb85bSJerome Glisse if (rfixed_trunc(wm0.dbpp) > 64) 1043c93bb85bSJerome Glisse a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); 1044c93bb85bSJerome Glisse else 1045c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 1046c93bb85bSJerome Glisse if (rfixed_trunc(wm1.dbpp) > 64) 1047c93bb85bSJerome Glisse b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); 1048c93bb85bSJerome Glisse else 1049c93bb85bSJerome Glisse b.full = wm1.num_line_pair.full; 1050c93bb85bSJerome Glisse a.full += b.full; 1051c93bb85bSJerome Glisse fill_rate.full = rfixed_div(wm0.sclk, a); 1052c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 1053c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 1054c93bb85bSJerome Glisse b.full = rfixed_mul(b, wm0.active_time); 1055c93bb85bSJerome Glisse a.full = rfixed_const(16); 1056c93bb85bSJerome Glisse b.full = rfixed_div(b, a); 1057c93bb85bSJerome Glisse a.full = rfixed_mul(wm0.worst_case_latency, 1058c93bb85bSJerome Glisse wm0.consumption_rate); 1059c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 1060c93bb85bSJerome Glisse } else { 1061c93bb85bSJerome Glisse a.full = rfixed_mul(wm0.worst_case_latency, 1062c93bb85bSJerome Glisse wm0.consumption_rate); 1063c93bb85bSJerome Glisse b.full = rfixed_const(16 * 1000); 1064c93bb85bSJerome Glisse priority_mark02.full = rfixed_div(a, b); 1065c93bb85bSJerome Glisse } 1066c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 1067c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 1068c93bb85bSJerome Glisse b.full = rfixed_mul(b, wm1.active_time); 1069c93bb85bSJerome Glisse a.full = rfixed_const(16); 1070c93bb85bSJerome Glisse b.full = rfixed_div(b, a); 1071c93bb85bSJerome Glisse a.full = rfixed_mul(wm1.worst_case_latency, 1072c93bb85bSJerome Glisse wm1.consumption_rate); 1073c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 1074c93bb85bSJerome Glisse } else { 1075c93bb85bSJerome Glisse a.full = rfixed_mul(wm1.worst_case_latency, 1076c93bb85bSJerome Glisse wm1.consumption_rate); 1077c93bb85bSJerome Glisse b.full = rfixed_const(16 * 1000); 1078c93bb85bSJerome Glisse priority_mark12.full = rfixed_div(a, b); 1079c93bb85bSJerome Glisse } 1080c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 1081c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 1082c93bb85bSJerome Glisse if (rfixed_trunc(priority_mark02) < 0) 1083c93bb85bSJerome Glisse priority_mark02.full = 0; 1084c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1085c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 1086c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1087c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 1088c93bb85bSJerome Glisse if (rfixed_trunc(priority_mark12) < 0) 1089c93bb85bSJerome Glisse priority_mark12.full = 0; 1090c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1091c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 1092c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 1093c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 1094c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 1095c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 1096c93bb85bSJerome Glisse } else if (mode0) { 1097c93bb85bSJerome Glisse if (rfixed_trunc(wm0.dbpp) > 64) 1098c93bb85bSJerome Glisse a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); 1099c93bb85bSJerome Glisse else 1100c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 1101c93bb85bSJerome Glisse fill_rate.full = rfixed_div(wm0.sclk, a); 1102c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 1103c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 1104c93bb85bSJerome Glisse b.full = rfixed_mul(b, wm0.active_time); 1105c93bb85bSJerome Glisse a.full = rfixed_const(16); 1106c93bb85bSJerome Glisse b.full = rfixed_div(b, a); 1107c93bb85bSJerome Glisse a.full = rfixed_mul(wm0.worst_case_latency, 1108c93bb85bSJerome Glisse wm0.consumption_rate); 1109c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 1110c93bb85bSJerome Glisse } else { 1111c93bb85bSJerome Glisse a.full = rfixed_mul(wm0.worst_case_latency, 1112c93bb85bSJerome Glisse wm0.consumption_rate); 1113c93bb85bSJerome Glisse b.full = rfixed_const(16); 1114c93bb85bSJerome Glisse priority_mark02.full = rfixed_div(a, b); 1115c93bb85bSJerome Glisse } 1116c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 1117c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 1118c93bb85bSJerome Glisse if (rfixed_trunc(priority_mark02) < 0) 1119c93bb85bSJerome Glisse priority_mark02.full = 0; 1120c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1121c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 1122c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 1123c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 1124c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1125c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1126c93bb85bSJerome Glisse } else { 1127c93bb85bSJerome Glisse if (rfixed_trunc(wm1.dbpp) > 64) 1128c93bb85bSJerome Glisse a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); 1129c93bb85bSJerome Glisse else 1130c93bb85bSJerome Glisse a.full = wm1.num_line_pair.full; 1131c93bb85bSJerome Glisse fill_rate.full = rfixed_div(wm1.sclk, a); 1132c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 1133c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 1134c93bb85bSJerome Glisse b.full = rfixed_mul(b, wm1.active_time); 1135c93bb85bSJerome Glisse a.full = rfixed_const(16); 1136c93bb85bSJerome Glisse b.full = rfixed_div(b, a); 1137c93bb85bSJerome Glisse a.full = rfixed_mul(wm1.worst_case_latency, 1138c93bb85bSJerome Glisse wm1.consumption_rate); 1139c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 1140c93bb85bSJerome Glisse } else { 1141c93bb85bSJerome Glisse a.full = rfixed_mul(wm1.worst_case_latency, 1142c93bb85bSJerome Glisse wm1.consumption_rate); 1143c93bb85bSJerome Glisse b.full = rfixed_const(16 * 1000); 1144c93bb85bSJerome Glisse priority_mark12.full = rfixed_div(a, b); 1145c93bb85bSJerome Glisse } 1146c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1147c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 1148c93bb85bSJerome Glisse if (rfixed_trunc(priority_mark12) < 0) 1149c93bb85bSJerome Glisse priority_mark12.full = 0; 1150c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1151c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 1152c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1153c93bb85bSJerome Glisse WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1154c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 1155c93bb85bSJerome Glisse WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 1156c93bb85bSJerome Glisse } 1157c93bb85bSJerome Glisse } 1158c93bb85bSJerome Glisse 1159c93bb85bSJerome Glisse void rv515_bandwidth_update(struct radeon_device *rdev) 1160c93bb85bSJerome Glisse { 1161c93bb85bSJerome Glisse uint32_t tmp; 1162c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1163c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1164c93bb85bSJerome Glisse 1165c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1166c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1167c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1168c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1169c93bb85bSJerome Glisse /* 1170c93bb85bSJerome Glisse * Set display0/1 priority up in the memory controller for 1171c93bb85bSJerome Glisse * modes if the user specifies HIGH for displaypriority 1172c93bb85bSJerome Glisse * option. 1173c93bb85bSJerome Glisse */ 1174c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 1175c93bb85bSJerome Glisse tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1176c93bb85bSJerome Glisse tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1177c93bb85bSJerome Glisse tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1178c93bb85bSJerome Glisse if (mode1) 1179c93bb85bSJerome Glisse tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1180c93bb85bSJerome Glisse if (mode0) 1181c93bb85bSJerome Glisse tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1182c93bb85bSJerome Glisse WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1183c93bb85bSJerome Glisse } 1184c93bb85bSJerome Glisse rv515_bandwidth_avivo_update(rdev); 1185c93bb85bSJerome Glisse } 1186