1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28c182615fSSam Ravnborg 29771fe6b9SJerome Glisse #include <linux/seq_file.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 31c182615fSSam Ravnborg 32c182615fSSam Ravnborg #include <drm/drm_device.h> 33c182615fSSam Ravnborg #include <drm/drm_file.h> 34c182615fSSam Ravnborg 35c182615fSSam Ravnborg #include "atom.h" 36771fe6b9SJerome Glisse #include "radeon.h" 37e6990375SDaniel Vetter #include "radeon_asic.h" 3850f15303SDave Airlie #include "rv515_reg_safe.h" 39c182615fSSam Ravnborg #include "rv515d.h" 40771fe6b9SJerome Glisse 41d39c3b89SJerome Glisse /* This files gather functions specifics to: rv515 */ 421109ca09SLauri Kasanen static void rv515_gpu_init(struct radeon_device *rdev); 43771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev); 44771fe6b9SJerome Glisse 456253e4c7SAlex Deucher static const u32 crtc_offsets[2] = 466253e4c7SAlex Deucher { 476253e4c7SAlex Deucher 0, 486253e4c7SAlex Deucher AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 496253e4c7SAlex Deucher }; 506253e4c7SAlex Deucher 51f712812eSAlex Deucher void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 52771fe6b9SJerome Glisse { 53771fe6b9SJerome Glisse int r; 54771fe6b9SJerome Glisse 55e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 64); 56771fe6b9SJerome Glisse if (r) { 57771fe6b9SJerome Glisse return; 58771fe6b9SJerome Glisse } 59e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 60e32eb50dSChristian König radeon_ring_write(ring, 61c93bb85bSJerome Glisse ISYNC_ANY2D_IDLE3D | 62c93bb85bSJerome Glisse ISYNC_ANY3D_IDLE2D | 63c93bb85bSJerome Glisse ISYNC_WAIT_IDLEGUI | 64c93bb85bSJerome Glisse ISYNC_CPSCRATCH_IDLEGUI); 65e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 66e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 67e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 68e32eb50dSChristian König radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 69e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 70e32eb50dSChristian König radeon_ring_write(ring, 0); 71e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 72e32eb50dSChristian König radeon_ring_write(ring, 0); 73e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 74e32eb50dSChristian König radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 75e32eb50dSChristian König radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 76e32eb50dSChristian König radeon_ring_write(ring, 0); 77e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 78e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 79e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 80e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 81e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 82e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 83e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 84e32eb50dSChristian König radeon_ring_write(ring, 0); 85e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 86e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 87e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 88e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 89e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 90e32eb50dSChristian König radeon_ring_write(ring, 91c93bb85bSJerome Glisse ((6 << MS_X0_SHIFT) | 92c93bb85bSJerome Glisse (6 << MS_Y0_SHIFT) | 93c93bb85bSJerome Glisse (6 << MS_X1_SHIFT) | 94c93bb85bSJerome Glisse (6 << MS_Y1_SHIFT) | 95c93bb85bSJerome Glisse (6 << MS_X2_SHIFT) | 96c93bb85bSJerome Glisse (6 << MS_Y2_SHIFT) | 97c93bb85bSJerome Glisse (6 << MSBD0_Y_SHIFT) | 98c93bb85bSJerome Glisse (6 << MSBD0_X_SHIFT))); 99e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 100e32eb50dSChristian König radeon_ring_write(ring, 101c93bb85bSJerome Glisse ((6 << MS_X3_SHIFT) | 102c93bb85bSJerome Glisse (6 << MS_Y3_SHIFT) | 103c93bb85bSJerome Glisse (6 << MS_X4_SHIFT) | 104c93bb85bSJerome Glisse (6 << MS_Y4_SHIFT) | 105c93bb85bSJerome Glisse (6 << MS_X5_SHIFT) | 106c93bb85bSJerome Glisse (6 << MS_Y5_SHIFT) | 107c93bb85bSJerome Glisse (6 << MSBD1_SHIFT))); 108e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 109e32eb50dSChristian König radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 110e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 111e32eb50dSChristian König radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 112e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 113e32eb50dSChristian König radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 114e32eb50dSChristian König radeon_ring_write(ring, PACKET0(0x20C8, 0)); 115e32eb50dSChristian König radeon_ring_write(ring, 0); 1161538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 117771fe6b9SJerome Glisse } 118771fe6b9SJerome Glisse 119771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev) 120771fe6b9SJerome Glisse { 121771fe6b9SJerome Glisse unsigned i; 122771fe6b9SJerome Glisse uint32_t tmp; 123771fe6b9SJerome Glisse 124771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 125771fe6b9SJerome Glisse /* read MC_STATUS */ 126c93bb85bSJerome Glisse tmp = RREG32_MC(MC_STATUS); 127c93bb85bSJerome Glisse if (tmp & MC_STATUS_IDLE) { 128771fe6b9SJerome Glisse return 0; 129771fe6b9SJerome Glisse } 1300e1a351dSSam Ravnborg udelay(1); 131771fe6b9SJerome Glisse } 132771fe6b9SJerome Glisse return -1; 133771fe6b9SJerome Glisse } 134771fe6b9SJerome Glisse 135d39c3b89SJerome Glisse void rv515_vga_render_disable(struct radeon_device *rdev) 136d39c3b89SJerome Glisse { 137d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 138d39c3b89SJerome Glisse RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 139d39c3b89SJerome Glisse } 140d39c3b89SJerome Glisse 1411109ca09SLauri Kasanen static void rv515_gpu_init(struct radeon_device *rdev) 142771fe6b9SJerome Glisse { 143771fe6b9SJerome Glisse unsigned pipe_select_current, gb_pipe_select, tmp; 144771fe6b9SJerome Glisse 145771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 1467ca85295SJoe Perches pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 147771fe6b9SJerome Glisse } 148d39c3b89SJerome Glisse rv515_vga_render_disable(rdev); 149771fe6b9SJerome Glisse r420_pipes_init(rdev); 150d75ee3beSAlex Deucher gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 151d75ee3beSAlex Deucher tmp = RREG32(R300_DST_PIPE_CONFIG); 152771fe6b9SJerome Glisse pipe_select_current = (tmp >> 2) & 3; 153771fe6b9SJerome Glisse tmp = (1 << pipe_select_current) | 154771fe6b9SJerome Glisse (((gb_pipe_select >> 8) & 0xF) << 4); 155771fe6b9SJerome Glisse WREG32_PLL(0x000D, tmp); 156771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 1577ca85295SJoe Perches pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 158771fe6b9SJerome Glisse } 159771fe6b9SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) { 1607ca85295SJoe Perches pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 161771fe6b9SJerome Glisse } 162771fe6b9SJerome Glisse } 163771fe6b9SJerome Glisse 164771fe6b9SJerome Glisse static void rv515_vram_get_type(struct radeon_device *rdev) 165771fe6b9SJerome Glisse { 166771fe6b9SJerome Glisse uint32_t tmp; 167771fe6b9SJerome Glisse 168771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 169771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 170c93bb85bSJerome Glisse tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 171771fe6b9SJerome Glisse switch (tmp) { 172771fe6b9SJerome Glisse case 0: 173771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 174771fe6b9SJerome Glisse break; 175771fe6b9SJerome Glisse case 1: 176771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 177771fe6b9SJerome Glisse break; 178771fe6b9SJerome Glisse default: 179771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 180771fe6b9SJerome Glisse break; 181771fe6b9SJerome Glisse } 182771fe6b9SJerome Glisse } 183771fe6b9SJerome Glisse 1841109ca09SLauri Kasanen static void rv515_mc_init(struct radeon_device *rdev) 185771fe6b9SJerome Glisse { 186771fe6b9SJerome Glisse 187c93bb85bSJerome Glisse rv515_vram_get_type(rdev); 1880924d942SDave Airlie r100_vram_init_sizes(rdev); 189d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, 0); 1908d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 191d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 192d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 193f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 194771fe6b9SJerome Glisse } 195771fe6b9SJerome Glisse 196771fe6b9SJerome Glisse uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 197771fe6b9SJerome Glisse { 1980a5b7b0bSAlex Deucher unsigned long flags; 199771fe6b9SJerome Glisse uint32_t r; 200771fe6b9SJerome Glisse 2010a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->mc_idx_lock, flags); 202c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 203c93bb85bSJerome Glisse r = RREG32(MC_IND_DATA); 204c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 2050a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 2060a5b7b0bSAlex Deucher 207771fe6b9SJerome Glisse return r; 208771fe6b9SJerome Glisse } 209771fe6b9SJerome Glisse 210771fe6b9SJerome Glisse void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 211771fe6b9SJerome Glisse { 2120a5b7b0bSAlex Deucher unsigned long flags; 2130a5b7b0bSAlex Deucher 2140a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->mc_idx_lock, flags); 215c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 216c93bb85bSJerome Glisse WREG32(MC_IND_DATA, (v)); 217c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 2180a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 219771fe6b9SJerome Glisse } 220771fe6b9SJerome Glisse 221771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2225b54d679SNirmoy Das static int rv515_debugfs_pipes_info_show(struct seq_file *m, void *unused) 223771fe6b9SJerome Glisse { 2245b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 225771fe6b9SJerome Glisse uint32_t tmp; 226771fe6b9SJerome Glisse 227c93bb85bSJerome Glisse tmp = RREG32(GB_PIPE_SELECT); 228771fe6b9SJerome Glisse seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 229c93bb85bSJerome Glisse tmp = RREG32(SU_REG_DEST); 230771fe6b9SJerome Glisse seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 231c93bb85bSJerome Glisse tmp = RREG32(GB_TILE_CONFIG); 232771fe6b9SJerome Glisse seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 233c93bb85bSJerome Glisse tmp = RREG32(DST_PIPE_CONFIG); 234771fe6b9SJerome Glisse seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 235771fe6b9SJerome Glisse return 0; 236771fe6b9SJerome Glisse } 237771fe6b9SJerome Glisse 2385b54d679SNirmoy Das static int rv515_debugfs_ga_info_show(struct seq_file *m, void *unused) 239771fe6b9SJerome Glisse { 2405b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 241771fe6b9SJerome Glisse uint32_t tmp; 242771fe6b9SJerome Glisse 243771fe6b9SJerome Glisse tmp = RREG32(0x2140); 244771fe6b9SJerome Glisse seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 245a2d07b74SJerome Glisse radeon_asic_reset(rdev); 246771fe6b9SJerome Glisse tmp = RREG32(0x425C); 247771fe6b9SJerome Glisse seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 248771fe6b9SJerome Glisse return 0; 249771fe6b9SJerome Glisse } 250771fe6b9SJerome Glisse 2515b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_pipes_info); 2525b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_ga_info); 253771fe6b9SJerome Glisse #endif 254771fe6b9SJerome Glisse 2555b54d679SNirmoy Das void rv515_debugfs(struct radeon_device *rdev) 256771fe6b9SJerome Glisse { 257771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2585b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 259771fe6b9SJerome Glisse 2605b54d679SNirmoy Das debugfs_create_file("rv515_pipes_info", 0444, root, rdev, 2615b54d679SNirmoy Das &rv515_debugfs_pipes_info_fops); 2625b54d679SNirmoy Das debugfs_create_file("rv515_ga_info", 0444, root, rdev, 2635b54d679SNirmoy Das &rv515_debugfs_ga_info_fops); 264771fe6b9SJerome Glisse #endif 2655b54d679SNirmoy Das r100_debugfs_rbbm_init(rdev); 266771fe6b9SJerome Glisse } 267068a117cSJerome Glisse 268d39c3b89SJerome Glisse void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 269d39c3b89SJerome Glisse { 2706253e4c7SAlex Deucher u32 crtc_enabled, tmp, frame_count, blackout; 2716253e4c7SAlex Deucher int i, j; 2726253e4c7SAlex Deucher 273d39c3b89SJerome Glisse save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 274d39c3b89SJerome Glisse save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 275d39c3b89SJerome Glisse 2766253e4c7SAlex Deucher /* disable VGA render */ 277d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 0); 2786253e4c7SAlex Deucher /* blank the display controllers */ 2796253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 2806253e4c7SAlex Deucher crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 2816253e4c7SAlex Deucher if (crtc_enabled) { 2826253e4c7SAlex Deucher save->crtc_enabled[i] = true; 2836253e4c7SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 2846253e4c7SAlex Deucher if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 2856253e4c7SAlex Deucher radeon_wait_for_vblank(rdev, i); 286e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2876253e4c7SAlex Deucher tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 2886253e4c7SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 289e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 2906253e4c7SAlex Deucher } 2916253e4c7SAlex Deucher /* wait for the next frame */ 2926253e4c7SAlex Deucher frame_count = radeon_get_vblank_counter(rdev, i); 2936253e4c7SAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 2946253e4c7SAlex Deucher if (radeon_get_vblank_counter(rdev, i) != frame_count) 2956253e4c7SAlex Deucher break; 2966253e4c7SAlex Deucher udelay(1); 2976253e4c7SAlex Deucher } 298e884fc64SAlex Deucher 299e884fc64SAlex Deucher /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 300e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 301e884fc64SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 302e884fc64SAlex Deucher tmp &= ~AVIVO_CRTC_EN; 303e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 304e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 305e884fc64SAlex Deucher save->crtc_enabled[i] = false; 306e884fc64SAlex Deucher /* ***** */ 3076253e4c7SAlex Deucher } else { 3086253e4c7SAlex Deucher save->crtc_enabled[i] = false; 3096253e4c7SAlex Deucher } 3106253e4c7SAlex Deucher } 3116253e4c7SAlex Deucher 3126253e4c7SAlex Deucher radeon_mc_wait_for_idle(rdev); 3136253e4c7SAlex Deucher 3146253e4c7SAlex Deucher if (rdev->family >= CHIP_R600) { 3156253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 3166253e4c7SAlex Deucher blackout = RREG32(R700_MC_CITF_CNTL); 3176253e4c7SAlex Deucher else 3186253e4c7SAlex Deucher blackout = RREG32(R600_CITF_CNTL); 3196253e4c7SAlex Deucher if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 3206253e4c7SAlex Deucher /* Block CPU access */ 3216253e4c7SAlex Deucher WREG32(R600_BIF_FB_EN, 0); 3226253e4c7SAlex Deucher /* blackout the MC */ 3236253e4c7SAlex Deucher blackout |= R600_BLACKOUT_MASK; 3246253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 3256253e4c7SAlex Deucher WREG32(R700_MC_CITF_CNTL, blackout); 3266253e4c7SAlex Deucher else 3276253e4c7SAlex Deucher WREG32(R600_CITF_CNTL, blackout); 3286253e4c7SAlex Deucher } 3296253e4c7SAlex Deucher } 33039dc9aabSAlex Deucher /* wait for the MC to settle */ 33139dc9aabSAlex Deucher udelay(100); 3322f86e2edSAlex Deucher 3332f86e2edSAlex Deucher /* lock double buffered regs */ 3342f86e2edSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3352f86e2edSAlex Deucher if (save->crtc_enabled[i]) { 3362f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 3372f86e2edSAlex Deucher if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 3382f86e2edSAlex Deucher tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 3392f86e2edSAlex Deucher WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 3402f86e2edSAlex Deucher } 3412f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 3422f86e2edSAlex Deucher if (!(tmp & 1)) { 3432f86e2edSAlex Deucher tmp |= 1; 3442f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 3452f86e2edSAlex Deucher } 3462f86e2edSAlex Deucher } 3472f86e2edSAlex Deucher } 348d39c3b89SJerome Glisse } 349d39c3b89SJerome Glisse 350d39c3b89SJerome Glisse void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 351d39c3b89SJerome Glisse { 3526253e4c7SAlex Deucher u32 tmp, frame_count; 3536253e4c7SAlex Deucher int i, j; 3546253e4c7SAlex Deucher 3556253e4c7SAlex Deucher /* update crtc base addresses */ 3566253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3576253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) { 358367cbe2fSAlex Deucher if (i == 0) { 3596253e4c7SAlex Deucher WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 3606253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3616253e4c7SAlex Deucher WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 3626253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3636253e4c7SAlex Deucher } else { 3646253e4c7SAlex Deucher WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 3656253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3666253e4c7SAlex Deucher WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 3676253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3686253e4c7SAlex Deucher } 3696253e4c7SAlex Deucher } 3706253e4c7SAlex Deucher WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 3716253e4c7SAlex Deucher (u32)rdev->mc.vram_start); 3726253e4c7SAlex Deucher WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 3736253e4c7SAlex Deucher (u32)rdev->mc.vram_start); 3746253e4c7SAlex Deucher } 3756253e4c7SAlex Deucher WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 3766253e4c7SAlex Deucher 3772f86e2edSAlex Deucher /* unlock regs and wait for update */ 3782f86e2edSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3792f86e2edSAlex Deucher if (save->crtc_enabled[i]) { 3802f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 381f53f81b2SMario Kleiner if ((tmp & 0x7) != 3) { 382f53f81b2SMario Kleiner tmp &= ~0x7; 383f53f81b2SMario Kleiner tmp |= 0x3; 3842f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 3852f86e2edSAlex Deucher } 3862f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 3872f86e2edSAlex Deucher if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 3882f86e2edSAlex Deucher tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 3892f86e2edSAlex Deucher WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 3902f86e2edSAlex Deucher } 3912f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 3922f86e2edSAlex Deucher if (tmp & 1) { 3932f86e2edSAlex Deucher tmp &= ~1; 3942f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 3952f86e2edSAlex Deucher } 3962f86e2edSAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 3972f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 3982f86e2edSAlex Deucher if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 3992f86e2edSAlex Deucher break; 4002f86e2edSAlex Deucher udelay(1); 4012f86e2edSAlex Deucher } 4022f86e2edSAlex Deucher } 4032f86e2edSAlex Deucher } 4042f86e2edSAlex Deucher 4056253e4c7SAlex Deucher if (rdev->family >= CHIP_R600) { 4066253e4c7SAlex Deucher /* unblackout the MC */ 4076253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 4086253e4c7SAlex Deucher tmp = RREG32(R700_MC_CITF_CNTL); 4096253e4c7SAlex Deucher else 4106253e4c7SAlex Deucher tmp = RREG32(R600_CITF_CNTL); 4116253e4c7SAlex Deucher tmp &= ~R600_BLACKOUT_MASK; 4126253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 4136253e4c7SAlex Deucher WREG32(R700_MC_CITF_CNTL, tmp); 4146253e4c7SAlex Deucher else 4156253e4c7SAlex Deucher WREG32(R600_CITF_CNTL, tmp); 4166253e4c7SAlex Deucher /* allow CPU access */ 4176253e4c7SAlex Deucher WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 4186253e4c7SAlex Deucher } 4196253e4c7SAlex Deucher 4206253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 4216253e4c7SAlex Deucher if (save->crtc_enabled[i]) { 4226253e4c7SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 4236253e4c7SAlex Deucher tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 4246253e4c7SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 4256253e4c7SAlex Deucher /* wait for the next frame */ 4266253e4c7SAlex Deucher frame_count = radeon_get_vblank_counter(rdev, i); 4276253e4c7SAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 4286253e4c7SAlex Deucher if (radeon_get_vblank_counter(rdev, i) != frame_count) 4296253e4c7SAlex Deucher break; 4306253e4c7SAlex Deucher udelay(1); 4316253e4c7SAlex Deucher } 4326253e4c7SAlex Deucher } 4336253e4c7SAlex Deucher } 4346253e4c7SAlex Deucher /* Unlock vga access */ 435d39c3b89SJerome Glisse WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 436d39c3b89SJerome Glisse mdelay(1); 437d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 438d39c3b89SJerome Glisse } 439d39c3b89SJerome Glisse 4401109ca09SLauri Kasanen static void rv515_mc_program(struct radeon_device *rdev) 441d39c3b89SJerome Glisse { 442d39c3b89SJerome Glisse struct rv515_mc_save save; 443d39c3b89SJerome Glisse 444d39c3b89SJerome Glisse /* Stops all mc clients */ 445d39c3b89SJerome Glisse rv515_mc_stop(rdev, &save); 446d39c3b89SJerome Glisse 447d39c3b89SJerome Glisse /* Wait for mc idle */ 448d39c3b89SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) 449d39c3b89SJerome Glisse dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 450d39c3b89SJerome Glisse /* Write VRAM size in case we are limiting it */ 451d39c3b89SJerome Glisse WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 452d39c3b89SJerome Glisse /* Program MC, should be a 32bits limited address space */ 453d39c3b89SJerome Glisse WREG32_MC(R_000001_MC_FB_LOCATION, 454d39c3b89SJerome Glisse S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 455d39c3b89SJerome Glisse S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 456d39c3b89SJerome Glisse WREG32(R_000134_HDP_FB_LOCATION, 457d39c3b89SJerome Glisse S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 458d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 459d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 460d39c3b89SJerome Glisse S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 461d39c3b89SJerome Glisse S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 462d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 463d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 464d39c3b89SJerome Glisse S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 465d39c3b89SJerome Glisse } else { 466d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 467d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, 0); 468d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 469d39c3b89SJerome Glisse } 470d39c3b89SJerome Glisse 471d39c3b89SJerome Glisse rv515_mc_resume(rdev, &save); 472d39c3b89SJerome Glisse } 473d39c3b89SJerome Glisse 474d39c3b89SJerome Glisse void rv515_clock_startup(struct radeon_device *rdev) 475d39c3b89SJerome Glisse { 476d39c3b89SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 477d39c3b89SJerome Glisse radeon_atom_set_clock_gating(rdev, 1); 478d39c3b89SJerome Glisse /* We need to force on some of the block */ 479d39c3b89SJerome Glisse WREG32_PLL(R_00000F_CP_DYN_CNTL, 480d39c3b89SJerome Glisse RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 481d39c3b89SJerome Glisse WREG32_PLL(R_000011_E2_DYN_CNTL, 482d39c3b89SJerome Glisse RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 483d39c3b89SJerome Glisse WREG32_PLL(R_000013_IDCT_DYN_CNTL, 484d39c3b89SJerome Glisse RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 485d39c3b89SJerome Glisse } 486d39c3b89SJerome Glisse 487d39c3b89SJerome Glisse static int rv515_startup(struct radeon_device *rdev) 488d39c3b89SJerome Glisse { 489d39c3b89SJerome Glisse int r; 490d39c3b89SJerome Glisse 491d39c3b89SJerome Glisse rv515_mc_program(rdev); 492d39c3b89SJerome Glisse /* Resume clock */ 493d39c3b89SJerome Glisse rv515_clock_startup(rdev); 494d39c3b89SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 495d39c3b89SJerome Glisse rv515_gpu_init(rdev); 496d39c3b89SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 497d39c3b89SJerome Glisse * memory through TTM but finalize after TTM) */ 498d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) { 499d39c3b89SJerome Glisse r = rv370_pcie_gart_enable(rdev); 500d39c3b89SJerome Glisse if (r) 501d39c3b89SJerome Glisse return r; 502d39c3b89SJerome Glisse } 503724c80e1SAlex Deucher 504724c80e1SAlex Deucher /* allocate wb buffer */ 505724c80e1SAlex Deucher r = radeon_wb_init(rdev); 506724c80e1SAlex Deucher if (r) 507724c80e1SAlex Deucher return r; 508724c80e1SAlex Deucher 50930eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 51030eb77f4SJerome Glisse if (r) { 51130eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 51230eb77f4SJerome Glisse return r; 51330eb77f4SJerome Glisse } 51430eb77f4SJerome Glisse 515d39c3b89SJerome Glisse /* Enable IRQ */ 516e49f3959SAdis Hamzić if (!rdev->irq.installed) { 517e49f3959SAdis Hamzić r = radeon_irq_kms_init(rdev); 518e49f3959SAdis Hamzić if (r) 519e49f3959SAdis Hamzić return r; 520e49f3959SAdis Hamzić } 521e49f3959SAdis Hamzić 522ac447df4SJerome Glisse rs600_irq_set(rdev); 523cafe6609SJerome Glisse rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 524d39c3b89SJerome Glisse /* 1M ring buffer */ 525d39c3b89SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 526d39c3b89SJerome Glisse if (r) { 527ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 528d39c3b89SJerome Glisse return r; 529d39c3b89SJerome Glisse } 530b15ba512SJerome Glisse 5312898c348SChristian König r = radeon_ib_pool_init(rdev); 5322898c348SChristian König if (r) { 5332898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 534b15ba512SJerome Glisse return r; 5352898c348SChristian König } 536b15ba512SJerome Glisse 537d39c3b89SJerome Glisse return 0; 538d39c3b89SJerome Glisse } 539d39c3b89SJerome Glisse 540d39c3b89SJerome Glisse int rv515_resume(struct radeon_device *rdev) 541d39c3b89SJerome Glisse { 5426b7746e8SJerome Glisse int r; 5436b7746e8SJerome Glisse 544d39c3b89SJerome Glisse /* Make sur GART are not working */ 545d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 546d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 547d39c3b89SJerome Glisse /* Resume clock before doing reset */ 548d39c3b89SJerome Glisse rv515_clock_startup(rdev); 549d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 550a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 551d39c3b89SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 552d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 553d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 554d39c3b89SJerome Glisse } 555d39c3b89SJerome Glisse /* post */ 556d39c3b89SJerome Glisse atom_asic_init(rdev->mode_info.atom_context); 557d39c3b89SJerome Glisse /* Resume clock after posting */ 558d39c3b89SJerome Glisse rv515_clock_startup(rdev); 559550e2d92SDave Airlie /* Initialize surface registers */ 560550e2d92SDave Airlie radeon_surface_init(rdev); 561b15ba512SJerome Glisse 562b15ba512SJerome Glisse rdev->accel_working = true; 5636b7746e8SJerome Glisse r = rv515_startup(rdev); 5646b7746e8SJerome Glisse if (r) { 5656b7746e8SJerome Glisse rdev->accel_working = false; 5666b7746e8SJerome Glisse } 5676b7746e8SJerome Glisse return r; 568d39c3b89SJerome Glisse } 569d39c3b89SJerome Glisse 570d39c3b89SJerome Glisse int rv515_suspend(struct radeon_device *rdev) 571d39c3b89SJerome Glisse { 5726c7bcceaSAlex Deucher radeon_pm_suspend(rdev); 573d39c3b89SJerome Glisse r100_cp_disable(rdev); 574724c80e1SAlex Deucher radeon_wb_disable(rdev); 575ac447df4SJerome Glisse rs600_irq_disable(rdev); 576d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 577d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 578d39c3b89SJerome Glisse return 0; 579d39c3b89SJerome Glisse } 580d39c3b89SJerome Glisse 581d39c3b89SJerome Glisse void rv515_set_safe_registers(struct radeon_device *rdev) 582068a117cSJerome Glisse { 58350f15303SDave Airlie rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 58450f15303SDave Airlie rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 585d39c3b89SJerome Glisse } 586d39c3b89SJerome Glisse 587d39c3b89SJerome Glisse void rv515_fini(struct radeon_device *rdev) 588d39c3b89SJerome Glisse { 5896c7bcceaSAlex Deucher radeon_pm_fini(rdev); 590d39c3b89SJerome Glisse r100_cp_fini(rdev); 591724c80e1SAlex Deucher radeon_wb_fini(rdev); 5922898c348SChristian König radeon_ib_pool_fini(rdev); 593d39c3b89SJerome Glisse radeon_gem_fini(rdev); 594d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 595d39c3b89SJerome Glisse radeon_agp_fini(rdev); 596d39c3b89SJerome Glisse radeon_irq_kms_fini(rdev); 597d39c3b89SJerome Glisse radeon_fence_driver_fini(rdev); 5984c788679SJerome Glisse radeon_bo_fini(rdev); 599d39c3b89SJerome Glisse radeon_atombios_fini(rdev); 600d39c3b89SJerome Glisse kfree(rdev->bios); 601d39c3b89SJerome Glisse rdev->bios = NULL; 602d39c3b89SJerome Glisse } 603d39c3b89SJerome Glisse 604d39c3b89SJerome Glisse int rv515_init(struct radeon_device *rdev) 605d39c3b89SJerome Glisse { 606d39c3b89SJerome Glisse int r; 607d39c3b89SJerome Glisse 608d39c3b89SJerome Glisse /* Initialize scratch registers */ 609d39c3b89SJerome Glisse radeon_scratch_init(rdev); 610d39c3b89SJerome Glisse /* Initialize surface registers */ 611d39c3b89SJerome Glisse radeon_surface_init(rdev); 612d39c3b89SJerome Glisse /* TODO: disable VGA need to use VGA request */ 6134c712e6cSDave Airlie /* restore some register to sane defaults */ 6144c712e6cSDave Airlie r100_restore_sanity(rdev); 615d39c3b89SJerome Glisse /* BIOS*/ 616d39c3b89SJerome Glisse if (!radeon_get_bios(rdev)) { 617d39c3b89SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 618d39c3b89SJerome Glisse return -EINVAL; 619d39c3b89SJerome Glisse } 620d39c3b89SJerome Glisse if (rdev->is_atom_bios) { 621d39c3b89SJerome Glisse r = radeon_atombios_init(rdev); 622d39c3b89SJerome Glisse if (r) 623d39c3b89SJerome Glisse return r; 624d39c3b89SJerome Glisse } else { 625d39c3b89SJerome Glisse dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 626d39c3b89SJerome Glisse return -EINVAL; 627d39c3b89SJerome Glisse } 628d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 629a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 630d39c3b89SJerome Glisse dev_warn(rdev->dev, 631d39c3b89SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 632d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 633d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 634d39c3b89SJerome Glisse } 635d39c3b89SJerome Glisse /* check if cards are posted or not */ 63672542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 63772542d77SDave Airlie return -EINVAL; 638d39c3b89SJerome Glisse /* Initialize clocks */ 639d39c3b89SJerome Glisse radeon_get_clock_info(rdev->ddev); 640d594e46aSJerome Glisse /* initialize AGP */ 641d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 642d594e46aSJerome Glisse r = radeon_agp_init(rdev); 643d594e46aSJerome Glisse if (r) { 644d594e46aSJerome Glisse radeon_agp_disable(rdev); 645d594e46aSJerome Glisse } 646d594e46aSJerome Glisse } 647d594e46aSJerome Glisse /* initialize memory controller */ 648d594e46aSJerome Glisse rv515_mc_init(rdev); 649d39c3b89SJerome Glisse rv515_debugfs(rdev); 650d39c3b89SJerome Glisse /* Fence driver */ 651*519424d7SBernard Zhao radeon_fence_driver_init(rdev); 652d39c3b89SJerome Glisse /* Memory manager */ 6534c788679SJerome Glisse r = radeon_bo_init(rdev); 654d39c3b89SJerome Glisse if (r) 655d39c3b89SJerome Glisse return r; 656d39c3b89SJerome Glisse r = rv370_pcie_gart_init(rdev); 657d39c3b89SJerome Glisse if (r) 658d39c3b89SJerome Glisse return r; 659d39c3b89SJerome Glisse rv515_set_safe_registers(rdev); 660b15ba512SJerome Glisse 6616c7bcceaSAlex Deucher /* Initialize power management */ 6626c7bcceaSAlex Deucher radeon_pm_init(rdev); 6636c7bcceaSAlex Deucher 664d39c3b89SJerome Glisse rdev->accel_working = true; 665d39c3b89SJerome Glisse r = rv515_startup(rdev); 666d39c3b89SJerome Glisse if (r) { 667d39c3b89SJerome Glisse /* Somethings want wront with the accel init stop accel */ 668d39c3b89SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 669d39c3b89SJerome Glisse r100_cp_fini(rdev); 670724c80e1SAlex Deucher radeon_wb_fini(rdev); 6712898c348SChristian König radeon_ib_pool_fini(rdev); 672655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 673d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 674d39c3b89SJerome Glisse radeon_agp_fini(rdev); 675d39c3b89SJerome Glisse rdev->accel_working = false; 676d39c3b89SJerome Glisse } 677068a117cSJerome Glisse return 0; 678068a117cSJerome Glisse } 679c93bb85bSJerome Glisse 6804ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 681c93bb85bSJerome Glisse { 6824ce001abSDave Airlie int index_reg = 0x6578 + crtc->crtc_offset; 6834ce001abSDave Airlie int data_reg = 0x657c + crtc->crtc_offset; 684c93bb85bSJerome Glisse 6854ce001abSDave Airlie WREG32(0x659C + crtc->crtc_offset, 0x0); 6864ce001abSDave Airlie WREG32(0x6594 + crtc->crtc_offset, 0x705); 6874ce001abSDave Airlie WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 6884ce001abSDave Airlie WREG32(0x65D8 + crtc->crtc_offset, 0x0); 6894ce001abSDave Airlie WREG32(0x65B0 + crtc->crtc_offset, 0x0); 6904ce001abSDave Airlie WREG32(0x65C0 + crtc->crtc_offset, 0x0); 6914ce001abSDave Airlie WREG32(0x65D4 + crtc->crtc_offset, 0x0); 6924ce001abSDave Airlie WREG32(index_reg, 0x0); 6934ce001abSDave Airlie WREG32(data_reg, 0x841880A8); 6944ce001abSDave Airlie WREG32(index_reg, 0x1); 6954ce001abSDave Airlie WREG32(data_reg, 0x84208680); 6964ce001abSDave Airlie WREG32(index_reg, 0x2); 6974ce001abSDave Airlie WREG32(data_reg, 0xBFF880B0); 6984ce001abSDave Airlie WREG32(index_reg, 0x100); 6994ce001abSDave Airlie WREG32(data_reg, 0x83D88088); 7004ce001abSDave Airlie WREG32(index_reg, 0x101); 7014ce001abSDave Airlie WREG32(data_reg, 0x84608680); 7024ce001abSDave Airlie WREG32(index_reg, 0x102); 7034ce001abSDave Airlie WREG32(data_reg, 0xBFF080D0); 7044ce001abSDave Airlie WREG32(index_reg, 0x200); 7054ce001abSDave Airlie WREG32(data_reg, 0x83988068); 7064ce001abSDave Airlie WREG32(index_reg, 0x201); 7074ce001abSDave Airlie WREG32(data_reg, 0x84A08680); 7084ce001abSDave Airlie WREG32(index_reg, 0x202); 7094ce001abSDave Airlie WREG32(data_reg, 0xBFF080F8); 7104ce001abSDave Airlie WREG32(index_reg, 0x300); 7114ce001abSDave Airlie WREG32(data_reg, 0x83588058); 7124ce001abSDave Airlie WREG32(index_reg, 0x301); 7134ce001abSDave Airlie WREG32(data_reg, 0x84E08660); 7144ce001abSDave Airlie WREG32(index_reg, 0x302); 7154ce001abSDave Airlie WREG32(data_reg, 0xBFF88120); 7164ce001abSDave Airlie WREG32(index_reg, 0x400); 7174ce001abSDave Airlie WREG32(data_reg, 0x83188040); 7184ce001abSDave Airlie WREG32(index_reg, 0x401); 7194ce001abSDave Airlie WREG32(data_reg, 0x85008660); 7204ce001abSDave Airlie WREG32(index_reg, 0x402); 7214ce001abSDave Airlie WREG32(data_reg, 0xBFF88150); 7224ce001abSDave Airlie WREG32(index_reg, 0x500); 7234ce001abSDave Airlie WREG32(data_reg, 0x82D88030); 7244ce001abSDave Airlie WREG32(index_reg, 0x501); 7254ce001abSDave Airlie WREG32(data_reg, 0x85408640); 7264ce001abSDave Airlie WREG32(index_reg, 0x502); 7274ce001abSDave Airlie WREG32(data_reg, 0xBFF88180); 7284ce001abSDave Airlie WREG32(index_reg, 0x600); 7294ce001abSDave Airlie WREG32(data_reg, 0x82A08018); 7304ce001abSDave Airlie WREG32(index_reg, 0x601); 7314ce001abSDave Airlie WREG32(data_reg, 0x85808620); 7324ce001abSDave Airlie WREG32(index_reg, 0x602); 7334ce001abSDave Airlie WREG32(data_reg, 0xBFF081B8); 7344ce001abSDave Airlie WREG32(index_reg, 0x700); 7354ce001abSDave Airlie WREG32(data_reg, 0x82608010); 7364ce001abSDave Airlie WREG32(index_reg, 0x701); 7374ce001abSDave Airlie WREG32(data_reg, 0x85A08600); 7384ce001abSDave Airlie WREG32(index_reg, 0x702); 7394ce001abSDave Airlie WREG32(data_reg, 0x800081F0); 7404ce001abSDave Airlie WREG32(index_reg, 0x800); 7414ce001abSDave Airlie WREG32(data_reg, 0x8228BFF8); 7424ce001abSDave Airlie WREG32(index_reg, 0x801); 7434ce001abSDave Airlie WREG32(data_reg, 0x85E085E0); 7444ce001abSDave Airlie WREG32(index_reg, 0x802); 7454ce001abSDave Airlie WREG32(data_reg, 0xBFF88228); 7464ce001abSDave Airlie WREG32(index_reg, 0x10000); 7474ce001abSDave Airlie WREG32(data_reg, 0x82A8BF00); 7484ce001abSDave Airlie WREG32(index_reg, 0x10001); 7494ce001abSDave Airlie WREG32(data_reg, 0x82A08CC0); 7504ce001abSDave Airlie WREG32(index_reg, 0x10002); 7514ce001abSDave Airlie WREG32(data_reg, 0x8008BEF8); 7524ce001abSDave Airlie WREG32(index_reg, 0x10100); 7534ce001abSDave Airlie WREG32(data_reg, 0x81F0BF28); 7544ce001abSDave Airlie WREG32(index_reg, 0x10101); 7554ce001abSDave Airlie WREG32(data_reg, 0x83608CA0); 7564ce001abSDave Airlie WREG32(index_reg, 0x10102); 7574ce001abSDave Airlie WREG32(data_reg, 0x8018BED0); 7584ce001abSDave Airlie WREG32(index_reg, 0x10200); 7594ce001abSDave Airlie WREG32(data_reg, 0x8148BF38); 7604ce001abSDave Airlie WREG32(index_reg, 0x10201); 7614ce001abSDave Airlie WREG32(data_reg, 0x84408C80); 7624ce001abSDave Airlie WREG32(index_reg, 0x10202); 7634ce001abSDave Airlie WREG32(data_reg, 0x8008BEB8); 7644ce001abSDave Airlie WREG32(index_reg, 0x10300); 7654ce001abSDave Airlie WREG32(data_reg, 0x80B0BF78); 7664ce001abSDave Airlie WREG32(index_reg, 0x10301); 7674ce001abSDave Airlie WREG32(data_reg, 0x85008C20); 7684ce001abSDave Airlie WREG32(index_reg, 0x10302); 7694ce001abSDave Airlie WREG32(data_reg, 0x8020BEA0); 7704ce001abSDave Airlie WREG32(index_reg, 0x10400); 7714ce001abSDave Airlie WREG32(data_reg, 0x8028BF90); 7724ce001abSDave Airlie WREG32(index_reg, 0x10401); 7734ce001abSDave Airlie WREG32(data_reg, 0x85E08BC0); 7744ce001abSDave Airlie WREG32(index_reg, 0x10402); 7754ce001abSDave Airlie WREG32(data_reg, 0x8018BE90); 7764ce001abSDave Airlie WREG32(index_reg, 0x10500); 7774ce001abSDave Airlie WREG32(data_reg, 0xBFB8BFB0); 7784ce001abSDave Airlie WREG32(index_reg, 0x10501); 7794ce001abSDave Airlie WREG32(data_reg, 0x86C08B40); 7804ce001abSDave Airlie WREG32(index_reg, 0x10502); 7814ce001abSDave Airlie WREG32(data_reg, 0x8010BE90); 7824ce001abSDave Airlie WREG32(index_reg, 0x10600); 7834ce001abSDave Airlie WREG32(data_reg, 0xBF58BFC8); 7844ce001abSDave Airlie WREG32(index_reg, 0x10601); 7854ce001abSDave Airlie WREG32(data_reg, 0x87A08AA0); 7864ce001abSDave Airlie WREG32(index_reg, 0x10602); 7874ce001abSDave Airlie WREG32(data_reg, 0x8010BE98); 7884ce001abSDave Airlie WREG32(index_reg, 0x10700); 7894ce001abSDave Airlie WREG32(data_reg, 0xBF10BFF0); 7904ce001abSDave Airlie WREG32(index_reg, 0x10701); 7914ce001abSDave Airlie WREG32(data_reg, 0x886089E0); 7924ce001abSDave Airlie WREG32(index_reg, 0x10702); 7934ce001abSDave Airlie WREG32(data_reg, 0x8018BEB0); 7944ce001abSDave Airlie WREG32(index_reg, 0x10800); 7954ce001abSDave Airlie WREG32(data_reg, 0xBED8BFE8); 7964ce001abSDave Airlie WREG32(index_reg, 0x10801); 7974ce001abSDave Airlie WREG32(data_reg, 0x89408940); 7984ce001abSDave Airlie WREG32(index_reg, 0x10802); 7994ce001abSDave Airlie WREG32(data_reg, 0xBFE8BED8); 8004ce001abSDave Airlie WREG32(index_reg, 0x20000); 8014ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8024ce001abSDave Airlie WREG32(index_reg, 0x20001); 8034ce001abSDave Airlie WREG32(data_reg, 0x90008000); 8044ce001abSDave Airlie WREG32(index_reg, 0x20002); 8054ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8064ce001abSDave Airlie WREG32(index_reg, 0x20003); 8074ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8084ce001abSDave Airlie WREG32(index_reg, 0x20100); 8094ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8104ce001abSDave Airlie WREG32(index_reg, 0x20101); 8114ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF70); 8124ce001abSDave Airlie WREG32(index_reg, 0x20102); 8134ce001abSDave Airlie WREG32(data_reg, 0xBFE880C0); 8144ce001abSDave Airlie WREG32(index_reg, 0x20103); 8154ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8164ce001abSDave Airlie WREG32(index_reg, 0x20200); 8174ce001abSDave Airlie WREG32(data_reg, 0x8018BFF8); 8184ce001abSDave Airlie WREG32(index_reg, 0x20201); 8194ce001abSDave Airlie WREG32(data_reg, 0x8F80BF08); 8204ce001abSDave Airlie WREG32(index_reg, 0x20202); 8214ce001abSDave Airlie WREG32(data_reg, 0xBFD081A0); 8224ce001abSDave Airlie WREG32(index_reg, 0x20203); 8234ce001abSDave Airlie WREG32(data_reg, 0xBFF88000); 8244ce001abSDave Airlie WREG32(index_reg, 0x20300); 8254ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8264ce001abSDave Airlie WREG32(index_reg, 0x20301); 8274ce001abSDave Airlie WREG32(data_reg, 0x8EE0BEC0); 8284ce001abSDave Airlie WREG32(index_reg, 0x20302); 8294ce001abSDave Airlie WREG32(data_reg, 0xBFB082A0); 8304ce001abSDave Airlie WREG32(index_reg, 0x20303); 8314ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8324ce001abSDave Airlie WREG32(index_reg, 0x20400); 8334ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8344ce001abSDave Airlie WREG32(index_reg, 0x20401); 8354ce001abSDave Airlie WREG32(data_reg, 0x8E00BEA0); 8364ce001abSDave Airlie WREG32(index_reg, 0x20402); 8374ce001abSDave Airlie WREG32(data_reg, 0xBF8883C0); 8384ce001abSDave Airlie WREG32(index_reg, 0x20403); 8394ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8404ce001abSDave Airlie WREG32(index_reg, 0x20500); 8414ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8424ce001abSDave Airlie WREG32(index_reg, 0x20501); 8434ce001abSDave Airlie WREG32(data_reg, 0x8D00BE90); 8444ce001abSDave Airlie WREG32(index_reg, 0x20502); 8454ce001abSDave Airlie WREG32(data_reg, 0xBF588500); 8464ce001abSDave Airlie WREG32(index_reg, 0x20503); 8474ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8484ce001abSDave Airlie WREG32(index_reg, 0x20600); 8494ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8504ce001abSDave Airlie WREG32(index_reg, 0x20601); 8514ce001abSDave Airlie WREG32(data_reg, 0x8BC0BE98); 8524ce001abSDave Airlie WREG32(index_reg, 0x20602); 8534ce001abSDave Airlie WREG32(data_reg, 0xBF308660); 8544ce001abSDave Airlie WREG32(index_reg, 0x20603); 8554ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8564ce001abSDave Airlie WREG32(index_reg, 0x20700); 8574ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8584ce001abSDave Airlie WREG32(index_reg, 0x20701); 8594ce001abSDave Airlie WREG32(data_reg, 0x8A80BEB0); 8604ce001abSDave Airlie WREG32(index_reg, 0x20702); 8614ce001abSDave Airlie WREG32(data_reg, 0xBF0087C0); 8624ce001abSDave Airlie WREG32(index_reg, 0x20703); 8634ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8644ce001abSDave Airlie WREG32(index_reg, 0x20800); 8654ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8664ce001abSDave Airlie WREG32(index_reg, 0x20801); 8674ce001abSDave Airlie WREG32(data_reg, 0x8920BED0); 8684ce001abSDave Airlie WREG32(index_reg, 0x20802); 8694ce001abSDave Airlie WREG32(data_reg, 0xBED08920); 8704ce001abSDave Airlie WREG32(index_reg, 0x20803); 8714ce001abSDave Airlie WREG32(data_reg, 0x80008010); 8724ce001abSDave Airlie WREG32(index_reg, 0x30000); 8734ce001abSDave Airlie WREG32(data_reg, 0x90008000); 8744ce001abSDave Airlie WREG32(index_reg, 0x30001); 8754ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8764ce001abSDave Airlie WREG32(index_reg, 0x30100); 8774ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF90); 8784ce001abSDave Airlie WREG32(index_reg, 0x30101); 8794ce001abSDave Airlie WREG32(data_reg, 0xBFF880A0); 8804ce001abSDave Airlie WREG32(index_reg, 0x30200); 8814ce001abSDave Airlie WREG32(data_reg, 0x8F60BF40); 8824ce001abSDave Airlie WREG32(index_reg, 0x30201); 8834ce001abSDave Airlie WREG32(data_reg, 0xBFE88180); 8844ce001abSDave Airlie WREG32(index_reg, 0x30300); 8854ce001abSDave Airlie WREG32(data_reg, 0x8EC0BF00); 8864ce001abSDave Airlie WREG32(index_reg, 0x30301); 8874ce001abSDave Airlie WREG32(data_reg, 0xBFC88280); 8884ce001abSDave Airlie WREG32(index_reg, 0x30400); 8894ce001abSDave Airlie WREG32(data_reg, 0x8DE0BEE0); 8904ce001abSDave Airlie WREG32(index_reg, 0x30401); 8914ce001abSDave Airlie WREG32(data_reg, 0xBFA083A0); 8924ce001abSDave Airlie WREG32(index_reg, 0x30500); 8934ce001abSDave Airlie WREG32(data_reg, 0x8CE0BED0); 8944ce001abSDave Airlie WREG32(index_reg, 0x30501); 8954ce001abSDave Airlie WREG32(data_reg, 0xBF7884E0); 8964ce001abSDave Airlie WREG32(index_reg, 0x30600); 8974ce001abSDave Airlie WREG32(data_reg, 0x8BA0BED8); 8984ce001abSDave Airlie WREG32(index_reg, 0x30601); 8994ce001abSDave Airlie WREG32(data_reg, 0xBF508640); 9004ce001abSDave Airlie WREG32(index_reg, 0x30700); 9014ce001abSDave Airlie WREG32(data_reg, 0x8A60BEE8); 9024ce001abSDave Airlie WREG32(index_reg, 0x30701); 9034ce001abSDave Airlie WREG32(data_reg, 0xBF2087A0); 9044ce001abSDave Airlie WREG32(index_reg, 0x30800); 9054ce001abSDave Airlie WREG32(data_reg, 0x8900BF00); 9064ce001abSDave Airlie WREG32(index_reg, 0x30801); 9074ce001abSDave Airlie WREG32(data_reg, 0xBF008900); 908c93bb85bSJerome Glisse } 909c93bb85bSJerome Glisse 910c93bb85bSJerome Glisse struct rv515_watermark { 911c93bb85bSJerome Glisse u32 lb_request_fifo_depth; 912c93bb85bSJerome Glisse fixed20_12 num_line_pair; 913c93bb85bSJerome Glisse fixed20_12 estimated_width; 914c93bb85bSJerome Glisse fixed20_12 worst_case_latency; 915c93bb85bSJerome Glisse fixed20_12 consumption_rate; 916c93bb85bSJerome Glisse fixed20_12 active_time; 917c93bb85bSJerome Glisse fixed20_12 dbpp; 918c93bb85bSJerome Glisse fixed20_12 priority_mark_max; 919c93bb85bSJerome Glisse fixed20_12 priority_mark; 920c93bb85bSJerome Glisse fixed20_12 sclk; 921c93bb85bSJerome Glisse }; 922c93bb85bSJerome Glisse 9231109ca09SLauri Kasanen static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 924c93bb85bSJerome Glisse struct radeon_crtc *crtc, 9257d99e517SAlex Deucher struct rv515_watermark *wm, 9267d99e517SAlex Deucher bool low) 927c93bb85bSJerome Glisse { 928c93bb85bSJerome Glisse struct drm_display_mode *mode = &crtc->base.mode; 929c93bb85bSJerome Glisse fixed20_12 a, b, c; 930c93bb85bSJerome Glisse fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 931c93bb85bSJerome Glisse fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 9327d99e517SAlex Deucher fixed20_12 sclk; 9337d99e517SAlex Deucher u32 selected_sclk; 934c93bb85bSJerome Glisse 935c93bb85bSJerome Glisse if (!crtc->base.enabled) { 936c93bb85bSJerome Glisse /* FIXME: wouldn't it better to set priority mark to maximum */ 937c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 938c93bb85bSJerome Glisse return; 939c93bb85bSJerome Glisse } 940c93bb85bSJerome Glisse 9417d99e517SAlex Deucher /* rv6xx, rv7xx */ 9427d99e517SAlex Deucher if ((rdev->family >= CHIP_RV610) && 9437d99e517SAlex Deucher (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 9447d99e517SAlex Deucher selected_sclk = radeon_dpm_get_sclk(rdev, low); 9457d99e517SAlex Deucher else 9467d99e517SAlex Deucher selected_sclk = rdev->pm.current_sclk; 9477d99e517SAlex Deucher 9487d99e517SAlex Deucher /* sclk in Mhz */ 9497d99e517SAlex Deucher a.full = dfixed_const(100); 9507d99e517SAlex Deucher sclk.full = dfixed_const(selected_sclk); 9517d99e517SAlex Deucher sclk.full = dfixed_div(sclk, a); 9527d99e517SAlex Deucher 95368adac5eSBen Skeggs if (crtc->vsc.full > dfixed_const(2)) 95468adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(2); 955c93bb85bSJerome Glisse else 95668adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(1); 957c93bb85bSJerome Glisse 95868adac5eSBen Skeggs b.full = dfixed_const(mode->crtc_hdisplay); 95968adac5eSBen Skeggs c.full = dfixed_const(256); 96068adac5eSBen Skeggs a.full = dfixed_div(b, c); 96168adac5eSBen Skeggs request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 96268adac5eSBen Skeggs request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 96368adac5eSBen Skeggs if (a.full < dfixed_const(4)) { 964c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 965c93bb85bSJerome Glisse } else { 96668adac5eSBen Skeggs wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 967c93bb85bSJerome Glisse } 968c93bb85bSJerome Glisse 969c93bb85bSJerome Glisse /* Determine consumption rate 970c93bb85bSJerome Glisse * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 971c93bb85bSJerome Glisse * vtaps = number of vertical taps, 972c93bb85bSJerome Glisse * vsc = vertical scaling ratio, defined as source/destination 973c93bb85bSJerome Glisse * hsc = horizontal scaling ration, defined as source/destination 974c93bb85bSJerome Glisse */ 97568adac5eSBen Skeggs a.full = dfixed_const(mode->clock); 97668adac5eSBen Skeggs b.full = dfixed_const(1000); 97768adac5eSBen Skeggs a.full = dfixed_div(a, b); 97868adac5eSBen Skeggs pclk.full = dfixed_div(b, a); 979c93bb85bSJerome Glisse if (crtc->rmx_type != RMX_OFF) { 98068adac5eSBen Skeggs b.full = dfixed_const(2); 981c93bb85bSJerome Glisse if (crtc->vsc.full > b.full) 982c93bb85bSJerome Glisse b.full = crtc->vsc.full; 98368adac5eSBen Skeggs b.full = dfixed_mul(b, crtc->hsc); 98468adac5eSBen Skeggs c.full = dfixed_const(2); 98568adac5eSBen Skeggs b.full = dfixed_div(b, c); 98668adac5eSBen Skeggs consumption_time.full = dfixed_div(pclk, b); 987c93bb85bSJerome Glisse } else { 988c93bb85bSJerome Glisse consumption_time.full = pclk.full; 989c93bb85bSJerome Glisse } 99068adac5eSBen Skeggs a.full = dfixed_const(1); 99168adac5eSBen Skeggs wm->consumption_rate.full = dfixed_div(a, consumption_time); 992c93bb85bSJerome Glisse 993c93bb85bSJerome Glisse 994c93bb85bSJerome Glisse /* Determine line time 995c93bb85bSJerome Glisse * LineTime = total time for one line of displayhtotal 996c93bb85bSJerome Glisse * LineTime = total number of horizontal pixels 997c93bb85bSJerome Glisse * pclk = pixel clock period(ns) 998c93bb85bSJerome Glisse */ 99968adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 100068adac5eSBen Skeggs line_time.full = dfixed_mul(a, pclk); 1001c93bb85bSJerome Glisse 1002c93bb85bSJerome Glisse /* Determine active time 1003c93bb85bSJerome Glisse * ActiveTime = time of active region of display within one line, 1004c93bb85bSJerome Glisse * hactive = total number of horizontal active pixels 1005c93bb85bSJerome Glisse * htotal = total number of horizontal pixels 1006c93bb85bSJerome Glisse */ 100768adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 100868adac5eSBen Skeggs b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 100968adac5eSBen Skeggs wm->active_time.full = dfixed_mul(line_time, b); 101068adac5eSBen Skeggs wm->active_time.full = dfixed_div(wm->active_time, a); 1011c93bb85bSJerome Glisse 1012c93bb85bSJerome Glisse /* Determine chunk time 1013c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk of data 1014c93bb85bSJerome Glisse * to the LB which consists of pipeline delay and inter chunk gap 1015c93bb85bSJerome Glisse * sclk = system clock(Mhz) 1016c93bb85bSJerome Glisse */ 101768adac5eSBen Skeggs a.full = dfixed_const(600 * 1000); 10187d99e517SAlex Deucher chunk_time.full = dfixed_div(a, sclk); 101968adac5eSBen Skeggs read_delay_latency.full = dfixed_const(1000); 1020c93bb85bSJerome Glisse 1021c93bb85bSJerome Glisse /* Determine the worst case latency 1022c93bb85bSJerome Glisse * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1023c93bb85bSJerome Glisse * WorstCaseLatency = worst case time from urgent to when the MC starts 1024c93bb85bSJerome Glisse * to return data 1025c93bb85bSJerome Glisse * READ_DELAY_IDLE_MAX = constant of 1us 1026c93bb85bSJerome Glisse * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1027c93bb85bSJerome Glisse * which consists of pipeline delay and inter chunk gap 1028c93bb85bSJerome Glisse */ 102968adac5eSBen Skeggs if (dfixed_trunc(wm->num_line_pair) > 1) { 103068adac5eSBen Skeggs a.full = dfixed_const(3); 103168adac5eSBen Skeggs wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1032c93bb85bSJerome Glisse wm->worst_case_latency.full += read_delay_latency.full; 1033c93bb85bSJerome Glisse } else { 1034c93bb85bSJerome Glisse wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1035c93bb85bSJerome Glisse } 1036c93bb85bSJerome Glisse 1037c93bb85bSJerome Glisse /* Determine the tolerable latency 1038c93bb85bSJerome Glisse * TolerableLatency = Any given request has only 1 line time 1039c93bb85bSJerome Glisse * for the data to be returned 1040c93bb85bSJerome Glisse * LBRequestFifoDepth = Number of chunk requests the LB can 1041c93bb85bSJerome Glisse * put into the request FIFO for a display 1042c93bb85bSJerome Glisse * LineTime = total time for one line of display 1043c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk 1044c93bb85bSJerome Glisse * of data to the LB which consists of 1045c93bb85bSJerome Glisse * pipeline delay and inter chunk gap 1046c93bb85bSJerome Glisse */ 104768adac5eSBen Skeggs if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1048c93bb85bSJerome Glisse tolerable_latency.full = line_time.full; 1049c93bb85bSJerome Glisse } else { 105068adac5eSBen Skeggs tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1051c93bb85bSJerome Glisse tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 105268adac5eSBen Skeggs tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1053c93bb85bSJerome Glisse tolerable_latency.full = line_time.full - tolerable_latency.full; 1054c93bb85bSJerome Glisse } 1055c93bb85bSJerome Glisse /* We assume worst case 32bits (4 bytes) */ 105668adac5eSBen Skeggs wm->dbpp.full = dfixed_const(2 * 16); 1057c93bb85bSJerome Glisse 1058c93bb85bSJerome Glisse /* Determine the maximum priority mark 1059c93bb85bSJerome Glisse * width = viewport width in pixels 1060c93bb85bSJerome Glisse */ 106168adac5eSBen Skeggs a.full = dfixed_const(16); 106268adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 106368adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 106468adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1065c93bb85bSJerome Glisse 1066c93bb85bSJerome Glisse /* Determine estimated width */ 1067c93bb85bSJerome Glisse estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 106868adac5eSBen Skeggs estimated_width.full = dfixed_div(estimated_width, consumption_time); 106968adac5eSBen Skeggs if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 107069b3b5e5SAlex Deucher wm->priority_mark.full = wm->priority_mark_max.full; 1071c93bb85bSJerome Glisse } else { 107268adac5eSBen Skeggs a.full = dfixed_const(16); 107368adac5eSBen Skeggs wm->priority_mark.full = dfixed_div(estimated_width, a); 107468adac5eSBen Skeggs wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1075c93bb85bSJerome Glisse wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1076c93bb85bSJerome Glisse } 1077c93bb85bSJerome Glisse } 1078c93bb85bSJerome Glisse 10797d99e517SAlex Deucher static void rv515_compute_mode_priority(struct radeon_device *rdev, 10807d99e517SAlex Deucher struct rv515_watermark *wm0, 10817d99e517SAlex Deucher struct rv515_watermark *wm1, 10827d99e517SAlex Deucher struct drm_display_mode *mode0, 10837d99e517SAlex Deucher struct drm_display_mode *mode1, 10847d99e517SAlex Deucher u32 *d1mode_priority_a_cnt, 10857d99e517SAlex Deucher u32 *d2mode_priority_a_cnt) 10867d99e517SAlex Deucher { 10877d99e517SAlex Deucher fixed20_12 priority_mark02, priority_mark12, fill_rate; 10887d99e517SAlex Deucher fixed20_12 a, b; 10897d99e517SAlex Deucher 10907d99e517SAlex Deucher *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 10917d99e517SAlex Deucher *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 10927d99e517SAlex Deucher 10937d99e517SAlex Deucher if (mode0 && mode1) { 10947d99e517SAlex Deucher if (dfixed_trunc(wm0->dbpp) > 64) 10957d99e517SAlex Deucher a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 10967d99e517SAlex Deucher else 10977d99e517SAlex Deucher a.full = wm0->num_line_pair.full; 10987d99e517SAlex Deucher if (dfixed_trunc(wm1->dbpp) > 64) 10997d99e517SAlex Deucher b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 11007d99e517SAlex Deucher else 11017d99e517SAlex Deucher b.full = wm1->num_line_pair.full; 11027d99e517SAlex Deucher a.full += b.full; 11037d99e517SAlex Deucher fill_rate.full = dfixed_div(wm0->sclk, a); 11047d99e517SAlex Deucher if (wm0->consumption_rate.full > fill_rate.full) { 11057d99e517SAlex Deucher b.full = wm0->consumption_rate.full - fill_rate.full; 11067d99e517SAlex Deucher b.full = dfixed_mul(b, wm0->active_time); 11077d99e517SAlex Deucher a.full = dfixed_const(16); 11087d99e517SAlex Deucher b.full = dfixed_div(b, a); 11097d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11107d99e517SAlex Deucher wm0->consumption_rate); 11117d99e517SAlex Deucher priority_mark02.full = a.full + b.full; 11127d99e517SAlex Deucher } else { 11137d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11147d99e517SAlex Deucher wm0->consumption_rate); 11157d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 11167d99e517SAlex Deucher priority_mark02.full = dfixed_div(a, b); 11177d99e517SAlex Deucher } 11187d99e517SAlex Deucher if (wm1->consumption_rate.full > fill_rate.full) { 11197d99e517SAlex Deucher b.full = wm1->consumption_rate.full - fill_rate.full; 11207d99e517SAlex Deucher b.full = dfixed_mul(b, wm1->active_time); 11217d99e517SAlex Deucher a.full = dfixed_const(16); 11227d99e517SAlex Deucher b.full = dfixed_div(b, a); 11237d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11247d99e517SAlex Deucher wm1->consumption_rate); 11257d99e517SAlex Deucher priority_mark12.full = a.full + b.full; 11267d99e517SAlex Deucher } else { 11277d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11287d99e517SAlex Deucher wm1->consumption_rate); 11297d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 11307d99e517SAlex Deucher priority_mark12.full = dfixed_div(a, b); 11317d99e517SAlex Deucher } 11327d99e517SAlex Deucher if (wm0->priority_mark.full > priority_mark02.full) 11337d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark.full; 11347d99e517SAlex Deucher if (wm0->priority_mark_max.full > priority_mark02.full) 11357d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark_max.full; 11367d99e517SAlex Deucher if (wm1->priority_mark.full > priority_mark12.full) 11377d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark.full; 11387d99e517SAlex Deucher if (wm1->priority_mark_max.full > priority_mark12.full) 11397d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark_max.full; 11407d99e517SAlex Deucher *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 11417d99e517SAlex Deucher *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 11427d99e517SAlex Deucher if (rdev->disp_priority == 2) { 11437d99e517SAlex Deucher *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 11447d99e517SAlex Deucher *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 11457d99e517SAlex Deucher } 11467d99e517SAlex Deucher } else if (mode0) { 11477d99e517SAlex Deucher if (dfixed_trunc(wm0->dbpp) > 64) 11487d99e517SAlex Deucher a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 11497d99e517SAlex Deucher else 11507d99e517SAlex Deucher a.full = wm0->num_line_pair.full; 11517d99e517SAlex Deucher fill_rate.full = dfixed_div(wm0->sclk, a); 11527d99e517SAlex Deucher if (wm0->consumption_rate.full > fill_rate.full) { 11537d99e517SAlex Deucher b.full = wm0->consumption_rate.full - fill_rate.full; 11547d99e517SAlex Deucher b.full = dfixed_mul(b, wm0->active_time); 11557d99e517SAlex Deucher a.full = dfixed_const(16); 11567d99e517SAlex Deucher b.full = dfixed_div(b, a); 11577d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11587d99e517SAlex Deucher wm0->consumption_rate); 11597d99e517SAlex Deucher priority_mark02.full = a.full + b.full; 11607d99e517SAlex Deucher } else { 11617d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11627d99e517SAlex Deucher wm0->consumption_rate); 11637d99e517SAlex Deucher b.full = dfixed_const(16); 11647d99e517SAlex Deucher priority_mark02.full = dfixed_div(a, b); 11657d99e517SAlex Deucher } 11667d99e517SAlex Deucher if (wm0->priority_mark.full > priority_mark02.full) 11677d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark.full; 11687d99e517SAlex Deucher if (wm0->priority_mark_max.full > priority_mark02.full) 11697d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark_max.full; 11707d99e517SAlex Deucher *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 11717d99e517SAlex Deucher if (rdev->disp_priority == 2) 11727d99e517SAlex Deucher *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 11737d99e517SAlex Deucher } else if (mode1) { 11747d99e517SAlex Deucher if (dfixed_trunc(wm1->dbpp) > 64) 11757d99e517SAlex Deucher a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 11767d99e517SAlex Deucher else 11777d99e517SAlex Deucher a.full = wm1->num_line_pair.full; 11787d99e517SAlex Deucher fill_rate.full = dfixed_div(wm1->sclk, a); 11797d99e517SAlex Deucher if (wm1->consumption_rate.full > fill_rate.full) { 11807d99e517SAlex Deucher b.full = wm1->consumption_rate.full - fill_rate.full; 11817d99e517SAlex Deucher b.full = dfixed_mul(b, wm1->active_time); 11827d99e517SAlex Deucher a.full = dfixed_const(16); 11837d99e517SAlex Deucher b.full = dfixed_div(b, a); 11847d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11857d99e517SAlex Deucher wm1->consumption_rate); 11867d99e517SAlex Deucher priority_mark12.full = a.full + b.full; 11877d99e517SAlex Deucher } else { 11887d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11897d99e517SAlex Deucher wm1->consumption_rate); 11907d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 11917d99e517SAlex Deucher priority_mark12.full = dfixed_div(a, b); 11927d99e517SAlex Deucher } 11937d99e517SAlex Deucher if (wm1->priority_mark.full > priority_mark12.full) 11947d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark.full; 11957d99e517SAlex Deucher if (wm1->priority_mark_max.full > priority_mark12.full) 11967d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark_max.full; 11977d99e517SAlex Deucher *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 11987d99e517SAlex Deucher if (rdev->disp_priority == 2) 11997d99e517SAlex Deucher *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 12007d99e517SAlex Deucher } 12017d99e517SAlex Deucher } 12027d99e517SAlex Deucher 1203c93bb85bSJerome Glisse void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1204c93bb85bSJerome Glisse { 1205c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1206c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 12077d99e517SAlex Deucher struct rv515_watermark wm0_high, wm0_low; 12087d99e517SAlex Deucher struct rv515_watermark wm1_high, wm1_low; 1209e06b14eeSAlex Deucher u32 tmp; 12107d99e517SAlex Deucher u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 12117d99e517SAlex Deucher u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1212c93bb85bSJerome Glisse 1213c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1214c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1215c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1216c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1217c93bb85bSJerome Glisse rs690_line_buffer_adjust(rdev, mode0, mode1); 1218c93bb85bSJerome Glisse 12197d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 12207d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1221c93bb85bSJerome Glisse 12227d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 12237d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 12247d99e517SAlex Deucher 12257d99e517SAlex Deucher tmp = wm0_high.lb_request_fifo_depth; 12267d99e517SAlex Deucher tmp |= wm1_high.lb_request_fifo_depth << 16; 1227c93bb85bSJerome Glisse WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1228c93bb85bSJerome Glisse 12297d99e517SAlex Deucher rv515_compute_mode_priority(rdev, 12307d99e517SAlex Deucher &wm0_high, &wm1_high, 12317d99e517SAlex Deucher mode0, mode1, 12327d99e517SAlex Deucher &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 12337d99e517SAlex Deucher rv515_compute_mode_priority(rdev, 12347d99e517SAlex Deucher &wm0_low, &wm1_low, 12357d99e517SAlex Deucher mode0, mode1, 12367d99e517SAlex Deucher &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1237e06b14eeSAlex Deucher 1238e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 12397d99e517SAlex Deucher WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1240f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 12417d99e517SAlex Deucher WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1242c93bb85bSJerome Glisse } 1243c93bb85bSJerome Glisse 1244c93bb85bSJerome Glisse void rv515_bandwidth_update(struct radeon_device *rdev) 1245c93bb85bSJerome Glisse { 1246c93bb85bSJerome Glisse uint32_t tmp; 1247c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1248c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1249c93bb85bSJerome Glisse 12508efe82caSAlex Deucher if (!rdev->mode_info.mode_config_initialized) 12518efe82caSAlex Deucher return; 12528efe82caSAlex Deucher 1253f46c0120SAlex Deucher radeon_update_display_priority(rdev); 1254f46c0120SAlex Deucher 1255c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1256c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1257c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1258c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1259c93bb85bSJerome Glisse /* 1260c93bb85bSJerome Glisse * Set display0/1 priority up in the memory controller for 1261c93bb85bSJerome Glisse * modes if the user specifies HIGH for displaypriority 1262c93bb85bSJerome Glisse * option. 1263c93bb85bSJerome Glisse */ 1264f46c0120SAlex Deucher if ((rdev->disp_priority == 2) && 1265f46c0120SAlex Deucher (rdev->family == CHIP_RV515)) { 1266c93bb85bSJerome Glisse tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1267c93bb85bSJerome Glisse tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1268c93bb85bSJerome Glisse tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1269c93bb85bSJerome Glisse if (mode1) 1270c93bb85bSJerome Glisse tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1271c93bb85bSJerome Glisse if (mode0) 1272c93bb85bSJerome Glisse tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1273c93bb85bSJerome Glisse WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1274c93bb85bSJerome Glisse } 1275c93bb85bSJerome Glisse rv515_bandwidth_avivo_update(rdev); 1276c93bb85bSJerome Glisse } 1277