1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse #include <linux/seq_file.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 30771fe6b9SJerome Glisse #include "drmP.h" 313ce0a23dSJerome Glisse #include "rv515d.h" 32771fe6b9SJerome Glisse #include "radeon.h" 33e6990375SDaniel Vetter #include "radeon_asic.h" 34d39c3b89SJerome Glisse #include "atom.h" 3550f15303SDave Airlie #include "rv515_reg_safe.h" 36771fe6b9SJerome Glisse 37d39c3b89SJerome Glisse /* This files gather functions specifics to: rv515 */ 38771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev); 41771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42771fe6b9SJerome Glisse 43f0ed1f65SJerome Glisse void rv515_debugfs(struct radeon_device *rdev) 44771fe6b9SJerome Glisse { 45771fe6b9SJerome Glisse if (r100_debugfs_rbbm_init(rdev)) { 46771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 47771fe6b9SJerome Glisse } 48771fe6b9SJerome Glisse if (rv515_debugfs_pipes_info_init(rdev)) { 49771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 50771fe6b9SJerome Glisse } 51771fe6b9SJerome Glisse if (rv515_debugfs_ga_info_init(rdev)) { 52771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 53771fe6b9SJerome Glisse } 54771fe6b9SJerome Glisse } 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse void rv515_ring_start(struct radeon_device *rdev) 57771fe6b9SJerome Glisse { 58e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 59771fe6b9SJerome Glisse int r; 60771fe6b9SJerome Glisse 61e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 64); 62771fe6b9SJerome Glisse if (r) { 63771fe6b9SJerome Glisse return; 64771fe6b9SJerome Glisse } 65e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 66e32eb50dSChristian König radeon_ring_write(ring, 67c93bb85bSJerome Glisse ISYNC_ANY2D_IDLE3D | 68c93bb85bSJerome Glisse ISYNC_ANY3D_IDLE2D | 69c93bb85bSJerome Glisse ISYNC_WAIT_IDLEGUI | 70c93bb85bSJerome Glisse ISYNC_CPSCRATCH_IDLEGUI); 71e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 72e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 73e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 74e32eb50dSChristian König radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 75e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 76e32eb50dSChristian König radeon_ring_write(ring, 0); 77e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 78e32eb50dSChristian König radeon_ring_write(ring, 0); 79e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 80e32eb50dSChristian König radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 81e32eb50dSChristian König radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 82e32eb50dSChristian König radeon_ring_write(ring, 0); 83e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 84e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 85e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 86e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 87e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 88e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 89e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 90e32eb50dSChristian König radeon_ring_write(ring, 0); 91e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 92e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 93e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 94e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 95e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 96e32eb50dSChristian König radeon_ring_write(ring, 97c93bb85bSJerome Glisse ((6 << MS_X0_SHIFT) | 98c93bb85bSJerome Glisse (6 << MS_Y0_SHIFT) | 99c93bb85bSJerome Glisse (6 << MS_X1_SHIFT) | 100c93bb85bSJerome Glisse (6 << MS_Y1_SHIFT) | 101c93bb85bSJerome Glisse (6 << MS_X2_SHIFT) | 102c93bb85bSJerome Glisse (6 << MS_Y2_SHIFT) | 103c93bb85bSJerome Glisse (6 << MSBD0_Y_SHIFT) | 104c93bb85bSJerome Glisse (6 << MSBD0_X_SHIFT))); 105e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 106e32eb50dSChristian König radeon_ring_write(ring, 107c93bb85bSJerome Glisse ((6 << MS_X3_SHIFT) | 108c93bb85bSJerome Glisse (6 << MS_Y3_SHIFT) | 109c93bb85bSJerome Glisse (6 << MS_X4_SHIFT) | 110c93bb85bSJerome Glisse (6 << MS_Y4_SHIFT) | 111c93bb85bSJerome Glisse (6 << MS_X5_SHIFT) | 112c93bb85bSJerome Glisse (6 << MS_Y5_SHIFT) | 113c93bb85bSJerome Glisse (6 << MSBD1_SHIFT))); 114e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 115e32eb50dSChristian König radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 116e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 117e32eb50dSChristian König radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 118e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 119e32eb50dSChristian König radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 120e32eb50dSChristian König radeon_ring_write(ring, PACKET0(0x20C8, 0)); 121e32eb50dSChristian König radeon_ring_write(ring, 0); 122e32eb50dSChristian König radeon_ring_unlock_commit(rdev, ring); 123771fe6b9SJerome Glisse } 124771fe6b9SJerome Glisse 125771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev) 126771fe6b9SJerome Glisse { 127771fe6b9SJerome Glisse unsigned i; 128771fe6b9SJerome Glisse uint32_t tmp; 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 131771fe6b9SJerome Glisse /* read MC_STATUS */ 132c93bb85bSJerome Glisse tmp = RREG32_MC(MC_STATUS); 133c93bb85bSJerome Glisse if (tmp & MC_STATUS_IDLE) { 134771fe6b9SJerome Glisse return 0; 135771fe6b9SJerome Glisse } 136771fe6b9SJerome Glisse DRM_UDELAY(1); 137771fe6b9SJerome Glisse } 138771fe6b9SJerome Glisse return -1; 139771fe6b9SJerome Glisse } 140771fe6b9SJerome Glisse 141d39c3b89SJerome Glisse void rv515_vga_render_disable(struct radeon_device *rdev) 142d39c3b89SJerome Glisse { 143d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 144d39c3b89SJerome Glisse RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 145d39c3b89SJerome Glisse } 146d39c3b89SJerome Glisse 147771fe6b9SJerome Glisse void rv515_gpu_init(struct radeon_device *rdev) 148771fe6b9SJerome Glisse { 149771fe6b9SJerome Glisse unsigned pipe_select_current, gb_pipe_select, tmp; 150771fe6b9SJerome Glisse 151771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 152771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 153481e6283SMasanari Iida "resetting GPU. Bad things might happen.\n"); 154771fe6b9SJerome Glisse } 155d39c3b89SJerome Glisse rv515_vga_render_disable(rdev); 156771fe6b9SJerome Glisse r420_pipes_init(rdev); 157d75ee3beSAlex Deucher gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 158d75ee3beSAlex Deucher tmp = RREG32(R300_DST_PIPE_CONFIG); 159771fe6b9SJerome Glisse pipe_select_current = (tmp >> 2) & 3; 160771fe6b9SJerome Glisse tmp = (1 << pipe_select_current) | 161771fe6b9SJerome Glisse (((gb_pipe_select >> 8) & 0xF) << 4); 162771fe6b9SJerome Glisse WREG32_PLL(0x000D, tmp); 163771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 164771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 165481e6283SMasanari Iida "resetting GPU. Bad things might happen.\n"); 166771fe6b9SJerome Glisse } 167771fe6b9SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) { 168771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait MC idle while " 169771fe6b9SJerome Glisse "programming pipes. Bad things might happen.\n"); 170771fe6b9SJerome Glisse } 171771fe6b9SJerome Glisse } 172771fe6b9SJerome Glisse 173771fe6b9SJerome Glisse static void rv515_vram_get_type(struct radeon_device *rdev) 174771fe6b9SJerome Glisse { 175771fe6b9SJerome Glisse uint32_t tmp; 176771fe6b9SJerome Glisse 177771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 178771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 179c93bb85bSJerome Glisse tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 180771fe6b9SJerome Glisse switch (tmp) { 181771fe6b9SJerome Glisse case 0: 182771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 183771fe6b9SJerome Glisse break; 184771fe6b9SJerome Glisse case 1: 185771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 186771fe6b9SJerome Glisse break; 187771fe6b9SJerome Glisse default: 188771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 189771fe6b9SJerome Glisse break; 190771fe6b9SJerome Glisse } 191771fe6b9SJerome Glisse } 192771fe6b9SJerome Glisse 193d594e46aSJerome Glisse void rv515_mc_init(struct radeon_device *rdev) 194771fe6b9SJerome Glisse { 195771fe6b9SJerome Glisse 196c93bb85bSJerome Glisse rv515_vram_get_type(rdev); 1970924d942SDave Airlie r100_vram_init_sizes(rdev); 198d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, 0); 1998d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 200d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 201d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 202f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 203771fe6b9SJerome Glisse } 204771fe6b9SJerome Glisse 205771fe6b9SJerome Glisse uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 206771fe6b9SJerome Glisse { 207771fe6b9SJerome Glisse uint32_t r; 208771fe6b9SJerome Glisse 209c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 210c93bb85bSJerome Glisse r = RREG32(MC_IND_DATA); 211c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 212771fe6b9SJerome Glisse return r; 213771fe6b9SJerome Glisse } 214771fe6b9SJerome Glisse 215771fe6b9SJerome Glisse void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 216771fe6b9SJerome Glisse { 217c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 218c93bb85bSJerome Glisse WREG32(MC_IND_DATA, (v)); 219c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 220771fe6b9SJerome Glisse } 221771fe6b9SJerome Glisse 222771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 223771fe6b9SJerome Glisse static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 224771fe6b9SJerome Glisse { 225771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 226771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 227771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 228771fe6b9SJerome Glisse uint32_t tmp; 229771fe6b9SJerome Glisse 230c93bb85bSJerome Glisse tmp = RREG32(GB_PIPE_SELECT); 231771fe6b9SJerome Glisse seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 232c93bb85bSJerome Glisse tmp = RREG32(SU_REG_DEST); 233771fe6b9SJerome Glisse seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 234c93bb85bSJerome Glisse tmp = RREG32(GB_TILE_CONFIG); 235771fe6b9SJerome Glisse seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 236c93bb85bSJerome Glisse tmp = RREG32(DST_PIPE_CONFIG); 237771fe6b9SJerome Glisse seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 238771fe6b9SJerome Glisse return 0; 239771fe6b9SJerome Glisse } 240771fe6b9SJerome Glisse 241771fe6b9SJerome Glisse static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 242771fe6b9SJerome Glisse { 243771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 244771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 245771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 246771fe6b9SJerome Glisse uint32_t tmp; 247771fe6b9SJerome Glisse 248771fe6b9SJerome Glisse tmp = RREG32(0x2140); 249771fe6b9SJerome Glisse seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 250a2d07b74SJerome Glisse radeon_asic_reset(rdev); 251771fe6b9SJerome Glisse tmp = RREG32(0x425C); 252771fe6b9SJerome Glisse seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 253771fe6b9SJerome Glisse return 0; 254771fe6b9SJerome Glisse } 255771fe6b9SJerome Glisse 256771fe6b9SJerome Glisse static struct drm_info_list rv515_pipes_info_list[] = { 257771fe6b9SJerome Glisse {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 258771fe6b9SJerome Glisse }; 259771fe6b9SJerome Glisse 260771fe6b9SJerome Glisse static struct drm_info_list rv515_ga_info_list[] = { 261771fe6b9SJerome Glisse {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 262771fe6b9SJerome Glisse }; 263771fe6b9SJerome Glisse #endif 264771fe6b9SJerome Glisse 265771fe6b9SJerome Glisse int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 266771fe6b9SJerome Glisse { 267771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 268771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 269771fe6b9SJerome Glisse #else 270771fe6b9SJerome Glisse return 0; 271771fe6b9SJerome Glisse #endif 272771fe6b9SJerome Glisse } 273771fe6b9SJerome Glisse 274771fe6b9SJerome Glisse int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 275771fe6b9SJerome Glisse { 276771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 277771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 278771fe6b9SJerome Glisse #else 279771fe6b9SJerome Glisse return 0; 280771fe6b9SJerome Glisse #endif 281771fe6b9SJerome Glisse } 282068a117cSJerome Glisse 283d39c3b89SJerome Glisse void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 284d39c3b89SJerome Glisse { 285d39c3b89SJerome Glisse save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); 286d39c3b89SJerome Glisse save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); 287d39c3b89SJerome Glisse save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 288d39c3b89SJerome Glisse save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 289d39c3b89SJerome Glisse save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); 290d39c3b89SJerome Glisse save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 291d39c3b89SJerome Glisse 292d39c3b89SJerome Glisse /* Stop all video */ 293d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 294d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 0); 295d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 296d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 297d39c3b89SJerome Glisse WREG32(R_006080_D1CRTC_CONTROL, 0); 298d39c3b89SJerome Glisse WREG32(R_006880_D2CRTC_CONTROL, 0); 299d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 300d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 301ef630627SDave Airlie WREG32(R_000330_D1VGA_CONTROL, 0); 302ef630627SDave Airlie WREG32(R_000338_D2VGA_CONTROL, 0); 303d39c3b89SJerome Glisse } 304d39c3b89SJerome Glisse 305d39c3b89SJerome Glisse void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 306d39c3b89SJerome Glisse { 307d39c3b89SJerome Glisse WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 308d39c3b89SJerome Glisse WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 309d39c3b89SJerome Glisse WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 310d39c3b89SJerome Glisse WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 311d39c3b89SJerome Glisse WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 312d39c3b89SJerome Glisse /* Unlock host access */ 313d39c3b89SJerome Glisse WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 314d39c3b89SJerome Glisse mdelay(1); 315d39c3b89SJerome Glisse /* Restore video state */ 316ef630627SDave Airlie WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); 317ef630627SDave Airlie WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); 318d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 319d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 320d39c3b89SJerome Glisse WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 321d39c3b89SJerome Glisse WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 322d39c3b89SJerome Glisse WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 323d39c3b89SJerome Glisse WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 324d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 325d39c3b89SJerome Glisse } 326d39c3b89SJerome Glisse 327d39c3b89SJerome Glisse void rv515_mc_program(struct radeon_device *rdev) 328d39c3b89SJerome Glisse { 329d39c3b89SJerome Glisse struct rv515_mc_save save; 330d39c3b89SJerome Glisse 331d39c3b89SJerome Glisse /* Stops all mc clients */ 332d39c3b89SJerome Glisse rv515_mc_stop(rdev, &save); 333d39c3b89SJerome Glisse 334d39c3b89SJerome Glisse /* Wait for mc idle */ 335d39c3b89SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) 336d39c3b89SJerome Glisse dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 337d39c3b89SJerome Glisse /* Write VRAM size in case we are limiting it */ 338d39c3b89SJerome Glisse WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 339d39c3b89SJerome Glisse /* Program MC, should be a 32bits limited address space */ 340d39c3b89SJerome Glisse WREG32_MC(R_000001_MC_FB_LOCATION, 341d39c3b89SJerome Glisse S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 342d39c3b89SJerome Glisse S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 343d39c3b89SJerome Glisse WREG32(R_000134_HDP_FB_LOCATION, 344d39c3b89SJerome Glisse S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 345d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 346d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 347d39c3b89SJerome Glisse S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 348d39c3b89SJerome Glisse S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 349d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 350d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 351d39c3b89SJerome Glisse S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 352d39c3b89SJerome Glisse } else { 353d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 354d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, 0); 355d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 356d39c3b89SJerome Glisse } 357d39c3b89SJerome Glisse 358d39c3b89SJerome Glisse rv515_mc_resume(rdev, &save); 359d39c3b89SJerome Glisse } 360d39c3b89SJerome Glisse 361d39c3b89SJerome Glisse void rv515_clock_startup(struct radeon_device *rdev) 362d39c3b89SJerome Glisse { 363d39c3b89SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 364d39c3b89SJerome Glisse radeon_atom_set_clock_gating(rdev, 1); 365d39c3b89SJerome Glisse /* We need to force on some of the block */ 366d39c3b89SJerome Glisse WREG32_PLL(R_00000F_CP_DYN_CNTL, 367d39c3b89SJerome Glisse RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 368d39c3b89SJerome Glisse WREG32_PLL(R_000011_E2_DYN_CNTL, 369d39c3b89SJerome Glisse RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 370d39c3b89SJerome Glisse WREG32_PLL(R_000013_IDCT_DYN_CNTL, 371d39c3b89SJerome Glisse RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 372d39c3b89SJerome Glisse } 373d39c3b89SJerome Glisse 374d39c3b89SJerome Glisse static int rv515_startup(struct radeon_device *rdev) 375d39c3b89SJerome Glisse { 376d39c3b89SJerome Glisse int r; 377d39c3b89SJerome Glisse 378d39c3b89SJerome Glisse rv515_mc_program(rdev); 379d39c3b89SJerome Glisse /* Resume clock */ 380d39c3b89SJerome Glisse rv515_clock_startup(rdev); 381d39c3b89SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 382d39c3b89SJerome Glisse rv515_gpu_init(rdev); 383d39c3b89SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 384d39c3b89SJerome Glisse * memory through TTM but finalize after TTM) */ 385d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) { 386d39c3b89SJerome Glisse r = rv370_pcie_gart_enable(rdev); 387d39c3b89SJerome Glisse if (r) 388d39c3b89SJerome Glisse return r; 389d39c3b89SJerome Glisse } 390724c80e1SAlex Deucher 391724c80e1SAlex Deucher /* allocate wb buffer */ 392724c80e1SAlex Deucher r = radeon_wb_init(rdev); 393724c80e1SAlex Deucher if (r) 394724c80e1SAlex Deucher return r; 395724c80e1SAlex Deucher 39630eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 39730eb77f4SJerome Glisse if (r) { 39830eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 39930eb77f4SJerome Glisse return r; 40030eb77f4SJerome Glisse } 40130eb77f4SJerome Glisse 402d39c3b89SJerome Glisse /* Enable IRQ */ 403ac447df4SJerome Glisse rs600_irq_set(rdev); 404cafe6609SJerome Glisse rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 405d39c3b89SJerome Glisse /* 1M ring buffer */ 406d39c3b89SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 407d39c3b89SJerome Glisse if (r) { 408ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 409d39c3b89SJerome Glisse return r; 410d39c3b89SJerome Glisse } 411b15ba512SJerome Glisse 412b15ba512SJerome Glisse r = radeon_ib_pool_start(rdev); 413b15ba512SJerome Glisse if (r) 414b15ba512SJerome Glisse return r; 415b15ba512SJerome Glisse 416b15ba512SJerome Glisse r = r100_ib_test(rdev); 417d39c3b89SJerome Glisse if (r) { 418b15ba512SJerome Glisse dev_err(rdev->dev, "failed testing IB (%d).\n", r); 419b15ba512SJerome Glisse rdev->accel_working = false; 420d39c3b89SJerome Glisse return r; 421d39c3b89SJerome Glisse } 422d39c3b89SJerome Glisse return 0; 423d39c3b89SJerome Glisse } 424d39c3b89SJerome Glisse 425d39c3b89SJerome Glisse int rv515_resume(struct radeon_device *rdev) 426d39c3b89SJerome Glisse { 427d39c3b89SJerome Glisse /* Make sur GART are not working */ 428d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 429d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 430d39c3b89SJerome Glisse /* Resume clock before doing reset */ 431d39c3b89SJerome Glisse rv515_clock_startup(rdev); 432d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 433a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 434d39c3b89SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 435d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 436d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 437d39c3b89SJerome Glisse } 438d39c3b89SJerome Glisse /* post */ 439d39c3b89SJerome Glisse atom_asic_init(rdev->mode_info.atom_context); 440d39c3b89SJerome Glisse /* Resume clock after posting */ 441d39c3b89SJerome Glisse rv515_clock_startup(rdev); 442550e2d92SDave Airlie /* Initialize surface registers */ 443550e2d92SDave Airlie radeon_surface_init(rdev); 444b15ba512SJerome Glisse 445b15ba512SJerome Glisse rdev->accel_working = true; 446d39c3b89SJerome Glisse return rv515_startup(rdev); 447d39c3b89SJerome Glisse } 448d39c3b89SJerome Glisse 449d39c3b89SJerome Glisse int rv515_suspend(struct radeon_device *rdev) 450d39c3b89SJerome Glisse { 451d39c3b89SJerome Glisse r100_cp_disable(rdev); 452724c80e1SAlex Deucher radeon_wb_disable(rdev); 453ac447df4SJerome Glisse rs600_irq_disable(rdev); 454d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 455d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 456d39c3b89SJerome Glisse return 0; 457d39c3b89SJerome Glisse } 458d39c3b89SJerome Glisse 459d39c3b89SJerome Glisse void rv515_set_safe_registers(struct radeon_device *rdev) 460068a117cSJerome Glisse { 46150f15303SDave Airlie rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 46250f15303SDave Airlie rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 463d39c3b89SJerome Glisse } 464d39c3b89SJerome Glisse 465d39c3b89SJerome Glisse void rv515_fini(struct radeon_device *rdev) 466d39c3b89SJerome Glisse { 467d39c3b89SJerome Glisse r100_cp_fini(rdev); 468724c80e1SAlex Deucher radeon_wb_fini(rdev); 469d39c3b89SJerome Glisse r100_ib_fini(rdev); 470d39c3b89SJerome Glisse radeon_gem_fini(rdev); 471d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 472d39c3b89SJerome Glisse radeon_agp_fini(rdev); 473d39c3b89SJerome Glisse radeon_irq_kms_fini(rdev); 474d39c3b89SJerome Glisse radeon_fence_driver_fini(rdev); 4754c788679SJerome Glisse radeon_bo_fini(rdev); 476d39c3b89SJerome Glisse radeon_atombios_fini(rdev); 477d39c3b89SJerome Glisse kfree(rdev->bios); 478d39c3b89SJerome Glisse rdev->bios = NULL; 479d39c3b89SJerome Glisse } 480d39c3b89SJerome Glisse 481d39c3b89SJerome Glisse int rv515_init(struct radeon_device *rdev) 482d39c3b89SJerome Glisse { 483d39c3b89SJerome Glisse int r; 484d39c3b89SJerome Glisse 485d39c3b89SJerome Glisse /* Initialize scratch registers */ 486d39c3b89SJerome Glisse radeon_scratch_init(rdev); 487d39c3b89SJerome Glisse /* Initialize surface registers */ 488d39c3b89SJerome Glisse radeon_surface_init(rdev); 489d39c3b89SJerome Glisse /* TODO: disable VGA need to use VGA request */ 4904c712e6cSDave Airlie /* restore some register to sane defaults */ 4914c712e6cSDave Airlie r100_restore_sanity(rdev); 492d39c3b89SJerome Glisse /* BIOS*/ 493d39c3b89SJerome Glisse if (!radeon_get_bios(rdev)) { 494d39c3b89SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 495d39c3b89SJerome Glisse return -EINVAL; 496d39c3b89SJerome Glisse } 497d39c3b89SJerome Glisse if (rdev->is_atom_bios) { 498d39c3b89SJerome Glisse r = radeon_atombios_init(rdev); 499d39c3b89SJerome Glisse if (r) 500d39c3b89SJerome Glisse return r; 501d39c3b89SJerome Glisse } else { 502d39c3b89SJerome Glisse dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 503d39c3b89SJerome Glisse return -EINVAL; 504d39c3b89SJerome Glisse } 505d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 506a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 507d39c3b89SJerome Glisse dev_warn(rdev->dev, 508d39c3b89SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 509d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 510d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 511d39c3b89SJerome Glisse } 512d39c3b89SJerome Glisse /* check if cards are posted or not */ 51372542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 51472542d77SDave Airlie return -EINVAL; 515d39c3b89SJerome Glisse /* Initialize clocks */ 516d39c3b89SJerome Glisse radeon_get_clock_info(rdev->ddev); 517d594e46aSJerome Glisse /* initialize AGP */ 518d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 519d594e46aSJerome Glisse r = radeon_agp_init(rdev); 520d594e46aSJerome Glisse if (r) { 521d594e46aSJerome Glisse radeon_agp_disable(rdev); 522d594e46aSJerome Glisse } 523d594e46aSJerome Glisse } 524d594e46aSJerome Glisse /* initialize memory controller */ 525d594e46aSJerome Glisse rv515_mc_init(rdev); 526d39c3b89SJerome Glisse rv515_debugfs(rdev); 527d39c3b89SJerome Glisse /* Fence driver */ 52830eb77f4SJerome Glisse r = radeon_fence_driver_init(rdev); 529d39c3b89SJerome Glisse if (r) 530d39c3b89SJerome Glisse return r; 531d39c3b89SJerome Glisse r = radeon_irq_kms_init(rdev); 532d39c3b89SJerome Glisse if (r) 533d39c3b89SJerome Glisse return r; 534d39c3b89SJerome Glisse /* Memory manager */ 5354c788679SJerome Glisse r = radeon_bo_init(rdev); 536d39c3b89SJerome Glisse if (r) 537d39c3b89SJerome Glisse return r; 538d39c3b89SJerome Glisse r = rv370_pcie_gart_init(rdev); 539d39c3b89SJerome Glisse if (r) 540d39c3b89SJerome Glisse return r; 541d39c3b89SJerome Glisse rv515_set_safe_registers(rdev); 542b15ba512SJerome Glisse 543b15ba512SJerome Glisse r = radeon_ib_pool_init(rdev); 544d39c3b89SJerome Glisse rdev->accel_working = true; 545b15ba512SJerome Glisse if (r) { 546b15ba512SJerome Glisse dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 547b15ba512SJerome Glisse rdev->accel_working = false; 548b15ba512SJerome Glisse } 549b15ba512SJerome Glisse 550d39c3b89SJerome Glisse r = rv515_startup(rdev); 551d39c3b89SJerome Glisse if (r) { 552d39c3b89SJerome Glisse /* Somethings want wront with the accel init stop accel */ 553d39c3b89SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 554d39c3b89SJerome Glisse r100_cp_fini(rdev); 555724c80e1SAlex Deucher radeon_wb_fini(rdev); 556d39c3b89SJerome Glisse r100_ib_fini(rdev); 557655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 558d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 559d39c3b89SJerome Glisse radeon_agp_fini(rdev); 560d39c3b89SJerome Glisse rdev->accel_working = false; 561d39c3b89SJerome Glisse } 562068a117cSJerome Glisse return 0; 563068a117cSJerome Glisse } 564c93bb85bSJerome Glisse 5654ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 566c93bb85bSJerome Glisse { 5674ce001abSDave Airlie int index_reg = 0x6578 + crtc->crtc_offset; 5684ce001abSDave Airlie int data_reg = 0x657c + crtc->crtc_offset; 569c93bb85bSJerome Glisse 5704ce001abSDave Airlie WREG32(0x659C + crtc->crtc_offset, 0x0); 5714ce001abSDave Airlie WREG32(0x6594 + crtc->crtc_offset, 0x705); 5724ce001abSDave Airlie WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 5734ce001abSDave Airlie WREG32(0x65D8 + crtc->crtc_offset, 0x0); 5744ce001abSDave Airlie WREG32(0x65B0 + crtc->crtc_offset, 0x0); 5754ce001abSDave Airlie WREG32(0x65C0 + crtc->crtc_offset, 0x0); 5764ce001abSDave Airlie WREG32(0x65D4 + crtc->crtc_offset, 0x0); 5774ce001abSDave Airlie WREG32(index_reg, 0x0); 5784ce001abSDave Airlie WREG32(data_reg, 0x841880A8); 5794ce001abSDave Airlie WREG32(index_reg, 0x1); 5804ce001abSDave Airlie WREG32(data_reg, 0x84208680); 5814ce001abSDave Airlie WREG32(index_reg, 0x2); 5824ce001abSDave Airlie WREG32(data_reg, 0xBFF880B0); 5834ce001abSDave Airlie WREG32(index_reg, 0x100); 5844ce001abSDave Airlie WREG32(data_reg, 0x83D88088); 5854ce001abSDave Airlie WREG32(index_reg, 0x101); 5864ce001abSDave Airlie WREG32(data_reg, 0x84608680); 5874ce001abSDave Airlie WREG32(index_reg, 0x102); 5884ce001abSDave Airlie WREG32(data_reg, 0xBFF080D0); 5894ce001abSDave Airlie WREG32(index_reg, 0x200); 5904ce001abSDave Airlie WREG32(data_reg, 0x83988068); 5914ce001abSDave Airlie WREG32(index_reg, 0x201); 5924ce001abSDave Airlie WREG32(data_reg, 0x84A08680); 5934ce001abSDave Airlie WREG32(index_reg, 0x202); 5944ce001abSDave Airlie WREG32(data_reg, 0xBFF080F8); 5954ce001abSDave Airlie WREG32(index_reg, 0x300); 5964ce001abSDave Airlie WREG32(data_reg, 0x83588058); 5974ce001abSDave Airlie WREG32(index_reg, 0x301); 5984ce001abSDave Airlie WREG32(data_reg, 0x84E08660); 5994ce001abSDave Airlie WREG32(index_reg, 0x302); 6004ce001abSDave Airlie WREG32(data_reg, 0xBFF88120); 6014ce001abSDave Airlie WREG32(index_reg, 0x400); 6024ce001abSDave Airlie WREG32(data_reg, 0x83188040); 6034ce001abSDave Airlie WREG32(index_reg, 0x401); 6044ce001abSDave Airlie WREG32(data_reg, 0x85008660); 6054ce001abSDave Airlie WREG32(index_reg, 0x402); 6064ce001abSDave Airlie WREG32(data_reg, 0xBFF88150); 6074ce001abSDave Airlie WREG32(index_reg, 0x500); 6084ce001abSDave Airlie WREG32(data_reg, 0x82D88030); 6094ce001abSDave Airlie WREG32(index_reg, 0x501); 6104ce001abSDave Airlie WREG32(data_reg, 0x85408640); 6114ce001abSDave Airlie WREG32(index_reg, 0x502); 6124ce001abSDave Airlie WREG32(data_reg, 0xBFF88180); 6134ce001abSDave Airlie WREG32(index_reg, 0x600); 6144ce001abSDave Airlie WREG32(data_reg, 0x82A08018); 6154ce001abSDave Airlie WREG32(index_reg, 0x601); 6164ce001abSDave Airlie WREG32(data_reg, 0x85808620); 6174ce001abSDave Airlie WREG32(index_reg, 0x602); 6184ce001abSDave Airlie WREG32(data_reg, 0xBFF081B8); 6194ce001abSDave Airlie WREG32(index_reg, 0x700); 6204ce001abSDave Airlie WREG32(data_reg, 0x82608010); 6214ce001abSDave Airlie WREG32(index_reg, 0x701); 6224ce001abSDave Airlie WREG32(data_reg, 0x85A08600); 6234ce001abSDave Airlie WREG32(index_reg, 0x702); 6244ce001abSDave Airlie WREG32(data_reg, 0x800081F0); 6254ce001abSDave Airlie WREG32(index_reg, 0x800); 6264ce001abSDave Airlie WREG32(data_reg, 0x8228BFF8); 6274ce001abSDave Airlie WREG32(index_reg, 0x801); 6284ce001abSDave Airlie WREG32(data_reg, 0x85E085E0); 6294ce001abSDave Airlie WREG32(index_reg, 0x802); 6304ce001abSDave Airlie WREG32(data_reg, 0xBFF88228); 6314ce001abSDave Airlie WREG32(index_reg, 0x10000); 6324ce001abSDave Airlie WREG32(data_reg, 0x82A8BF00); 6334ce001abSDave Airlie WREG32(index_reg, 0x10001); 6344ce001abSDave Airlie WREG32(data_reg, 0x82A08CC0); 6354ce001abSDave Airlie WREG32(index_reg, 0x10002); 6364ce001abSDave Airlie WREG32(data_reg, 0x8008BEF8); 6374ce001abSDave Airlie WREG32(index_reg, 0x10100); 6384ce001abSDave Airlie WREG32(data_reg, 0x81F0BF28); 6394ce001abSDave Airlie WREG32(index_reg, 0x10101); 6404ce001abSDave Airlie WREG32(data_reg, 0x83608CA0); 6414ce001abSDave Airlie WREG32(index_reg, 0x10102); 6424ce001abSDave Airlie WREG32(data_reg, 0x8018BED0); 6434ce001abSDave Airlie WREG32(index_reg, 0x10200); 6444ce001abSDave Airlie WREG32(data_reg, 0x8148BF38); 6454ce001abSDave Airlie WREG32(index_reg, 0x10201); 6464ce001abSDave Airlie WREG32(data_reg, 0x84408C80); 6474ce001abSDave Airlie WREG32(index_reg, 0x10202); 6484ce001abSDave Airlie WREG32(data_reg, 0x8008BEB8); 6494ce001abSDave Airlie WREG32(index_reg, 0x10300); 6504ce001abSDave Airlie WREG32(data_reg, 0x80B0BF78); 6514ce001abSDave Airlie WREG32(index_reg, 0x10301); 6524ce001abSDave Airlie WREG32(data_reg, 0x85008C20); 6534ce001abSDave Airlie WREG32(index_reg, 0x10302); 6544ce001abSDave Airlie WREG32(data_reg, 0x8020BEA0); 6554ce001abSDave Airlie WREG32(index_reg, 0x10400); 6564ce001abSDave Airlie WREG32(data_reg, 0x8028BF90); 6574ce001abSDave Airlie WREG32(index_reg, 0x10401); 6584ce001abSDave Airlie WREG32(data_reg, 0x85E08BC0); 6594ce001abSDave Airlie WREG32(index_reg, 0x10402); 6604ce001abSDave Airlie WREG32(data_reg, 0x8018BE90); 6614ce001abSDave Airlie WREG32(index_reg, 0x10500); 6624ce001abSDave Airlie WREG32(data_reg, 0xBFB8BFB0); 6634ce001abSDave Airlie WREG32(index_reg, 0x10501); 6644ce001abSDave Airlie WREG32(data_reg, 0x86C08B40); 6654ce001abSDave Airlie WREG32(index_reg, 0x10502); 6664ce001abSDave Airlie WREG32(data_reg, 0x8010BE90); 6674ce001abSDave Airlie WREG32(index_reg, 0x10600); 6684ce001abSDave Airlie WREG32(data_reg, 0xBF58BFC8); 6694ce001abSDave Airlie WREG32(index_reg, 0x10601); 6704ce001abSDave Airlie WREG32(data_reg, 0x87A08AA0); 6714ce001abSDave Airlie WREG32(index_reg, 0x10602); 6724ce001abSDave Airlie WREG32(data_reg, 0x8010BE98); 6734ce001abSDave Airlie WREG32(index_reg, 0x10700); 6744ce001abSDave Airlie WREG32(data_reg, 0xBF10BFF0); 6754ce001abSDave Airlie WREG32(index_reg, 0x10701); 6764ce001abSDave Airlie WREG32(data_reg, 0x886089E0); 6774ce001abSDave Airlie WREG32(index_reg, 0x10702); 6784ce001abSDave Airlie WREG32(data_reg, 0x8018BEB0); 6794ce001abSDave Airlie WREG32(index_reg, 0x10800); 6804ce001abSDave Airlie WREG32(data_reg, 0xBED8BFE8); 6814ce001abSDave Airlie WREG32(index_reg, 0x10801); 6824ce001abSDave Airlie WREG32(data_reg, 0x89408940); 6834ce001abSDave Airlie WREG32(index_reg, 0x10802); 6844ce001abSDave Airlie WREG32(data_reg, 0xBFE8BED8); 6854ce001abSDave Airlie WREG32(index_reg, 0x20000); 6864ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6874ce001abSDave Airlie WREG32(index_reg, 0x20001); 6884ce001abSDave Airlie WREG32(data_reg, 0x90008000); 6894ce001abSDave Airlie WREG32(index_reg, 0x20002); 6904ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6914ce001abSDave Airlie WREG32(index_reg, 0x20003); 6924ce001abSDave Airlie WREG32(data_reg, 0x80008000); 6934ce001abSDave Airlie WREG32(index_reg, 0x20100); 6944ce001abSDave Airlie WREG32(data_reg, 0x80108000); 6954ce001abSDave Airlie WREG32(index_reg, 0x20101); 6964ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF70); 6974ce001abSDave Airlie WREG32(index_reg, 0x20102); 6984ce001abSDave Airlie WREG32(data_reg, 0xBFE880C0); 6994ce001abSDave Airlie WREG32(index_reg, 0x20103); 7004ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7014ce001abSDave Airlie WREG32(index_reg, 0x20200); 7024ce001abSDave Airlie WREG32(data_reg, 0x8018BFF8); 7034ce001abSDave Airlie WREG32(index_reg, 0x20201); 7044ce001abSDave Airlie WREG32(data_reg, 0x8F80BF08); 7054ce001abSDave Airlie WREG32(index_reg, 0x20202); 7064ce001abSDave Airlie WREG32(data_reg, 0xBFD081A0); 7074ce001abSDave Airlie WREG32(index_reg, 0x20203); 7084ce001abSDave Airlie WREG32(data_reg, 0xBFF88000); 7094ce001abSDave Airlie WREG32(index_reg, 0x20300); 7104ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7114ce001abSDave Airlie WREG32(index_reg, 0x20301); 7124ce001abSDave Airlie WREG32(data_reg, 0x8EE0BEC0); 7134ce001abSDave Airlie WREG32(index_reg, 0x20302); 7144ce001abSDave Airlie WREG32(data_reg, 0xBFB082A0); 7154ce001abSDave Airlie WREG32(index_reg, 0x20303); 7164ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7174ce001abSDave Airlie WREG32(index_reg, 0x20400); 7184ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7194ce001abSDave Airlie WREG32(index_reg, 0x20401); 7204ce001abSDave Airlie WREG32(data_reg, 0x8E00BEA0); 7214ce001abSDave Airlie WREG32(index_reg, 0x20402); 7224ce001abSDave Airlie WREG32(data_reg, 0xBF8883C0); 7234ce001abSDave Airlie WREG32(index_reg, 0x20403); 7244ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7254ce001abSDave Airlie WREG32(index_reg, 0x20500); 7264ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7274ce001abSDave Airlie WREG32(index_reg, 0x20501); 7284ce001abSDave Airlie WREG32(data_reg, 0x8D00BE90); 7294ce001abSDave Airlie WREG32(index_reg, 0x20502); 7304ce001abSDave Airlie WREG32(data_reg, 0xBF588500); 7314ce001abSDave Airlie WREG32(index_reg, 0x20503); 7324ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7334ce001abSDave Airlie WREG32(index_reg, 0x20600); 7344ce001abSDave Airlie WREG32(data_reg, 0x80188000); 7354ce001abSDave Airlie WREG32(index_reg, 0x20601); 7364ce001abSDave Airlie WREG32(data_reg, 0x8BC0BE98); 7374ce001abSDave Airlie WREG32(index_reg, 0x20602); 7384ce001abSDave Airlie WREG32(data_reg, 0xBF308660); 7394ce001abSDave Airlie WREG32(index_reg, 0x20603); 7404ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7414ce001abSDave Airlie WREG32(index_reg, 0x20700); 7424ce001abSDave Airlie WREG32(data_reg, 0x80108000); 7434ce001abSDave Airlie WREG32(index_reg, 0x20701); 7444ce001abSDave Airlie WREG32(data_reg, 0x8A80BEB0); 7454ce001abSDave Airlie WREG32(index_reg, 0x20702); 7464ce001abSDave Airlie WREG32(data_reg, 0xBF0087C0); 7474ce001abSDave Airlie WREG32(index_reg, 0x20703); 7484ce001abSDave Airlie WREG32(data_reg, 0x80008008); 7494ce001abSDave Airlie WREG32(index_reg, 0x20800); 7504ce001abSDave Airlie WREG32(data_reg, 0x80108000); 7514ce001abSDave Airlie WREG32(index_reg, 0x20801); 7524ce001abSDave Airlie WREG32(data_reg, 0x8920BED0); 7534ce001abSDave Airlie WREG32(index_reg, 0x20802); 7544ce001abSDave Airlie WREG32(data_reg, 0xBED08920); 7554ce001abSDave Airlie WREG32(index_reg, 0x20803); 7564ce001abSDave Airlie WREG32(data_reg, 0x80008010); 7574ce001abSDave Airlie WREG32(index_reg, 0x30000); 7584ce001abSDave Airlie WREG32(data_reg, 0x90008000); 7594ce001abSDave Airlie WREG32(index_reg, 0x30001); 7604ce001abSDave Airlie WREG32(data_reg, 0x80008000); 7614ce001abSDave Airlie WREG32(index_reg, 0x30100); 7624ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF90); 7634ce001abSDave Airlie WREG32(index_reg, 0x30101); 7644ce001abSDave Airlie WREG32(data_reg, 0xBFF880A0); 7654ce001abSDave Airlie WREG32(index_reg, 0x30200); 7664ce001abSDave Airlie WREG32(data_reg, 0x8F60BF40); 7674ce001abSDave Airlie WREG32(index_reg, 0x30201); 7684ce001abSDave Airlie WREG32(data_reg, 0xBFE88180); 7694ce001abSDave Airlie WREG32(index_reg, 0x30300); 7704ce001abSDave Airlie WREG32(data_reg, 0x8EC0BF00); 7714ce001abSDave Airlie WREG32(index_reg, 0x30301); 7724ce001abSDave Airlie WREG32(data_reg, 0xBFC88280); 7734ce001abSDave Airlie WREG32(index_reg, 0x30400); 7744ce001abSDave Airlie WREG32(data_reg, 0x8DE0BEE0); 7754ce001abSDave Airlie WREG32(index_reg, 0x30401); 7764ce001abSDave Airlie WREG32(data_reg, 0xBFA083A0); 7774ce001abSDave Airlie WREG32(index_reg, 0x30500); 7784ce001abSDave Airlie WREG32(data_reg, 0x8CE0BED0); 7794ce001abSDave Airlie WREG32(index_reg, 0x30501); 7804ce001abSDave Airlie WREG32(data_reg, 0xBF7884E0); 7814ce001abSDave Airlie WREG32(index_reg, 0x30600); 7824ce001abSDave Airlie WREG32(data_reg, 0x8BA0BED8); 7834ce001abSDave Airlie WREG32(index_reg, 0x30601); 7844ce001abSDave Airlie WREG32(data_reg, 0xBF508640); 7854ce001abSDave Airlie WREG32(index_reg, 0x30700); 7864ce001abSDave Airlie WREG32(data_reg, 0x8A60BEE8); 7874ce001abSDave Airlie WREG32(index_reg, 0x30701); 7884ce001abSDave Airlie WREG32(data_reg, 0xBF2087A0); 7894ce001abSDave Airlie WREG32(index_reg, 0x30800); 7904ce001abSDave Airlie WREG32(data_reg, 0x8900BF00); 7914ce001abSDave Airlie WREG32(index_reg, 0x30801); 7924ce001abSDave Airlie WREG32(data_reg, 0xBF008900); 793c93bb85bSJerome Glisse } 794c93bb85bSJerome Glisse 795c93bb85bSJerome Glisse struct rv515_watermark { 796c93bb85bSJerome Glisse u32 lb_request_fifo_depth; 797c93bb85bSJerome Glisse fixed20_12 num_line_pair; 798c93bb85bSJerome Glisse fixed20_12 estimated_width; 799c93bb85bSJerome Glisse fixed20_12 worst_case_latency; 800c93bb85bSJerome Glisse fixed20_12 consumption_rate; 801c93bb85bSJerome Glisse fixed20_12 active_time; 802c93bb85bSJerome Glisse fixed20_12 dbpp; 803c93bb85bSJerome Glisse fixed20_12 priority_mark_max; 804c93bb85bSJerome Glisse fixed20_12 priority_mark; 805c93bb85bSJerome Glisse fixed20_12 sclk; 806c93bb85bSJerome Glisse }; 807c93bb85bSJerome Glisse 808c93bb85bSJerome Glisse void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 809c93bb85bSJerome Glisse struct radeon_crtc *crtc, 810c93bb85bSJerome Glisse struct rv515_watermark *wm) 811c93bb85bSJerome Glisse { 812c93bb85bSJerome Glisse struct drm_display_mode *mode = &crtc->base.mode; 813c93bb85bSJerome Glisse fixed20_12 a, b, c; 814c93bb85bSJerome Glisse fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 815c93bb85bSJerome Glisse fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 816c93bb85bSJerome Glisse 817c93bb85bSJerome Glisse if (!crtc->base.enabled) { 818c93bb85bSJerome Glisse /* FIXME: wouldn't it better to set priority mark to maximum */ 819c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 820c93bb85bSJerome Glisse return; 821c93bb85bSJerome Glisse } 822c93bb85bSJerome Glisse 82368adac5eSBen Skeggs if (crtc->vsc.full > dfixed_const(2)) 82468adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(2); 825c93bb85bSJerome Glisse else 82668adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(1); 827c93bb85bSJerome Glisse 82868adac5eSBen Skeggs b.full = dfixed_const(mode->crtc_hdisplay); 82968adac5eSBen Skeggs c.full = dfixed_const(256); 83068adac5eSBen Skeggs a.full = dfixed_div(b, c); 83168adac5eSBen Skeggs request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 83268adac5eSBen Skeggs request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 83368adac5eSBen Skeggs if (a.full < dfixed_const(4)) { 834c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 835c93bb85bSJerome Glisse } else { 83668adac5eSBen Skeggs wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 837c93bb85bSJerome Glisse } 838c93bb85bSJerome Glisse 839c93bb85bSJerome Glisse /* Determine consumption rate 840c93bb85bSJerome Glisse * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 841c93bb85bSJerome Glisse * vtaps = number of vertical taps, 842c93bb85bSJerome Glisse * vsc = vertical scaling ratio, defined as source/destination 843c93bb85bSJerome Glisse * hsc = horizontal scaling ration, defined as source/destination 844c93bb85bSJerome Glisse */ 84568adac5eSBen Skeggs a.full = dfixed_const(mode->clock); 84668adac5eSBen Skeggs b.full = dfixed_const(1000); 84768adac5eSBen Skeggs a.full = dfixed_div(a, b); 84868adac5eSBen Skeggs pclk.full = dfixed_div(b, a); 849c93bb85bSJerome Glisse if (crtc->rmx_type != RMX_OFF) { 85068adac5eSBen Skeggs b.full = dfixed_const(2); 851c93bb85bSJerome Glisse if (crtc->vsc.full > b.full) 852c93bb85bSJerome Glisse b.full = crtc->vsc.full; 85368adac5eSBen Skeggs b.full = dfixed_mul(b, crtc->hsc); 85468adac5eSBen Skeggs c.full = dfixed_const(2); 85568adac5eSBen Skeggs b.full = dfixed_div(b, c); 85668adac5eSBen Skeggs consumption_time.full = dfixed_div(pclk, b); 857c93bb85bSJerome Glisse } else { 858c93bb85bSJerome Glisse consumption_time.full = pclk.full; 859c93bb85bSJerome Glisse } 86068adac5eSBen Skeggs a.full = dfixed_const(1); 86168adac5eSBen Skeggs wm->consumption_rate.full = dfixed_div(a, consumption_time); 862c93bb85bSJerome Glisse 863c93bb85bSJerome Glisse 864c93bb85bSJerome Glisse /* Determine line time 865c93bb85bSJerome Glisse * LineTime = total time for one line of displayhtotal 866c93bb85bSJerome Glisse * LineTime = total number of horizontal pixels 867c93bb85bSJerome Glisse * pclk = pixel clock period(ns) 868c93bb85bSJerome Glisse */ 86968adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 87068adac5eSBen Skeggs line_time.full = dfixed_mul(a, pclk); 871c93bb85bSJerome Glisse 872c93bb85bSJerome Glisse /* Determine active time 873c93bb85bSJerome Glisse * ActiveTime = time of active region of display within one line, 874c93bb85bSJerome Glisse * hactive = total number of horizontal active pixels 875c93bb85bSJerome Glisse * htotal = total number of horizontal pixels 876c93bb85bSJerome Glisse */ 87768adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 87868adac5eSBen Skeggs b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 87968adac5eSBen Skeggs wm->active_time.full = dfixed_mul(line_time, b); 88068adac5eSBen Skeggs wm->active_time.full = dfixed_div(wm->active_time, a); 881c93bb85bSJerome Glisse 882c93bb85bSJerome Glisse /* Determine chunk time 883c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk of data 884c93bb85bSJerome Glisse * to the LB which consists of pipeline delay and inter chunk gap 885c93bb85bSJerome Glisse * sclk = system clock(Mhz) 886c93bb85bSJerome Glisse */ 88768adac5eSBen Skeggs a.full = dfixed_const(600 * 1000); 88868adac5eSBen Skeggs chunk_time.full = dfixed_div(a, rdev->pm.sclk); 88968adac5eSBen Skeggs read_delay_latency.full = dfixed_const(1000); 890c93bb85bSJerome Glisse 891c93bb85bSJerome Glisse /* Determine the worst case latency 892c93bb85bSJerome Glisse * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 893c93bb85bSJerome Glisse * WorstCaseLatency = worst case time from urgent to when the MC starts 894c93bb85bSJerome Glisse * to return data 895c93bb85bSJerome Glisse * READ_DELAY_IDLE_MAX = constant of 1us 896c93bb85bSJerome Glisse * ChunkTime = time it takes the DCP to send one chunk of data to the LB 897c93bb85bSJerome Glisse * which consists of pipeline delay and inter chunk gap 898c93bb85bSJerome Glisse */ 89968adac5eSBen Skeggs if (dfixed_trunc(wm->num_line_pair) > 1) { 90068adac5eSBen Skeggs a.full = dfixed_const(3); 90168adac5eSBen Skeggs wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 902c93bb85bSJerome Glisse wm->worst_case_latency.full += read_delay_latency.full; 903c93bb85bSJerome Glisse } else { 904c93bb85bSJerome Glisse wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 905c93bb85bSJerome Glisse } 906c93bb85bSJerome Glisse 907c93bb85bSJerome Glisse /* Determine the tolerable latency 908c93bb85bSJerome Glisse * TolerableLatency = Any given request has only 1 line time 909c93bb85bSJerome Glisse * for the data to be returned 910c93bb85bSJerome Glisse * LBRequestFifoDepth = Number of chunk requests the LB can 911c93bb85bSJerome Glisse * put into the request FIFO for a display 912c93bb85bSJerome Glisse * LineTime = total time for one line of display 913c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk 914c93bb85bSJerome Glisse * of data to the LB which consists of 915c93bb85bSJerome Glisse * pipeline delay and inter chunk gap 916c93bb85bSJerome Glisse */ 91768adac5eSBen Skeggs if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 918c93bb85bSJerome Glisse tolerable_latency.full = line_time.full; 919c93bb85bSJerome Glisse } else { 92068adac5eSBen Skeggs tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 921c93bb85bSJerome Glisse tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 92268adac5eSBen Skeggs tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 923c93bb85bSJerome Glisse tolerable_latency.full = line_time.full - tolerable_latency.full; 924c93bb85bSJerome Glisse } 925c93bb85bSJerome Glisse /* We assume worst case 32bits (4 bytes) */ 92668adac5eSBen Skeggs wm->dbpp.full = dfixed_const(2 * 16); 927c93bb85bSJerome Glisse 928c93bb85bSJerome Glisse /* Determine the maximum priority mark 929c93bb85bSJerome Glisse * width = viewport width in pixels 930c93bb85bSJerome Glisse */ 93168adac5eSBen Skeggs a.full = dfixed_const(16); 93268adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 93368adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 93468adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 935c93bb85bSJerome Glisse 936c93bb85bSJerome Glisse /* Determine estimated width */ 937c93bb85bSJerome Glisse estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 93868adac5eSBen Skeggs estimated_width.full = dfixed_div(estimated_width, consumption_time); 93968adac5eSBen Skeggs if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 94069b3b5e5SAlex Deucher wm->priority_mark.full = wm->priority_mark_max.full; 941c93bb85bSJerome Glisse } else { 94268adac5eSBen Skeggs a.full = dfixed_const(16); 94368adac5eSBen Skeggs wm->priority_mark.full = dfixed_div(estimated_width, a); 94468adac5eSBen Skeggs wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 945c93bb85bSJerome Glisse wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 946c93bb85bSJerome Glisse } 947c93bb85bSJerome Glisse } 948c93bb85bSJerome Glisse 949c93bb85bSJerome Glisse void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 950c93bb85bSJerome Glisse { 951c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 952c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 953c93bb85bSJerome Glisse struct rv515_watermark wm0; 954c93bb85bSJerome Glisse struct rv515_watermark wm1; 955e06b14eeSAlex Deucher u32 tmp; 956e06b14eeSAlex Deucher u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 957e06b14eeSAlex Deucher u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 958c93bb85bSJerome Glisse fixed20_12 priority_mark02, priority_mark12, fill_rate; 959c93bb85bSJerome Glisse fixed20_12 a, b; 960c93bb85bSJerome Glisse 961c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 962c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 963c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 964c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 965c93bb85bSJerome Glisse rs690_line_buffer_adjust(rdev, mode0, mode1); 966c93bb85bSJerome Glisse 967c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 968c93bb85bSJerome Glisse rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 969c93bb85bSJerome Glisse 970c93bb85bSJerome Glisse tmp = wm0.lb_request_fifo_depth; 971c93bb85bSJerome Glisse tmp |= wm1.lb_request_fifo_depth << 16; 972c93bb85bSJerome Glisse WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 973c93bb85bSJerome Glisse 974c93bb85bSJerome Glisse if (mode0 && mode1) { 97568adac5eSBen Skeggs if (dfixed_trunc(wm0.dbpp) > 64) 97668adac5eSBen Skeggs a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 977c93bb85bSJerome Glisse else 978c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 97968adac5eSBen Skeggs if (dfixed_trunc(wm1.dbpp) > 64) 98068adac5eSBen Skeggs b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 981c93bb85bSJerome Glisse else 982c93bb85bSJerome Glisse b.full = wm1.num_line_pair.full; 983c93bb85bSJerome Glisse a.full += b.full; 98468adac5eSBen Skeggs fill_rate.full = dfixed_div(wm0.sclk, a); 985c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 986c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 98768adac5eSBen Skeggs b.full = dfixed_mul(b, wm0.active_time); 98868adac5eSBen Skeggs a.full = dfixed_const(16); 98968adac5eSBen Skeggs b.full = dfixed_div(b, a); 99068adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 991c93bb85bSJerome Glisse wm0.consumption_rate); 992c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 993c93bb85bSJerome Glisse } else { 99468adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 995c93bb85bSJerome Glisse wm0.consumption_rate); 99668adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 99768adac5eSBen Skeggs priority_mark02.full = dfixed_div(a, b); 998c93bb85bSJerome Glisse } 999c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 1000c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 100168adac5eSBen Skeggs b.full = dfixed_mul(b, wm1.active_time); 100268adac5eSBen Skeggs a.full = dfixed_const(16); 100368adac5eSBen Skeggs b.full = dfixed_div(b, a); 100468adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1005c93bb85bSJerome Glisse wm1.consumption_rate); 1006c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 1007c93bb85bSJerome Glisse } else { 100868adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1009c93bb85bSJerome Glisse wm1.consumption_rate); 101068adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 101168adac5eSBen Skeggs priority_mark12.full = dfixed_div(a, b); 1012c93bb85bSJerome Glisse } 1013c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 1014c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 101568adac5eSBen Skeggs if (dfixed_trunc(priority_mark02) < 0) 1016c93bb85bSJerome Glisse priority_mark02.full = 0; 1017c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1018c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 1019c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1020c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 102168adac5eSBen Skeggs if (dfixed_trunc(priority_mark12) < 0) 1022c93bb85bSJerome Glisse priority_mark12.full = 0; 1023c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1024c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 102568adac5eSBen Skeggs d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 102668adac5eSBen Skeggs d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1027f46c0120SAlex Deucher if (rdev->disp_priority == 2) { 1028f46c0120SAlex Deucher d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1029f46c0120SAlex Deucher d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1030f46c0120SAlex Deucher } 1031c93bb85bSJerome Glisse } else if (mode0) { 103268adac5eSBen Skeggs if (dfixed_trunc(wm0.dbpp) > 64) 103368adac5eSBen Skeggs a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1034c93bb85bSJerome Glisse else 1035c93bb85bSJerome Glisse a.full = wm0.num_line_pair.full; 103668adac5eSBen Skeggs fill_rate.full = dfixed_div(wm0.sclk, a); 1037c93bb85bSJerome Glisse if (wm0.consumption_rate.full > fill_rate.full) { 1038c93bb85bSJerome Glisse b.full = wm0.consumption_rate.full - fill_rate.full; 103968adac5eSBen Skeggs b.full = dfixed_mul(b, wm0.active_time); 104068adac5eSBen Skeggs a.full = dfixed_const(16); 104168adac5eSBen Skeggs b.full = dfixed_div(b, a); 104268adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 1043c93bb85bSJerome Glisse wm0.consumption_rate); 1044c93bb85bSJerome Glisse priority_mark02.full = a.full + b.full; 1045c93bb85bSJerome Glisse } else { 104668adac5eSBen Skeggs a.full = dfixed_mul(wm0.worst_case_latency, 1047c93bb85bSJerome Glisse wm0.consumption_rate); 104868adac5eSBen Skeggs b.full = dfixed_const(16); 104968adac5eSBen Skeggs priority_mark02.full = dfixed_div(a, b); 1050c93bb85bSJerome Glisse } 1051c93bb85bSJerome Glisse if (wm0.priority_mark.full > priority_mark02.full) 1052c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark.full; 105368adac5eSBen Skeggs if (dfixed_trunc(priority_mark02) < 0) 1054c93bb85bSJerome Glisse priority_mark02.full = 0; 1055c93bb85bSJerome Glisse if (wm0.priority_mark_max.full > priority_mark02.full) 1056c93bb85bSJerome Glisse priority_mark02.full = wm0.priority_mark_max.full; 105768adac5eSBen Skeggs d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1058f46c0120SAlex Deucher if (rdev->disp_priority == 2) 1059f46c0120SAlex Deucher d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1060e06b14eeSAlex Deucher } else if (mode1) { 106168adac5eSBen Skeggs if (dfixed_trunc(wm1.dbpp) > 64) 106268adac5eSBen Skeggs a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1063c93bb85bSJerome Glisse else 1064c93bb85bSJerome Glisse a.full = wm1.num_line_pair.full; 106568adac5eSBen Skeggs fill_rate.full = dfixed_div(wm1.sclk, a); 1066c93bb85bSJerome Glisse if (wm1.consumption_rate.full > fill_rate.full) { 1067c93bb85bSJerome Glisse b.full = wm1.consumption_rate.full - fill_rate.full; 106868adac5eSBen Skeggs b.full = dfixed_mul(b, wm1.active_time); 106968adac5eSBen Skeggs a.full = dfixed_const(16); 107068adac5eSBen Skeggs b.full = dfixed_div(b, a); 107168adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1072c93bb85bSJerome Glisse wm1.consumption_rate); 1073c93bb85bSJerome Glisse priority_mark12.full = a.full + b.full; 1074c93bb85bSJerome Glisse } else { 107568adac5eSBen Skeggs a.full = dfixed_mul(wm1.worst_case_latency, 1076c93bb85bSJerome Glisse wm1.consumption_rate); 107768adac5eSBen Skeggs b.full = dfixed_const(16 * 1000); 107868adac5eSBen Skeggs priority_mark12.full = dfixed_div(a, b); 1079c93bb85bSJerome Glisse } 1080c93bb85bSJerome Glisse if (wm1.priority_mark.full > priority_mark12.full) 1081c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark.full; 108268adac5eSBen Skeggs if (dfixed_trunc(priority_mark12) < 0) 1083c93bb85bSJerome Glisse priority_mark12.full = 0; 1084c93bb85bSJerome Glisse if (wm1.priority_mark_max.full > priority_mark12.full) 1085c93bb85bSJerome Glisse priority_mark12.full = wm1.priority_mark_max.full; 108668adac5eSBen Skeggs d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1087f46c0120SAlex Deucher if (rdev->disp_priority == 2) 1088f46c0120SAlex Deucher d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1089e06b14eeSAlex Deucher } 1090e06b14eeSAlex Deucher 1091e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1092e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1093f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1094f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1095c93bb85bSJerome Glisse } 1096c93bb85bSJerome Glisse 1097c93bb85bSJerome Glisse void rv515_bandwidth_update(struct radeon_device *rdev) 1098c93bb85bSJerome Glisse { 1099c93bb85bSJerome Glisse uint32_t tmp; 1100c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1101c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1102c93bb85bSJerome Glisse 1103f46c0120SAlex Deucher radeon_update_display_priority(rdev); 1104f46c0120SAlex Deucher 1105c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1106c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1107c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1108c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1109c93bb85bSJerome Glisse /* 1110c93bb85bSJerome Glisse * Set display0/1 priority up in the memory controller for 1111c93bb85bSJerome Glisse * modes if the user specifies HIGH for displaypriority 1112c93bb85bSJerome Glisse * option. 1113c93bb85bSJerome Glisse */ 1114f46c0120SAlex Deucher if ((rdev->disp_priority == 2) && 1115f46c0120SAlex Deucher (rdev->family == CHIP_RV515)) { 1116c93bb85bSJerome Glisse tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1117c93bb85bSJerome Glisse tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1118c93bb85bSJerome Glisse tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1119c93bb85bSJerome Glisse if (mode1) 1120c93bb85bSJerome Glisse tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1121c93bb85bSJerome Glisse if (mode0) 1122c93bb85bSJerome Glisse tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1123c93bb85bSJerome Glisse WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1124c93bb85bSJerome Glisse } 1125c93bb85bSJerome Glisse rv515_bandwidth_avivo_update(rdev); 1126c93bb85bSJerome Glisse } 1127