1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse #include <linux/seq_file.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 30760285e7SDavid Howells #include <drm/drmP.h> 313ce0a23dSJerome Glisse #include "rv515d.h" 32771fe6b9SJerome Glisse #include "radeon.h" 33e6990375SDaniel Vetter #include "radeon_asic.h" 34d39c3b89SJerome Glisse #include "atom.h" 3550f15303SDave Airlie #include "rv515_reg_safe.h" 36771fe6b9SJerome Glisse 37d39c3b89SJerome Glisse /* This files gather functions specifics to: rv515 */ 381109ca09SLauri Kasanen static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 391109ca09SLauri Kasanen static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 401109ca09SLauri Kasanen static void rv515_gpu_init(struct radeon_device *rdev); 41771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42771fe6b9SJerome Glisse 436253e4c7SAlex Deucher static const u32 crtc_offsets[2] = 446253e4c7SAlex Deucher { 456253e4c7SAlex Deucher 0, 466253e4c7SAlex Deucher AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 476253e4c7SAlex Deucher }; 486253e4c7SAlex Deucher 49f0ed1f65SJerome Glisse void rv515_debugfs(struct radeon_device *rdev) 50771fe6b9SJerome Glisse { 51771fe6b9SJerome Glisse if (r100_debugfs_rbbm_init(rdev)) { 52771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 53771fe6b9SJerome Glisse } 54771fe6b9SJerome Glisse if (rv515_debugfs_pipes_info_init(rdev)) { 55771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 56771fe6b9SJerome Glisse } 57771fe6b9SJerome Glisse if (rv515_debugfs_ga_info_init(rdev)) { 58771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for pipes !\n"); 59771fe6b9SJerome Glisse } 60771fe6b9SJerome Glisse } 61771fe6b9SJerome Glisse 62f712812eSAlex Deucher void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 63771fe6b9SJerome Glisse { 64771fe6b9SJerome Glisse int r; 65771fe6b9SJerome Glisse 66e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 64); 67771fe6b9SJerome Glisse if (r) { 68771fe6b9SJerome Glisse return; 69771fe6b9SJerome Glisse } 70e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 71e32eb50dSChristian König radeon_ring_write(ring, 72c93bb85bSJerome Glisse ISYNC_ANY2D_IDLE3D | 73c93bb85bSJerome Glisse ISYNC_ANY3D_IDLE2D | 74c93bb85bSJerome Glisse ISYNC_WAIT_IDLEGUI | 75c93bb85bSJerome Glisse ISYNC_CPSCRATCH_IDLEGUI); 76e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 77e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 78e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 79e32eb50dSChristian König radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 80e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 81e32eb50dSChristian König radeon_ring_write(ring, 0); 82e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 83e32eb50dSChristian König radeon_ring_write(ring, 0); 84e32eb50dSChristian König radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 85e32eb50dSChristian König radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 86e32eb50dSChristian König radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 87e32eb50dSChristian König radeon_ring_write(ring, 0); 88e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 89e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 90e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 91e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 92e32eb50dSChristian König radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 93e32eb50dSChristian König radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 94e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 95e32eb50dSChristian König radeon_ring_write(ring, 0); 96e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 97e32eb50dSChristian König radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 98e32eb50dSChristian König radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 99e32eb50dSChristian König radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 100e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 101e32eb50dSChristian König radeon_ring_write(ring, 102c93bb85bSJerome Glisse ((6 << MS_X0_SHIFT) | 103c93bb85bSJerome Glisse (6 << MS_Y0_SHIFT) | 104c93bb85bSJerome Glisse (6 << MS_X1_SHIFT) | 105c93bb85bSJerome Glisse (6 << MS_Y1_SHIFT) | 106c93bb85bSJerome Glisse (6 << MS_X2_SHIFT) | 107c93bb85bSJerome Glisse (6 << MS_Y2_SHIFT) | 108c93bb85bSJerome Glisse (6 << MSBD0_Y_SHIFT) | 109c93bb85bSJerome Glisse (6 << MSBD0_X_SHIFT))); 110e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 111e32eb50dSChristian König radeon_ring_write(ring, 112c93bb85bSJerome Glisse ((6 << MS_X3_SHIFT) | 113c93bb85bSJerome Glisse (6 << MS_Y3_SHIFT) | 114c93bb85bSJerome Glisse (6 << MS_X4_SHIFT) | 115c93bb85bSJerome Glisse (6 << MS_Y4_SHIFT) | 116c93bb85bSJerome Glisse (6 << MS_X5_SHIFT) | 117c93bb85bSJerome Glisse (6 << MS_Y5_SHIFT) | 118c93bb85bSJerome Glisse (6 << MSBD1_SHIFT))); 119e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 120e32eb50dSChristian König radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 121e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 122e32eb50dSChristian König radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 123e32eb50dSChristian König radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 124e32eb50dSChristian König radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 125e32eb50dSChristian König radeon_ring_write(ring, PACKET0(0x20C8, 0)); 126e32eb50dSChristian König radeon_ring_write(ring, 0); 1271538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 128771fe6b9SJerome Glisse } 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse int rv515_mc_wait_for_idle(struct radeon_device *rdev) 131771fe6b9SJerome Glisse { 132771fe6b9SJerome Glisse unsigned i; 133771fe6b9SJerome Glisse uint32_t tmp; 134771fe6b9SJerome Glisse 135771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 136771fe6b9SJerome Glisse /* read MC_STATUS */ 137c93bb85bSJerome Glisse tmp = RREG32_MC(MC_STATUS); 138c93bb85bSJerome Glisse if (tmp & MC_STATUS_IDLE) { 139771fe6b9SJerome Glisse return 0; 140771fe6b9SJerome Glisse } 1410e1a351dSSam Ravnborg udelay(1); 142771fe6b9SJerome Glisse } 143771fe6b9SJerome Glisse return -1; 144771fe6b9SJerome Glisse } 145771fe6b9SJerome Glisse 146d39c3b89SJerome Glisse void rv515_vga_render_disable(struct radeon_device *rdev) 147d39c3b89SJerome Glisse { 148d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 149d39c3b89SJerome Glisse RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 150d39c3b89SJerome Glisse } 151d39c3b89SJerome Glisse 1521109ca09SLauri Kasanen static void rv515_gpu_init(struct radeon_device *rdev) 153771fe6b9SJerome Glisse { 154771fe6b9SJerome Glisse unsigned pipe_select_current, gb_pipe_select, tmp; 155771fe6b9SJerome Glisse 156771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 1577ca85295SJoe Perches pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 158771fe6b9SJerome Glisse } 159d39c3b89SJerome Glisse rv515_vga_render_disable(rdev); 160771fe6b9SJerome Glisse r420_pipes_init(rdev); 161d75ee3beSAlex Deucher gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 162d75ee3beSAlex Deucher tmp = RREG32(R300_DST_PIPE_CONFIG); 163771fe6b9SJerome Glisse pipe_select_current = (tmp >> 2) & 3; 164771fe6b9SJerome Glisse tmp = (1 << pipe_select_current) | 165771fe6b9SJerome Glisse (((gb_pipe_select >> 8) & 0xF) << 4); 166771fe6b9SJerome Glisse WREG32_PLL(0x000D, tmp); 167771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 1687ca85295SJoe Perches pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 169771fe6b9SJerome Glisse } 170771fe6b9SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) { 1717ca85295SJoe Perches pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 172771fe6b9SJerome Glisse } 173771fe6b9SJerome Glisse } 174771fe6b9SJerome Glisse 175771fe6b9SJerome Glisse static void rv515_vram_get_type(struct radeon_device *rdev) 176771fe6b9SJerome Glisse { 177771fe6b9SJerome Glisse uint32_t tmp; 178771fe6b9SJerome Glisse 179771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 180771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 181c93bb85bSJerome Glisse tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 182771fe6b9SJerome Glisse switch (tmp) { 183771fe6b9SJerome Glisse case 0: 184771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 185771fe6b9SJerome Glisse break; 186771fe6b9SJerome Glisse case 1: 187771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 188771fe6b9SJerome Glisse break; 189771fe6b9SJerome Glisse default: 190771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 191771fe6b9SJerome Glisse break; 192771fe6b9SJerome Glisse } 193771fe6b9SJerome Glisse } 194771fe6b9SJerome Glisse 1951109ca09SLauri Kasanen static void rv515_mc_init(struct radeon_device *rdev) 196771fe6b9SJerome Glisse { 197771fe6b9SJerome Glisse 198c93bb85bSJerome Glisse rv515_vram_get_type(rdev); 1990924d942SDave Airlie r100_vram_init_sizes(rdev); 200d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, 0); 2018d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 202d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 203d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 204f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 205771fe6b9SJerome Glisse } 206771fe6b9SJerome Glisse 207771fe6b9SJerome Glisse uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 208771fe6b9SJerome Glisse { 2090a5b7b0bSAlex Deucher unsigned long flags; 210771fe6b9SJerome Glisse uint32_t r; 211771fe6b9SJerome Glisse 2120a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->mc_idx_lock, flags); 213c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 214c93bb85bSJerome Glisse r = RREG32(MC_IND_DATA); 215c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 2160a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 2170a5b7b0bSAlex Deucher 218771fe6b9SJerome Glisse return r; 219771fe6b9SJerome Glisse } 220771fe6b9SJerome Glisse 221771fe6b9SJerome Glisse void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 222771fe6b9SJerome Glisse { 2230a5b7b0bSAlex Deucher unsigned long flags; 2240a5b7b0bSAlex Deucher 2250a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->mc_idx_lock, flags); 226c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 227c93bb85bSJerome Glisse WREG32(MC_IND_DATA, (v)); 228c93bb85bSJerome Glisse WREG32(MC_IND_INDEX, 0); 2290a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 230771fe6b9SJerome Glisse } 231771fe6b9SJerome Glisse 232771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 233771fe6b9SJerome Glisse static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 234771fe6b9SJerome Glisse { 235771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 236771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 237771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 238771fe6b9SJerome Glisse uint32_t tmp; 239771fe6b9SJerome Glisse 240c93bb85bSJerome Glisse tmp = RREG32(GB_PIPE_SELECT); 241771fe6b9SJerome Glisse seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 242c93bb85bSJerome Glisse tmp = RREG32(SU_REG_DEST); 243771fe6b9SJerome Glisse seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 244c93bb85bSJerome Glisse tmp = RREG32(GB_TILE_CONFIG); 245771fe6b9SJerome Glisse seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 246c93bb85bSJerome Glisse tmp = RREG32(DST_PIPE_CONFIG); 247771fe6b9SJerome Glisse seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 248771fe6b9SJerome Glisse return 0; 249771fe6b9SJerome Glisse } 250771fe6b9SJerome Glisse 251771fe6b9SJerome Glisse static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 252771fe6b9SJerome Glisse { 253771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 254771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 255771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 256771fe6b9SJerome Glisse uint32_t tmp; 257771fe6b9SJerome Glisse 258771fe6b9SJerome Glisse tmp = RREG32(0x2140); 259771fe6b9SJerome Glisse seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 260a2d07b74SJerome Glisse radeon_asic_reset(rdev); 261771fe6b9SJerome Glisse tmp = RREG32(0x425C); 262771fe6b9SJerome Glisse seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 263771fe6b9SJerome Glisse return 0; 264771fe6b9SJerome Glisse } 265771fe6b9SJerome Glisse 266771fe6b9SJerome Glisse static struct drm_info_list rv515_pipes_info_list[] = { 267771fe6b9SJerome Glisse {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 268771fe6b9SJerome Glisse }; 269771fe6b9SJerome Glisse 270771fe6b9SJerome Glisse static struct drm_info_list rv515_ga_info_list[] = { 271771fe6b9SJerome Glisse {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 272771fe6b9SJerome Glisse }; 273771fe6b9SJerome Glisse #endif 274771fe6b9SJerome Glisse 2751109ca09SLauri Kasanen static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 276771fe6b9SJerome Glisse { 277771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 278771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 279771fe6b9SJerome Glisse #else 280771fe6b9SJerome Glisse return 0; 281771fe6b9SJerome Glisse #endif 282771fe6b9SJerome Glisse } 283771fe6b9SJerome Glisse 2841109ca09SLauri Kasanen static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 285771fe6b9SJerome Glisse { 286771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 287771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 288771fe6b9SJerome Glisse #else 289771fe6b9SJerome Glisse return 0; 290771fe6b9SJerome Glisse #endif 291771fe6b9SJerome Glisse } 292068a117cSJerome Glisse 293d39c3b89SJerome Glisse void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 294d39c3b89SJerome Glisse { 2956253e4c7SAlex Deucher u32 crtc_enabled, tmp, frame_count, blackout; 2966253e4c7SAlex Deucher int i, j; 2976253e4c7SAlex Deucher 298d39c3b89SJerome Glisse save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 299d39c3b89SJerome Glisse save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 300d39c3b89SJerome Glisse 3016253e4c7SAlex Deucher /* disable VGA render */ 302d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, 0); 3036253e4c7SAlex Deucher /* blank the display controllers */ 3046253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3056253e4c7SAlex Deucher crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 3066253e4c7SAlex Deucher if (crtc_enabled) { 3076253e4c7SAlex Deucher save->crtc_enabled[i] = true; 3086253e4c7SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 3096253e4c7SAlex Deucher if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 3106253e4c7SAlex Deucher radeon_wait_for_vblank(rdev, i); 311e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 3126253e4c7SAlex Deucher tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 3136253e4c7SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 314e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 3156253e4c7SAlex Deucher } 3166253e4c7SAlex Deucher /* wait for the next frame */ 3176253e4c7SAlex Deucher frame_count = radeon_get_vblank_counter(rdev, i); 3186253e4c7SAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 3196253e4c7SAlex Deucher if (radeon_get_vblank_counter(rdev, i) != frame_count) 3206253e4c7SAlex Deucher break; 3216253e4c7SAlex Deucher udelay(1); 3226253e4c7SAlex Deucher } 323e884fc64SAlex Deucher 324e884fc64SAlex Deucher /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 325e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 326e884fc64SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 327e884fc64SAlex Deucher tmp &= ~AVIVO_CRTC_EN; 328e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 329e884fc64SAlex Deucher WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 330e884fc64SAlex Deucher save->crtc_enabled[i] = false; 331e884fc64SAlex Deucher /* ***** */ 3326253e4c7SAlex Deucher } else { 3336253e4c7SAlex Deucher save->crtc_enabled[i] = false; 3346253e4c7SAlex Deucher } 3356253e4c7SAlex Deucher } 3366253e4c7SAlex Deucher 3376253e4c7SAlex Deucher radeon_mc_wait_for_idle(rdev); 3386253e4c7SAlex Deucher 3396253e4c7SAlex Deucher if (rdev->family >= CHIP_R600) { 3406253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 3416253e4c7SAlex Deucher blackout = RREG32(R700_MC_CITF_CNTL); 3426253e4c7SAlex Deucher else 3436253e4c7SAlex Deucher blackout = RREG32(R600_CITF_CNTL); 3446253e4c7SAlex Deucher if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 3456253e4c7SAlex Deucher /* Block CPU access */ 3466253e4c7SAlex Deucher WREG32(R600_BIF_FB_EN, 0); 3476253e4c7SAlex Deucher /* blackout the MC */ 3486253e4c7SAlex Deucher blackout |= R600_BLACKOUT_MASK; 3496253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 3506253e4c7SAlex Deucher WREG32(R700_MC_CITF_CNTL, blackout); 3516253e4c7SAlex Deucher else 3526253e4c7SAlex Deucher WREG32(R600_CITF_CNTL, blackout); 3536253e4c7SAlex Deucher } 3546253e4c7SAlex Deucher } 35539dc9aabSAlex Deucher /* wait for the MC to settle */ 35639dc9aabSAlex Deucher udelay(100); 3572f86e2edSAlex Deucher 3582f86e2edSAlex Deucher /* lock double buffered regs */ 3592f86e2edSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3602f86e2edSAlex Deucher if (save->crtc_enabled[i]) { 3612f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 3622f86e2edSAlex Deucher if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 3632f86e2edSAlex Deucher tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 3642f86e2edSAlex Deucher WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 3652f86e2edSAlex Deucher } 3662f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 3672f86e2edSAlex Deucher if (!(tmp & 1)) { 3682f86e2edSAlex Deucher tmp |= 1; 3692f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 3702f86e2edSAlex Deucher } 3712f86e2edSAlex Deucher } 3722f86e2edSAlex Deucher } 373d39c3b89SJerome Glisse } 374d39c3b89SJerome Glisse 375d39c3b89SJerome Glisse void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 376d39c3b89SJerome Glisse { 3776253e4c7SAlex Deucher u32 tmp, frame_count; 3786253e4c7SAlex Deucher int i, j; 3796253e4c7SAlex Deucher 3806253e4c7SAlex Deucher /* update crtc base addresses */ 3816253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 3826253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) { 383367cbe2fSAlex Deucher if (i == 0) { 3846253e4c7SAlex Deucher WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 3856253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3866253e4c7SAlex Deucher WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 3876253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3886253e4c7SAlex Deucher } else { 3896253e4c7SAlex Deucher WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 3906253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3916253e4c7SAlex Deucher WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 3926253e4c7SAlex Deucher upper_32_bits(rdev->mc.vram_start)); 3936253e4c7SAlex Deucher } 3946253e4c7SAlex Deucher } 3956253e4c7SAlex Deucher WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 3966253e4c7SAlex Deucher (u32)rdev->mc.vram_start); 3976253e4c7SAlex Deucher WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 3986253e4c7SAlex Deucher (u32)rdev->mc.vram_start); 3996253e4c7SAlex Deucher } 4006253e4c7SAlex Deucher WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 4016253e4c7SAlex Deucher 4022f86e2edSAlex Deucher /* unlock regs and wait for update */ 4032f86e2edSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 4042f86e2edSAlex Deucher if (save->crtc_enabled[i]) { 4052f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 406f53f81b2SMario Kleiner if ((tmp & 0x7) != 3) { 407f53f81b2SMario Kleiner tmp &= ~0x7; 408f53f81b2SMario Kleiner tmp |= 0x3; 4092f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 4102f86e2edSAlex Deucher } 4112f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 4122f86e2edSAlex Deucher if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 4132f86e2edSAlex Deucher tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 4142f86e2edSAlex Deucher WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 4152f86e2edSAlex Deucher } 4162f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 4172f86e2edSAlex Deucher if (tmp & 1) { 4182f86e2edSAlex Deucher tmp &= ~1; 4192f86e2edSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 4202f86e2edSAlex Deucher } 4212f86e2edSAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 4222f86e2edSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 4232f86e2edSAlex Deucher if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 4242f86e2edSAlex Deucher break; 4252f86e2edSAlex Deucher udelay(1); 4262f86e2edSAlex Deucher } 4272f86e2edSAlex Deucher } 4282f86e2edSAlex Deucher } 4292f86e2edSAlex Deucher 4306253e4c7SAlex Deucher if (rdev->family >= CHIP_R600) { 4316253e4c7SAlex Deucher /* unblackout the MC */ 4326253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 4336253e4c7SAlex Deucher tmp = RREG32(R700_MC_CITF_CNTL); 4346253e4c7SAlex Deucher else 4356253e4c7SAlex Deucher tmp = RREG32(R600_CITF_CNTL); 4366253e4c7SAlex Deucher tmp &= ~R600_BLACKOUT_MASK; 4376253e4c7SAlex Deucher if (rdev->family >= CHIP_RV770) 4386253e4c7SAlex Deucher WREG32(R700_MC_CITF_CNTL, tmp); 4396253e4c7SAlex Deucher else 4406253e4c7SAlex Deucher WREG32(R600_CITF_CNTL, tmp); 4416253e4c7SAlex Deucher /* allow CPU access */ 4426253e4c7SAlex Deucher WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 4436253e4c7SAlex Deucher } 4446253e4c7SAlex Deucher 4456253e4c7SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 4466253e4c7SAlex Deucher if (save->crtc_enabled[i]) { 4476253e4c7SAlex Deucher tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 4486253e4c7SAlex Deucher tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 4496253e4c7SAlex Deucher WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 4506253e4c7SAlex Deucher /* wait for the next frame */ 4516253e4c7SAlex Deucher frame_count = radeon_get_vblank_counter(rdev, i); 4526253e4c7SAlex Deucher for (j = 0; j < rdev->usec_timeout; j++) { 4536253e4c7SAlex Deucher if (radeon_get_vblank_counter(rdev, i) != frame_count) 4546253e4c7SAlex Deucher break; 4556253e4c7SAlex Deucher udelay(1); 4566253e4c7SAlex Deucher } 4576253e4c7SAlex Deucher } 4586253e4c7SAlex Deucher } 4596253e4c7SAlex Deucher /* Unlock vga access */ 460d39c3b89SJerome Glisse WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 461d39c3b89SJerome Glisse mdelay(1); 462d39c3b89SJerome Glisse WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 463d39c3b89SJerome Glisse } 464d39c3b89SJerome Glisse 4651109ca09SLauri Kasanen static void rv515_mc_program(struct radeon_device *rdev) 466d39c3b89SJerome Glisse { 467d39c3b89SJerome Glisse struct rv515_mc_save save; 468d39c3b89SJerome Glisse 469d39c3b89SJerome Glisse /* Stops all mc clients */ 470d39c3b89SJerome Glisse rv515_mc_stop(rdev, &save); 471d39c3b89SJerome Glisse 472d39c3b89SJerome Glisse /* Wait for mc idle */ 473d39c3b89SJerome Glisse if (rv515_mc_wait_for_idle(rdev)) 474d39c3b89SJerome Glisse dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 475d39c3b89SJerome Glisse /* Write VRAM size in case we are limiting it */ 476d39c3b89SJerome Glisse WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 477d39c3b89SJerome Glisse /* Program MC, should be a 32bits limited address space */ 478d39c3b89SJerome Glisse WREG32_MC(R_000001_MC_FB_LOCATION, 479d39c3b89SJerome Glisse S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 480d39c3b89SJerome Glisse S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 481d39c3b89SJerome Glisse WREG32(R_000134_HDP_FB_LOCATION, 482d39c3b89SJerome Glisse S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 483d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 484d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 485d39c3b89SJerome Glisse S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 486d39c3b89SJerome Glisse S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 487d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 488d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 489d39c3b89SJerome Glisse S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 490d39c3b89SJerome Glisse } else { 491d39c3b89SJerome Glisse WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 492d39c3b89SJerome Glisse WREG32_MC(R_000003_MC_AGP_BASE, 0); 493d39c3b89SJerome Glisse WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 494d39c3b89SJerome Glisse } 495d39c3b89SJerome Glisse 496d39c3b89SJerome Glisse rv515_mc_resume(rdev, &save); 497d39c3b89SJerome Glisse } 498d39c3b89SJerome Glisse 499d39c3b89SJerome Glisse void rv515_clock_startup(struct radeon_device *rdev) 500d39c3b89SJerome Glisse { 501d39c3b89SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 502d39c3b89SJerome Glisse radeon_atom_set_clock_gating(rdev, 1); 503d39c3b89SJerome Glisse /* We need to force on some of the block */ 504d39c3b89SJerome Glisse WREG32_PLL(R_00000F_CP_DYN_CNTL, 505d39c3b89SJerome Glisse RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 506d39c3b89SJerome Glisse WREG32_PLL(R_000011_E2_DYN_CNTL, 507d39c3b89SJerome Glisse RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 508d39c3b89SJerome Glisse WREG32_PLL(R_000013_IDCT_DYN_CNTL, 509d39c3b89SJerome Glisse RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 510d39c3b89SJerome Glisse } 511d39c3b89SJerome Glisse 512d39c3b89SJerome Glisse static int rv515_startup(struct radeon_device *rdev) 513d39c3b89SJerome Glisse { 514d39c3b89SJerome Glisse int r; 515d39c3b89SJerome Glisse 516d39c3b89SJerome Glisse rv515_mc_program(rdev); 517d39c3b89SJerome Glisse /* Resume clock */ 518d39c3b89SJerome Glisse rv515_clock_startup(rdev); 519d39c3b89SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 520d39c3b89SJerome Glisse rv515_gpu_init(rdev); 521d39c3b89SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 522d39c3b89SJerome Glisse * memory through TTM but finalize after TTM) */ 523d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) { 524d39c3b89SJerome Glisse r = rv370_pcie_gart_enable(rdev); 525d39c3b89SJerome Glisse if (r) 526d39c3b89SJerome Glisse return r; 527d39c3b89SJerome Glisse } 528724c80e1SAlex Deucher 529724c80e1SAlex Deucher /* allocate wb buffer */ 530724c80e1SAlex Deucher r = radeon_wb_init(rdev); 531724c80e1SAlex Deucher if (r) 532724c80e1SAlex Deucher return r; 533724c80e1SAlex Deucher 53430eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 53530eb77f4SJerome Glisse if (r) { 53630eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 53730eb77f4SJerome Glisse return r; 53830eb77f4SJerome Glisse } 53930eb77f4SJerome Glisse 540d39c3b89SJerome Glisse /* Enable IRQ */ 541e49f3959SAdis Hamzić if (!rdev->irq.installed) { 542e49f3959SAdis Hamzić r = radeon_irq_kms_init(rdev); 543e49f3959SAdis Hamzić if (r) 544e49f3959SAdis Hamzić return r; 545e49f3959SAdis Hamzić } 546e49f3959SAdis Hamzić 547ac447df4SJerome Glisse rs600_irq_set(rdev); 548cafe6609SJerome Glisse rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 549d39c3b89SJerome Glisse /* 1M ring buffer */ 550d39c3b89SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 551d39c3b89SJerome Glisse if (r) { 552ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 553d39c3b89SJerome Glisse return r; 554d39c3b89SJerome Glisse } 555b15ba512SJerome Glisse 5562898c348SChristian König r = radeon_ib_pool_init(rdev); 5572898c348SChristian König if (r) { 5582898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 559b15ba512SJerome Glisse return r; 5602898c348SChristian König } 561b15ba512SJerome Glisse 562d39c3b89SJerome Glisse return 0; 563d39c3b89SJerome Glisse } 564d39c3b89SJerome Glisse 565d39c3b89SJerome Glisse int rv515_resume(struct radeon_device *rdev) 566d39c3b89SJerome Glisse { 5676b7746e8SJerome Glisse int r; 5686b7746e8SJerome Glisse 569d39c3b89SJerome Glisse /* Make sur GART are not working */ 570d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 571d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 572d39c3b89SJerome Glisse /* Resume clock before doing reset */ 573d39c3b89SJerome Glisse rv515_clock_startup(rdev); 574d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 575a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 576d39c3b89SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 577d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 578d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 579d39c3b89SJerome Glisse } 580d39c3b89SJerome Glisse /* post */ 581d39c3b89SJerome Glisse atom_asic_init(rdev->mode_info.atom_context); 582d39c3b89SJerome Glisse /* Resume clock after posting */ 583d39c3b89SJerome Glisse rv515_clock_startup(rdev); 584550e2d92SDave Airlie /* Initialize surface registers */ 585550e2d92SDave Airlie radeon_surface_init(rdev); 586b15ba512SJerome Glisse 587b15ba512SJerome Glisse rdev->accel_working = true; 5886b7746e8SJerome Glisse r = rv515_startup(rdev); 5896b7746e8SJerome Glisse if (r) { 5906b7746e8SJerome Glisse rdev->accel_working = false; 5916b7746e8SJerome Glisse } 5926b7746e8SJerome Glisse return r; 593d39c3b89SJerome Glisse } 594d39c3b89SJerome Glisse 595d39c3b89SJerome Glisse int rv515_suspend(struct radeon_device *rdev) 596d39c3b89SJerome Glisse { 5976c7bcceaSAlex Deucher radeon_pm_suspend(rdev); 598d39c3b89SJerome Glisse r100_cp_disable(rdev); 599724c80e1SAlex Deucher radeon_wb_disable(rdev); 600ac447df4SJerome Glisse rs600_irq_disable(rdev); 601d39c3b89SJerome Glisse if (rdev->flags & RADEON_IS_PCIE) 602d39c3b89SJerome Glisse rv370_pcie_gart_disable(rdev); 603d39c3b89SJerome Glisse return 0; 604d39c3b89SJerome Glisse } 605d39c3b89SJerome Glisse 606d39c3b89SJerome Glisse void rv515_set_safe_registers(struct radeon_device *rdev) 607068a117cSJerome Glisse { 60850f15303SDave Airlie rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 60950f15303SDave Airlie rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 610d39c3b89SJerome Glisse } 611d39c3b89SJerome Glisse 612d39c3b89SJerome Glisse void rv515_fini(struct radeon_device *rdev) 613d39c3b89SJerome Glisse { 6146c7bcceaSAlex Deucher radeon_pm_fini(rdev); 615d39c3b89SJerome Glisse r100_cp_fini(rdev); 616724c80e1SAlex Deucher radeon_wb_fini(rdev); 6172898c348SChristian König radeon_ib_pool_fini(rdev); 618d39c3b89SJerome Glisse radeon_gem_fini(rdev); 619d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 620d39c3b89SJerome Glisse radeon_agp_fini(rdev); 621d39c3b89SJerome Glisse radeon_irq_kms_fini(rdev); 622d39c3b89SJerome Glisse radeon_fence_driver_fini(rdev); 6234c788679SJerome Glisse radeon_bo_fini(rdev); 624d39c3b89SJerome Glisse radeon_atombios_fini(rdev); 625d39c3b89SJerome Glisse kfree(rdev->bios); 626d39c3b89SJerome Glisse rdev->bios = NULL; 627d39c3b89SJerome Glisse } 628d39c3b89SJerome Glisse 629d39c3b89SJerome Glisse int rv515_init(struct radeon_device *rdev) 630d39c3b89SJerome Glisse { 631d39c3b89SJerome Glisse int r; 632d39c3b89SJerome Glisse 633d39c3b89SJerome Glisse /* Initialize scratch registers */ 634d39c3b89SJerome Glisse radeon_scratch_init(rdev); 635d39c3b89SJerome Glisse /* Initialize surface registers */ 636d39c3b89SJerome Glisse radeon_surface_init(rdev); 637d39c3b89SJerome Glisse /* TODO: disable VGA need to use VGA request */ 6384c712e6cSDave Airlie /* restore some register to sane defaults */ 6394c712e6cSDave Airlie r100_restore_sanity(rdev); 640d39c3b89SJerome Glisse /* BIOS*/ 641d39c3b89SJerome Glisse if (!radeon_get_bios(rdev)) { 642d39c3b89SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 643d39c3b89SJerome Glisse return -EINVAL; 644d39c3b89SJerome Glisse } 645d39c3b89SJerome Glisse if (rdev->is_atom_bios) { 646d39c3b89SJerome Glisse r = radeon_atombios_init(rdev); 647d39c3b89SJerome Glisse if (r) 648d39c3b89SJerome Glisse return r; 649d39c3b89SJerome Glisse } else { 650d39c3b89SJerome Glisse dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 651d39c3b89SJerome Glisse return -EINVAL; 652d39c3b89SJerome Glisse } 653d39c3b89SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 654a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 655d39c3b89SJerome Glisse dev_warn(rdev->dev, 656d39c3b89SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 657d39c3b89SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 658d39c3b89SJerome Glisse RREG32(R_0007C0_CP_STAT)); 659d39c3b89SJerome Glisse } 660d39c3b89SJerome Glisse /* check if cards are posted or not */ 66172542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 66272542d77SDave Airlie return -EINVAL; 663d39c3b89SJerome Glisse /* Initialize clocks */ 664d39c3b89SJerome Glisse radeon_get_clock_info(rdev->ddev); 665d594e46aSJerome Glisse /* initialize AGP */ 666d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 667d594e46aSJerome Glisse r = radeon_agp_init(rdev); 668d594e46aSJerome Glisse if (r) { 669d594e46aSJerome Glisse radeon_agp_disable(rdev); 670d594e46aSJerome Glisse } 671d594e46aSJerome Glisse } 672d594e46aSJerome Glisse /* initialize memory controller */ 673d594e46aSJerome Glisse rv515_mc_init(rdev); 674d39c3b89SJerome Glisse rv515_debugfs(rdev); 675d39c3b89SJerome Glisse /* Fence driver */ 67630eb77f4SJerome Glisse r = radeon_fence_driver_init(rdev); 677d39c3b89SJerome Glisse if (r) 678d39c3b89SJerome Glisse return r; 679d39c3b89SJerome Glisse /* Memory manager */ 6804c788679SJerome Glisse r = radeon_bo_init(rdev); 681d39c3b89SJerome Glisse if (r) 682d39c3b89SJerome Glisse return r; 683d39c3b89SJerome Glisse r = rv370_pcie_gart_init(rdev); 684d39c3b89SJerome Glisse if (r) 685d39c3b89SJerome Glisse return r; 686d39c3b89SJerome Glisse rv515_set_safe_registers(rdev); 687b15ba512SJerome Glisse 6886c7bcceaSAlex Deucher /* Initialize power management */ 6896c7bcceaSAlex Deucher radeon_pm_init(rdev); 6906c7bcceaSAlex Deucher 691d39c3b89SJerome Glisse rdev->accel_working = true; 692d39c3b89SJerome Glisse r = rv515_startup(rdev); 693d39c3b89SJerome Glisse if (r) { 694d39c3b89SJerome Glisse /* Somethings want wront with the accel init stop accel */ 695d39c3b89SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 696d39c3b89SJerome Glisse r100_cp_fini(rdev); 697724c80e1SAlex Deucher radeon_wb_fini(rdev); 6982898c348SChristian König radeon_ib_pool_fini(rdev); 699655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 700d39c3b89SJerome Glisse rv370_pcie_gart_fini(rdev); 701d39c3b89SJerome Glisse radeon_agp_fini(rdev); 702d39c3b89SJerome Glisse rdev->accel_working = false; 703d39c3b89SJerome Glisse } 704068a117cSJerome Glisse return 0; 705068a117cSJerome Glisse } 706c93bb85bSJerome Glisse 7074ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 708c93bb85bSJerome Glisse { 7094ce001abSDave Airlie int index_reg = 0x6578 + crtc->crtc_offset; 7104ce001abSDave Airlie int data_reg = 0x657c + crtc->crtc_offset; 711c93bb85bSJerome Glisse 7124ce001abSDave Airlie WREG32(0x659C + crtc->crtc_offset, 0x0); 7134ce001abSDave Airlie WREG32(0x6594 + crtc->crtc_offset, 0x705); 7144ce001abSDave Airlie WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 7154ce001abSDave Airlie WREG32(0x65D8 + crtc->crtc_offset, 0x0); 7164ce001abSDave Airlie WREG32(0x65B0 + crtc->crtc_offset, 0x0); 7174ce001abSDave Airlie WREG32(0x65C0 + crtc->crtc_offset, 0x0); 7184ce001abSDave Airlie WREG32(0x65D4 + crtc->crtc_offset, 0x0); 7194ce001abSDave Airlie WREG32(index_reg, 0x0); 7204ce001abSDave Airlie WREG32(data_reg, 0x841880A8); 7214ce001abSDave Airlie WREG32(index_reg, 0x1); 7224ce001abSDave Airlie WREG32(data_reg, 0x84208680); 7234ce001abSDave Airlie WREG32(index_reg, 0x2); 7244ce001abSDave Airlie WREG32(data_reg, 0xBFF880B0); 7254ce001abSDave Airlie WREG32(index_reg, 0x100); 7264ce001abSDave Airlie WREG32(data_reg, 0x83D88088); 7274ce001abSDave Airlie WREG32(index_reg, 0x101); 7284ce001abSDave Airlie WREG32(data_reg, 0x84608680); 7294ce001abSDave Airlie WREG32(index_reg, 0x102); 7304ce001abSDave Airlie WREG32(data_reg, 0xBFF080D0); 7314ce001abSDave Airlie WREG32(index_reg, 0x200); 7324ce001abSDave Airlie WREG32(data_reg, 0x83988068); 7334ce001abSDave Airlie WREG32(index_reg, 0x201); 7344ce001abSDave Airlie WREG32(data_reg, 0x84A08680); 7354ce001abSDave Airlie WREG32(index_reg, 0x202); 7364ce001abSDave Airlie WREG32(data_reg, 0xBFF080F8); 7374ce001abSDave Airlie WREG32(index_reg, 0x300); 7384ce001abSDave Airlie WREG32(data_reg, 0x83588058); 7394ce001abSDave Airlie WREG32(index_reg, 0x301); 7404ce001abSDave Airlie WREG32(data_reg, 0x84E08660); 7414ce001abSDave Airlie WREG32(index_reg, 0x302); 7424ce001abSDave Airlie WREG32(data_reg, 0xBFF88120); 7434ce001abSDave Airlie WREG32(index_reg, 0x400); 7444ce001abSDave Airlie WREG32(data_reg, 0x83188040); 7454ce001abSDave Airlie WREG32(index_reg, 0x401); 7464ce001abSDave Airlie WREG32(data_reg, 0x85008660); 7474ce001abSDave Airlie WREG32(index_reg, 0x402); 7484ce001abSDave Airlie WREG32(data_reg, 0xBFF88150); 7494ce001abSDave Airlie WREG32(index_reg, 0x500); 7504ce001abSDave Airlie WREG32(data_reg, 0x82D88030); 7514ce001abSDave Airlie WREG32(index_reg, 0x501); 7524ce001abSDave Airlie WREG32(data_reg, 0x85408640); 7534ce001abSDave Airlie WREG32(index_reg, 0x502); 7544ce001abSDave Airlie WREG32(data_reg, 0xBFF88180); 7554ce001abSDave Airlie WREG32(index_reg, 0x600); 7564ce001abSDave Airlie WREG32(data_reg, 0x82A08018); 7574ce001abSDave Airlie WREG32(index_reg, 0x601); 7584ce001abSDave Airlie WREG32(data_reg, 0x85808620); 7594ce001abSDave Airlie WREG32(index_reg, 0x602); 7604ce001abSDave Airlie WREG32(data_reg, 0xBFF081B8); 7614ce001abSDave Airlie WREG32(index_reg, 0x700); 7624ce001abSDave Airlie WREG32(data_reg, 0x82608010); 7634ce001abSDave Airlie WREG32(index_reg, 0x701); 7644ce001abSDave Airlie WREG32(data_reg, 0x85A08600); 7654ce001abSDave Airlie WREG32(index_reg, 0x702); 7664ce001abSDave Airlie WREG32(data_reg, 0x800081F0); 7674ce001abSDave Airlie WREG32(index_reg, 0x800); 7684ce001abSDave Airlie WREG32(data_reg, 0x8228BFF8); 7694ce001abSDave Airlie WREG32(index_reg, 0x801); 7704ce001abSDave Airlie WREG32(data_reg, 0x85E085E0); 7714ce001abSDave Airlie WREG32(index_reg, 0x802); 7724ce001abSDave Airlie WREG32(data_reg, 0xBFF88228); 7734ce001abSDave Airlie WREG32(index_reg, 0x10000); 7744ce001abSDave Airlie WREG32(data_reg, 0x82A8BF00); 7754ce001abSDave Airlie WREG32(index_reg, 0x10001); 7764ce001abSDave Airlie WREG32(data_reg, 0x82A08CC0); 7774ce001abSDave Airlie WREG32(index_reg, 0x10002); 7784ce001abSDave Airlie WREG32(data_reg, 0x8008BEF8); 7794ce001abSDave Airlie WREG32(index_reg, 0x10100); 7804ce001abSDave Airlie WREG32(data_reg, 0x81F0BF28); 7814ce001abSDave Airlie WREG32(index_reg, 0x10101); 7824ce001abSDave Airlie WREG32(data_reg, 0x83608CA0); 7834ce001abSDave Airlie WREG32(index_reg, 0x10102); 7844ce001abSDave Airlie WREG32(data_reg, 0x8018BED0); 7854ce001abSDave Airlie WREG32(index_reg, 0x10200); 7864ce001abSDave Airlie WREG32(data_reg, 0x8148BF38); 7874ce001abSDave Airlie WREG32(index_reg, 0x10201); 7884ce001abSDave Airlie WREG32(data_reg, 0x84408C80); 7894ce001abSDave Airlie WREG32(index_reg, 0x10202); 7904ce001abSDave Airlie WREG32(data_reg, 0x8008BEB8); 7914ce001abSDave Airlie WREG32(index_reg, 0x10300); 7924ce001abSDave Airlie WREG32(data_reg, 0x80B0BF78); 7934ce001abSDave Airlie WREG32(index_reg, 0x10301); 7944ce001abSDave Airlie WREG32(data_reg, 0x85008C20); 7954ce001abSDave Airlie WREG32(index_reg, 0x10302); 7964ce001abSDave Airlie WREG32(data_reg, 0x8020BEA0); 7974ce001abSDave Airlie WREG32(index_reg, 0x10400); 7984ce001abSDave Airlie WREG32(data_reg, 0x8028BF90); 7994ce001abSDave Airlie WREG32(index_reg, 0x10401); 8004ce001abSDave Airlie WREG32(data_reg, 0x85E08BC0); 8014ce001abSDave Airlie WREG32(index_reg, 0x10402); 8024ce001abSDave Airlie WREG32(data_reg, 0x8018BE90); 8034ce001abSDave Airlie WREG32(index_reg, 0x10500); 8044ce001abSDave Airlie WREG32(data_reg, 0xBFB8BFB0); 8054ce001abSDave Airlie WREG32(index_reg, 0x10501); 8064ce001abSDave Airlie WREG32(data_reg, 0x86C08B40); 8074ce001abSDave Airlie WREG32(index_reg, 0x10502); 8084ce001abSDave Airlie WREG32(data_reg, 0x8010BE90); 8094ce001abSDave Airlie WREG32(index_reg, 0x10600); 8104ce001abSDave Airlie WREG32(data_reg, 0xBF58BFC8); 8114ce001abSDave Airlie WREG32(index_reg, 0x10601); 8124ce001abSDave Airlie WREG32(data_reg, 0x87A08AA0); 8134ce001abSDave Airlie WREG32(index_reg, 0x10602); 8144ce001abSDave Airlie WREG32(data_reg, 0x8010BE98); 8154ce001abSDave Airlie WREG32(index_reg, 0x10700); 8164ce001abSDave Airlie WREG32(data_reg, 0xBF10BFF0); 8174ce001abSDave Airlie WREG32(index_reg, 0x10701); 8184ce001abSDave Airlie WREG32(data_reg, 0x886089E0); 8194ce001abSDave Airlie WREG32(index_reg, 0x10702); 8204ce001abSDave Airlie WREG32(data_reg, 0x8018BEB0); 8214ce001abSDave Airlie WREG32(index_reg, 0x10800); 8224ce001abSDave Airlie WREG32(data_reg, 0xBED8BFE8); 8234ce001abSDave Airlie WREG32(index_reg, 0x10801); 8244ce001abSDave Airlie WREG32(data_reg, 0x89408940); 8254ce001abSDave Airlie WREG32(index_reg, 0x10802); 8264ce001abSDave Airlie WREG32(data_reg, 0xBFE8BED8); 8274ce001abSDave Airlie WREG32(index_reg, 0x20000); 8284ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8294ce001abSDave Airlie WREG32(index_reg, 0x20001); 8304ce001abSDave Airlie WREG32(data_reg, 0x90008000); 8314ce001abSDave Airlie WREG32(index_reg, 0x20002); 8324ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8334ce001abSDave Airlie WREG32(index_reg, 0x20003); 8344ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8354ce001abSDave Airlie WREG32(index_reg, 0x20100); 8364ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8374ce001abSDave Airlie WREG32(index_reg, 0x20101); 8384ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF70); 8394ce001abSDave Airlie WREG32(index_reg, 0x20102); 8404ce001abSDave Airlie WREG32(data_reg, 0xBFE880C0); 8414ce001abSDave Airlie WREG32(index_reg, 0x20103); 8424ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8434ce001abSDave Airlie WREG32(index_reg, 0x20200); 8444ce001abSDave Airlie WREG32(data_reg, 0x8018BFF8); 8454ce001abSDave Airlie WREG32(index_reg, 0x20201); 8464ce001abSDave Airlie WREG32(data_reg, 0x8F80BF08); 8474ce001abSDave Airlie WREG32(index_reg, 0x20202); 8484ce001abSDave Airlie WREG32(data_reg, 0xBFD081A0); 8494ce001abSDave Airlie WREG32(index_reg, 0x20203); 8504ce001abSDave Airlie WREG32(data_reg, 0xBFF88000); 8514ce001abSDave Airlie WREG32(index_reg, 0x20300); 8524ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8534ce001abSDave Airlie WREG32(index_reg, 0x20301); 8544ce001abSDave Airlie WREG32(data_reg, 0x8EE0BEC0); 8554ce001abSDave Airlie WREG32(index_reg, 0x20302); 8564ce001abSDave Airlie WREG32(data_reg, 0xBFB082A0); 8574ce001abSDave Airlie WREG32(index_reg, 0x20303); 8584ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8594ce001abSDave Airlie WREG32(index_reg, 0x20400); 8604ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8614ce001abSDave Airlie WREG32(index_reg, 0x20401); 8624ce001abSDave Airlie WREG32(data_reg, 0x8E00BEA0); 8634ce001abSDave Airlie WREG32(index_reg, 0x20402); 8644ce001abSDave Airlie WREG32(data_reg, 0xBF8883C0); 8654ce001abSDave Airlie WREG32(index_reg, 0x20403); 8664ce001abSDave Airlie WREG32(data_reg, 0x80008000); 8674ce001abSDave Airlie WREG32(index_reg, 0x20500); 8684ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8694ce001abSDave Airlie WREG32(index_reg, 0x20501); 8704ce001abSDave Airlie WREG32(data_reg, 0x8D00BE90); 8714ce001abSDave Airlie WREG32(index_reg, 0x20502); 8724ce001abSDave Airlie WREG32(data_reg, 0xBF588500); 8734ce001abSDave Airlie WREG32(index_reg, 0x20503); 8744ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8754ce001abSDave Airlie WREG32(index_reg, 0x20600); 8764ce001abSDave Airlie WREG32(data_reg, 0x80188000); 8774ce001abSDave Airlie WREG32(index_reg, 0x20601); 8784ce001abSDave Airlie WREG32(data_reg, 0x8BC0BE98); 8794ce001abSDave Airlie WREG32(index_reg, 0x20602); 8804ce001abSDave Airlie WREG32(data_reg, 0xBF308660); 8814ce001abSDave Airlie WREG32(index_reg, 0x20603); 8824ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8834ce001abSDave Airlie WREG32(index_reg, 0x20700); 8844ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8854ce001abSDave Airlie WREG32(index_reg, 0x20701); 8864ce001abSDave Airlie WREG32(data_reg, 0x8A80BEB0); 8874ce001abSDave Airlie WREG32(index_reg, 0x20702); 8884ce001abSDave Airlie WREG32(data_reg, 0xBF0087C0); 8894ce001abSDave Airlie WREG32(index_reg, 0x20703); 8904ce001abSDave Airlie WREG32(data_reg, 0x80008008); 8914ce001abSDave Airlie WREG32(index_reg, 0x20800); 8924ce001abSDave Airlie WREG32(data_reg, 0x80108000); 8934ce001abSDave Airlie WREG32(index_reg, 0x20801); 8944ce001abSDave Airlie WREG32(data_reg, 0x8920BED0); 8954ce001abSDave Airlie WREG32(index_reg, 0x20802); 8964ce001abSDave Airlie WREG32(data_reg, 0xBED08920); 8974ce001abSDave Airlie WREG32(index_reg, 0x20803); 8984ce001abSDave Airlie WREG32(data_reg, 0x80008010); 8994ce001abSDave Airlie WREG32(index_reg, 0x30000); 9004ce001abSDave Airlie WREG32(data_reg, 0x90008000); 9014ce001abSDave Airlie WREG32(index_reg, 0x30001); 9024ce001abSDave Airlie WREG32(data_reg, 0x80008000); 9034ce001abSDave Airlie WREG32(index_reg, 0x30100); 9044ce001abSDave Airlie WREG32(data_reg, 0x8FE0BF90); 9054ce001abSDave Airlie WREG32(index_reg, 0x30101); 9064ce001abSDave Airlie WREG32(data_reg, 0xBFF880A0); 9074ce001abSDave Airlie WREG32(index_reg, 0x30200); 9084ce001abSDave Airlie WREG32(data_reg, 0x8F60BF40); 9094ce001abSDave Airlie WREG32(index_reg, 0x30201); 9104ce001abSDave Airlie WREG32(data_reg, 0xBFE88180); 9114ce001abSDave Airlie WREG32(index_reg, 0x30300); 9124ce001abSDave Airlie WREG32(data_reg, 0x8EC0BF00); 9134ce001abSDave Airlie WREG32(index_reg, 0x30301); 9144ce001abSDave Airlie WREG32(data_reg, 0xBFC88280); 9154ce001abSDave Airlie WREG32(index_reg, 0x30400); 9164ce001abSDave Airlie WREG32(data_reg, 0x8DE0BEE0); 9174ce001abSDave Airlie WREG32(index_reg, 0x30401); 9184ce001abSDave Airlie WREG32(data_reg, 0xBFA083A0); 9194ce001abSDave Airlie WREG32(index_reg, 0x30500); 9204ce001abSDave Airlie WREG32(data_reg, 0x8CE0BED0); 9214ce001abSDave Airlie WREG32(index_reg, 0x30501); 9224ce001abSDave Airlie WREG32(data_reg, 0xBF7884E0); 9234ce001abSDave Airlie WREG32(index_reg, 0x30600); 9244ce001abSDave Airlie WREG32(data_reg, 0x8BA0BED8); 9254ce001abSDave Airlie WREG32(index_reg, 0x30601); 9264ce001abSDave Airlie WREG32(data_reg, 0xBF508640); 9274ce001abSDave Airlie WREG32(index_reg, 0x30700); 9284ce001abSDave Airlie WREG32(data_reg, 0x8A60BEE8); 9294ce001abSDave Airlie WREG32(index_reg, 0x30701); 9304ce001abSDave Airlie WREG32(data_reg, 0xBF2087A0); 9314ce001abSDave Airlie WREG32(index_reg, 0x30800); 9324ce001abSDave Airlie WREG32(data_reg, 0x8900BF00); 9334ce001abSDave Airlie WREG32(index_reg, 0x30801); 9344ce001abSDave Airlie WREG32(data_reg, 0xBF008900); 935c93bb85bSJerome Glisse } 936c93bb85bSJerome Glisse 937c93bb85bSJerome Glisse struct rv515_watermark { 938c93bb85bSJerome Glisse u32 lb_request_fifo_depth; 939c93bb85bSJerome Glisse fixed20_12 num_line_pair; 940c93bb85bSJerome Glisse fixed20_12 estimated_width; 941c93bb85bSJerome Glisse fixed20_12 worst_case_latency; 942c93bb85bSJerome Glisse fixed20_12 consumption_rate; 943c93bb85bSJerome Glisse fixed20_12 active_time; 944c93bb85bSJerome Glisse fixed20_12 dbpp; 945c93bb85bSJerome Glisse fixed20_12 priority_mark_max; 946c93bb85bSJerome Glisse fixed20_12 priority_mark; 947c93bb85bSJerome Glisse fixed20_12 sclk; 948c93bb85bSJerome Glisse }; 949c93bb85bSJerome Glisse 9501109ca09SLauri Kasanen static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 951c93bb85bSJerome Glisse struct radeon_crtc *crtc, 9527d99e517SAlex Deucher struct rv515_watermark *wm, 9537d99e517SAlex Deucher bool low) 954c93bb85bSJerome Glisse { 955c93bb85bSJerome Glisse struct drm_display_mode *mode = &crtc->base.mode; 956c93bb85bSJerome Glisse fixed20_12 a, b, c; 957c93bb85bSJerome Glisse fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 958c93bb85bSJerome Glisse fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 9597d99e517SAlex Deucher fixed20_12 sclk; 9607d99e517SAlex Deucher u32 selected_sclk; 961c93bb85bSJerome Glisse 962c93bb85bSJerome Glisse if (!crtc->base.enabled) { 963c93bb85bSJerome Glisse /* FIXME: wouldn't it better to set priority mark to maximum */ 964c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 965c93bb85bSJerome Glisse return; 966c93bb85bSJerome Glisse } 967c93bb85bSJerome Glisse 9687d99e517SAlex Deucher /* rv6xx, rv7xx */ 9697d99e517SAlex Deucher if ((rdev->family >= CHIP_RV610) && 9707d99e517SAlex Deucher (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 9717d99e517SAlex Deucher selected_sclk = radeon_dpm_get_sclk(rdev, low); 9727d99e517SAlex Deucher else 9737d99e517SAlex Deucher selected_sclk = rdev->pm.current_sclk; 9747d99e517SAlex Deucher 9757d99e517SAlex Deucher /* sclk in Mhz */ 9767d99e517SAlex Deucher a.full = dfixed_const(100); 9777d99e517SAlex Deucher sclk.full = dfixed_const(selected_sclk); 9787d99e517SAlex Deucher sclk.full = dfixed_div(sclk, a); 9797d99e517SAlex Deucher 98068adac5eSBen Skeggs if (crtc->vsc.full > dfixed_const(2)) 98168adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(2); 982c93bb85bSJerome Glisse else 98368adac5eSBen Skeggs wm->num_line_pair.full = dfixed_const(1); 984c93bb85bSJerome Glisse 98568adac5eSBen Skeggs b.full = dfixed_const(mode->crtc_hdisplay); 98668adac5eSBen Skeggs c.full = dfixed_const(256); 98768adac5eSBen Skeggs a.full = dfixed_div(b, c); 98868adac5eSBen Skeggs request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 98968adac5eSBen Skeggs request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 99068adac5eSBen Skeggs if (a.full < dfixed_const(4)) { 991c93bb85bSJerome Glisse wm->lb_request_fifo_depth = 4; 992c93bb85bSJerome Glisse } else { 99368adac5eSBen Skeggs wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 994c93bb85bSJerome Glisse } 995c93bb85bSJerome Glisse 996c93bb85bSJerome Glisse /* Determine consumption rate 997c93bb85bSJerome Glisse * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 998c93bb85bSJerome Glisse * vtaps = number of vertical taps, 999c93bb85bSJerome Glisse * vsc = vertical scaling ratio, defined as source/destination 1000c93bb85bSJerome Glisse * hsc = horizontal scaling ration, defined as source/destination 1001c93bb85bSJerome Glisse */ 100268adac5eSBen Skeggs a.full = dfixed_const(mode->clock); 100368adac5eSBen Skeggs b.full = dfixed_const(1000); 100468adac5eSBen Skeggs a.full = dfixed_div(a, b); 100568adac5eSBen Skeggs pclk.full = dfixed_div(b, a); 1006c93bb85bSJerome Glisse if (crtc->rmx_type != RMX_OFF) { 100768adac5eSBen Skeggs b.full = dfixed_const(2); 1008c93bb85bSJerome Glisse if (crtc->vsc.full > b.full) 1009c93bb85bSJerome Glisse b.full = crtc->vsc.full; 101068adac5eSBen Skeggs b.full = dfixed_mul(b, crtc->hsc); 101168adac5eSBen Skeggs c.full = dfixed_const(2); 101268adac5eSBen Skeggs b.full = dfixed_div(b, c); 101368adac5eSBen Skeggs consumption_time.full = dfixed_div(pclk, b); 1014c93bb85bSJerome Glisse } else { 1015c93bb85bSJerome Glisse consumption_time.full = pclk.full; 1016c93bb85bSJerome Glisse } 101768adac5eSBen Skeggs a.full = dfixed_const(1); 101868adac5eSBen Skeggs wm->consumption_rate.full = dfixed_div(a, consumption_time); 1019c93bb85bSJerome Glisse 1020c93bb85bSJerome Glisse 1021c93bb85bSJerome Glisse /* Determine line time 1022c93bb85bSJerome Glisse * LineTime = total time for one line of displayhtotal 1023c93bb85bSJerome Glisse * LineTime = total number of horizontal pixels 1024c93bb85bSJerome Glisse * pclk = pixel clock period(ns) 1025c93bb85bSJerome Glisse */ 102668adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 102768adac5eSBen Skeggs line_time.full = dfixed_mul(a, pclk); 1028c93bb85bSJerome Glisse 1029c93bb85bSJerome Glisse /* Determine active time 1030c93bb85bSJerome Glisse * ActiveTime = time of active region of display within one line, 1031c93bb85bSJerome Glisse * hactive = total number of horizontal active pixels 1032c93bb85bSJerome Glisse * htotal = total number of horizontal pixels 1033c93bb85bSJerome Glisse */ 103468adac5eSBen Skeggs a.full = dfixed_const(crtc->base.mode.crtc_htotal); 103568adac5eSBen Skeggs b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 103668adac5eSBen Skeggs wm->active_time.full = dfixed_mul(line_time, b); 103768adac5eSBen Skeggs wm->active_time.full = dfixed_div(wm->active_time, a); 1038c93bb85bSJerome Glisse 1039c93bb85bSJerome Glisse /* Determine chunk time 1040c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk of data 1041c93bb85bSJerome Glisse * to the LB which consists of pipeline delay and inter chunk gap 1042c93bb85bSJerome Glisse * sclk = system clock(Mhz) 1043c93bb85bSJerome Glisse */ 104468adac5eSBen Skeggs a.full = dfixed_const(600 * 1000); 10457d99e517SAlex Deucher chunk_time.full = dfixed_div(a, sclk); 104668adac5eSBen Skeggs read_delay_latency.full = dfixed_const(1000); 1047c93bb85bSJerome Glisse 1048c93bb85bSJerome Glisse /* Determine the worst case latency 1049c93bb85bSJerome Glisse * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1050c93bb85bSJerome Glisse * WorstCaseLatency = worst case time from urgent to when the MC starts 1051c93bb85bSJerome Glisse * to return data 1052c93bb85bSJerome Glisse * READ_DELAY_IDLE_MAX = constant of 1us 1053c93bb85bSJerome Glisse * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1054c93bb85bSJerome Glisse * which consists of pipeline delay and inter chunk gap 1055c93bb85bSJerome Glisse */ 105668adac5eSBen Skeggs if (dfixed_trunc(wm->num_line_pair) > 1) { 105768adac5eSBen Skeggs a.full = dfixed_const(3); 105868adac5eSBen Skeggs wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1059c93bb85bSJerome Glisse wm->worst_case_latency.full += read_delay_latency.full; 1060c93bb85bSJerome Glisse } else { 1061c93bb85bSJerome Glisse wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1062c93bb85bSJerome Glisse } 1063c93bb85bSJerome Glisse 1064c93bb85bSJerome Glisse /* Determine the tolerable latency 1065c93bb85bSJerome Glisse * TolerableLatency = Any given request has only 1 line time 1066c93bb85bSJerome Glisse * for the data to be returned 1067c93bb85bSJerome Glisse * LBRequestFifoDepth = Number of chunk requests the LB can 1068c93bb85bSJerome Glisse * put into the request FIFO for a display 1069c93bb85bSJerome Glisse * LineTime = total time for one line of display 1070c93bb85bSJerome Glisse * ChunkTime = the time it takes the DCP to send one chunk 1071c93bb85bSJerome Glisse * of data to the LB which consists of 1072c93bb85bSJerome Glisse * pipeline delay and inter chunk gap 1073c93bb85bSJerome Glisse */ 107468adac5eSBen Skeggs if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1075c93bb85bSJerome Glisse tolerable_latency.full = line_time.full; 1076c93bb85bSJerome Glisse } else { 107768adac5eSBen Skeggs tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1078c93bb85bSJerome Glisse tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 107968adac5eSBen Skeggs tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1080c93bb85bSJerome Glisse tolerable_latency.full = line_time.full - tolerable_latency.full; 1081c93bb85bSJerome Glisse } 1082c93bb85bSJerome Glisse /* We assume worst case 32bits (4 bytes) */ 108368adac5eSBen Skeggs wm->dbpp.full = dfixed_const(2 * 16); 1084c93bb85bSJerome Glisse 1085c93bb85bSJerome Glisse /* Determine the maximum priority mark 1086c93bb85bSJerome Glisse * width = viewport width in pixels 1087c93bb85bSJerome Glisse */ 108868adac5eSBen Skeggs a.full = dfixed_const(16); 108968adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 109068adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 109168adac5eSBen Skeggs wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1092c93bb85bSJerome Glisse 1093c93bb85bSJerome Glisse /* Determine estimated width */ 1094c93bb85bSJerome Glisse estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 109568adac5eSBen Skeggs estimated_width.full = dfixed_div(estimated_width, consumption_time); 109668adac5eSBen Skeggs if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 109769b3b5e5SAlex Deucher wm->priority_mark.full = wm->priority_mark_max.full; 1098c93bb85bSJerome Glisse } else { 109968adac5eSBen Skeggs a.full = dfixed_const(16); 110068adac5eSBen Skeggs wm->priority_mark.full = dfixed_div(estimated_width, a); 110168adac5eSBen Skeggs wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1102c93bb85bSJerome Glisse wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1103c93bb85bSJerome Glisse } 1104c93bb85bSJerome Glisse } 1105c93bb85bSJerome Glisse 11067d99e517SAlex Deucher static void rv515_compute_mode_priority(struct radeon_device *rdev, 11077d99e517SAlex Deucher struct rv515_watermark *wm0, 11087d99e517SAlex Deucher struct rv515_watermark *wm1, 11097d99e517SAlex Deucher struct drm_display_mode *mode0, 11107d99e517SAlex Deucher struct drm_display_mode *mode1, 11117d99e517SAlex Deucher u32 *d1mode_priority_a_cnt, 11127d99e517SAlex Deucher u32 *d2mode_priority_a_cnt) 11137d99e517SAlex Deucher { 11147d99e517SAlex Deucher fixed20_12 priority_mark02, priority_mark12, fill_rate; 11157d99e517SAlex Deucher fixed20_12 a, b; 11167d99e517SAlex Deucher 11177d99e517SAlex Deucher *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 11187d99e517SAlex Deucher *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 11197d99e517SAlex Deucher 11207d99e517SAlex Deucher if (mode0 && mode1) { 11217d99e517SAlex Deucher if (dfixed_trunc(wm0->dbpp) > 64) 11227d99e517SAlex Deucher a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 11237d99e517SAlex Deucher else 11247d99e517SAlex Deucher a.full = wm0->num_line_pair.full; 11257d99e517SAlex Deucher if (dfixed_trunc(wm1->dbpp) > 64) 11267d99e517SAlex Deucher b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 11277d99e517SAlex Deucher else 11287d99e517SAlex Deucher b.full = wm1->num_line_pair.full; 11297d99e517SAlex Deucher a.full += b.full; 11307d99e517SAlex Deucher fill_rate.full = dfixed_div(wm0->sclk, a); 11317d99e517SAlex Deucher if (wm0->consumption_rate.full > fill_rate.full) { 11327d99e517SAlex Deucher b.full = wm0->consumption_rate.full - fill_rate.full; 11337d99e517SAlex Deucher b.full = dfixed_mul(b, wm0->active_time); 11347d99e517SAlex Deucher a.full = dfixed_const(16); 11357d99e517SAlex Deucher b.full = dfixed_div(b, a); 11367d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11377d99e517SAlex Deucher wm0->consumption_rate); 11387d99e517SAlex Deucher priority_mark02.full = a.full + b.full; 11397d99e517SAlex Deucher } else { 11407d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11417d99e517SAlex Deucher wm0->consumption_rate); 11427d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 11437d99e517SAlex Deucher priority_mark02.full = dfixed_div(a, b); 11447d99e517SAlex Deucher } 11457d99e517SAlex Deucher if (wm1->consumption_rate.full > fill_rate.full) { 11467d99e517SAlex Deucher b.full = wm1->consumption_rate.full - fill_rate.full; 11477d99e517SAlex Deucher b.full = dfixed_mul(b, wm1->active_time); 11487d99e517SAlex Deucher a.full = dfixed_const(16); 11497d99e517SAlex Deucher b.full = dfixed_div(b, a); 11507d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11517d99e517SAlex Deucher wm1->consumption_rate); 11527d99e517SAlex Deucher priority_mark12.full = a.full + b.full; 11537d99e517SAlex Deucher } else { 11547d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 11557d99e517SAlex Deucher wm1->consumption_rate); 11567d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 11577d99e517SAlex Deucher priority_mark12.full = dfixed_div(a, b); 11587d99e517SAlex Deucher } 11597d99e517SAlex Deucher if (wm0->priority_mark.full > priority_mark02.full) 11607d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark.full; 11617d99e517SAlex Deucher if (wm0->priority_mark_max.full > priority_mark02.full) 11627d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark_max.full; 11637d99e517SAlex Deucher if (wm1->priority_mark.full > priority_mark12.full) 11647d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark.full; 11657d99e517SAlex Deucher if (wm1->priority_mark_max.full > priority_mark12.full) 11667d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark_max.full; 11677d99e517SAlex Deucher *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 11687d99e517SAlex Deucher *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 11697d99e517SAlex Deucher if (rdev->disp_priority == 2) { 11707d99e517SAlex Deucher *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 11717d99e517SAlex Deucher *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 11727d99e517SAlex Deucher } 11737d99e517SAlex Deucher } else if (mode0) { 11747d99e517SAlex Deucher if (dfixed_trunc(wm0->dbpp) > 64) 11757d99e517SAlex Deucher a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 11767d99e517SAlex Deucher else 11777d99e517SAlex Deucher a.full = wm0->num_line_pair.full; 11787d99e517SAlex Deucher fill_rate.full = dfixed_div(wm0->sclk, a); 11797d99e517SAlex Deucher if (wm0->consumption_rate.full > fill_rate.full) { 11807d99e517SAlex Deucher b.full = wm0->consumption_rate.full - fill_rate.full; 11817d99e517SAlex Deucher b.full = dfixed_mul(b, wm0->active_time); 11827d99e517SAlex Deucher a.full = dfixed_const(16); 11837d99e517SAlex Deucher b.full = dfixed_div(b, a); 11847d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11857d99e517SAlex Deucher wm0->consumption_rate); 11867d99e517SAlex Deucher priority_mark02.full = a.full + b.full; 11877d99e517SAlex Deucher } else { 11887d99e517SAlex Deucher a.full = dfixed_mul(wm0->worst_case_latency, 11897d99e517SAlex Deucher wm0->consumption_rate); 11907d99e517SAlex Deucher b.full = dfixed_const(16); 11917d99e517SAlex Deucher priority_mark02.full = dfixed_div(a, b); 11927d99e517SAlex Deucher } 11937d99e517SAlex Deucher if (wm0->priority_mark.full > priority_mark02.full) 11947d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark.full; 11957d99e517SAlex Deucher if (wm0->priority_mark_max.full > priority_mark02.full) 11967d99e517SAlex Deucher priority_mark02.full = wm0->priority_mark_max.full; 11977d99e517SAlex Deucher *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 11987d99e517SAlex Deucher if (rdev->disp_priority == 2) 11997d99e517SAlex Deucher *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 12007d99e517SAlex Deucher } else if (mode1) { 12017d99e517SAlex Deucher if (dfixed_trunc(wm1->dbpp) > 64) 12027d99e517SAlex Deucher a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 12037d99e517SAlex Deucher else 12047d99e517SAlex Deucher a.full = wm1->num_line_pair.full; 12057d99e517SAlex Deucher fill_rate.full = dfixed_div(wm1->sclk, a); 12067d99e517SAlex Deucher if (wm1->consumption_rate.full > fill_rate.full) { 12077d99e517SAlex Deucher b.full = wm1->consumption_rate.full - fill_rate.full; 12087d99e517SAlex Deucher b.full = dfixed_mul(b, wm1->active_time); 12097d99e517SAlex Deucher a.full = dfixed_const(16); 12107d99e517SAlex Deucher b.full = dfixed_div(b, a); 12117d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 12127d99e517SAlex Deucher wm1->consumption_rate); 12137d99e517SAlex Deucher priority_mark12.full = a.full + b.full; 12147d99e517SAlex Deucher } else { 12157d99e517SAlex Deucher a.full = dfixed_mul(wm1->worst_case_latency, 12167d99e517SAlex Deucher wm1->consumption_rate); 12177d99e517SAlex Deucher b.full = dfixed_const(16 * 1000); 12187d99e517SAlex Deucher priority_mark12.full = dfixed_div(a, b); 12197d99e517SAlex Deucher } 12207d99e517SAlex Deucher if (wm1->priority_mark.full > priority_mark12.full) 12217d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark.full; 12227d99e517SAlex Deucher if (wm1->priority_mark_max.full > priority_mark12.full) 12237d99e517SAlex Deucher priority_mark12.full = wm1->priority_mark_max.full; 12247d99e517SAlex Deucher *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 12257d99e517SAlex Deucher if (rdev->disp_priority == 2) 12267d99e517SAlex Deucher *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 12277d99e517SAlex Deucher } 12287d99e517SAlex Deucher } 12297d99e517SAlex Deucher 1230c93bb85bSJerome Glisse void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1231c93bb85bSJerome Glisse { 1232c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1233c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 12347d99e517SAlex Deucher struct rv515_watermark wm0_high, wm0_low; 12357d99e517SAlex Deucher struct rv515_watermark wm1_high, wm1_low; 1236e06b14eeSAlex Deucher u32 tmp; 12377d99e517SAlex Deucher u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 12387d99e517SAlex Deucher u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1239c93bb85bSJerome Glisse 1240c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1241c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1242c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1243c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1244c93bb85bSJerome Glisse rs690_line_buffer_adjust(rdev, mode0, mode1); 1245c93bb85bSJerome Glisse 12467d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 12477d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1248c93bb85bSJerome Glisse 12497d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 12507d99e517SAlex Deucher rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 12517d99e517SAlex Deucher 12527d99e517SAlex Deucher tmp = wm0_high.lb_request_fifo_depth; 12537d99e517SAlex Deucher tmp |= wm1_high.lb_request_fifo_depth << 16; 1254c93bb85bSJerome Glisse WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1255c93bb85bSJerome Glisse 12567d99e517SAlex Deucher rv515_compute_mode_priority(rdev, 12577d99e517SAlex Deucher &wm0_high, &wm1_high, 12587d99e517SAlex Deucher mode0, mode1, 12597d99e517SAlex Deucher &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 12607d99e517SAlex Deucher rv515_compute_mode_priority(rdev, 12617d99e517SAlex Deucher &wm0_low, &wm1_low, 12627d99e517SAlex Deucher mode0, mode1, 12637d99e517SAlex Deucher &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1264e06b14eeSAlex Deucher 1265e06b14eeSAlex Deucher WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 12667d99e517SAlex Deucher WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1267f46c0120SAlex Deucher WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 12687d99e517SAlex Deucher WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1269c93bb85bSJerome Glisse } 1270c93bb85bSJerome Glisse 1271c93bb85bSJerome Glisse void rv515_bandwidth_update(struct radeon_device *rdev) 1272c93bb85bSJerome Glisse { 1273c93bb85bSJerome Glisse uint32_t tmp; 1274c93bb85bSJerome Glisse struct drm_display_mode *mode0 = NULL; 1275c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 1276c93bb85bSJerome Glisse 12778efe82caSAlex Deucher if (!rdev->mode_info.mode_config_initialized) 12788efe82caSAlex Deucher return; 12798efe82caSAlex Deucher 1280f46c0120SAlex Deucher radeon_update_display_priority(rdev); 1281f46c0120SAlex Deucher 1282c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) 1283c93bb85bSJerome Glisse mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1284c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) 1285c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1286c93bb85bSJerome Glisse /* 1287c93bb85bSJerome Glisse * Set display0/1 priority up in the memory controller for 1288c93bb85bSJerome Glisse * modes if the user specifies HIGH for displaypriority 1289c93bb85bSJerome Glisse * option. 1290c93bb85bSJerome Glisse */ 1291f46c0120SAlex Deucher if ((rdev->disp_priority == 2) && 1292f46c0120SAlex Deucher (rdev->family == CHIP_RV515)) { 1293c93bb85bSJerome Glisse tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1294c93bb85bSJerome Glisse tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1295c93bb85bSJerome Glisse tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1296c93bb85bSJerome Glisse if (mode1) 1297c93bb85bSJerome Glisse tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1298c93bb85bSJerome Glisse if (mode0) 1299c93bb85bSJerome Glisse tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1300c93bb85bSJerome Glisse WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1301c93bb85bSJerome Glisse } 1302c93bb85bSJerome Glisse rv515_bandwidth_avivo_update(rdev); 1303c93bb85bSJerome Glisse } 1304