1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "radeon_audio.h" 32 #include "atom.h" 33 #include "rs690d.h" 34 35 int rs690_mc_wait_for_idle(struct radeon_device *rdev) 36 { 37 unsigned i; 38 uint32_t tmp; 39 40 for (i = 0; i < rdev->usec_timeout; i++) { 41 /* read MC_STATUS */ 42 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 43 if (G_000090_MC_SYSTEM_IDLE(tmp)) 44 return 0; 45 udelay(1); 46 } 47 return -1; 48 } 49 50 static void rs690_gpu_init(struct radeon_device *rdev) 51 { 52 /* FIXME: is this correct ? */ 53 r420_pipes_init(rdev); 54 if (rs690_mc_wait_for_idle(rdev)) { 55 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 56 } 57 } 58 59 union igp_info { 60 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 62 }; 63 64 void rs690_pm_info(struct radeon_device *rdev) 65 { 66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 67 union igp_info *info; 68 uint16_t data_offset; 69 uint8_t frev, crev; 70 fixed20_12 tmp; 71 72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 73 &frev, &crev, &data_offset)) { 74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 75 76 /* Get various system informations from bios */ 77 switch (crev) { 78 case 1: 79 tmp.full = dfixed_const(100); 80 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 82 if (le16_to_cpu(info->info.usK8MemoryClock)) 83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 84 else if (rdev->clock.default_mclk) { 85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 87 } else 88 rdev->pm.igp_system_mclk.full = dfixed_const(400); 89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 91 break; 92 case 2: 93 tmp.full = dfixed_const(100); 94 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 96 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 98 else if (rdev->clock.default_mclk) 99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 100 else 101 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 106 break; 107 default: 108 /* We assume the slower possible clock ie worst case */ 109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 110 rdev->pm.igp_system_mclk.full = dfixed_const(200); 111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 112 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 113 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 114 break; 115 } 116 } else { 117 /* We assume the slower possible clock ie worst case */ 118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 119 rdev->pm.igp_system_mclk.full = dfixed_const(200); 120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 121 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 122 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 123 } 124 /* Compute various bandwidth */ 125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 126 tmp.full = dfixed_const(4); 127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 129 * = ht_clk * ht_width / 5 130 */ 131 tmp.full = dfixed_const(5); 132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 133 rdev->pm.igp_ht_link_width); 134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 135 if (tmp.full < rdev->pm.max_bandwidth.full) { 136 /* HT link is a limiting factor */ 137 rdev->pm.max_bandwidth.full = tmp.full; 138 } 139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 140 * = (sideport_clk * 14) / 10 141 */ 142 tmp.full = dfixed_const(14); 143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 144 tmp.full = dfixed_const(10); 145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 146 } 147 148 static void rs690_mc_init(struct radeon_device *rdev) 149 { 150 u64 base; 151 uint32_t h_addr, l_addr; 152 unsigned long long k8_addr; 153 154 rs400_gart_adjust_size(rdev); 155 rdev->mc.vram_is_ddr = true; 156 rdev->mc.vram_width = 128; 157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 161 rdev->mc.visible_vram_size = rdev->mc.aper_size; 162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 163 base = G_000100_MC_FB_START(base) << 16; 164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 165 /* Some boards seem to be configured for 128MB of sideport memory, 166 * but really only have 64MB. Just skip the sideport and use 167 * UMA memory. 168 */ 169 if (rdev->mc.igp_sideport_enabled && 170 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { 171 base += 128 * 1024 * 1024; 172 rdev->mc.real_vram_size -= 128 * 1024 * 1024; 173 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 174 } 175 176 /* Use K8 direct mapping for fast fb access. */ 177 rdev->fastfb_working = false; 178 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); 179 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); 180 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 181 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 182 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 183 #endif 184 { 185 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 186 * memory is present. 187 */ 188 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 189 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 190 (unsigned long long)rdev->mc.aper_base, k8_addr); 191 rdev->mc.aper_base = (resource_size_t)k8_addr; 192 rdev->fastfb_working = true; 193 } 194 } 195 196 rs690_pm_info(rdev); 197 radeon_vram_location(rdev, &rdev->mc, base); 198 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 199 radeon_gtt_location(rdev, &rdev->mc); 200 radeon_update_bandwidth_info(rdev); 201 } 202 203 void rs690_line_buffer_adjust(struct radeon_device *rdev, 204 struct drm_display_mode *mode1, 205 struct drm_display_mode *mode2) 206 { 207 u32 tmp; 208 209 /* Guess line buffer size to be 8192 pixels */ 210 u32 lb_size = 8192; 211 212 /* 213 * Line Buffer Setup 214 * There is a single line buffer shared by both display controllers. 215 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 216 * the display controllers. The paritioning can either be done 217 * manually or via one of four preset allocations specified in bits 1:0: 218 * 0 - line buffer is divided in half and shared between crtc 219 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 220 * 2 - D1 gets the whole buffer 221 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 222 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 223 * allocation mode. In manual allocation mode, D1 always starts at 0, 224 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 225 */ 226 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 227 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 228 /* auto */ 229 if (mode1 && mode2) { 230 if (mode1->hdisplay > mode2->hdisplay) { 231 if (mode1->hdisplay > 2560) 232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 233 else 234 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 235 } else if (mode2->hdisplay > mode1->hdisplay) { 236 if (mode2->hdisplay > 2560) 237 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 238 else 239 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 240 } else 241 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 242 } else if (mode1) { 243 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 244 } else if (mode2) { 245 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 246 } 247 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 248 249 /* Save number of lines the linebuffer leads before the scanout */ 250 if (mode1) 251 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 252 253 if (mode2) 254 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 255 } 256 257 struct rs690_watermark { 258 u32 lb_request_fifo_depth; 259 fixed20_12 num_line_pair; 260 fixed20_12 estimated_width; 261 fixed20_12 worst_case_latency; 262 fixed20_12 consumption_rate; 263 fixed20_12 active_time; 264 fixed20_12 dbpp; 265 fixed20_12 priority_mark_max; 266 fixed20_12 priority_mark; 267 fixed20_12 sclk; 268 }; 269 270 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 271 struct radeon_crtc *crtc, 272 struct rs690_watermark *wm, 273 bool low) 274 { 275 struct drm_display_mode *mode = &crtc->base.mode; 276 fixed20_12 a, b, c; 277 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 278 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 279 fixed20_12 sclk, core_bandwidth, max_bandwidth; 280 u32 selected_sclk; 281 282 if (!crtc->base.enabled) { 283 /* FIXME: wouldn't it better to set priority mark to maximum */ 284 wm->lb_request_fifo_depth = 4; 285 return; 286 } 287 288 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) && 289 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 290 selected_sclk = radeon_dpm_get_sclk(rdev, low); 291 else 292 selected_sclk = rdev->pm.current_sclk; 293 294 /* sclk in Mhz */ 295 a.full = dfixed_const(100); 296 sclk.full = dfixed_const(selected_sclk); 297 sclk.full = dfixed_div(sclk, a); 298 299 /* core_bandwidth = sclk(Mhz) * 16 */ 300 a.full = dfixed_const(16); 301 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 302 303 if (crtc->vsc.full > dfixed_const(2)) 304 wm->num_line_pair.full = dfixed_const(2); 305 else 306 wm->num_line_pair.full = dfixed_const(1); 307 308 b.full = dfixed_const(mode->crtc_hdisplay); 309 c.full = dfixed_const(256); 310 a.full = dfixed_div(b, c); 311 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 312 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 313 if (a.full < dfixed_const(4)) { 314 wm->lb_request_fifo_depth = 4; 315 } else { 316 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 317 } 318 319 /* Determine consumption rate 320 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 321 * vtaps = number of vertical taps, 322 * vsc = vertical scaling ratio, defined as source/destination 323 * hsc = horizontal scaling ration, defined as source/destination 324 */ 325 a.full = dfixed_const(mode->clock); 326 b.full = dfixed_const(1000); 327 a.full = dfixed_div(a, b); 328 pclk.full = dfixed_div(b, a); 329 if (crtc->rmx_type != RMX_OFF) { 330 b.full = dfixed_const(2); 331 if (crtc->vsc.full > b.full) 332 b.full = crtc->vsc.full; 333 b.full = dfixed_mul(b, crtc->hsc); 334 c.full = dfixed_const(2); 335 b.full = dfixed_div(b, c); 336 consumption_time.full = dfixed_div(pclk, b); 337 } else { 338 consumption_time.full = pclk.full; 339 } 340 a.full = dfixed_const(1); 341 wm->consumption_rate.full = dfixed_div(a, consumption_time); 342 343 344 /* Determine line time 345 * LineTime = total time for one line of displayhtotal 346 * LineTime = total number of horizontal pixels 347 * pclk = pixel clock period(ns) 348 */ 349 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 350 line_time.full = dfixed_mul(a, pclk); 351 352 /* Determine active time 353 * ActiveTime = time of active region of display within one line, 354 * hactive = total number of horizontal active pixels 355 * htotal = total number of horizontal pixels 356 */ 357 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 358 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 359 wm->active_time.full = dfixed_mul(line_time, b); 360 wm->active_time.full = dfixed_div(wm->active_time, a); 361 362 /* Maximun bandwidth is the minimun bandwidth of all component */ 363 max_bandwidth = core_bandwidth; 364 if (rdev->mc.igp_sideport_enabled) { 365 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 366 rdev->pm.sideport_bandwidth.full) 367 max_bandwidth = rdev->pm.sideport_bandwidth; 368 read_delay_latency.full = dfixed_const(370 * 800); 369 a.full = dfixed_const(1000); 370 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a); 371 read_delay_latency.full = dfixed_div(read_delay_latency, b); 372 read_delay_latency.full = dfixed_mul(read_delay_latency, a); 373 } else { 374 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 375 rdev->pm.k8_bandwidth.full) 376 max_bandwidth = rdev->pm.k8_bandwidth; 377 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && 378 rdev->pm.ht_bandwidth.full) 379 max_bandwidth = rdev->pm.ht_bandwidth; 380 read_delay_latency.full = dfixed_const(5000); 381 } 382 383 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 384 a.full = dfixed_const(16); 385 sclk.full = dfixed_mul(max_bandwidth, a); 386 a.full = dfixed_const(1000); 387 sclk.full = dfixed_div(a, sclk); 388 /* Determine chunk time 389 * ChunkTime = the time it takes the DCP to send one chunk of data 390 * to the LB which consists of pipeline delay and inter chunk gap 391 * sclk = system clock(ns) 392 */ 393 a.full = dfixed_const(256 * 13); 394 chunk_time.full = dfixed_mul(sclk, a); 395 a.full = dfixed_const(10); 396 chunk_time.full = dfixed_div(chunk_time, a); 397 398 /* Determine the worst case latency 399 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 400 * WorstCaseLatency = worst case time from urgent to when the MC starts 401 * to return data 402 * READ_DELAY_IDLE_MAX = constant of 1us 403 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 404 * which consists of pipeline delay and inter chunk gap 405 */ 406 if (dfixed_trunc(wm->num_line_pair) > 1) { 407 a.full = dfixed_const(3); 408 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 409 wm->worst_case_latency.full += read_delay_latency.full; 410 } else { 411 a.full = dfixed_const(2); 412 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 413 wm->worst_case_latency.full += read_delay_latency.full; 414 } 415 416 /* Determine the tolerable latency 417 * TolerableLatency = Any given request has only 1 line time 418 * for the data to be returned 419 * LBRequestFifoDepth = Number of chunk requests the LB can 420 * put into the request FIFO for a display 421 * LineTime = total time for one line of display 422 * ChunkTime = the time it takes the DCP to send one chunk 423 * of data to the LB which consists of 424 * pipeline delay and inter chunk gap 425 */ 426 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 427 tolerable_latency.full = line_time.full; 428 } else { 429 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 430 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 431 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 432 tolerable_latency.full = line_time.full - tolerable_latency.full; 433 } 434 /* We assume worst case 32bits (4 bytes) */ 435 wm->dbpp.full = dfixed_const(4 * 8); 436 437 /* Determine the maximum priority mark 438 * width = viewport width in pixels 439 */ 440 a.full = dfixed_const(16); 441 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 442 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 443 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 444 445 /* Determine estimated width */ 446 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 447 estimated_width.full = dfixed_div(estimated_width, consumption_time); 448 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 449 wm->priority_mark.full = dfixed_const(10); 450 } else { 451 a.full = dfixed_const(16); 452 wm->priority_mark.full = dfixed_div(estimated_width, a); 453 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 454 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 455 } 456 } 457 458 static void rs690_compute_mode_priority(struct radeon_device *rdev, 459 struct rs690_watermark *wm0, 460 struct rs690_watermark *wm1, 461 struct drm_display_mode *mode0, 462 struct drm_display_mode *mode1, 463 u32 *d1mode_priority_a_cnt, 464 u32 *d2mode_priority_a_cnt) 465 { 466 fixed20_12 priority_mark02, priority_mark12, fill_rate; 467 fixed20_12 a, b; 468 469 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 470 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 471 472 if (mode0 && mode1) { 473 if (dfixed_trunc(wm0->dbpp) > 64) 474 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 475 else 476 a.full = wm0->num_line_pair.full; 477 if (dfixed_trunc(wm1->dbpp) > 64) 478 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 479 else 480 b.full = wm1->num_line_pair.full; 481 a.full += b.full; 482 fill_rate.full = dfixed_div(wm0->sclk, a); 483 if (wm0->consumption_rate.full > fill_rate.full) { 484 b.full = wm0->consumption_rate.full - fill_rate.full; 485 b.full = dfixed_mul(b, wm0->active_time); 486 a.full = dfixed_mul(wm0->worst_case_latency, 487 wm0->consumption_rate); 488 a.full = a.full + b.full; 489 b.full = dfixed_const(16 * 1000); 490 priority_mark02.full = dfixed_div(a, b); 491 } else { 492 a.full = dfixed_mul(wm0->worst_case_latency, 493 wm0->consumption_rate); 494 b.full = dfixed_const(16 * 1000); 495 priority_mark02.full = dfixed_div(a, b); 496 } 497 if (wm1->consumption_rate.full > fill_rate.full) { 498 b.full = wm1->consumption_rate.full - fill_rate.full; 499 b.full = dfixed_mul(b, wm1->active_time); 500 a.full = dfixed_mul(wm1->worst_case_latency, 501 wm1->consumption_rate); 502 a.full = a.full + b.full; 503 b.full = dfixed_const(16 * 1000); 504 priority_mark12.full = dfixed_div(a, b); 505 } else { 506 a.full = dfixed_mul(wm1->worst_case_latency, 507 wm1->consumption_rate); 508 b.full = dfixed_const(16 * 1000); 509 priority_mark12.full = dfixed_div(a, b); 510 } 511 if (wm0->priority_mark.full > priority_mark02.full) 512 priority_mark02.full = wm0->priority_mark.full; 513 if (wm0->priority_mark_max.full > priority_mark02.full) 514 priority_mark02.full = wm0->priority_mark_max.full; 515 if (wm1->priority_mark.full > priority_mark12.full) 516 priority_mark12.full = wm1->priority_mark.full; 517 if (wm1->priority_mark_max.full > priority_mark12.full) 518 priority_mark12.full = wm1->priority_mark_max.full; 519 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 520 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 521 if (rdev->disp_priority == 2) { 522 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 523 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 524 } 525 } else if (mode0) { 526 if (dfixed_trunc(wm0->dbpp) > 64) 527 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 528 else 529 a.full = wm0->num_line_pair.full; 530 fill_rate.full = dfixed_div(wm0->sclk, a); 531 if (wm0->consumption_rate.full > fill_rate.full) { 532 b.full = wm0->consumption_rate.full - fill_rate.full; 533 b.full = dfixed_mul(b, wm0->active_time); 534 a.full = dfixed_mul(wm0->worst_case_latency, 535 wm0->consumption_rate); 536 a.full = a.full + b.full; 537 b.full = dfixed_const(16 * 1000); 538 priority_mark02.full = dfixed_div(a, b); 539 } else { 540 a.full = dfixed_mul(wm0->worst_case_latency, 541 wm0->consumption_rate); 542 b.full = dfixed_const(16 * 1000); 543 priority_mark02.full = dfixed_div(a, b); 544 } 545 if (wm0->priority_mark.full > priority_mark02.full) 546 priority_mark02.full = wm0->priority_mark.full; 547 if (wm0->priority_mark_max.full > priority_mark02.full) 548 priority_mark02.full = wm0->priority_mark_max.full; 549 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 550 if (rdev->disp_priority == 2) 551 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 552 } else if (mode1) { 553 if (dfixed_trunc(wm1->dbpp) > 64) 554 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 555 else 556 a.full = wm1->num_line_pair.full; 557 fill_rate.full = dfixed_div(wm1->sclk, a); 558 if (wm1->consumption_rate.full > fill_rate.full) { 559 b.full = wm1->consumption_rate.full - fill_rate.full; 560 b.full = dfixed_mul(b, wm1->active_time); 561 a.full = dfixed_mul(wm1->worst_case_latency, 562 wm1->consumption_rate); 563 a.full = a.full + b.full; 564 b.full = dfixed_const(16 * 1000); 565 priority_mark12.full = dfixed_div(a, b); 566 } else { 567 a.full = dfixed_mul(wm1->worst_case_latency, 568 wm1->consumption_rate); 569 b.full = dfixed_const(16 * 1000); 570 priority_mark12.full = dfixed_div(a, b); 571 } 572 if (wm1->priority_mark.full > priority_mark12.full) 573 priority_mark12.full = wm1->priority_mark.full; 574 if (wm1->priority_mark_max.full > priority_mark12.full) 575 priority_mark12.full = wm1->priority_mark_max.full; 576 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 577 if (rdev->disp_priority == 2) 578 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 579 } 580 } 581 582 void rs690_bandwidth_update(struct radeon_device *rdev) 583 { 584 struct drm_display_mode *mode0 = NULL; 585 struct drm_display_mode *mode1 = NULL; 586 struct rs690_watermark wm0_high, wm0_low; 587 struct rs690_watermark wm1_high, wm1_low; 588 u32 tmp; 589 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 590 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 591 592 if (!rdev->mode_info.mode_config_initialized) 593 return; 594 595 radeon_update_display_priority(rdev); 596 597 if (rdev->mode_info.crtcs[0]->base.enabled) 598 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 599 if (rdev->mode_info.crtcs[1]->base.enabled) 600 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 601 /* 602 * Set display0/1 priority up in the memory controller for 603 * modes if the user specifies HIGH for displaypriority 604 * option. 605 */ 606 if ((rdev->disp_priority == 2) && 607 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 608 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 609 tmp &= C_000104_MC_DISP0R_INIT_LAT; 610 tmp &= C_000104_MC_DISP1R_INIT_LAT; 611 if (mode0) 612 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 613 if (mode1) 614 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 615 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 616 } 617 rs690_line_buffer_adjust(rdev, mode0, mode1); 618 619 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 620 WREG32(R_006C9C_DCP_CONTROL, 0); 621 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 622 WREG32(R_006C9C_DCP_CONTROL, 2); 623 624 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 625 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 626 627 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); 628 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); 629 630 tmp = (wm0_high.lb_request_fifo_depth - 1); 631 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16; 632 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 633 634 rs690_compute_mode_priority(rdev, 635 &wm0_high, &wm1_high, 636 mode0, mode1, 637 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 638 rs690_compute_mode_priority(rdev, 639 &wm0_low, &wm1_low, 640 mode0, mode1, 641 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 642 643 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 644 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 645 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 646 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 647 } 648 649 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 650 { 651 unsigned long flags; 652 uint32_t r; 653 654 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 655 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 656 r = RREG32(R_00007C_MC_DATA); 657 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 658 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 659 return r; 660 } 661 662 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 663 { 664 unsigned long flags; 665 666 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 667 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 668 S_000078_MC_IND_WR_EN(1)); 669 WREG32(R_00007C_MC_DATA, v); 670 WREG32(R_000078_MC_INDEX, 0x7F); 671 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 672 } 673 674 static void rs690_mc_program(struct radeon_device *rdev) 675 { 676 struct rv515_mc_save save; 677 678 /* Stops all mc clients */ 679 rv515_mc_stop(rdev, &save); 680 681 /* Wait for mc idle */ 682 if (rs690_mc_wait_for_idle(rdev)) 683 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 684 /* Program MC, should be a 32bits limited address space */ 685 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 686 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 687 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 688 WREG32(R_000134_HDP_FB_LOCATION, 689 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 690 691 rv515_mc_resume(rdev, &save); 692 } 693 694 static int rs690_startup(struct radeon_device *rdev) 695 { 696 int r; 697 698 rs690_mc_program(rdev); 699 /* Resume clock */ 700 rv515_clock_startup(rdev); 701 /* Initialize GPU configuration (# pipes, ...) */ 702 rs690_gpu_init(rdev); 703 /* Initialize GART (initialize after TTM so we can allocate 704 * memory through TTM but finalize after TTM) */ 705 r = rs400_gart_enable(rdev); 706 if (r) 707 return r; 708 709 /* allocate wb buffer */ 710 r = radeon_wb_init(rdev); 711 if (r) 712 return r; 713 714 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 715 if (r) { 716 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 717 return r; 718 } 719 720 /* Enable IRQ */ 721 if (!rdev->irq.installed) { 722 r = radeon_irq_kms_init(rdev); 723 if (r) 724 return r; 725 } 726 727 rs600_irq_set(rdev); 728 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 729 /* 1M ring buffer */ 730 r = r100_cp_init(rdev, 1024 * 1024); 731 if (r) { 732 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 733 return r; 734 } 735 736 r = radeon_ib_pool_init(rdev); 737 if (r) { 738 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 739 return r; 740 } 741 742 r = radeon_audio_init(rdev); 743 if (r) { 744 dev_err(rdev->dev, "failed initializing audio\n"); 745 return r; 746 } 747 748 return 0; 749 } 750 751 int rs690_resume(struct radeon_device *rdev) 752 { 753 int r; 754 755 /* Make sur GART are not working */ 756 rs400_gart_disable(rdev); 757 /* Resume clock before doing reset */ 758 rv515_clock_startup(rdev); 759 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 760 if (radeon_asic_reset(rdev)) { 761 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 762 RREG32(R_000E40_RBBM_STATUS), 763 RREG32(R_0007C0_CP_STAT)); 764 } 765 /* post */ 766 atom_asic_init(rdev->mode_info.atom_context); 767 /* Resume clock after posting */ 768 rv515_clock_startup(rdev); 769 /* Initialize surface registers */ 770 radeon_surface_init(rdev); 771 772 rdev->accel_working = true; 773 r = rs690_startup(rdev); 774 if (r) { 775 rdev->accel_working = false; 776 } 777 return r; 778 } 779 780 int rs690_suspend(struct radeon_device *rdev) 781 { 782 radeon_pm_suspend(rdev); 783 radeon_audio_fini(rdev); 784 r100_cp_disable(rdev); 785 radeon_wb_disable(rdev); 786 rs600_irq_disable(rdev); 787 rs400_gart_disable(rdev); 788 return 0; 789 } 790 791 void rs690_fini(struct radeon_device *rdev) 792 { 793 radeon_pm_fini(rdev); 794 radeon_audio_fini(rdev); 795 r100_cp_fini(rdev); 796 radeon_wb_fini(rdev); 797 radeon_ib_pool_fini(rdev); 798 radeon_gem_fini(rdev); 799 rs400_gart_fini(rdev); 800 radeon_irq_kms_fini(rdev); 801 radeon_fence_driver_fini(rdev); 802 radeon_bo_fini(rdev); 803 radeon_atombios_fini(rdev); 804 kfree(rdev->bios); 805 rdev->bios = NULL; 806 } 807 808 int rs690_init(struct radeon_device *rdev) 809 { 810 int r; 811 812 /* Disable VGA */ 813 rv515_vga_render_disable(rdev); 814 /* Initialize scratch registers */ 815 radeon_scratch_init(rdev); 816 /* Initialize surface registers */ 817 radeon_surface_init(rdev); 818 /* restore some register to sane defaults */ 819 r100_restore_sanity(rdev); 820 /* TODO: disable VGA need to use VGA request */ 821 /* BIOS*/ 822 if (!radeon_get_bios(rdev)) { 823 if (ASIC_IS_AVIVO(rdev)) 824 return -EINVAL; 825 } 826 if (rdev->is_atom_bios) { 827 r = radeon_atombios_init(rdev); 828 if (r) 829 return r; 830 } else { 831 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 832 return -EINVAL; 833 } 834 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 835 if (radeon_asic_reset(rdev)) { 836 dev_warn(rdev->dev, 837 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 838 RREG32(R_000E40_RBBM_STATUS), 839 RREG32(R_0007C0_CP_STAT)); 840 } 841 /* check if cards are posted or not */ 842 if (radeon_boot_test_post_card(rdev) == false) 843 return -EINVAL; 844 845 /* Initialize clocks */ 846 radeon_get_clock_info(rdev->ddev); 847 /* initialize memory controller */ 848 rs690_mc_init(rdev); 849 rv515_debugfs(rdev); 850 /* Fence driver */ 851 r = radeon_fence_driver_init(rdev); 852 if (r) 853 return r; 854 /* Memory manager */ 855 r = radeon_bo_init(rdev); 856 if (r) 857 return r; 858 r = rs400_gart_init(rdev); 859 if (r) 860 return r; 861 rs600_set_safe_registers(rdev); 862 863 /* Initialize power management */ 864 radeon_pm_init(rdev); 865 866 rdev->accel_working = true; 867 r = rs690_startup(rdev); 868 if (r) { 869 /* Somethings want wront with the accel init stop accel */ 870 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 871 r100_cp_fini(rdev); 872 radeon_wb_fini(rdev); 873 radeon_ib_pool_fini(rdev); 874 rs400_gart_fini(rdev); 875 radeon_irq_kms_fini(rdev); 876 rdev->accel_working = false; 877 } 878 return 0; 879 } 880