1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include <drm/drmP.h> 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_audio.h" 42 #include "atom.h" 43 #include "rs600d.h" 44 45 #include "rs600_reg_safe.h" 46 47 static void rs600_gpu_init(struct radeon_device *rdev); 48 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 49 50 static const u32 crtc_offsets[2] = 51 { 52 0, 53 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 54 }; 55 56 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 57 { 58 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 59 return true; 60 else 61 return false; 62 } 63 64 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 65 { 66 u32 pos1, pos2; 67 68 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 69 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 70 71 if (pos1 != pos2) 72 return true; 73 else 74 return false; 75 } 76 77 /** 78 * avivo_wait_for_vblank - vblank wait asic callback. 79 * 80 * @rdev: radeon_device pointer 81 * @crtc: crtc to wait for vblank on 82 * 83 * Wait for vblank on the requested crtc (r5xx-r7xx). 84 */ 85 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 86 { 87 unsigned i = 0; 88 89 if (crtc >= rdev->num_crtc) 90 return; 91 92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 93 return; 94 95 /* depending on when we hit vblank, we may be close to active; if so, 96 * wait for another frame. 97 */ 98 while (avivo_is_in_vblank(rdev, crtc)) { 99 if (i++ % 100 == 0) { 100 if (!avivo_is_counter_moving(rdev, crtc)) 101 break; 102 } 103 } 104 105 while (!avivo_is_in_vblank(rdev, crtc)) { 106 if (i++ % 100 == 0) { 107 if (!avivo_is_counter_moving(rdev, crtc)) 108 break; 109 } 110 } 111 } 112 113 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 114 { 115 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 117 int i; 118 119 /* Lock the graphics update lock */ 120 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 121 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 122 123 /* update the scanout addresses */ 124 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 125 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); 126 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 127 (u32)crtc_base); 128 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 129 (u32)crtc_base); 130 131 /* Wait for update_pending to go high. */ 132 for (i = 0; i < rdev->usec_timeout; i++) { 133 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 134 break; 135 udelay(1); 136 } 137 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 138 139 /* Unlock the lock, so double-buffering can take place inside vblank */ 140 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 141 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 142 } 143 144 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) 145 { 146 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 147 148 /* Return current update_pending status: */ 149 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 150 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 151 } 152 153 void avivo_program_fmt(struct drm_encoder *encoder) 154 { 155 struct drm_device *dev = encoder->dev; 156 struct radeon_device *rdev = dev->dev_private; 157 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 158 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 159 int bpc = 0; 160 u32 tmp = 0; 161 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 162 163 if (connector) { 164 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 165 bpc = radeon_get_monitor_bpc(connector); 166 dither = radeon_connector->dither; 167 } 168 169 /* LVDS FMT is set up by atom */ 170 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 171 return; 172 173 if (bpc == 0) 174 return; 175 176 switch (bpc) { 177 case 6: 178 if (dither == RADEON_FMT_DITHER_ENABLE) 179 /* XXX sort out optimal dither settings */ 180 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 181 else 182 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; 183 break; 184 case 8: 185 if (dither == RADEON_FMT_DITHER_ENABLE) 186 /* XXX sort out optimal dither settings */ 187 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | 188 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); 189 else 190 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | 191 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); 192 break; 193 case 10: 194 default: 195 /* not needed */ 196 break; 197 } 198 199 switch (radeon_encoder->encoder_id) { 200 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 201 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); 202 break; 203 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 204 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); 205 break; 206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 207 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); 208 break; 209 case ENCODER_OBJECT_ID_INTERNAL_DDI: 210 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); 211 break; 212 default: 213 break; 214 } 215 } 216 217 void rs600_pm_misc(struct radeon_device *rdev) 218 { 219 int requested_index = rdev->pm.requested_power_state_index; 220 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 221 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 222 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 223 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 224 225 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 226 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 227 tmp = RREG32(voltage->gpio.reg); 228 if (voltage->active_high) 229 tmp |= voltage->gpio.mask; 230 else 231 tmp &= ~(voltage->gpio.mask); 232 WREG32(voltage->gpio.reg, tmp); 233 if (voltage->delay) 234 udelay(voltage->delay); 235 } else { 236 tmp = RREG32(voltage->gpio.reg); 237 if (voltage->active_high) 238 tmp &= ~voltage->gpio.mask; 239 else 240 tmp |= voltage->gpio.mask; 241 WREG32(voltage->gpio.reg, tmp); 242 if (voltage->delay) 243 udelay(voltage->delay); 244 } 245 } else if (voltage->type == VOLTAGE_VDDC) 246 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 247 248 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 249 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 250 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 251 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 252 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 253 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 254 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 255 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 256 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 257 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 258 } 259 } else { 260 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 261 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 262 } 263 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 264 265 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 266 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 267 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 268 if (voltage->delay) { 269 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 270 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 271 } else 272 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 273 } else 274 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 275 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 276 277 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 278 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 279 hdp_dyn_cntl &= ~HDP_FORCEON; 280 else 281 hdp_dyn_cntl |= HDP_FORCEON; 282 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 283 #if 0 284 /* mc_host_dyn seems to cause hangs from time to time */ 285 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 286 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 287 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 288 else 289 mc_host_dyn_cntl |= MC_HOST_FORCEON; 290 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 291 #endif 292 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 293 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 294 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 295 else 296 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 297 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 298 299 /* set pcie lanes */ 300 if ((rdev->flags & RADEON_IS_PCIE) && 301 !(rdev->flags & RADEON_IS_IGP) && 302 rdev->asic->pm.set_pcie_lanes && 303 (ps->pcie_lanes != 304 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 305 radeon_set_pcie_lanes(rdev, 306 ps->pcie_lanes); 307 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 308 } 309 } 310 311 void rs600_pm_prepare(struct radeon_device *rdev) 312 { 313 struct drm_device *ddev = rdev->ddev; 314 struct drm_crtc *crtc; 315 struct radeon_crtc *radeon_crtc; 316 u32 tmp; 317 318 /* disable any active CRTCs */ 319 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 320 radeon_crtc = to_radeon_crtc(crtc); 321 if (radeon_crtc->enabled) { 322 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 323 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 324 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 325 } 326 } 327 } 328 329 void rs600_pm_finish(struct radeon_device *rdev) 330 { 331 struct drm_device *ddev = rdev->ddev; 332 struct drm_crtc *crtc; 333 struct radeon_crtc *radeon_crtc; 334 u32 tmp; 335 336 /* enable any active CRTCs */ 337 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 338 radeon_crtc = to_radeon_crtc(crtc); 339 if (radeon_crtc->enabled) { 340 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 341 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 342 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 343 } 344 } 345 } 346 347 /* hpd for digital panel detect/disconnect */ 348 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 349 { 350 u32 tmp; 351 bool connected = false; 352 353 switch (hpd) { 354 case RADEON_HPD_1: 355 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 356 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 357 connected = true; 358 break; 359 case RADEON_HPD_2: 360 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 361 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 362 connected = true; 363 break; 364 default: 365 break; 366 } 367 return connected; 368 } 369 370 void rs600_hpd_set_polarity(struct radeon_device *rdev, 371 enum radeon_hpd_id hpd) 372 { 373 u32 tmp; 374 bool connected = rs600_hpd_sense(rdev, hpd); 375 376 switch (hpd) { 377 case RADEON_HPD_1: 378 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 379 if (connected) 380 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 381 else 382 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 383 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 384 break; 385 case RADEON_HPD_2: 386 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 387 if (connected) 388 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 389 else 390 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 391 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 392 break; 393 default: 394 break; 395 } 396 } 397 398 void rs600_hpd_init(struct radeon_device *rdev) 399 { 400 struct drm_device *dev = rdev->ddev; 401 struct drm_connector *connector; 402 unsigned enable = 0; 403 404 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 405 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 406 switch (radeon_connector->hpd.hpd) { 407 case RADEON_HPD_1: 408 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 409 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 410 break; 411 case RADEON_HPD_2: 412 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 413 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 414 break; 415 default: 416 break; 417 } 418 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 419 enable |= 1 << radeon_connector->hpd.hpd; 420 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 421 } 422 radeon_irq_kms_enable_hpd(rdev, enable); 423 } 424 425 void rs600_hpd_fini(struct radeon_device *rdev) 426 { 427 struct drm_device *dev = rdev->ddev; 428 struct drm_connector *connector; 429 unsigned disable = 0; 430 431 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 432 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 433 switch (radeon_connector->hpd.hpd) { 434 case RADEON_HPD_1: 435 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 436 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 437 break; 438 case RADEON_HPD_2: 439 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 440 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 441 break; 442 default: 443 break; 444 } 445 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 446 disable |= 1 << radeon_connector->hpd.hpd; 447 } 448 radeon_irq_kms_disable_hpd(rdev, disable); 449 } 450 451 int rs600_asic_reset(struct radeon_device *rdev, bool hard) 452 { 453 struct rv515_mc_save save; 454 u32 status, tmp; 455 int ret = 0; 456 457 status = RREG32(R_000E40_RBBM_STATUS); 458 if (!G_000E40_GUI_ACTIVE(status)) { 459 return 0; 460 } 461 /* Stops all mc clients */ 462 rv515_mc_stop(rdev, &save); 463 status = RREG32(R_000E40_RBBM_STATUS); 464 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 465 /* stop CP */ 466 WREG32(RADEON_CP_CSQ_CNTL, 0); 467 tmp = RREG32(RADEON_CP_RB_CNTL); 468 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 469 WREG32(RADEON_CP_RB_RPTR_WR, 0); 470 WREG32(RADEON_CP_RB_WPTR, 0); 471 WREG32(RADEON_CP_RB_CNTL, tmp); 472 pci_save_state(rdev->pdev); 473 /* disable bus mastering */ 474 pci_clear_master(rdev->pdev); 475 mdelay(1); 476 /* reset GA+VAP */ 477 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 478 S_0000F0_SOFT_RESET_GA(1)); 479 RREG32(R_0000F0_RBBM_SOFT_RESET); 480 mdelay(500); 481 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 482 mdelay(1); 483 status = RREG32(R_000E40_RBBM_STATUS); 484 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 485 /* reset CP */ 486 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 487 RREG32(R_0000F0_RBBM_SOFT_RESET); 488 mdelay(500); 489 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 490 mdelay(1); 491 status = RREG32(R_000E40_RBBM_STATUS); 492 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 493 /* reset MC */ 494 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 495 RREG32(R_0000F0_RBBM_SOFT_RESET); 496 mdelay(500); 497 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 498 mdelay(1); 499 status = RREG32(R_000E40_RBBM_STATUS); 500 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 501 /* restore PCI & busmastering */ 502 pci_restore_state(rdev->pdev); 503 /* Check if GPU is idle */ 504 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 505 dev_err(rdev->dev, "failed to reset GPU\n"); 506 ret = -1; 507 } else 508 dev_info(rdev->dev, "GPU reset succeed\n"); 509 rv515_mc_resume(rdev, &save); 510 return ret; 511 } 512 513 /* 514 * GART. 515 */ 516 void rs600_gart_tlb_flush(struct radeon_device *rdev) 517 { 518 uint32_t tmp; 519 520 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 521 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 522 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 523 524 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 525 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 526 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 527 528 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 529 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 530 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 531 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 532 } 533 534 static int rs600_gart_init(struct radeon_device *rdev) 535 { 536 int r; 537 538 if (rdev->gart.robj) { 539 WARN(1, "RS600 GART already initialized\n"); 540 return 0; 541 } 542 /* Initialize common gart structure */ 543 r = radeon_gart_init(rdev); 544 if (r) { 545 return r; 546 } 547 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 548 return radeon_gart_table_vram_alloc(rdev); 549 } 550 551 static int rs600_gart_enable(struct radeon_device *rdev) 552 { 553 u32 tmp; 554 int r, i; 555 556 if (rdev->gart.robj == NULL) { 557 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 558 return -EINVAL; 559 } 560 r = radeon_gart_table_vram_pin(rdev); 561 if (r) 562 return r; 563 /* Enable bus master */ 564 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 565 WREG32(RADEON_BUS_CNTL, tmp); 566 /* FIXME: setup default page */ 567 WREG32_MC(R_000100_MC_PT0_CNTL, 568 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 569 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 570 571 for (i = 0; i < 19; i++) { 572 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 573 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 574 S_00016C_SYSTEM_ACCESS_MODE_MASK( 575 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 576 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 577 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 578 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 579 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 580 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 581 } 582 /* enable first context */ 583 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 584 S_000102_ENABLE_PAGE_TABLE(1) | 585 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 586 587 /* disable all other contexts */ 588 for (i = 1; i < 8; i++) 589 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 590 591 /* setup the page table */ 592 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 593 rdev->gart.table_addr); 594 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 595 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 596 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 597 598 /* System context maps to VRAM space */ 599 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 600 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 601 602 /* enable page tables */ 603 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 604 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 605 tmp = RREG32_MC(R_000009_MC_CNTL1); 606 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 607 rs600_gart_tlb_flush(rdev); 608 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 609 (unsigned)(rdev->mc.gtt_size >> 20), 610 (unsigned long long)rdev->gart.table_addr); 611 rdev->gart.ready = true; 612 return 0; 613 } 614 615 static void rs600_gart_disable(struct radeon_device *rdev) 616 { 617 u32 tmp; 618 619 /* FIXME: disable out of gart access */ 620 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 621 tmp = RREG32_MC(R_000009_MC_CNTL1); 622 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 623 radeon_gart_table_vram_unpin(rdev); 624 } 625 626 static void rs600_gart_fini(struct radeon_device *rdev) 627 { 628 radeon_gart_fini(rdev); 629 rs600_gart_disable(rdev); 630 radeon_gart_table_vram_free(rdev); 631 } 632 633 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) 634 { 635 addr = addr & 0xFFFFFFFFFFFFF000ULL; 636 addr |= R600_PTE_SYSTEM; 637 if (flags & RADEON_GART_PAGE_VALID) 638 addr |= R600_PTE_VALID; 639 if (flags & RADEON_GART_PAGE_READ) 640 addr |= R600_PTE_READABLE; 641 if (flags & RADEON_GART_PAGE_WRITE) 642 addr |= R600_PTE_WRITEABLE; 643 if (flags & RADEON_GART_PAGE_SNOOP) 644 addr |= R600_PTE_SNOOPED; 645 return addr; 646 } 647 648 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 649 uint64_t entry) 650 { 651 void __iomem *ptr = (void *)rdev->gart.ptr; 652 writeq(entry, ptr + (i * 8)); 653 } 654 655 int rs600_irq_set(struct radeon_device *rdev) 656 { 657 uint32_t tmp = 0; 658 uint32_t mode_int = 0; 659 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 660 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 661 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 662 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 663 u32 hdmi0; 664 if (ASIC_IS_DCE2(rdev)) 665 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 666 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 667 else 668 hdmi0 = 0; 669 670 if (!rdev->irq.installed) { 671 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 672 WREG32(R_000040_GEN_INT_CNTL, 0); 673 return -EINVAL; 674 } 675 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 676 tmp |= S_000040_SW_INT_EN(1); 677 } 678 if (rdev->irq.crtc_vblank_int[0] || 679 atomic_read(&rdev->irq.pflip[0])) { 680 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 681 } 682 if (rdev->irq.crtc_vblank_int[1] || 683 atomic_read(&rdev->irq.pflip[1])) { 684 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 685 } 686 if (rdev->irq.hpd[0]) { 687 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 688 } 689 if (rdev->irq.hpd[1]) { 690 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 691 } 692 if (rdev->irq.afmt[0]) { 693 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 694 } 695 WREG32(R_000040_GEN_INT_CNTL, tmp); 696 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 697 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 698 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 699 if (ASIC_IS_DCE2(rdev)) 700 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 701 702 /* posting read */ 703 RREG32(R_000040_GEN_INT_CNTL); 704 705 return 0; 706 } 707 708 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 709 { 710 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 711 uint32_t irq_mask = S_000044_SW_INT(1); 712 u32 tmp; 713 714 if (G_000044_DISPLAY_INT_STAT(irqs)) { 715 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 716 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 717 WREG32(R_006534_D1MODE_VBLANK_STATUS, 718 S_006534_D1MODE_VBLANK_ACK(1)); 719 } 720 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 721 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 722 S_006D34_D2MODE_VBLANK_ACK(1)); 723 } 724 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 725 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 726 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 727 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 728 } 729 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 730 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 731 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 732 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 733 } 734 } else { 735 rdev->irq.stat_regs.r500.disp_int = 0; 736 } 737 738 if (ASIC_IS_DCE2(rdev)) { 739 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 740 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 741 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 742 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 743 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 744 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 745 } 746 } else 747 rdev->irq.stat_regs.r500.hdmi0_status = 0; 748 749 if (irqs) { 750 WREG32(R_000044_GEN_INT_STATUS, irqs); 751 } 752 return irqs & irq_mask; 753 } 754 755 void rs600_irq_disable(struct radeon_device *rdev) 756 { 757 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 758 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 759 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 760 WREG32(R_000040_GEN_INT_CNTL, 0); 761 WREG32(R_006540_DxMODE_INT_MASK, 0); 762 /* Wait and acknowledge irq */ 763 mdelay(1); 764 rs600_irq_ack(rdev); 765 } 766 767 int rs600_irq_process(struct radeon_device *rdev) 768 { 769 u32 status, msi_rearm; 770 bool queue_hotplug = false; 771 bool queue_hdmi = false; 772 773 status = rs600_irq_ack(rdev); 774 if (!status && 775 !rdev->irq.stat_regs.r500.disp_int && 776 !rdev->irq.stat_regs.r500.hdmi0_status) { 777 return IRQ_NONE; 778 } 779 while (status || 780 rdev->irq.stat_regs.r500.disp_int || 781 rdev->irq.stat_regs.r500.hdmi0_status) { 782 /* SW interrupt */ 783 if (G_000044_SW_INT(status)) { 784 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 785 } 786 /* Vertical blank interrupts */ 787 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 788 if (rdev->irq.crtc_vblank_int[0]) { 789 drm_handle_vblank(rdev->ddev, 0); 790 rdev->pm.vblank_sync = true; 791 wake_up(&rdev->irq.vblank_queue); 792 } 793 if (atomic_read(&rdev->irq.pflip[0])) 794 radeon_crtc_handle_vblank(rdev, 0); 795 } 796 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 797 if (rdev->irq.crtc_vblank_int[1]) { 798 drm_handle_vblank(rdev->ddev, 1); 799 rdev->pm.vblank_sync = true; 800 wake_up(&rdev->irq.vblank_queue); 801 } 802 if (atomic_read(&rdev->irq.pflip[1])) 803 radeon_crtc_handle_vblank(rdev, 1); 804 } 805 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 806 queue_hotplug = true; 807 DRM_DEBUG("HPD1\n"); 808 } 809 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 810 queue_hotplug = true; 811 DRM_DEBUG("HPD2\n"); 812 } 813 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 814 queue_hdmi = true; 815 DRM_DEBUG("HDMI0\n"); 816 } 817 status = rs600_irq_ack(rdev); 818 } 819 if (queue_hotplug) 820 schedule_delayed_work(&rdev->hotplug_work, 0); 821 if (queue_hdmi) 822 schedule_work(&rdev->audio_work); 823 if (rdev->msi_enabled) { 824 switch (rdev->family) { 825 case CHIP_RS600: 826 case CHIP_RS690: 827 case CHIP_RS740: 828 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 829 WREG32(RADEON_BUS_CNTL, msi_rearm); 830 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 831 break; 832 default: 833 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 834 break; 835 } 836 } 837 return IRQ_HANDLED; 838 } 839 840 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 841 { 842 if (crtc == 0) 843 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 844 else 845 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 846 } 847 848 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 849 { 850 unsigned i; 851 852 for (i = 0; i < rdev->usec_timeout; i++) { 853 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 854 return 0; 855 udelay(1); 856 } 857 return -1; 858 } 859 860 static void rs600_gpu_init(struct radeon_device *rdev) 861 { 862 r420_pipes_init(rdev); 863 /* Wait for mc idle */ 864 if (rs600_mc_wait_for_idle(rdev)) 865 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 866 } 867 868 static void rs600_mc_init(struct radeon_device *rdev) 869 { 870 u64 base; 871 872 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 873 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 874 rdev->mc.vram_is_ddr = true; 875 rdev->mc.vram_width = 128; 876 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 877 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 878 rdev->mc.visible_vram_size = rdev->mc.aper_size; 879 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 880 base = RREG32_MC(R_000004_MC_FB_LOCATION); 881 base = G_000004_MC_FB_START(base) << 16; 882 radeon_vram_location(rdev, &rdev->mc, base); 883 rdev->mc.gtt_base_align = 0; 884 radeon_gtt_location(rdev, &rdev->mc); 885 radeon_update_bandwidth_info(rdev); 886 } 887 888 void rs600_bandwidth_update(struct radeon_device *rdev) 889 { 890 struct drm_display_mode *mode0 = NULL; 891 struct drm_display_mode *mode1 = NULL; 892 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 893 /* FIXME: implement full support */ 894 895 if (!rdev->mode_info.mode_config_initialized) 896 return; 897 898 radeon_update_display_priority(rdev); 899 900 if (rdev->mode_info.crtcs[0]->base.enabled) 901 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 902 if (rdev->mode_info.crtcs[1]->base.enabled) 903 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 904 905 rs690_line_buffer_adjust(rdev, mode0, mode1); 906 907 if (rdev->disp_priority == 2) { 908 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 909 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 910 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 911 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 912 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 913 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 914 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 915 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 916 } 917 } 918 919 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 920 { 921 unsigned long flags; 922 u32 r; 923 924 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 925 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 926 S_000070_MC_IND_CITF_ARB0(1)); 927 r = RREG32(R_000074_MC_IND_DATA); 928 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 929 return r; 930 } 931 932 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 933 { 934 unsigned long flags; 935 936 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 937 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 938 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 939 WREG32(R_000074_MC_IND_DATA, v); 940 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 941 } 942 943 static void rs600_debugfs(struct radeon_device *rdev) 944 { 945 if (r100_debugfs_rbbm_init(rdev)) 946 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 947 } 948 949 void rs600_set_safe_registers(struct radeon_device *rdev) 950 { 951 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 952 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 953 } 954 955 static void rs600_mc_program(struct radeon_device *rdev) 956 { 957 struct rv515_mc_save save; 958 959 /* Stops all mc clients */ 960 rv515_mc_stop(rdev, &save); 961 962 /* Wait for mc idle */ 963 if (rs600_mc_wait_for_idle(rdev)) 964 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 965 966 /* FIXME: What does AGP means for such chipset ? */ 967 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 968 WREG32_MC(R_000006_AGP_BASE, 0); 969 WREG32_MC(R_000007_AGP_BASE_2, 0); 970 /* Program MC */ 971 WREG32_MC(R_000004_MC_FB_LOCATION, 972 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 973 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 974 WREG32(R_000134_HDP_FB_LOCATION, 975 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 976 977 rv515_mc_resume(rdev, &save); 978 } 979 980 static int rs600_startup(struct radeon_device *rdev) 981 { 982 int r; 983 984 rs600_mc_program(rdev); 985 /* Resume clock */ 986 rv515_clock_startup(rdev); 987 /* Initialize GPU configuration (# pipes, ...) */ 988 rs600_gpu_init(rdev); 989 /* Initialize GART (initialize after TTM so we can allocate 990 * memory through TTM but finalize after TTM) */ 991 r = rs600_gart_enable(rdev); 992 if (r) 993 return r; 994 995 /* allocate wb buffer */ 996 r = radeon_wb_init(rdev); 997 if (r) 998 return r; 999 1000 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1001 if (r) { 1002 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1003 return r; 1004 } 1005 1006 /* Enable IRQ */ 1007 if (!rdev->irq.installed) { 1008 r = radeon_irq_kms_init(rdev); 1009 if (r) 1010 return r; 1011 } 1012 1013 rs600_irq_set(rdev); 1014 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1015 /* 1M ring buffer */ 1016 r = r100_cp_init(rdev, 1024 * 1024); 1017 if (r) { 1018 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1019 return r; 1020 } 1021 1022 r = radeon_ib_pool_init(rdev); 1023 if (r) { 1024 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1025 return r; 1026 } 1027 1028 r = radeon_audio_init(rdev); 1029 if (r) { 1030 dev_err(rdev->dev, "failed initializing audio\n"); 1031 return r; 1032 } 1033 1034 return 0; 1035 } 1036 1037 int rs600_resume(struct radeon_device *rdev) 1038 { 1039 int r; 1040 1041 /* Make sur GART are not working */ 1042 rs600_gart_disable(rdev); 1043 /* Resume clock before doing reset */ 1044 rv515_clock_startup(rdev); 1045 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1046 if (radeon_asic_reset(rdev)) { 1047 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1048 RREG32(R_000E40_RBBM_STATUS), 1049 RREG32(R_0007C0_CP_STAT)); 1050 } 1051 /* post */ 1052 atom_asic_init(rdev->mode_info.atom_context); 1053 /* Resume clock after posting */ 1054 rv515_clock_startup(rdev); 1055 /* Initialize surface registers */ 1056 radeon_surface_init(rdev); 1057 1058 rdev->accel_working = true; 1059 r = rs600_startup(rdev); 1060 if (r) { 1061 rdev->accel_working = false; 1062 } 1063 return r; 1064 } 1065 1066 int rs600_suspend(struct radeon_device *rdev) 1067 { 1068 radeon_pm_suspend(rdev); 1069 radeon_audio_fini(rdev); 1070 r100_cp_disable(rdev); 1071 radeon_wb_disable(rdev); 1072 rs600_irq_disable(rdev); 1073 rs600_gart_disable(rdev); 1074 return 0; 1075 } 1076 1077 void rs600_fini(struct radeon_device *rdev) 1078 { 1079 radeon_pm_fini(rdev); 1080 radeon_audio_fini(rdev); 1081 r100_cp_fini(rdev); 1082 radeon_wb_fini(rdev); 1083 radeon_ib_pool_fini(rdev); 1084 radeon_gem_fini(rdev); 1085 rs600_gart_fini(rdev); 1086 radeon_irq_kms_fini(rdev); 1087 radeon_fence_driver_fini(rdev); 1088 radeon_bo_fini(rdev); 1089 radeon_atombios_fini(rdev); 1090 kfree(rdev->bios); 1091 rdev->bios = NULL; 1092 } 1093 1094 int rs600_init(struct radeon_device *rdev) 1095 { 1096 int r; 1097 1098 /* Disable VGA */ 1099 rv515_vga_render_disable(rdev); 1100 /* Initialize scratch registers */ 1101 radeon_scratch_init(rdev); 1102 /* Initialize surface registers */ 1103 radeon_surface_init(rdev); 1104 /* restore some register to sane defaults */ 1105 r100_restore_sanity(rdev); 1106 /* BIOS */ 1107 if (!radeon_get_bios(rdev)) { 1108 if (ASIC_IS_AVIVO(rdev)) 1109 return -EINVAL; 1110 } 1111 if (rdev->is_atom_bios) { 1112 r = radeon_atombios_init(rdev); 1113 if (r) 1114 return r; 1115 } else { 1116 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1117 return -EINVAL; 1118 } 1119 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1120 if (radeon_asic_reset(rdev)) { 1121 dev_warn(rdev->dev, 1122 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1123 RREG32(R_000E40_RBBM_STATUS), 1124 RREG32(R_0007C0_CP_STAT)); 1125 } 1126 /* check if cards are posted or not */ 1127 if (radeon_boot_test_post_card(rdev) == false) 1128 return -EINVAL; 1129 1130 /* Initialize clocks */ 1131 radeon_get_clock_info(rdev->ddev); 1132 /* initialize memory controller */ 1133 rs600_mc_init(rdev); 1134 rs600_debugfs(rdev); 1135 /* Fence driver */ 1136 r = radeon_fence_driver_init(rdev); 1137 if (r) 1138 return r; 1139 /* Memory manager */ 1140 r = radeon_bo_init(rdev); 1141 if (r) 1142 return r; 1143 r = rs600_gart_init(rdev); 1144 if (r) 1145 return r; 1146 rs600_set_safe_registers(rdev); 1147 1148 /* Initialize power management */ 1149 radeon_pm_init(rdev); 1150 1151 rdev->accel_working = true; 1152 r = rs600_startup(rdev); 1153 if (r) { 1154 /* Somethings want wront with the accel init stop accel */ 1155 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1156 r100_cp_fini(rdev); 1157 radeon_wb_fini(rdev); 1158 radeon_ib_pool_fini(rdev); 1159 rs600_gart_fini(rdev); 1160 radeon_irq_kms_fini(rdev); 1161 rdev->accel_working = false; 1162 } 1163 return 0; 1164 } 1165