1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include "drmP.h" 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "atom.h" 42 #include "rs600d.h" 43 44 #include "rs600_reg_safe.h" 45 46 void rs600_gpu_init(struct radeon_device *rdev); 47 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 48 49 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 50 { 51 /* enable the pflip int */ 52 radeon_irq_kms_pflip_irq_get(rdev, crtc); 53 } 54 55 void rs600_post_page_flip(struct radeon_device *rdev, int crtc) 56 { 57 /* disable the pflip int */ 58 radeon_irq_kms_pflip_irq_put(rdev, crtc); 59 } 60 61 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 62 { 63 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 64 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 65 66 /* Lock the graphics update lock */ 67 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 68 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 69 70 /* update the scanout addresses */ 71 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 72 (u32)crtc_base); 73 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 74 (u32)crtc_base); 75 76 /* Wait for update_pending to go high. */ 77 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); 78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 79 80 /* Unlock the lock, so double-buffering can take place inside vblank */ 81 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 82 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 83 84 /* Return current update_pending status: */ 85 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 86 } 87 88 void rs600_pm_misc(struct radeon_device *rdev) 89 { 90 int requested_index = rdev->pm.requested_power_state_index; 91 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 92 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 93 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 94 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 95 96 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 97 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 98 tmp = RREG32(voltage->gpio.reg); 99 if (voltage->active_high) 100 tmp |= voltage->gpio.mask; 101 else 102 tmp &= ~(voltage->gpio.mask); 103 WREG32(voltage->gpio.reg, tmp); 104 if (voltage->delay) 105 udelay(voltage->delay); 106 } else { 107 tmp = RREG32(voltage->gpio.reg); 108 if (voltage->active_high) 109 tmp &= ~voltage->gpio.mask; 110 else 111 tmp |= voltage->gpio.mask; 112 WREG32(voltage->gpio.reg, tmp); 113 if (voltage->delay) 114 udelay(voltage->delay); 115 } 116 } else if (voltage->type == VOLTAGE_VDDC) 117 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 118 119 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 120 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 121 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 122 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 123 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 124 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 125 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 126 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 127 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 128 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 129 } 130 } else { 131 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 132 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 133 } 134 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 135 136 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 137 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 138 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 139 if (voltage->delay) { 140 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 141 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 142 } else 143 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 144 } else 145 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 146 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 147 148 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 149 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 150 hdp_dyn_cntl &= ~HDP_FORCEON; 151 else 152 hdp_dyn_cntl |= HDP_FORCEON; 153 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 154 #if 0 155 /* mc_host_dyn seems to cause hangs from time to time */ 156 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 157 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 158 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 159 else 160 mc_host_dyn_cntl |= MC_HOST_FORCEON; 161 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 162 #endif 163 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 164 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 165 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 166 else 167 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 168 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 169 170 /* set pcie lanes */ 171 if ((rdev->flags & RADEON_IS_PCIE) && 172 !(rdev->flags & RADEON_IS_IGP) && 173 rdev->asic->set_pcie_lanes && 174 (ps->pcie_lanes != 175 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 176 radeon_set_pcie_lanes(rdev, 177 ps->pcie_lanes); 178 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 179 } 180 } 181 182 void rs600_pm_prepare(struct radeon_device *rdev) 183 { 184 struct drm_device *ddev = rdev->ddev; 185 struct drm_crtc *crtc; 186 struct radeon_crtc *radeon_crtc; 187 u32 tmp; 188 189 /* disable any active CRTCs */ 190 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 191 radeon_crtc = to_radeon_crtc(crtc); 192 if (radeon_crtc->enabled) { 193 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 194 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 195 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 196 } 197 } 198 } 199 200 void rs600_pm_finish(struct radeon_device *rdev) 201 { 202 struct drm_device *ddev = rdev->ddev; 203 struct drm_crtc *crtc; 204 struct radeon_crtc *radeon_crtc; 205 u32 tmp; 206 207 /* enable any active CRTCs */ 208 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 209 radeon_crtc = to_radeon_crtc(crtc); 210 if (radeon_crtc->enabled) { 211 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 212 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 213 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 214 } 215 } 216 } 217 218 /* hpd for digital panel detect/disconnect */ 219 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 220 { 221 u32 tmp; 222 bool connected = false; 223 224 switch (hpd) { 225 case RADEON_HPD_1: 226 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 227 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 228 connected = true; 229 break; 230 case RADEON_HPD_2: 231 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 232 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 233 connected = true; 234 break; 235 default: 236 break; 237 } 238 return connected; 239 } 240 241 void rs600_hpd_set_polarity(struct radeon_device *rdev, 242 enum radeon_hpd_id hpd) 243 { 244 u32 tmp; 245 bool connected = rs600_hpd_sense(rdev, hpd); 246 247 switch (hpd) { 248 case RADEON_HPD_1: 249 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 250 if (connected) 251 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 252 else 253 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 254 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 255 break; 256 case RADEON_HPD_2: 257 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 258 if (connected) 259 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 260 else 261 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 262 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 263 break; 264 default: 265 break; 266 } 267 } 268 269 void rs600_hpd_init(struct radeon_device *rdev) 270 { 271 struct drm_device *dev = rdev->ddev; 272 struct drm_connector *connector; 273 274 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 275 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 276 switch (radeon_connector->hpd.hpd) { 277 case RADEON_HPD_1: 278 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 279 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 280 rdev->irq.hpd[0] = true; 281 break; 282 case RADEON_HPD_2: 283 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 284 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 285 rdev->irq.hpd[1] = true; 286 break; 287 default: 288 break; 289 } 290 } 291 if (rdev->irq.installed) 292 rs600_irq_set(rdev); 293 } 294 295 void rs600_hpd_fini(struct radeon_device *rdev) 296 { 297 struct drm_device *dev = rdev->ddev; 298 struct drm_connector *connector; 299 300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 301 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 302 switch (radeon_connector->hpd.hpd) { 303 case RADEON_HPD_1: 304 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 305 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 306 rdev->irq.hpd[0] = false; 307 break; 308 case RADEON_HPD_2: 309 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 310 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 311 rdev->irq.hpd[1] = false; 312 break; 313 default: 314 break; 315 } 316 } 317 } 318 319 void rs600_bm_disable(struct radeon_device *rdev) 320 { 321 u32 tmp; 322 323 /* disable bus mastering */ 324 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); 325 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); 326 mdelay(1); 327 } 328 329 int rs600_asic_reset(struct radeon_device *rdev) 330 { 331 struct rv515_mc_save save; 332 u32 status, tmp; 333 int ret = 0; 334 335 status = RREG32(R_000E40_RBBM_STATUS); 336 if (!G_000E40_GUI_ACTIVE(status)) { 337 return 0; 338 } 339 /* Stops all mc clients */ 340 rv515_mc_stop(rdev, &save); 341 status = RREG32(R_000E40_RBBM_STATUS); 342 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 343 /* stop CP */ 344 WREG32(RADEON_CP_CSQ_CNTL, 0); 345 tmp = RREG32(RADEON_CP_RB_CNTL); 346 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 347 WREG32(RADEON_CP_RB_RPTR_WR, 0); 348 WREG32(RADEON_CP_RB_WPTR, 0); 349 WREG32(RADEON_CP_RB_CNTL, tmp); 350 pci_save_state(rdev->pdev); 351 /* disable bus mastering */ 352 rs600_bm_disable(rdev); 353 /* reset GA+VAP */ 354 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 355 S_0000F0_SOFT_RESET_GA(1)); 356 RREG32(R_0000F0_RBBM_SOFT_RESET); 357 mdelay(500); 358 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 359 mdelay(1); 360 status = RREG32(R_000E40_RBBM_STATUS); 361 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 362 /* reset CP */ 363 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 364 RREG32(R_0000F0_RBBM_SOFT_RESET); 365 mdelay(500); 366 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 367 mdelay(1); 368 status = RREG32(R_000E40_RBBM_STATUS); 369 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 370 /* reset MC */ 371 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 372 RREG32(R_0000F0_RBBM_SOFT_RESET); 373 mdelay(500); 374 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 375 mdelay(1); 376 status = RREG32(R_000E40_RBBM_STATUS); 377 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 378 /* restore PCI & busmastering */ 379 pci_restore_state(rdev->pdev); 380 /* Check if GPU is idle */ 381 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 382 dev_err(rdev->dev, "failed to reset GPU\n"); 383 rdev->gpu_lockup = true; 384 ret = -1; 385 } else 386 dev_info(rdev->dev, "GPU reset succeed\n"); 387 rv515_mc_resume(rdev, &save); 388 return ret; 389 } 390 391 /* 392 * GART. 393 */ 394 void rs600_gart_tlb_flush(struct radeon_device *rdev) 395 { 396 uint32_t tmp; 397 398 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 399 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 400 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 401 402 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 403 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 404 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 405 406 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 407 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 408 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 409 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 410 } 411 412 int rs600_gart_init(struct radeon_device *rdev) 413 { 414 int r; 415 416 if (rdev->gart.table.vram.robj) { 417 WARN(1, "RS600 GART already initialized\n"); 418 return 0; 419 } 420 /* Initialize common gart structure */ 421 r = radeon_gart_init(rdev); 422 if (r) { 423 return r; 424 } 425 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 426 return radeon_gart_table_vram_alloc(rdev); 427 } 428 429 static int rs600_gart_enable(struct radeon_device *rdev) 430 { 431 u32 tmp; 432 int r, i; 433 434 if (rdev->gart.table.vram.robj == NULL) { 435 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 436 return -EINVAL; 437 } 438 r = radeon_gart_table_vram_pin(rdev); 439 if (r) 440 return r; 441 radeon_gart_restore(rdev); 442 /* Enable bus master */ 443 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 444 WREG32(RADEON_BUS_CNTL, tmp); 445 /* FIXME: setup default page */ 446 WREG32_MC(R_000100_MC_PT0_CNTL, 447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 448 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 449 450 for (i = 0; i < 19; i++) { 451 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 452 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 453 S_00016C_SYSTEM_ACCESS_MODE_MASK( 454 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 455 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 456 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 457 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 458 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 459 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 460 } 461 /* enable first context */ 462 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 463 S_000102_ENABLE_PAGE_TABLE(1) | 464 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 465 466 /* disable all other contexts */ 467 for (i = 1; i < 8; i++) 468 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 469 470 /* setup the page table */ 471 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 472 rdev->gart.table_addr); 473 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 474 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 475 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 476 477 /* System context maps to VRAM space */ 478 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 479 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 480 481 /* enable page tables */ 482 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 483 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 484 tmp = RREG32_MC(R_000009_MC_CNTL1); 485 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 486 rs600_gart_tlb_flush(rdev); 487 rdev->gart.ready = true; 488 return 0; 489 } 490 491 void rs600_gart_disable(struct radeon_device *rdev) 492 { 493 u32 tmp; 494 int r; 495 496 /* FIXME: disable out of gart access */ 497 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 498 tmp = RREG32_MC(R_000009_MC_CNTL1); 499 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 500 if (rdev->gart.table.vram.robj) { 501 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 502 if (r == 0) { 503 radeon_bo_kunmap(rdev->gart.table.vram.robj); 504 radeon_bo_unpin(rdev->gart.table.vram.robj); 505 radeon_bo_unreserve(rdev->gart.table.vram.robj); 506 } 507 } 508 } 509 510 void rs600_gart_fini(struct radeon_device *rdev) 511 { 512 radeon_gart_fini(rdev); 513 rs600_gart_disable(rdev); 514 radeon_gart_table_vram_free(rdev); 515 } 516 517 #define R600_PTE_VALID (1 << 0) 518 #define R600_PTE_SYSTEM (1 << 1) 519 #define R600_PTE_SNOOPED (1 << 2) 520 #define R600_PTE_READABLE (1 << 5) 521 #define R600_PTE_WRITEABLE (1 << 6) 522 523 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 524 { 525 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 526 527 if (i < 0 || i > rdev->gart.num_gpu_pages) { 528 return -EINVAL; 529 } 530 addr = addr & 0xFFFFFFFFFFFFF000ULL; 531 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 532 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 533 writeq(addr, ((void __iomem *)ptr) + (i * 8)); 534 return 0; 535 } 536 537 int rs600_irq_set(struct radeon_device *rdev) 538 { 539 uint32_t tmp = 0; 540 uint32_t mode_int = 0; 541 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 542 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 543 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 544 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 545 546 if (!rdev->irq.installed) { 547 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 548 WREG32(R_000040_GEN_INT_CNTL, 0); 549 return -EINVAL; 550 } 551 if (rdev->irq.sw_int) { 552 tmp |= S_000040_SW_INT_EN(1); 553 } 554 if (rdev->irq.gui_idle) { 555 tmp |= S_000040_GUI_IDLE(1); 556 } 557 if (rdev->irq.crtc_vblank_int[0] || 558 rdev->irq.pflip[0]) { 559 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 560 } 561 if (rdev->irq.crtc_vblank_int[1] || 562 rdev->irq.pflip[1]) { 563 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 564 } 565 if (rdev->irq.hpd[0]) { 566 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 567 } 568 if (rdev->irq.hpd[1]) { 569 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 570 } 571 WREG32(R_000040_GEN_INT_CNTL, tmp); 572 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 573 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 574 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 575 return 0; 576 } 577 578 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 579 { 580 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 581 uint32_t irq_mask = S_000044_SW_INT(1); 582 u32 tmp; 583 584 /* the interrupt works, but the status bit is permanently asserted */ 585 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 586 if (!rdev->irq.gui_idle_acked) 587 irq_mask |= S_000044_GUI_IDLE_STAT(1); 588 } 589 590 if (G_000044_DISPLAY_INT_STAT(irqs)) { 591 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 592 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 593 WREG32(R_006534_D1MODE_VBLANK_STATUS, 594 S_006534_D1MODE_VBLANK_ACK(1)); 595 } 596 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 597 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 598 S_006D34_D2MODE_VBLANK_ACK(1)); 599 } 600 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 601 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 602 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 603 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 604 } 605 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 606 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 607 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 608 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 609 } 610 } else { 611 rdev->irq.stat_regs.r500.disp_int = 0; 612 } 613 614 if (irqs) { 615 WREG32(R_000044_GEN_INT_STATUS, irqs); 616 } 617 return irqs & irq_mask; 618 } 619 620 void rs600_irq_disable(struct radeon_device *rdev) 621 { 622 WREG32(R_000040_GEN_INT_CNTL, 0); 623 WREG32(R_006540_DxMODE_INT_MASK, 0); 624 /* Wait and acknowledge irq */ 625 mdelay(1); 626 rs600_irq_ack(rdev); 627 } 628 629 int rs600_irq_process(struct radeon_device *rdev) 630 { 631 u32 status, msi_rearm; 632 bool queue_hotplug = false; 633 634 /* reset gui idle ack. the status bit is broken */ 635 rdev->irq.gui_idle_acked = false; 636 637 status = rs600_irq_ack(rdev); 638 if (!status && !rdev->irq.stat_regs.r500.disp_int) { 639 return IRQ_NONE; 640 } 641 while (status || rdev->irq.stat_regs.r500.disp_int) { 642 /* SW interrupt */ 643 if (G_000044_SW_INT(status)) { 644 radeon_fence_process(rdev); 645 } 646 /* GUI idle */ 647 if (G_000040_GUI_IDLE(status)) { 648 rdev->irq.gui_idle_acked = true; 649 rdev->pm.gui_idle = true; 650 wake_up(&rdev->irq.idle_queue); 651 } 652 /* Vertical blank interrupts */ 653 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 654 if (rdev->irq.crtc_vblank_int[0]) { 655 drm_handle_vblank(rdev->ddev, 0); 656 rdev->pm.vblank_sync = true; 657 wake_up(&rdev->irq.vblank_queue); 658 } 659 if (rdev->irq.pflip[0]) 660 radeon_crtc_handle_flip(rdev, 0); 661 } 662 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 663 if (rdev->irq.crtc_vblank_int[1]) { 664 drm_handle_vblank(rdev->ddev, 1); 665 rdev->pm.vblank_sync = true; 666 wake_up(&rdev->irq.vblank_queue); 667 } 668 if (rdev->irq.pflip[1]) 669 radeon_crtc_handle_flip(rdev, 1); 670 } 671 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 672 queue_hotplug = true; 673 DRM_DEBUG("HPD1\n"); 674 } 675 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 676 queue_hotplug = true; 677 DRM_DEBUG("HPD2\n"); 678 } 679 status = rs600_irq_ack(rdev); 680 } 681 /* reset gui idle ack. the status bit is broken */ 682 rdev->irq.gui_idle_acked = false; 683 if (queue_hotplug) 684 schedule_work(&rdev->hotplug_work); 685 if (rdev->msi_enabled) { 686 switch (rdev->family) { 687 case CHIP_RS600: 688 case CHIP_RS690: 689 case CHIP_RS740: 690 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 691 WREG32(RADEON_BUS_CNTL, msi_rearm); 692 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 693 break; 694 default: 695 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 696 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 697 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 698 break; 699 } 700 } 701 return IRQ_HANDLED; 702 } 703 704 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 705 { 706 if (crtc == 0) 707 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 708 else 709 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 710 } 711 712 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 713 { 714 unsigned i; 715 716 for (i = 0; i < rdev->usec_timeout; i++) { 717 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 718 return 0; 719 udelay(1); 720 } 721 return -1; 722 } 723 724 void rs600_gpu_init(struct radeon_device *rdev) 725 { 726 r420_pipes_init(rdev); 727 /* Wait for mc idle */ 728 if (rs600_mc_wait_for_idle(rdev)) 729 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 730 } 731 732 void rs600_mc_init(struct radeon_device *rdev) 733 { 734 u64 base; 735 736 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 737 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 738 rdev->mc.vram_is_ddr = true; 739 rdev->mc.vram_width = 128; 740 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 741 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 742 rdev->mc.visible_vram_size = rdev->mc.aper_size; 743 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 744 base = RREG32_MC(R_000004_MC_FB_LOCATION); 745 base = G_000004_MC_FB_START(base) << 16; 746 radeon_vram_location(rdev, &rdev->mc, base); 747 rdev->mc.gtt_base_align = 0; 748 radeon_gtt_location(rdev, &rdev->mc); 749 radeon_update_bandwidth_info(rdev); 750 } 751 752 void rs600_bandwidth_update(struct radeon_device *rdev) 753 { 754 struct drm_display_mode *mode0 = NULL; 755 struct drm_display_mode *mode1 = NULL; 756 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 757 /* FIXME: implement full support */ 758 759 radeon_update_display_priority(rdev); 760 761 if (rdev->mode_info.crtcs[0]->base.enabled) 762 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 763 if (rdev->mode_info.crtcs[1]->base.enabled) 764 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 765 766 rs690_line_buffer_adjust(rdev, mode0, mode1); 767 768 if (rdev->disp_priority == 2) { 769 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 770 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 771 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 772 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 773 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 774 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 775 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 776 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 777 } 778 } 779 780 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 781 { 782 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 783 S_000070_MC_IND_CITF_ARB0(1)); 784 return RREG32(R_000074_MC_IND_DATA); 785 } 786 787 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 788 { 789 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 790 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 791 WREG32(R_000074_MC_IND_DATA, v); 792 } 793 794 void rs600_debugfs(struct radeon_device *rdev) 795 { 796 if (r100_debugfs_rbbm_init(rdev)) 797 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 798 } 799 800 void rs600_set_safe_registers(struct radeon_device *rdev) 801 { 802 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 803 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 804 } 805 806 static void rs600_mc_program(struct radeon_device *rdev) 807 { 808 struct rv515_mc_save save; 809 810 /* Stops all mc clients */ 811 rv515_mc_stop(rdev, &save); 812 813 /* Wait for mc idle */ 814 if (rs600_mc_wait_for_idle(rdev)) 815 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 816 817 /* FIXME: What does AGP means for such chipset ? */ 818 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 819 WREG32_MC(R_000006_AGP_BASE, 0); 820 WREG32_MC(R_000007_AGP_BASE_2, 0); 821 /* Program MC */ 822 WREG32_MC(R_000004_MC_FB_LOCATION, 823 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 824 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 825 WREG32(R_000134_HDP_FB_LOCATION, 826 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 827 828 rv515_mc_resume(rdev, &save); 829 } 830 831 static int rs600_startup(struct radeon_device *rdev) 832 { 833 int r; 834 835 rs600_mc_program(rdev); 836 /* Resume clock */ 837 rv515_clock_startup(rdev); 838 /* Initialize GPU configuration (# pipes, ...) */ 839 rs600_gpu_init(rdev); 840 /* Initialize GART (initialize after TTM so we can allocate 841 * memory through TTM but finalize after TTM) */ 842 r = rs600_gart_enable(rdev); 843 if (r) 844 return r; 845 846 /* allocate wb buffer */ 847 r = radeon_wb_init(rdev); 848 if (r) 849 return r; 850 851 /* Enable IRQ */ 852 rs600_irq_set(rdev); 853 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 854 /* 1M ring buffer */ 855 r = r100_cp_init(rdev, 1024 * 1024); 856 if (r) { 857 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 858 return r; 859 } 860 r = r100_ib_init(rdev); 861 if (r) { 862 dev_err(rdev->dev, "failed initializing IB (%d).\n", r); 863 return r; 864 } 865 866 r = r600_audio_init(rdev); 867 if (r) { 868 dev_err(rdev->dev, "failed initializing audio\n"); 869 return r; 870 } 871 872 return 0; 873 } 874 875 int rs600_resume(struct radeon_device *rdev) 876 { 877 /* Make sur GART are not working */ 878 rs600_gart_disable(rdev); 879 /* Resume clock before doing reset */ 880 rv515_clock_startup(rdev); 881 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 882 if (radeon_asic_reset(rdev)) { 883 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 884 RREG32(R_000E40_RBBM_STATUS), 885 RREG32(R_0007C0_CP_STAT)); 886 } 887 /* post */ 888 atom_asic_init(rdev->mode_info.atom_context); 889 /* Resume clock after posting */ 890 rv515_clock_startup(rdev); 891 /* Initialize surface registers */ 892 radeon_surface_init(rdev); 893 return rs600_startup(rdev); 894 } 895 896 int rs600_suspend(struct radeon_device *rdev) 897 { 898 r600_audio_fini(rdev); 899 r100_cp_disable(rdev); 900 radeon_wb_disable(rdev); 901 rs600_irq_disable(rdev); 902 rs600_gart_disable(rdev); 903 return 0; 904 } 905 906 void rs600_fini(struct radeon_device *rdev) 907 { 908 r600_audio_fini(rdev); 909 r100_cp_fini(rdev); 910 radeon_wb_fini(rdev); 911 r100_ib_fini(rdev); 912 radeon_gem_fini(rdev); 913 rs600_gart_fini(rdev); 914 radeon_irq_kms_fini(rdev); 915 radeon_fence_driver_fini(rdev); 916 radeon_bo_fini(rdev); 917 radeon_atombios_fini(rdev); 918 kfree(rdev->bios); 919 rdev->bios = NULL; 920 } 921 922 int rs600_init(struct radeon_device *rdev) 923 { 924 int r; 925 926 /* Disable VGA */ 927 rv515_vga_render_disable(rdev); 928 /* Initialize scratch registers */ 929 radeon_scratch_init(rdev); 930 /* Initialize surface registers */ 931 radeon_surface_init(rdev); 932 /* restore some register to sane defaults */ 933 r100_restore_sanity(rdev); 934 /* BIOS */ 935 if (!radeon_get_bios(rdev)) { 936 if (ASIC_IS_AVIVO(rdev)) 937 return -EINVAL; 938 } 939 if (rdev->is_atom_bios) { 940 r = radeon_atombios_init(rdev); 941 if (r) 942 return r; 943 } else { 944 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 945 return -EINVAL; 946 } 947 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 948 if (radeon_asic_reset(rdev)) { 949 dev_warn(rdev->dev, 950 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 951 RREG32(R_000E40_RBBM_STATUS), 952 RREG32(R_0007C0_CP_STAT)); 953 } 954 /* check if cards are posted or not */ 955 if (radeon_boot_test_post_card(rdev) == false) 956 return -EINVAL; 957 958 /* Initialize clocks */ 959 radeon_get_clock_info(rdev->ddev); 960 /* initialize memory controller */ 961 rs600_mc_init(rdev); 962 rs600_debugfs(rdev); 963 /* Fence driver */ 964 r = radeon_fence_driver_init(rdev); 965 if (r) 966 return r; 967 r = radeon_irq_kms_init(rdev); 968 if (r) 969 return r; 970 /* Memory manager */ 971 r = radeon_bo_init(rdev); 972 if (r) 973 return r; 974 r = rs600_gart_init(rdev); 975 if (r) 976 return r; 977 rs600_set_safe_registers(rdev); 978 rdev->accel_working = true; 979 r = rs600_startup(rdev); 980 if (r) { 981 /* Somethings want wront with the accel init stop accel */ 982 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 983 r100_cp_fini(rdev); 984 radeon_wb_fini(rdev); 985 r100_ib_fini(rdev); 986 rs600_gart_fini(rdev); 987 radeon_irq_kms_fini(rdev); 988 rdev->accel_working = false; 989 } 990 return 0; 991 } 992