1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "rs400d.h" 34 35 /* This files gather functions specifics to : rs400,rs480 */ 36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 37 38 void rs400_gart_adjust_size(struct radeon_device *rdev) 39 { 40 /* Check gart size */ 41 switch (rdev->mc.gtt_size/(1024*1024)) { 42 case 32: 43 case 64: 44 case 128: 45 case 256: 46 case 512: 47 case 1024: 48 case 2048: 49 break; 50 default: 51 DRM_ERROR("Unable to use IGP GART size %uM\n", 52 (unsigned)(rdev->mc.gtt_size >> 20)); 53 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 54 DRM_ERROR("Forcing to 32M GART size\n"); 55 rdev->mc.gtt_size = 32 * 1024 * 1024; 56 return; 57 } 58 } 59 60 void rs400_gart_tlb_flush(struct radeon_device *rdev) 61 { 62 uint32_t tmp; 63 unsigned int timeout = rdev->usec_timeout; 64 65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 66 do { 67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 69 break; 70 DRM_UDELAY(1); 71 timeout--; 72 } while (timeout > 0); 73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 74 } 75 76 int rs400_gart_init(struct radeon_device *rdev) 77 { 78 int r; 79 80 if (rdev->gart.ptr) { 81 WARN(1, "RS400 GART already initialized\n"); 82 return 0; 83 } 84 /* Check gart size */ 85 switch(rdev->mc.gtt_size / (1024 * 1024)) { 86 case 32: 87 case 64: 88 case 128: 89 case 256: 90 case 512: 91 case 1024: 92 case 2048: 93 break; 94 default: 95 return -EINVAL; 96 } 97 /* Initialize common gart structure */ 98 r = radeon_gart_init(rdev); 99 if (r) 100 return r; 101 if (rs400_debugfs_pcie_gart_info_init(rdev)) 102 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 104 return radeon_gart_table_ram_alloc(rdev); 105 } 106 107 int rs400_gart_enable(struct radeon_device *rdev) 108 { 109 uint32_t size_reg; 110 uint32_t tmp; 111 112 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 113 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 115 /* Check gart size */ 116 switch(rdev->mc.gtt_size / (1024 * 1024)) { 117 case 32: 118 size_reg = RS480_VA_SIZE_32MB; 119 break; 120 case 64: 121 size_reg = RS480_VA_SIZE_64MB; 122 break; 123 case 128: 124 size_reg = RS480_VA_SIZE_128MB; 125 break; 126 case 256: 127 size_reg = RS480_VA_SIZE_256MB; 128 break; 129 case 512: 130 size_reg = RS480_VA_SIZE_512MB; 131 break; 132 case 1024: 133 size_reg = RS480_VA_SIZE_1GB; 134 break; 135 case 2048: 136 size_reg = RS480_VA_SIZE_2GB; 137 break; 138 default: 139 return -EINVAL; 140 } 141 /* It should be fine to program it to max value */ 142 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 143 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 144 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 145 } else { 146 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 147 WREG32(RS480_AGP_BASE_2, 0); 148 } 149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 151 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 153 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 154 WREG32(RADEON_BUS_CNTL, tmp); 155 } else { 156 WREG32(RADEON_MC_AGP_LOCATION, tmp); 157 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 158 WREG32(RADEON_BUS_CNTL, tmp); 159 } 160 /* Table should be in 32bits address space so ignore bits above. */ 161 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 162 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 163 164 WREG32_MC(RS480_GART_BASE, tmp); 165 /* TODO: more tweaking here */ 166 WREG32_MC(RS480_GART_FEATURE_ID, 167 (RS480_TLB_ENABLE | 168 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 169 /* Disable snooping */ 170 WREG32_MC(RS480_AGP_MODE_CNTL, 171 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 172 /* Disable AGP mode */ 173 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 174 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 175 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 176 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 177 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 178 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 179 } else { 180 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 181 tmp |= RS480_GART_INDEX_REG_EN; 182 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 183 } 184 /* Enable gart */ 185 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 186 rs400_gart_tlb_flush(rdev); 187 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 188 (unsigned)(rdev->mc.gtt_size >> 20), 189 (unsigned long long)rdev->gart.table_addr); 190 rdev->gart.ready = true; 191 return 0; 192 } 193 194 void rs400_gart_disable(struct radeon_device *rdev) 195 { 196 uint32_t tmp; 197 198 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 199 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 200 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 202 } 203 204 void rs400_gart_fini(struct radeon_device *rdev) 205 { 206 radeon_gart_fini(rdev); 207 rs400_gart_disable(rdev); 208 radeon_gart_table_ram_free(rdev); 209 } 210 211 #define RS400_PTE_UNSNOOPED (1 << 0) 212 #define RS400_PTE_WRITEABLE (1 << 2) 213 #define RS400_PTE_READABLE (1 << 3) 214 215 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) 216 { 217 uint32_t entry; 218 219 entry = (lower_32_bits(addr) & PAGE_MASK) | 220 ((upper_32_bits(addr) & 0xff) << 4); 221 if (flags & RADEON_GART_PAGE_READ) 222 entry |= RS400_PTE_READABLE; 223 if (flags & RADEON_GART_PAGE_WRITE) 224 entry |= RS400_PTE_WRITEABLE; 225 if (!(flags & RADEON_GART_PAGE_SNOOP)) 226 entry |= RS400_PTE_UNSNOOPED; 227 return entry; 228 } 229 230 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 231 uint64_t entry) 232 { 233 u32 *gtt = rdev->gart.ptr; 234 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 235 } 236 237 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 238 { 239 unsigned i; 240 uint32_t tmp; 241 242 for (i = 0; i < rdev->usec_timeout; i++) { 243 /* read MC_STATUS */ 244 tmp = RREG32(RADEON_MC_STATUS); 245 if (tmp & RADEON_MC_IDLE) { 246 return 0; 247 } 248 DRM_UDELAY(1); 249 } 250 return -1; 251 } 252 253 static void rs400_gpu_init(struct radeon_device *rdev) 254 { 255 /* FIXME: is this correct ? */ 256 r420_pipes_init(rdev); 257 if (rs400_mc_wait_for_idle(rdev)) { 258 pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n", 259 RREG32(RADEON_MC_STATUS)); 260 } 261 } 262 263 static void rs400_mc_init(struct radeon_device *rdev) 264 { 265 u64 base; 266 267 rs400_gart_adjust_size(rdev); 268 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 269 /* DDR for all card after R300 & IGP */ 270 rdev->mc.vram_is_ddr = true; 271 rdev->mc.vram_width = 128; 272 r100_vram_init_sizes(rdev); 273 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 274 radeon_vram_location(rdev, &rdev->mc, base); 275 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 276 radeon_gtt_location(rdev, &rdev->mc); 277 radeon_update_bandwidth_info(rdev); 278 } 279 280 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 281 { 282 unsigned long flags; 283 uint32_t r; 284 285 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 286 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 287 r = RREG32(RS480_NB_MC_DATA); 288 WREG32(RS480_NB_MC_INDEX, 0xff); 289 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 290 return r; 291 } 292 293 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 294 { 295 unsigned long flags; 296 297 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 298 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 299 WREG32(RS480_NB_MC_DATA, (v)); 300 WREG32(RS480_NB_MC_INDEX, 0xff); 301 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 302 } 303 304 #if defined(CONFIG_DEBUG_FS) 305 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 306 { 307 struct drm_info_node *node = (struct drm_info_node *) m->private; 308 struct drm_device *dev = node->minor->dev; 309 struct radeon_device *rdev = dev->dev_private; 310 uint32_t tmp; 311 312 tmp = RREG32(RADEON_HOST_PATH_CNTL); 313 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 314 tmp = RREG32(RADEON_BUS_CNTL); 315 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 316 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 317 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 318 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 319 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 320 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 321 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 322 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 323 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 324 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 325 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 326 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 327 tmp = RREG32(RS690_HDP_FB_LOCATION); 328 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 329 } else { 330 tmp = RREG32(RADEON_AGP_BASE); 331 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 332 tmp = RREG32(RS480_AGP_BASE_2); 333 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 334 tmp = RREG32(RADEON_MC_AGP_LOCATION); 335 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 336 } 337 tmp = RREG32_MC(RS480_GART_BASE); 338 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 339 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 340 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 341 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 342 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 343 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 344 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 345 tmp = RREG32_MC(0x5F); 346 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 347 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 348 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 349 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 350 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 351 tmp = RREG32_MC(0x3B); 352 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 353 tmp = RREG32_MC(0x3C); 354 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x30); 356 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 357 tmp = RREG32_MC(0x31); 358 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 359 tmp = RREG32_MC(0x32); 360 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 361 tmp = RREG32_MC(0x33); 362 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 363 tmp = RREG32_MC(0x34); 364 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 365 tmp = RREG32_MC(0x35); 366 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 367 tmp = RREG32_MC(0x36); 368 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 369 tmp = RREG32_MC(0x37); 370 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 371 return 0; 372 } 373 374 static struct drm_info_list rs400_gart_info_list[] = { 375 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 376 }; 377 #endif 378 379 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 380 { 381 #if defined(CONFIG_DEBUG_FS) 382 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 383 #else 384 return 0; 385 #endif 386 } 387 388 static void rs400_mc_program(struct radeon_device *rdev) 389 { 390 struct r100_mc_save save; 391 392 /* Stops all mc clients */ 393 r100_mc_stop(rdev, &save); 394 395 /* Wait for mc idle */ 396 if (rs400_mc_wait_for_idle(rdev)) 397 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 398 WREG32(R_000148_MC_FB_LOCATION, 399 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 400 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 401 402 r100_mc_resume(rdev, &save); 403 } 404 405 static int rs400_startup(struct radeon_device *rdev) 406 { 407 int r; 408 409 r100_set_common_regs(rdev); 410 411 rs400_mc_program(rdev); 412 /* Resume clock */ 413 r300_clock_startup(rdev); 414 /* Initialize GPU configuration (# pipes, ...) */ 415 rs400_gpu_init(rdev); 416 r100_enable_bm(rdev); 417 /* Initialize GART (initialize after TTM so we can allocate 418 * memory through TTM but finalize after TTM) */ 419 r = rs400_gart_enable(rdev); 420 if (r) 421 return r; 422 423 /* allocate wb buffer */ 424 r = radeon_wb_init(rdev); 425 if (r) 426 return r; 427 428 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 429 if (r) { 430 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 431 return r; 432 } 433 434 /* Enable IRQ */ 435 if (!rdev->irq.installed) { 436 r = radeon_irq_kms_init(rdev); 437 if (r) 438 return r; 439 } 440 441 r100_irq_set(rdev); 442 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 443 /* 1M ring buffer */ 444 r = r100_cp_init(rdev, 1024 * 1024); 445 if (r) { 446 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 447 return r; 448 } 449 450 r = radeon_ib_pool_init(rdev); 451 if (r) { 452 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 453 return r; 454 } 455 456 return 0; 457 } 458 459 int rs400_resume(struct radeon_device *rdev) 460 { 461 int r; 462 463 /* Make sur GART are not working */ 464 rs400_gart_disable(rdev); 465 /* Resume clock before doing reset */ 466 r300_clock_startup(rdev); 467 /* setup MC before calling post tables */ 468 rs400_mc_program(rdev); 469 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 470 if (radeon_asic_reset(rdev)) { 471 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 472 RREG32(R_000E40_RBBM_STATUS), 473 RREG32(R_0007C0_CP_STAT)); 474 } 475 /* post */ 476 radeon_combios_asic_init(rdev->ddev); 477 /* Resume clock after posting */ 478 r300_clock_startup(rdev); 479 /* Initialize surface registers */ 480 radeon_surface_init(rdev); 481 482 rdev->accel_working = true; 483 r = rs400_startup(rdev); 484 if (r) { 485 rdev->accel_working = false; 486 } 487 return r; 488 } 489 490 int rs400_suspend(struct radeon_device *rdev) 491 { 492 radeon_pm_suspend(rdev); 493 r100_cp_disable(rdev); 494 radeon_wb_disable(rdev); 495 r100_irq_disable(rdev); 496 rs400_gart_disable(rdev); 497 return 0; 498 } 499 500 void rs400_fini(struct radeon_device *rdev) 501 { 502 radeon_pm_fini(rdev); 503 r100_cp_fini(rdev); 504 radeon_wb_fini(rdev); 505 radeon_ib_pool_fini(rdev); 506 radeon_gem_fini(rdev); 507 rs400_gart_fini(rdev); 508 radeon_irq_kms_fini(rdev); 509 radeon_fence_driver_fini(rdev); 510 radeon_bo_fini(rdev); 511 radeon_atombios_fini(rdev); 512 kfree(rdev->bios); 513 rdev->bios = NULL; 514 } 515 516 int rs400_init(struct radeon_device *rdev) 517 { 518 int r; 519 520 /* Disable VGA */ 521 r100_vga_render_disable(rdev); 522 /* Initialize scratch registers */ 523 radeon_scratch_init(rdev); 524 /* Initialize surface registers */ 525 radeon_surface_init(rdev); 526 /* TODO: disable VGA need to use VGA request */ 527 /* restore some register to sane defaults */ 528 r100_restore_sanity(rdev); 529 /* BIOS*/ 530 if (!radeon_get_bios(rdev)) { 531 if (ASIC_IS_AVIVO(rdev)) 532 return -EINVAL; 533 } 534 if (rdev->is_atom_bios) { 535 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 536 return -EINVAL; 537 } else { 538 r = radeon_combios_init(rdev); 539 if (r) 540 return r; 541 } 542 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 543 if (radeon_asic_reset(rdev)) { 544 dev_warn(rdev->dev, 545 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 546 RREG32(R_000E40_RBBM_STATUS), 547 RREG32(R_0007C0_CP_STAT)); 548 } 549 /* check if cards are posted or not */ 550 if (radeon_boot_test_post_card(rdev) == false) 551 return -EINVAL; 552 553 /* Initialize clocks */ 554 radeon_get_clock_info(rdev->ddev); 555 /* initialize memory controller */ 556 rs400_mc_init(rdev); 557 /* Fence driver */ 558 r = radeon_fence_driver_init(rdev); 559 if (r) 560 return r; 561 /* Memory manager */ 562 r = radeon_bo_init(rdev); 563 if (r) 564 return r; 565 r = rs400_gart_init(rdev); 566 if (r) 567 return r; 568 r300_set_reg_safe(rdev); 569 570 /* Initialize power management */ 571 radeon_pm_init(rdev); 572 573 rdev->accel_working = true; 574 r = rs400_startup(rdev); 575 if (r) { 576 /* Somethings want wront with the accel init stop accel */ 577 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 578 r100_cp_fini(rdev); 579 radeon_wb_fini(rdev); 580 radeon_ib_pool_fini(rdev); 581 rs400_gart_fini(rdev); 582 radeon_irq_kms_fini(rdev); 583 rdev->accel_working = false; 584 } 585 return 0; 586 } 587