1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/drm_device.h> 33 #include <drm/drm_file.h> 34 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "rs400d.h" 38 39 /* This files gather functions specifics to : rs400,rs480 */ 40 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 41 42 void rs400_gart_adjust_size(struct radeon_device *rdev) 43 { 44 /* Check gart size */ 45 switch (rdev->mc.gtt_size/(1024*1024)) { 46 case 32: 47 case 64: 48 case 128: 49 case 256: 50 case 512: 51 case 1024: 52 case 2048: 53 break; 54 default: 55 DRM_ERROR("Unable to use IGP GART size %uM\n", 56 (unsigned)(rdev->mc.gtt_size >> 20)); 57 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 58 DRM_ERROR("Forcing to 32M GART size\n"); 59 rdev->mc.gtt_size = 32 * 1024 * 1024; 60 return; 61 } 62 } 63 64 void rs400_gart_tlb_flush(struct radeon_device *rdev) 65 { 66 uint32_t tmp; 67 unsigned int timeout = rdev->usec_timeout; 68 69 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 70 do { 71 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 72 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 73 break; 74 udelay(1); 75 timeout--; 76 } while (timeout > 0); 77 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 78 } 79 80 int rs400_gart_init(struct radeon_device *rdev) 81 { 82 int r; 83 84 if (rdev->gart.ptr) { 85 WARN(1, "RS400 GART already initialized\n"); 86 return 0; 87 } 88 /* Check gart size */ 89 switch(rdev->mc.gtt_size / (1024 * 1024)) { 90 case 32: 91 case 64: 92 case 128: 93 case 256: 94 case 512: 95 case 1024: 96 case 2048: 97 break; 98 default: 99 return -EINVAL; 100 } 101 /* Initialize common gart structure */ 102 r = radeon_gart_init(rdev); 103 if (r) 104 return r; 105 rs400_debugfs_pcie_gart_info_init(rdev); 106 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 107 return radeon_gart_table_ram_alloc(rdev); 108 } 109 110 int rs400_gart_enable(struct radeon_device *rdev) 111 { 112 uint32_t size_reg; 113 uint32_t tmp; 114 115 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 116 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 117 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 118 /* Check gart size */ 119 switch(rdev->mc.gtt_size / (1024 * 1024)) { 120 case 32: 121 size_reg = RS480_VA_SIZE_32MB; 122 break; 123 case 64: 124 size_reg = RS480_VA_SIZE_64MB; 125 break; 126 case 128: 127 size_reg = RS480_VA_SIZE_128MB; 128 break; 129 case 256: 130 size_reg = RS480_VA_SIZE_256MB; 131 break; 132 case 512: 133 size_reg = RS480_VA_SIZE_512MB; 134 break; 135 case 1024: 136 size_reg = RS480_VA_SIZE_1GB; 137 break; 138 case 2048: 139 size_reg = RS480_VA_SIZE_2GB; 140 break; 141 default: 142 return -EINVAL; 143 } 144 /* It should be fine to program it to max value */ 145 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 146 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 147 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 148 } else { 149 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 150 WREG32(RS480_AGP_BASE_2, 0); 151 } 152 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 153 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 154 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 155 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 156 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 157 WREG32(RADEON_BUS_CNTL, tmp); 158 } else { 159 WREG32(RADEON_MC_AGP_LOCATION, tmp); 160 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 161 WREG32(RADEON_BUS_CNTL, tmp); 162 } 163 /* Table should be in 32bits address space so ignore bits above. */ 164 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 165 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 166 167 WREG32_MC(RS480_GART_BASE, tmp); 168 /* TODO: more tweaking here */ 169 WREG32_MC(RS480_GART_FEATURE_ID, 170 (RS480_TLB_ENABLE | 171 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 172 /* Disable snooping */ 173 WREG32_MC(RS480_AGP_MODE_CNTL, 174 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 175 /* Disable AGP mode */ 176 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 177 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 178 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 179 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 180 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 181 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 182 } else { 183 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 184 tmp |= RS480_GART_INDEX_REG_EN; 185 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 186 } 187 /* Enable gart */ 188 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 189 rs400_gart_tlb_flush(rdev); 190 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 191 (unsigned)(rdev->mc.gtt_size >> 20), 192 (unsigned long long)rdev->gart.table_addr); 193 rdev->gart.ready = true; 194 return 0; 195 } 196 197 void rs400_gart_disable(struct radeon_device *rdev) 198 { 199 uint32_t tmp; 200 201 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 202 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 203 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 204 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 205 } 206 207 void rs400_gart_fini(struct radeon_device *rdev) 208 { 209 radeon_gart_fini(rdev); 210 rs400_gart_disable(rdev); 211 radeon_gart_table_ram_free(rdev); 212 } 213 214 #define RS400_PTE_UNSNOOPED (1 << 0) 215 #define RS400_PTE_WRITEABLE (1 << 2) 216 #define RS400_PTE_READABLE (1 << 3) 217 218 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) 219 { 220 uint32_t entry; 221 222 entry = (lower_32_bits(addr) & PAGE_MASK) | 223 ((upper_32_bits(addr) & 0xff) << 4); 224 if (flags & RADEON_GART_PAGE_READ) 225 entry |= RS400_PTE_READABLE; 226 if (flags & RADEON_GART_PAGE_WRITE) 227 entry |= RS400_PTE_WRITEABLE; 228 if (!(flags & RADEON_GART_PAGE_SNOOP)) 229 entry |= RS400_PTE_UNSNOOPED; 230 return entry; 231 } 232 233 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 234 uint64_t entry) 235 { 236 u32 *gtt = rdev->gart.ptr; 237 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 238 } 239 240 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 241 { 242 unsigned i; 243 uint32_t tmp; 244 245 for (i = 0; i < rdev->usec_timeout; i++) { 246 /* read MC_STATUS */ 247 tmp = RREG32(RADEON_MC_STATUS); 248 if (tmp & RADEON_MC_IDLE) { 249 return 0; 250 } 251 udelay(1); 252 } 253 return -1; 254 } 255 256 static void rs400_gpu_init(struct radeon_device *rdev) 257 { 258 /* Earlier code was calling r420_pipes_init and then 259 * rs400_mc_wait_for_idle(rdev). The problem is that 260 * at least on my Mobility Radeon Xpress 200M RC410 card 261 * that ends up in this code path ends up num_gb_pipes == 3 262 * while the card seems to have only one pipe. With the 263 * r420 pipe initialization method. 264 * 265 * Problems shown up as HyperZ glitches, see: 266 * https://bugs.freedesktop.org/show_bug.cgi?id=110897 267 * 268 * Delegating initialization to r300 code seems to work 269 * and results in proper pipe numbers. The rs400 cards 270 * are said to be not r400, but r300 kind of cards. 271 */ 272 r300_gpu_init(rdev); 273 274 if (rs400_mc_wait_for_idle(rdev)) { 275 pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n", 276 RREG32(RADEON_MC_STATUS)); 277 } 278 } 279 280 static void rs400_mc_init(struct radeon_device *rdev) 281 { 282 u64 base; 283 284 rs400_gart_adjust_size(rdev); 285 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 286 /* DDR for all card after R300 & IGP */ 287 rdev->mc.vram_is_ddr = true; 288 rdev->mc.vram_width = 128; 289 r100_vram_init_sizes(rdev); 290 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 291 radeon_vram_location(rdev, &rdev->mc, base); 292 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 293 radeon_gtt_location(rdev, &rdev->mc); 294 radeon_update_bandwidth_info(rdev); 295 } 296 297 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 298 { 299 unsigned long flags; 300 uint32_t r; 301 302 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 303 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 304 r = RREG32(RS480_NB_MC_DATA); 305 WREG32(RS480_NB_MC_INDEX, 0xff); 306 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 307 return r; 308 } 309 310 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 311 { 312 unsigned long flags; 313 314 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 315 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 316 WREG32(RS480_NB_MC_DATA, (v)); 317 WREG32(RS480_NB_MC_INDEX, 0xff); 318 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 319 } 320 321 #if defined(CONFIG_DEBUG_FS) 322 static int rs400_debugfs_gart_info_show(struct seq_file *m, void *unused) 323 { 324 struct radeon_device *rdev = m->private; 325 uint32_t tmp; 326 327 tmp = RREG32(RADEON_HOST_PATH_CNTL); 328 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 329 tmp = RREG32(RADEON_BUS_CNTL); 330 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 331 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 332 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 333 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 334 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 335 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 336 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 337 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 338 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 339 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 340 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 341 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 342 tmp = RREG32(RS690_HDP_FB_LOCATION); 343 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 344 } else { 345 tmp = RREG32(RADEON_AGP_BASE); 346 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 347 tmp = RREG32(RS480_AGP_BASE_2); 348 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 349 tmp = RREG32(RADEON_MC_AGP_LOCATION); 350 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 351 } 352 tmp = RREG32_MC(RS480_GART_BASE); 353 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 354 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 355 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 356 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 357 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 358 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 359 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 360 tmp = RREG32_MC(0x5F); 361 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 362 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 363 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 364 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 365 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 366 tmp = RREG32_MC(0x3B); 367 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 368 tmp = RREG32_MC(0x3C); 369 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 370 tmp = RREG32_MC(0x30); 371 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 372 tmp = RREG32_MC(0x31); 373 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 374 tmp = RREG32_MC(0x32); 375 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 376 tmp = RREG32_MC(0x33); 377 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 378 tmp = RREG32_MC(0x34); 379 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 380 tmp = RREG32_MC(0x35); 381 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 382 tmp = RREG32_MC(0x36); 383 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 384 tmp = RREG32_MC(0x37); 385 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 386 return 0; 387 } 388 389 DEFINE_SHOW_ATTRIBUTE(rs400_debugfs_gart_info); 390 #endif 391 392 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 393 { 394 #if defined(CONFIG_DEBUG_FS) 395 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; 396 397 debugfs_create_file("rs400_gart_info", 0444, root, rdev, 398 &rs400_debugfs_gart_info_fops); 399 #endif 400 } 401 402 static void rs400_mc_program(struct radeon_device *rdev) 403 { 404 struct r100_mc_save save; 405 406 /* Stops all mc clients */ 407 r100_mc_stop(rdev, &save); 408 409 /* Wait for mc idle */ 410 if (rs400_mc_wait_for_idle(rdev)) 411 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 412 WREG32(R_000148_MC_FB_LOCATION, 413 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 414 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 415 416 r100_mc_resume(rdev, &save); 417 } 418 419 static int rs400_startup(struct radeon_device *rdev) 420 { 421 int r; 422 423 r100_set_common_regs(rdev); 424 425 rs400_mc_program(rdev); 426 /* Resume clock */ 427 r300_clock_startup(rdev); 428 /* Initialize GPU configuration (# pipes, ...) */ 429 rs400_gpu_init(rdev); 430 r100_enable_bm(rdev); 431 /* Initialize GART (initialize after TTM so we can allocate 432 * memory through TTM but finalize after TTM) */ 433 r = rs400_gart_enable(rdev); 434 if (r) 435 return r; 436 437 /* allocate wb buffer */ 438 r = radeon_wb_init(rdev); 439 if (r) 440 return r; 441 442 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 443 if (r) { 444 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 445 return r; 446 } 447 448 /* Enable IRQ */ 449 if (!rdev->irq.installed) { 450 r = radeon_irq_kms_init(rdev); 451 if (r) 452 return r; 453 } 454 455 r100_irq_set(rdev); 456 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 457 /* 1M ring buffer */ 458 r = r100_cp_init(rdev, 1024 * 1024); 459 if (r) { 460 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 461 return r; 462 } 463 464 r = radeon_ib_pool_init(rdev); 465 if (r) { 466 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 467 return r; 468 } 469 470 return 0; 471 } 472 473 int rs400_resume(struct radeon_device *rdev) 474 { 475 int r; 476 477 /* Make sur GART are not working */ 478 rs400_gart_disable(rdev); 479 /* Resume clock before doing reset */ 480 r300_clock_startup(rdev); 481 /* setup MC before calling post tables */ 482 rs400_mc_program(rdev); 483 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 484 if (radeon_asic_reset(rdev)) { 485 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 486 RREG32(R_000E40_RBBM_STATUS), 487 RREG32(R_0007C0_CP_STAT)); 488 } 489 /* post */ 490 radeon_combios_asic_init(rdev_to_drm(rdev)); 491 /* Resume clock after posting */ 492 r300_clock_startup(rdev); 493 /* Initialize surface registers */ 494 radeon_surface_init(rdev); 495 496 rdev->accel_working = true; 497 r = rs400_startup(rdev); 498 if (r) { 499 rdev->accel_working = false; 500 } 501 return r; 502 } 503 504 int rs400_suspend(struct radeon_device *rdev) 505 { 506 radeon_pm_suspend(rdev); 507 r100_cp_disable(rdev); 508 radeon_wb_disable(rdev); 509 r100_irq_disable(rdev); 510 rs400_gart_disable(rdev); 511 return 0; 512 } 513 514 void rs400_fini(struct radeon_device *rdev) 515 { 516 radeon_pm_fini(rdev); 517 r100_cp_fini(rdev); 518 radeon_wb_fini(rdev); 519 radeon_ib_pool_fini(rdev); 520 radeon_gem_fini(rdev); 521 rs400_gart_fini(rdev); 522 radeon_irq_kms_fini(rdev); 523 radeon_fence_driver_fini(rdev); 524 radeon_bo_fini(rdev); 525 radeon_atombios_fini(rdev); 526 kfree(rdev->bios); 527 rdev->bios = NULL; 528 } 529 530 int rs400_init(struct radeon_device *rdev) 531 { 532 int r; 533 534 /* Disable VGA */ 535 r100_vga_render_disable(rdev); 536 /* Initialize scratch registers */ 537 radeon_scratch_init(rdev); 538 /* Initialize surface registers */ 539 radeon_surface_init(rdev); 540 /* TODO: disable VGA need to use VGA request */ 541 /* restore some register to sane defaults */ 542 r100_restore_sanity(rdev); 543 /* BIOS*/ 544 if (!radeon_get_bios(rdev)) { 545 if (ASIC_IS_AVIVO(rdev)) 546 return -EINVAL; 547 } 548 if (rdev->is_atom_bios) { 549 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 550 return -EINVAL; 551 } else { 552 r = radeon_combios_init(rdev); 553 if (r) 554 return r; 555 } 556 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 557 if (radeon_asic_reset(rdev)) { 558 dev_warn(rdev->dev, 559 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 560 RREG32(R_000E40_RBBM_STATUS), 561 RREG32(R_0007C0_CP_STAT)); 562 } 563 /* check if cards are posted or not */ 564 if (radeon_boot_test_post_card(rdev) == false) 565 return -EINVAL; 566 567 /* Initialize clocks */ 568 radeon_get_clock_info(rdev_to_drm(rdev)); 569 /* initialize memory controller */ 570 rs400_mc_init(rdev); 571 /* Fence driver */ 572 radeon_fence_driver_init(rdev); 573 /* Memory manager */ 574 r = radeon_bo_init(rdev); 575 if (r) 576 return r; 577 r = rs400_gart_init(rdev); 578 if (r) 579 return r; 580 r300_set_reg_safe(rdev); 581 582 /* Initialize power management */ 583 radeon_pm_init(rdev); 584 585 rdev->accel_working = true; 586 r = rs400_startup(rdev); 587 if (r) { 588 /* Somethings want wront with the accel init stop accel */ 589 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 590 r100_cp_fini(rdev); 591 radeon_wb_fini(rdev); 592 radeon_ib_pool_fini(rdev); 593 rs400_gart_fini(rdev); 594 radeon_irq_kms_fini(rdev); 595 rdev->accel_working = false; 596 } 597 return 0; 598 } 599