xref: /openbmc/linux/drivers/gpu/drm/radeon/radeon_vm.c (revision 92a76f6d)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_trace.h"
32 
33 /*
34  * GPUVM
35  * GPUVM is similar to the legacy gart on older asics, however
36  * rather than there being a single global gart table
37  * for the entire GPU, there are multiple VM page tables active
38  * at any given time.  The VM page tables can contain a mix
39  * vram pages and system memory pages and system memory pages
40  * can be mapped as snooped (cached system pages) or unsnooped
41  * (uncached system pages).
42  * Each VM has an ID associated with it and there is a page table
43  * associated with each VMID.  When execting a command buffer,
44  * the kernel tells the the ring what VMID to use for that command
45  * buffer.  VMIDs are allocated dynamically as commands are submitted.
46  * The userspace drivers maintain their own address space and the kernel
47  * sets up their pages tables accordingly when they submit their
48  * command buffers and a VMID is assigned.
49  * Cayman/Trinity support up to 8 active VMs at any given time;
50  * SI supports 16.
51  */
52 
53 /**
54  * radeon_vm_num_pde - return the number of page directory entries
55  *
56  * @rdev: radeon_device pointer
57  *
58  * Calculate the number of page directory entries (cayman+).
59  */
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
61 {
62 	return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
63 }
64 
65 /**
66  * radeon_vm_directory_size - returns the size of the page directory in bytes
67  *
68  * @rdev: radeon_device pointer
69  *
70  * Calculate the size of the page directory in bytes (cayman+).
71  */
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
73 {
74 	return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
75 }
76 
77 /**
78  * radeon_vm_manager_init - init the vm manager
79  *
80  * @rdev: radeon_device pointer
81  *
82  * Init the vm manager (cayman+).
83  * Returns 0 for success, error for failure.
84  */
85 int radeon_vm_manager_init(struct radeon_device *rdev)
86 {
87 	int r;
88 
89 	if (!rdev->vm_manager.enabled) {
90 		r = radeon_asic_vm_init(rdev);
91 		if (r)
92 			return r;
93 
94 		rdev->vm_manager.enabled = true;
95 	}
96 	return 0;
97 }
98 
99 /**
100  * radeon_vm_manager_fini - tear down the vm manager
101  *
102  * @rdev: radeon_device pointer
103  *
104  * Tear down the VM manager (cayman+).
105  */
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
107 {
108 	int i;
109 
110 	if (!rdev->vm_manager.enabled)
111 		return;
112 
113 	for (i = 0; i < RADEON_NUM_VM; ++i)
114 		radeon_fence_unref(&rdev->vm_manager.active[i]);
115 	radeon_asic_vm_fini(rdev);
116 	rdev->vm_manager.enabled = false;
117 }
118 
119 /**
120  * radeon_vm_get_bos - add the vm BOs to a validation list
121  *
122  * @vm: vm providing the BOs
123  * @head: head of validation list
124  *
125  * Add the page directory to the list of BOs to
126  * validate for command submission (cayman+).
127  */
128 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
129 					  struct radeon_vm *vm,
130 					  struct list_head *head)
131 {
132 	struct radeon_bo_list *list;
133 	unsigned i, idx;
134 
135 	list = drm_malloc_ab(vm->max_pde_used + 2,
136 			     sizeof(struct radeon_bo_list));
137 	if (!list)
138 		return NULL;
139 
140 	/* add the vm page table to the list */
141 	list[0].robj = vm->page_directory;
142 	list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
143 	list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
144 	list[0].tv.bo = &vm->page_directory->tbo;
145 	list[0].tv.shared = true;
146 	list[0].tiling_flags = 0;
147 	list_add(&list[0].tv.head, head);
148 
149 	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
150 		if (!vm->page_tables[i].bo)
151 			continue;
152 
153 		list[idx].robj = vm->page_tables[i].bo;
154 		list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
155 		list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
156 		list[idx].tv.bo = &list[idx].robj->tbo;
157 		list[idx].tv.shared = true;
158 		list[idx].tiling_flags = 0;
159 		list_add(&list[idx++].tv.head, head);
160 	}
161 
162 	return list;
163 }
164 
165 /**
166  * radeon_vm_grab_id - allocate the next free VMID
167  *
168  * @rdev: radeon_device pointer
169  * @vm: vm to allocate id for
170  * @ring: ring we want to submit job to
171  *
172  * Allocate an id for the vm (cayman+).
173  * Returns the fence we need to sync to (if any).
174  *
175  * Global and local mutex must be locked!
176  */
177 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
178 				       struct radeon_vm *vm, int ring)
179 {
180 	struct radeon_fence *best[RADEON_NUM_RINGS] = {};
181 	struct radeon_vm_id *vm_id = &vm->ids[ring];
182 
183 	unsigned choices[2] = {};
184 	unsigned i;
185 
186 	/* check if the id is still valid */
187 	if (vm_id->id && vm_id->last_id_use &&
188 	    vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
189 		return NULL;
190 
191 	/* we definately need to flush */
192 	vm_id->pd_gpu_addr = ~0ll;
193 
194 	/* skip over VMID 0, since it is the system VM */
195 	for (i = 1; i < rdev->vm_manager.nvm; ++i) {
196 		struct radeon_fence *fence = rdev->vm_manager.active[i];
197 
198 		if (fence == NULL) {
199 			/* found a free one */
200 			vm_id->id = i;
201 			trace_radeon_vm_grab_id(i, ring);
202 			return NULL;
203 		}
204 
205 		if (radeon_fence_is_earlier(fence, best[fence->ring])) {
206 			best[fence->ring] = fence;
207 			choices[fence->ring == ring ? 0 : 1] = i;
208 		}
209 	}
210 
211 	for (i = 0; i < 2; ++i) {
212 		if (choices[i]) {
213 			vm_id->id = choices[i];
214 			trace_radeon_vm_grab_id(choices[i], ring);
215 			return rdev->vm_manager.active[choices[i]];
216 		}
217 	}
218 
219 	/* should never happen */
220 	BUG();
221 	return NULL;
222 }
223 
224 /**
225  * radeon_vm_flush - hardware flush the vm
226  *
227  * @rdev: radeon_device pointer
228  * @vm: vm we want to flush
229  * @ring: ring to use for flush
230  * @updates: last vm update that is waited for
231  *
232  * Flush the vm (cayman+).
233  *
234  * Global and local mutex must be locked!
235  */
236 void radeon_vm_flush(struct radeon_device *rdev,
237 		     struct radeon_vm *vm,
238 		     int ring, struct radeon_fence *updates)
239 {
240 	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
241 	struct radeon_vm_id *vm_id = &vm->ids[ring];
242 
243 	if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates ||
244 	    radeon_fence_is_earlier(vm_id->flushed_updates, updates)) {
245 
246 		trace_radeon_vm_flush(pd_addr, ring, vm->ids[ring].id);
247 		radeon_fence_unref(&vm_id->flushed_updates);
248 		vm_id->flushed_updates = radeon_fence_ref(updates);
249 		vm_id->pd_gpu_addr = pd_addr;
250 		radeon_ring_vm_flush(rdev, &rdev->ring[ring],
251 				     vm_id->id, vm_id->pd_gpu_addr);
252 
253 	}
254 }
255 
256 /**
257  * radeon_vm_fence - remember fence for vm
258  *
259  * @rdev: radeon_device pointer
260  * @vm: vm we want to fence
261  * @fence: fence to remember
262  *
263  * Fence the vm (cayman+).
264  * Set the fence used to protect page table and id.
265  *
266  * Global and local mutex must be locked!
267  */
268 void radeon_vm_fence(struct radeon_device *rdev,
269 		     struct radeon_vm *vm,
270 		     struct radeon_fence *fence)
271 {
272 	unsigned vm_id = vm->ids[fence->ring].id;
273 
274 	radeon_fence_unref(&rdev->vm_manager.active[vm_id]);
275 	rdev->vm_manager.active[vm_id] = radeon_fence_ref(fence);
276 
277 	radeon_fence_unref(&vm->ids[fence->ring].last_id_use);
278 	vm->ids[fence->ring].last_id_use = radeon_fence_ref(fence);
279 }
280 
281 /**
282  * radeon_vm_bo_find - find the bo_va for a specific vm & bo
283  *
284  * @vm: requested vm
285  * @bo: requested buffer object
286  *
287  * Find @bo inside the requested vm (cayman+).
288  * Search inside the @bos vm list for the requested vm
289  * Returns the found bo_va or NULL if none is found
290  *
291  * Object has to be reserved!
292  */
293 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
294 				       struct radeon_bo *bo)
295 {
296 	struct radeon_bo_va *bo_va;
297 
298 	list_for_each_entry(bo_va, &bo->va, bo_list) {
299 		if (bo_va->vm == vm) {
300 			return bo_va;
301 		}
302 	}
303 	return NULL;
304 }
305 
306 /**
307  * radeon_vm_bo_add - add a bo to a specific vm
308  *
309  * @rdev: radeon_device pointer
310  * @vm: requested vm
311  * @bo: radeon buffer object
312  *
313  * Add @bo into the requested vm (cayman+).
314  * Add @bo to the list of bos associated with the vm
315  * Returns newly added bo_va or NULL for failure
316  *
317  * Object has to be reserved!
318  */
319 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
320 				      struct radeon_vm *vm,
321 				      struct radeon_bo *bo)
322 {
323 	struct radeon_bo_va *bo_va;
324 
325 	bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
326 	if (bo_va == NULL) {
327 		return NULL;
328 	}
329 	bo_va->vm = vm;
330 	bo_va->bo = bo;
331 	bo_va->it.start = 0;
332 	bo_va->it.last = 0;
333 	bo_va->flags = 0;
334 	bo_va->ref_count = 1;
335 	INIT_LIST_HEAD(&bo_va->bo_list);
336 	INIT_LIST_HEAD(&bo_va->vm_status);
337 
338 	mutex_lock(&vm->mutex);
339 	list_add_tail(&bo_va->bo_list, &bo->va);
340 	mutex_unlock(&vm->mutex);
341 
342 	return bo_va;
343 }
344 
345 /**
346  * radeon_vm_set_pages - helper to call the right asic function
347  *
348  * @rdev: radeon_device pointer
349  * @ib: indirect buffer to fill with commands
350  * @pe: addr of the page entry
351  * @addr: dst addr to write into pe
352  * @count: number of page entries to update
353  * @incr: increase next addr by incr bytes
354  * @flags: hw access flags
355  *
356  * Traces the parameters and calls the right asic functions
357  * to setup the page table using the DMA.
358  */
359 static void radeon_vm_set_pages(struct radeon_device *rdev,
360 				struct radeon_ib *ib,
361 				uint64_t pe,
362 				uint64_t addr, unsigned count,
363 				uint32_t incr, uint32_t flags)
364 {
365 	trace_radeon_vm_set_page(pe, addr, count, incr, flags);
366 
367 	if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
368 		uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
369 		radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
370 
371 	} else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
372 		radeon_asic_vm_write_pages(rdev, ib, pe, addr,
373 					   count, incr, flags);
374 
375 	} else {
376 		radeon_asic_vm_set_pages(rdev, ib, pe, addr,
377 					 count, incr, flags);
378 	}
379 }
380 
381 /**
382  * radeon_vm_clear_bo - initially clear the page dir/table
383  *
384  * @rdev: radeon_device pointer
385  * @bo: bo to clear
386  */
387 static int radeon_vm_clear_bo(struct radeon_device *rdev,
388 			      struct radeon_bo *bo)
389 {
390 	struct radeon_ib ib;
391 	unsigned entries;
392 	uint64_t addr;
393 	int r;
394 
395 	r = radeon_bo_reserve(bo, false);
396 	if (r)
397 		return r;
398 
399 	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
400 	if (r)
401 		goto error_unreserve;
402 
403 	addr = radeon_bo_gpu_offset(bo);
404 	entries = radeon_bo_size(bo) / 8;
405 
406 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
407 	if (r)
408 		goto error_unreserve;
409 
410 	ib.length_dw = 0;
411 
412 	radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
413 	radeon_asic_vm_pad_ib(rdev, &ib);
414 	WARN_ON(ib.length_dw > 64);
415 
416 	r = radeon_ib_schedule(rdev, &ib, NULL, false);
417 	if (r)
418 		goto error_free;
419 
420 	ib.fence->is_vm_update = true;
421 	radeon_bo_fence(bo, ib.fence, false);
422 
423 error_free:
424 	radeon_ib_free(rdev, &ib);
425 
426 error_unreserve:
427 	radeon_bo_unreserve(bo);
428 	return r;
429 }
430 
431 /**
432  * radeon_vm_bo_set_addr - set bos virtual address inside a vm
433  *
434  * @rdev: radeon_device pointer
435  * @bo_va: bo_va to store the address
436  * @soffset: requested offset of the buffer in the VM address space
437  * @flags: attributes of pages (read/write/valid/etc.)
438  *
439  * Set offset of @bo_va (cayman+).
440  * Validate and set the offset requested within the vm address space.
441  * Returns 0 for success, error for failure.
442  *
443  * Object has to be reserved and gets unreserved by this function!
444  */
445 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
446 			  struct radeon_bo_va *bo_va,
447 			  uint64_t soffset,
448 			  uint32_t flags)
449 {
450 	uint64_t size = radeon_bo_size(bo_va->bo);
451 	struct radeon_vm *vm = bo_va->vm;
452 	unsigned last_pfn, pt_idx;
453 	uint64_t eoffset;
454 	int r;
455 
456 	if (soffset) {
457 		/* make sure object fit at this offset */
458 		eoffset = soffset + size - 1;
459 		if (soffset >= eoffset) {
460 			r = -EINVAL;
461 			goto error_unreserve;
462 		}
463 
464 		last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
465 		if (last_pfn >= rdev->vm_manager.max_pfn) {
466 			dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n",
467 				last_pfn, rdev->vm_manager.max_pfn);
468 			r = -EINVAL;
469 			goto error_unreserve;
470 		}
471 
472 	} else {
473 		eoffset = last_pfn = 0;
474 	}
475 
476 	mutex_lock(&vm->mutex);
477 	soffset /= RADEON_GPU_PAGE_SIZE;
478 	eoffset /= RADEON_GPU_PAGE_SIZE;
479 	if (soffset || eoffset) {
480 		struct interval_tree_node *it;
481 		it = interval_tree_iter_first(&vm->va, soffset, eoffset);
482 		if (it && it != &bo_va->it) {
483 			struct radeon_bo_va *tmp;
484 			tmp = container_of(it, struct radeon_bo_va, it);
485 			/* bo and tmp overlap, invalid offset */
486 			dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
487 				"(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
488 				soffset, tmp->bo, tmp->it.start, tmp->it.last);
489 			mutex_unlock(&vm->mutex);
490 			r = -EINVAL;
491 			goto error_unreserve;
492 		}
493 	}
494 
495 	if (bo_va->it.start || bo_va->it.last) {
496 		/* add a clone of the bo_va to clear the old address */
497 		struct radeon_bo_va *tmp;
498 		tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
499 		if (!tmp) {
500 			mutex_unlock(&vm->mutex);
501 			r = -ENOMEM;
502 			goto error_unreserve;
503 		}
504 		tmp->it.start = bo_va->it.start;
505 		tmp->it.last = bo_va->it.last;
506 		tmp->vm = vm;
507 		tmp->bo = radeon_bo_ref(bo_va->bo);
508 
509 		interval_tree_remove(&bo_va->it, &vm->va);
510 		spin_lock(&vm->status_lock);
511 		bo_va->it.start = 0;
512 		bo_va->it.last = 0;
513 		list_del_init(&bo_va->vm_status);
514 		list_add(&tmp->vm_status, &vm->freed);
515 		spin_unlock(&vm->status_lock);
516 	}
517 
518 	if (soffset || eoffset) {
519 		spin_lock(&vm->status_lock);
520 		bo_va->it.start = soffset;
521 		bo_va->it.last = eoffset;
522 		list_add(&bo_va->vm_status, &vm->cleared);
523 		spin_unlock(&vm->status_lock);
524 		interval_tree_insert(&bo_va->it, &vm->va);
525 	}
526 
527 	bo_va->flags = flags;
528 
529 	soffset >>= radeon_vm_block_size;
530 	eoffset >>= radeon_vm_block_size;
531 
532 	BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
533 
534 	if (eoffset > vm->max_pde_used)
535 		vm->max_pde_used = eoffset;
536 
537 	radeon_bo_unreserve(bo_va->bo);
538 
539 	/* walk over the address space and allocate the page tables */
540 	for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
541 		struct radeon_bo *pt;
542 
543 		if (vm->page_tables[pt_idx].bo)
544 			continue;
545 
546 		/* drop mutex to allocate and clear page table */
547 		mutex_unlock(&vm->mutex);
548 
549 		r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
550 				     RADEON_GPU_PAGE_SIZE, true,
551 				     RADEON_GEM_DOMAIN_VRAM, 0,
552 				     NULL, NULL, &pt);
553 		if (r)
554 			return r;
555 
556 		r = radeon_vm_clear_bo(rdev, pt);
557 		if (r) {
558 			radeon_bo_unref(&pt);
559 			return r;
560 		}
561 
562 		/* aquire mutex again */
563 		mutex_lock(&vm->mutex);
564 		if (vm->page_tables[pt_idx].bo) {
565 			/* someone else allocated the pt in the meantime */
566 			mutex_unlock(&vm->mutex);
567 			radeon_bo_unref(&pt);
568 			mutex_lock(&vm->mutex);
569 			continue;
570 		}
571 
572 		vm->page_tables[pt_idx].addr = 0;
573 		vm->page_tables[pt_idx].bo = pt;
574 	}
575 
576 	mutex_unlock(&vm->mutex);
577 	return 0;
578 
579 error_unreserve:
580 	radeon_bo_unreserve(bo_va->bo);
581 	return r;
582 }
583 
584 /**
585  * radeon_vm_map_gart - get the physical address of a gart page
586  *
587  * @rdev: radeon_device pointer
588  * @addr: the unmapped addr
589  *
590  * Look up the physical address of the page that the pte resolves
591  * to (cayman+).
592  * Returns the physical address of the page.
593  */
594 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
595 {
596 	uint64_t result;
597 
598 	/* page table offset */
599 	result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
600 	result &= ~RADEON_GPU_PAGE_MASK;
601 
602 	return result;
603 }
604 
605 /**
606  * radeon_vm_page_flags - translate page flags to what the hw uses
607  *
608  * @flags: flags comming from userspace
609  *
610  * Translate the flags the userspace ABI uses to hw flags.
611  */
612 static uint32_t radeon_vm_page_flags(uint32_t flags)
613 {
614 	uint32_t hw_flags = 0;
615 
616 	hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
617 	hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
618 	hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
619 	if (flags & RADEON_VM_PAGE_SYSTEM) {
620 		hw_flags |= R600_PTE_SYSTEM;
621 		hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
622 	}
623 	return hw_flags;
624 }
625 
626 /**
627  * radeon_vm_update_pdes - make sure that page directory is valid
628  *
629  * @rdev: radeon_device pointer
630  * @vm: requested vm
631  * @start: start of GPU address range
632  * @end: end of GPU address range
633  *
634  * Allocates new page tables if necessary
635  * and updates the page directory (cayman+).
636  * Returns 0 for success, error for failure.
637  *
638  * Global and local mutex must be locked!
639  */
640 int radeon_vm_update_page_directory(struct radeon_device *rdev,
641 				    struct radeon_vm *vm)
642 {
643 	struct radeon_bo *pd = vm->page_directory;
644 	uint64_t pd_addr = radeon_bo_gpu_offset(pd);
645 	uint32_t incr = RADEON_VM_PTE_COUNT * 8;
646 	uint64_t last_pde = ~0, last_pt = ~0;
647 	unsigned count = 0, pt_idx, ndw;
648 	struct radeon_ib ib;
649 	int r;
650 
651 	/* padding, etc. */
652 	ndw = 64;
653 
654 	/* assume the worst case */
655 	ndw += vm->max_pde_used * 6;
656 
657 	/* update too big for an IB */
658 	if (ndw > 0xfffff)
659 		return -ENOMEM;
660 
661 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
662 	if (r)
663 		return r;
664 	ib.length_dw = 0;
665 
666 	/* walk over the address space and update the page directory */
667 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
668 		struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
669 		uint64_t pde, pt;
670 
671 		if (bo == NULL)
672 			continue;
673 
674 		pt = radeon_bo_gpu_offset(bo);
675 		if (vm->page_tables[pt_idx].addr == pt)
676 			continue;
677 		vm->page_tables[pt_idx].addr = pt;
678 
679 		pde = pd_addr + pt_idx * 8;
680 		if (((last_pde + 8 * count) != pde) ||
681 		    ((last_pt + incr * count) != pt)) {
682 
683 			if (count) {
684 				radeon_vm_set_pages(rdev, &ib, last_pde,
685 						    last_pt, count, incr,
686 						    R600_PTE_VALID);
687 			}
688 
689 			count = 1;
690 			last_pde = pde;
691 			last_pt = pt;
692 		} else {
693 			++count;
694 		}
695 	}
696 
697 	if (count)
698 		radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
699 				    incr, R600_PTE_VALID);
700 
701 	if (ib.length_dw != 0) {
702 		radeon_asic_vm_pad_ib(rdev, &ib);
703 
704 		radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
705 		WARN_ON(ib.length_dw > ndw);
706 		r = radeon_ib_schedule(rdev, &ib, NULL, false);
707 		if (r) {
708 			radeon_ib_free(rdev, &ib);
709 			return r;
710 		}
711 		ib.fence->is_vm_update = true;
712 		radeon_bo_fence(pd, ib.fence, false);
713 	}
714 	radeon_ib_free(rdev, &ib);
715 
716 	return 0;
717 }
718 
719 /**
720  * radeon_vm_frag_ptes - add fragment information to PTEs
721  *
722  * @rdev: radeon_device pointer
723  * @ib: IB for the update
724  * @pe_start: first PTE to handle
725  * @pe_end: last PTE to handle
726  * @addr: addr those PTEs should point to
727  * @flags: hw mapping flags
728  *
729  * Global and local mutex must be locked!
730  */
731 static void radeon_vm_frag_ptes(struct radeon_device *rdev,
732 				struct radeon_ib *ib,
733 				uint64_t pe_start, uint64_t pe_end,
734 				uint64_t addr, uint32_t flags)
735 {
736 	/**
737 	 * The MC L1 TLB supports variable sized pages, based on a fragment
738 	 * field in the PTE. When this field is set to a non-zero value, page
739 	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
740 	 * flags are considered valid for all PTEs within the fragment range
741 	 * and corresponding mappings are assumed to be physically contiguous.
742 	 *
743 	 * The L1 TLB can store a single PTE for the whole fragment,
744 	 * significantly increasing the space available for translation
745 	 * caching. This leads to large improvements in throughput when the
746 	 * TLB is under pressure.
747 	 *
748 	 * The L2 TLB distributes small and large fragments into two
749 	 * asymmetric partitions. The large fragment cache is significantly
750 	 * larger. Thus, we try to use large fragments wherever possible.
751 	 * Userspace can support this by aligning virtual base address and
752 	 * allocation size to the fragment size.
753 	 */
754 
755 	/* NI is optimized for 256KB fragments, SI and newer for 64KB */
756 	uint64_t frag_flags = ((rdev->family == CHIP_CAYMAN) ||
757 			       (rdev->family == CHIP_ARUBA)) ?
758 			R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
759 	uint64_t frag_align = ((rdev->family == CHIP_CAYMAN) ||
760 			       (rdev->family == CHIP_ARUBA)) ? 0x200 : 0x80;
761 
762 	uint64_t frag_start = ALIGN(pe_start, frag_align);
763 	uint64_t frag_end = pe_end & ~(frag_align - 1);
764 
765 	unsigned count;
766 
767 	/* system pages are non continuously */
768 	if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
769 	    (frag_start >= frag_end)) {
770 
771 		count = (pe_end - pe_start) / 8;
772 		radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
773 				    RADEON_GPU_PAGE_SIZE, flags);
774 		return;
775 	}
776 
777 	/* handle the 4K area at the beginning */
778 	if (pe_start != frag_start) {
779 		count = (frag_start - pe_start) / 8;
780 		radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
781 				    RADEON_GPU_PAGE_SIZE, flags);
782 		addr += RADEON_GPU_PAGE_SIZE * count;
783 	}
784 
785 	/* handle the area in the middle */
786 	count = (frag_end - frag_start) / 8;
787 	radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
788 			    RADEON_GPU_PAGE_SIZE, flags | frag_flags);
789 
790 	/* handle the 4K area at the end */
791 	if (frag_end != pe_end) {
792 		addr += RADEON_GPU_PAGE_SIZE * count;
793 		count = (pe_end - frag_end) / 8;
794 		radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
795 				    RADEON_GPU_PAGE_SIZE, flags);
796 	}
797 }
798 
799 /**
800  * radeon_vm_update_ptes - make sure that page tables are valid
801  *
802  * @rdev: radeon_device pointer
803  * @vm: requested vm
804  * @start: start of GPU address range
805  * @end: end of GPU address range
806  * @dst: destination address to map to
807  * @flags: mapping flags
808  *
809  * Update the page tables in the range @start - @end (cayman+).
810  *
811  * Global and local mutex must be locked!
812  */
813 static int radeon_vm_update_ptes(struct radeon_device *rdev,
814 				 struct radeon_vm *vm,
815 				 struct radeon_ib *ib,
816 				 uint64_t start, uint64_t end,
817 				 uint64_t dst, uint32_t flags)
818 {
819 	uint64_t mask = RADEON_VM_PTE_COUNT - 1;
820 	uint64_t last_pte = ~0, last_dst = ~0;
821 	unsigned count = 0;
822 	uint64_t addr;
823 
824 	/* walk over the address space and update the page tables */
825 	for (addr = start; addr < end; ) {
826 		uint64_t pt_idx = addr >> radeon_vm_block_size;
827 		struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
828 		unsigned nptes;
829 		uint64_t pte;
830 		int r;
831 
832 		radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
833 		r = reservation_object_reserve_shared(pt->tbo.resv);
834 		if (r)
835 			return r;
836 
837 		if ((addr & ~mask) == (end & ~mask))
838 			nptes = end - addr;
839 		else
840 			nptes = RADEON_VM_PTE_COUNT - (addr & mask);
841 
842 		pte = radeon_bo_gpu_offset(pt);
843 		pte += (addr & mask) * 8;
844 
845 		if ((last_pte + 8 * count) != pte) {
846 
847 			if (count) {
848 				radeon_vm_frag_ptes(rdev, ib, last_pte,
849 						    last_pte + 8 * count,
850 						    last_dst, flags);
851 			}
852 
853 			count = nptes;
854 			last_pte = pte;
855 			last_dst = dst;
856 		} else {
857 			count += nptes;
858 		}
859 
860 		addr += nptes;
861 		dst += nptes * RADEON_GPU_PAGE_SIZE;
862 	}
863 
864 	if (count) {
865 		radeon_vm_frag_ptes(rdev, ib, last_pte,
866 				    last_pte + 8 * count,
867 				    last_dst, flags);
868 	}
869 
870 	return 0;
871 }
872 
873 /**
874  * radeon_vm_fence_pts - fence page tables after an update
875  *
876  * @vm: requested vm
877  * @start: start of GPU address range
878  * @end: end of GPU address range
879  * @fence: fence to use
880  *
881  * Fence the page tables in the range @start - @end (cayman+).
882  *
883  * Global and local mutex must be locked!
884  */
885 static void radeon_vm_fence_pts(struct radeon_vm *vm,
886 				uint64_t start, uint64_t end,
887 				struct radeon_fence *fence)
888 {
889 	unsigned i;
890 
891 	start >>= radeon_vm_block_size;
892 	end = (end - 1) >> radeon_vm_block_size;
893 
894 	for (i = start; i <= end; ++i)
895 		radeon_bo_fence(vm->page_tables[i].bo, fence, true);
896 }
897 
898 /**
899  * radeon_vm_bo_update - map a bo into the vm page table
900  *
901  * @rdev: radeon_device pointer
902  * @vm: requested vm
903  * @bo: radeon buffer object
904  * @mem: ttm mem
905  *
906  * Fill in the page table entries for @bo (cayman+).
907  * Returns 0 for success, -EINVAL for failure.
908  *
909  * Object have to be reserved and mutex must be locked!
910  */
911 int radeon_vm_bo_update(struct radeon_device *rdev,
912 			struct radeon_bo_va *bo_va,
913 			struct ttm_mem_reg *mem)
914 {
915 	struct radeon_vm *vm = bo_va->vm;
916 	struct radeon_ib ib;
917 	unsigned nptes, ncmds, ndw;
918 	uint64_t addr;
919 	uint32_t flags;
920 	int r;
921 
922 	if (!bo_va->it.start) {
923 		dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
924 			bo_va->bo, vm);
925 		return -EINVAL;
926 	}
927 
928 	spin_lock(&vm->status_lock);
929 	if (mem) {
930 		if (list_empty(&bo_va->vm_status)) {
931 			spin_unlock(&vm->status_lock);
932 			return 0;
933 		}
934 		list_del_init(&bo_va->vm_status);
935 	} else {
936 		list_del(&bo_va->vm_status);
937 		list_add(&bo_va->vm_status, &vm->cleared);
938 	}
939 	spin_unlock(&vm->status_lock);
940 
941 	bo_va->flags &= ~RADEON_VM_PAGE_VALID;
942 	bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
943 	bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
944 	if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))
945 		bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
946 
947 	if (mem) {
948 		addr = mem->start << PAGE_SHIFT;
949 		if (mem->mem_type != TTM_PL_SYSTEM) {
950 			bo_va->flags |= RADEON_VM_PAGE_VALID;
951 		}
952 		if (mem->mem_type == TTM_PL_TT) {
953 			bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
954 			if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
955 				bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
956 
957 		} else {
958 			addr += rdev->vm_manager.vram_base_offset;
959 		}
960 	} else {
961 		addr = 0;
962 	}
963 
964 	trace_radeon_vm_bo_update(bo_va);
965 
966 	nptes = bo_va->it.last - bo_va->it.start + 1;
967 
968 	/* reserve space for one command every (1 << BLOCK_SIZE) entries
969 	   or 2k dwords (whatever is smaller) */
970 	ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
971 
972 	/* padding, etc. */
973 	ndw = 64;
974 
975 	flags = radeon_vm_page_flags(bo_va->flags);
976 	if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
977 		/* only copy commands needed */
978 		ndw += ncmds * 7;
979 
980 	} else if (flags & R600_PTE_SYSTEM) {
981 		/* header for write data commands */
982 		ndw += ncmds * 4;
983 
984 		/* body of write data command */
985 		ndw += nptes * 2;
986 
987 	} else {
988 		/* set page commands needed */
989 		ndw += ncmds * 10;
990 
991 		/* two extra commands for begin/end of fragment */
992 		ndw += 2 * 10;
993 	}
994 
995 	/* update too big for an IB */
996 	if (ndw > 0xfffff)
997 		return -ENOMEM;
998 
999 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
1000 	if (r)
1001 		return r;
1002 	ib.length_dw = 0;
1003 
1004 	if (!(bo_va->flags & RADEON_VM_PAGE_VALID)) {
1005 		unsigned i;
1006 
1007 		for (i = 0; i < RADEON_NUM_RINGS; ++i)
1008 			radeon_sync_fence(&ib.sync, vm->ids[i].last_id_use);
1009 	}
1010 
1011 	r = radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
1012 				  bo_va->it.last + 1, addr,
1013 				  radeon_vm_page_flags(bo_va->flags));
1014 	if (r) {
1015 		radeon_ib_free(rdev, &ib);
1016 		return r;
1017 	}
1018 
1019 	radeon_asic_vm_pad_ib(rdev, &ib);
1020 	WARN_ON(ib.length_dw > ndw);
1021 
1022 	r = radeon_ib_schedule(rdev, &ib, NULL, false);
1023 	if (r) {
1024 		radeon_ib_free(rdev, &ib);
1025 		return r;
1026 	}
1027 	ib.fence->is_vm_update = true;
1028 	radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence);
1029 	radeon_fence_unref(&bo_va->last_pt_update);
1030 	bo_va->last_pt_update = radeon_fence_ref(ib.fence);
1031 	radeon_ib_free(rdev, &ib);
1032 
1033 	return 0;
1034 }
1035 
1036 /**
1037  * radeon_vm_clear_freed - clear freed BOs in the PT
1038  *
1039  * @rdev: radeon_device pointer
1040  * @vm: requested vm
1041  *
1042  * Make sure all freed BOs are cleared in the PT.
1043  * Returns 0 for success.
1044  *
1045  * PTs have to be reserved and mutex must be locked!
1046  */
1047 int radeon_vm_clear_freed(struct radeon_device *rdev,
1048 			  struct radeon_vm *vm)
1049 {
1050 	struct radeon_bo_va *bo_va;
1051 	int r = 0;
1052 
1053 	spin_lock(&vm->status_lock);
1054 	while (!list_empty(&vm->freed)) {
1055 		bo_va = list_first_entry(&vm->freed,
1056 			struct radeon_bo_va, vm_status);
1057 		spin_unlock(&vm->status_lock);
1058 
1059 		r = radeon_vm_bo_update(rdev, bo_va, NULL);
1060 		radeon_bo_unref(&bo_va->bo);
1061 		radeon_fence_unref(&bo_va->last_pt_update);
1062 		spin_lock(&vm->status_lock);
1063 		list_del(&bo_va->vm_status);
1064 		kfree(bo_va);
1065 		if (r)
1066 			break;
1067 
1068 	}
1069 	spin_unlock(&vm->status_lock);
1070 	return r;
1071 
1072 }
1073 
1074 /**
1075  * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1076  *
1077  * @rdev: radeon_device pointer
1078  * @vm: requested vm
1079  *
1080  * Make sure all invalidated BOs are cleared in the PT.
1081  * Returns 0 for success.
1082  *
1083  * PTs have to be reserved and mutex must be locked!
1084  */
1085 int radeon_vm_clear_invalids(struct radeon_device *rdev,
1086 			     struct radeon_vm *vm)
1087 {
1088 	struct radeon_bo_va *bo_va;
1089 	int r;
1090 
1091 	spin_lock(&vm->status_lock);
1092 	while (!list_empty(&vm->invalidated)) {
1093 		bo_va = list_first_entry(&vm->invalidated,
1094 			struct radeon_bo_va, vm_status);
1095 		spin_unlock(&vm->status_lock);
1096 
1097 		r = radeon_vm_bo_update(rdev, bo_va, NULL);
1098 		if (r)
1099 			return r;
1100 
1101 		spin_lock(&vm->status_lock);
1102 	}
1103 	spin_unlock(&vm->status_lock);
1104 
1105 	return 0;
1106 }
1107 
1108 /**
1109  * radeon_vm_bo_rmv - remove a bo to a specific vm
1110  *
1111  * @rdev: radeon_device pointer
1112  * @bo_va: requested bo_va
1113  *
1114  * Remove @bo_va->bo from the requested vm (cayman+).
1115  *
1116  * Object have to be reserved!
1117  */
1118 void radeon_vm_bo_rmv(struct radeon_device *rdev,
1119 		      struct radeon_bo_va *bo_va)
1120 {
1121 	struct radeon_vm *vm = bo_va->vm;
1122 
1123 	list_del(&bo_va->bo_list);
1124 
1125 	mutex_lock(&vm->mutex);
1126 	if (bo_va->it.start || bo_va->it.last)
1127 		interval_tree_remove(&bo_va->it, &vm->va);
1128 
1129 	spin_lock(&vm->status_lock);
1130 	list_del(&bo_va->vm_status);
1131 	if (bo_va->it.start || bo_va->it.last) {
1132 		bo_va->bo = radeon_bo_ref(bo_va->bo);
1133 		list_add(&bo_va->vm_status, &vm->freed);
1134 	} else {
1135 		radeon_fence_unref(&bo_va->last_pt_update);
1136 		kfree(bo_va);
1137 	}
1138 	spin_unlock(&vm->status_lock);
1139 
1140 	mutex_unlock(&vm->mutex);
1141 }
1142 
1143 /**
1144  * radeon_vm_bo_invalidate - mark the bo as invalid
1145  *
1146  * @rdev: radeon_device pointer
1147  * @vm: requested vm
1148  * @bo: radeon buffer object
1149  *
1150  * Mark @bo as invalid (cayman+).
1151  */
1152 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1153 			     struct radeon_bo *bo)
1154 {
1155 	struct radeon_bo_va *bo_va;
1156 
1157 	list_for_each_entry(bo_va, &bo->va, bo_list) {
1158 		spin_lock(&bo_va->vm->status_lock);
1159 		if (list_empty(&bo_va->vm_status) &&
1160 		    (bo_va->it.start || bo_va->it.last))
1161 			list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1162 		spin_unlock(&bo_va->vm->status_lock);
1163 	}
1164 }
1165 
1166 /**
1167  * radeon_vm_init - initialize a vm instance
1168  *
1169  * @rdev: radeon_device pointer
1170  * @vm: requested vm
1171  *
1172  * Init @vm fields (cayman+).
1173  */
1174 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1175 {
1176 	const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
1177 		RADEON_VM_PTE_COUNT * 8);
1178 	unsigned pd_size, pd_entries, pts_size;
1179 	int i, r;
1180 
1181 	vm->ib_bo_va = NULL;
1182 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1183 		vm->ids[i].id = 0;
1184 		vm->ids[i].flushed_updates = NULL;
1185 		vm->ids[i].last_id_use = NULL;
1186 	}
1187 	mutex_init(&vm->mutex);
1188 	vm->va = RB_ROOT;
1189 	spin_lock_init(&vm->status_lock);
1190 	INIT_LIST_HEAD(&vm->invalidated);
1191 	INIT_LIST_HEAD(&vm->freed);
1192 	INIT_LIST_HEAD(&vm->cleared);
1193 
1194 	pd_size = radeon_vm_directory_size(rdev);
1195 	pd_entries = radeon_vm_num_pdes(rdev);
1196 
1197 	/* allocate page table array */
1198 	pts_size = pd_entries * sizeof(struct radeon_vm_pt);
1199 	vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1200 	if (vm->page_tables == NULL) {
1201 		DRM_ERROR("Cannot allocate memory for page table array\n");
1202 		return -ENOMEM;
1203 	}
1204 
1205 	r = radeon_bo_create(rdev, pd_size, align, true,
1206 			     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1207 			     NULL, &vm->page_directory);
1208 	if (r)
1209 		return r;
1210 
1211 	r = radeon_vm_clear_bo(rdev, vm->page_directory);
1212 	if (r) {
1213 		radeon_bo_unref(&vm->page_directory);
1214 		vm->page_directory = NULL;
1215 		return r;
1216 	}
1217 
1218 	return 0;
1219 }
1220 
1221 /**
1222  * radeon_vm_fini - tear down a vm instance
1223  *
1224  * @rdev: radeon_device pointer
1225  * @vm: requested vm
1226  *
1227  * Tear down @vm (cayman+).
1228  * Unbind the VM and remove all bos from the vm bo list
1229  */
1230 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1231 {
1232 	struct radeon_bo_va *bo_va, *tmp;
1233 	int i, r;
1234 
1235 	if (!RB_EMPTY_ROOT(&vm->va)) {
1236 		dev_err(rdev->dev, "still active bo inside vm\n");
1237 	}
1238 	rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
1239 		interval_tree_remove(&bo_va->it, &vm->va);
1240 		r = radeon_bo_reserve(bo_va->bo, false);
1241 		if (!r) {
1242 			list_del_init(&bo_va->bo_list);
1243 			radeon_bo_unreserve(bo_va->bo);
1244 			radeon_fence_unref(&bo_va->last_pt_update);
1245 			kfree(bo_va);
1246 		}
1247 	}
1248 	list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1249 		radeon_bo_unref(&bo_va->bo);
1250 		radeon_fence_unref(&bo_va->last_pt_update);
1251 		kfree(bo_va);
1252 	}
1253 
1254 	for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
1255 		radeon_bo_unref(&vm->page_tables[i].bo);
1256 	kfree(vm->page_tables);
1257 
1258 	radeon_bo_unref(&vm->page_directory);
1259 
1260 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1261 		radeon_fence_unref(&vm->ids[i].flushed_updates);
1262 		radeon_fence_unref(&vm->ids[i].last_id_use);
1263 	}
1264 
1265 	mutex_destroy(&vm->mutex);
1266 }
1267