1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "radeon.h" 37 #include "r600d.h" 38 39 /* 1 second timeout */ 40 #define UVD_IDLE_TIMEOUT_MS 1000 41 42 /* Firmware Names */ 43 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 44 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 45 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 46 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 47 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" 48 49 MODULE_FIRMWARE(FIRMWARE_RV710); 50 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 51 MODULE_FIRMWARE(FIRMWARE_SUMO); 52 MODULE_FIRMWARE(FIRMWARE_TAHITI); 53 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 54 55 static void radeon_uvd_idle_work_handler(struct work_struct *work); 56 57 int radeon_uvd_init(struct radeon_device *rdev) 58 { 59 unsigned long bo_size; 60 const char *fw_name; 61 int i, r; 62 63 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 64 65 switch (rdev->family) { 66 case CHIP_RV710: 67 case CHIP_RV730: 68 case CHIP_RV740: 69 fw_name = FIRMWARE_RV710; 70 break; 71 72 case CHIP_CYPRESS: 73 case CHIP_HEMLOCK: 74 case CHIP_JUNIPER: 75 case CHIP_REDWOOD: 76 case CHIP_CEDAR: 77 fw_name = FIRMWARE_CYPRESS; 78 break; 79 80 case CHIP_SUMO: 81 case CHIP_SUMO2: 82 case CHIP_PALM: 83 case CHIP_CAYMAN: 84 case CHIP_BARTS: 85 case CHIP_TURKS: 86 case CHIP_CAICOS: 87 fw_name = FIRMWARE_SUMO; 88 break; 89 90 case CHIP_TAHITI: 91 case CHIP_VERDE: 92 case CHIP_PITCAIRN: 93 case CHIP_ARUBA: 94 fw_name = FIRMWARE_TAHITI; 95 break; 96 97 case CHIP_BONAIRE: 98 case CHIP_KABINI: 99 case CHIP_KAVERI: 100 fw_name = FIRMWARE_BONAIRE; 101 break; 102 103 default: 104 return -EINVAL; 105 } 106 107 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 108 if (r) { 109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 110 fw_name); 111 return r; 112 } 113 114 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 115 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE; 116 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 117 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo); 118 if (r) { 119 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 120 return r; 121 } 122 123 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 124 if (r) { 125 radeon_bo_unref(&rdev->uvd.vcpu_bo); 126 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 127 return r; 128 } 129 130 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 131 &rdev->uvd.gpu_addr); 132 if (r) { 133 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 134 radeon_bo_unref(&rdev->uvd.vcpu_bo); 135 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 136 return r; 137 } 138 139 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 140 if (r) { 141 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 142 return r; 143 } 144 145 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 146 147 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 148 atomic_set(&rdev->uvd.handles[i], 0); 149 rdev->uvd.filp[i] = NULL; 150 rdev->uvd.img_size[i] = 0; 151 } 152 153 return 0; 154 } 155 156 void radeon_uvd_fini(struct radeon_device *rdev) 157 { 158 int r; 159 160 if (rdev->uvd.vcpu_bo == NULL) 161 return; 162 163 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 164 if (!r) { 165 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 166 radeon_bo_unpin(rdev->uvd.vcpu_bo); 167 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 168 } 169 170 radeon_bo_unref(&rdev->uvd.vcpu_bo); 171 172 release_firmware(rdev->uvd_fw); 173 } 174 175 int radeon_uvd_suspend(struct radeon_device *rdev) 176 { 177 unsigned size; 178 void *ptr; 179 int i; 180 181 if (rdev->uvd.vcpu_bo == NULL) 182 return 0; 183 184 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 185 if (atomic_read(&rdev->uvd.handles[i])) 186 break; 187 188 if (i == RADEON_MAX_UVD_HANDLES) 189 return 0; 190 191 size = radeon_bo_size(rdev->uvd.vcpu_bo); 192 size -= rdev->uvd_fw->size; 193 194 ptr = rdev->uvd.cpu_addr; 195 ptr += rdev->uvd_fw->size; 196 197 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 198 memcpy(rdev->uvd.saved_bo, ptr, size); 199 200 return 0; 201 } 202 203 int radeon_uvd_resume(struct radeon_device *rdev) 204 { 205 unsigned size; 206 void *ptr; 207 208 if (rdev->uvd.vcpu_bo == NULL) 209 return -EINVAL; 210 211 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 212 213 size = radeon_bo_size(rdev->uvd.vcpu_bo); 214 size -= rdev->uvd_fw->size; 215 216 ptr = rdev->uvd.cpu_addr; 217 ptr += rdev->uvd_fw->size; 218 219 if (rdev->uvd.saved_bo != NULL) { 220 memcpy(ptr, rdev->uvd.saved_bo, size); 221 kfree(rdev->uvd.saved_bo); 222 rdev->uvd.saved_bo = NULL; 223 } else 224 memset(ptr, 0, size); 225 226 return 0; 227 } 228 229 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo) 230 { 231 rbo->placement.fpfn = 0 >> PAGE_SHIFT; 232 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 233 } 234 235 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 236 { 237 int i, r; 238 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 239 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 240 if (handle != 0 && rdev->uvd.filp[i] == filp) { 241 struct radeon_fence *fence; 242 243 r = radeon_uvd_get_destroy_msg(rdev, 244 R600_RING_TYPE_UVD_INDEX, handle, &fence); 245 if (r) { 246 DRM_ERROR("Error destroying UVD (%d)!\n", r); 247 continue; 248 } 249 250 radeon_fence_wait(fence, false); 251 radeon_fence_unref(&fence); 252 253 rdev->uvd.filp[i] = NULL; 254 atomic_set(&rdev->uvd.handles[i], 0); 255 } 256 } 257 } 258 259 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 260 { 261 unsigned stream_type = msg[4]; 262 unsigned width = msg[6]; 263 unsigned height = msg[7]; 264 unsigned dpb_size = msg[9]; 265 unsigned pitch = msg[28]; 266 267 unsigned width_in_mb = width / 16; 268 unsigned height_in_mb = ALIGN(height / 16, 2); 269 270 unsigned image_size, tmp, min_dpb_size; 271 272 image_size = width * height; 273 image_size += image_size / 2; 274 image_size = ALIGN(image_size, 1024); 275 276 switch (stream_type) { 277 case 0: /* H264 */ 278 279 /* reference picture buffer */ 280 min_dpb_size = image_size * 17; 281 282 /* macroblock context buffer */ 283 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 284 285 /* IT surface buffer */ 286 min_dpb_size += width_in_mb * height_in_mb * 32; 287 break; 288 289 case 1: /* VC1 */ 290 291 /* reference picture buffer */ 292 min_dpb_size = image_size * 3; 293 294 /* CONTEXT_BUFFER */ 295 min_dpb_size += width_in_mb * height_in_mb * 128; 296 297 /* IT surface buffer */ 298 min_dpb_size += width_in_mb * 64; 299 300 /* DB surface buffer */ 301 min_dpb_size += width_in_mb * 128; 302 303 /* BP */ 304 tmp = max(width_in_mb, height_in_mb); 305 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 306 break; 307 308 case 3: /* MPEG2 */ 309 310 /* reference picture buffer */ 311 min_dpb_size = image_size * 3; 312 break; 313 314 case 4: /* MPEG4 */ 315 316 /* reference picture buffer */ 317 min_dpb_size = image_size * 3; 318 319 /* CM */ 320 min_dpb_size += width_in_mb * height_in_mb * 64; 321 322 /* IT surface buffer */ 323 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 324 break; 325 326 default: 327 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 328 return -EINVAL; 329 } 330 331 if (width > pitch) { 332 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 333 return -EINVAL; 334 } 335 336 if (dpb_size < min_dpb_size) { 337 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 338 dpb_size, min_dpb_size); 339 return -EINVAL; 340 } 341 342 buf_sizes[0x1] = dpb_size; 343 buf_sizes[0x2] = image_size; 344 return 0; 345 } 346 347 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 348 unsigned offset, unsigned buf_sizes[]) 349 { 350 int32_t *msg, msg_type, handle; 351 unsigned img_size = 0; 352 void *ptr; 353 354 int i, r; 355 356 if (offset & 0x3F) { 357 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 358 return -EINVAL; 359 } 360 361 if (bo->tbo.sync_obj) { 362 r = radeon_fence_wait(bo->tbo.sync_obj, false); 363 if (r) { 364 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 365 return r; 366 } 367 } 368 369 r = radeon_bo_kmap(bo, &ptr); 370 if (r) { 371 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 372 return r; 373 } 374 375 msg = ptr + offset; 376 377 msg_type = msg[1]; 378 handle = msg[2]; 379 380 if (handle == 0) { 381 DRM_ERROR("Invalid UVD handle!\n"); 382 return -EINVAL; 383 } 384 385 if (msg_type == 1) { 386 /* it's a decode msg, calc buffer sizes */ 387 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 388 /* calc image size (width * height) */ 389 img_size = msg[6] * msg[7]; 390 radeon_bo_kunmap(bo); 391 if (r) 392 return r; 393 394 } else if (msg_type == 2) { 395 /* it's a destroy msg, free the handle */ 396 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 397 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 398 radeon_bo_kunmap(bo); 399 return 0; 400 } else { 401 /* it's a create msg, calc image size (width * height) */ 402 img_size = msg[7] * msg[8]; 403 radeon_bo_kunmap(bo); 404 405 if (msg_type != 0) { 406 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 407 return -EINVAL; 408 } 409 410 /* it's a create msg, no special handling needed */ 411 } 412 413 /* create or decode, validate the handle */ 414 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 415 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) 416 return 0; 417 } 418 419 /* handle not found try to alloc a new one */ 420 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 421 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 422 p->rdev->uvd.filp[i] = p->filp; 423 p->rdev->uvd.img_size[i] = img_size; 424 return 0; 425 } 426 } 427 428 DRM_ERROR("No more free UVD handles!\n"); 429 return -EINVAL; 430 } 431 432 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 433 int data0, int data1, 434 unsigned buf_sizes[], bool *has_msg_cmd) 435 { 436 struct radeon_cs_chunk *relocs_chunk; 437 struct radeon_cs_reloc *reloc; 438 unsigned idx, cmd, offset; 439 uint64_t start, end; 440 int r; 441 442 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 443 offset = radeon_get_ib_value(p, data0); 444 idx = radeon_get_ib_value(p, data1); 445 if (idx >= relocs_chunk->length_dw) { 446 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 447 idx, relocs_chunk->length_dw); 448 return -EINVAL; 449 } 450 451 reloc = p->relocs_ptr[(idx / 4)]; 452 start = reloc->lobj.gpu_offset; 453 end = start + radeon_bo_size(reloc->robj); 454 start += offset; 455 456 p->ib.ptr[data0] = start & 0xFFFFFFFF; 457 p->ib.ptr[data1] = start >> 32; 458 459 cmd = radeon_get_ib_value(p, p->idx) >> 1; 460 461 if (cmd < 0x4) { 462 if ((end - start) < buf_sizes[cmd]) { 463 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 464 (unsigned)(end - start), buf_sizes[cmd]); 465 return -EINVAL; 466 } 467 468 } else if (cmd != 0x100) { 469 DRM_ERROR("invalid UVD command %X!\n", cmd); 470 return -EINVAL; 471 } 472 473 if ((start >> 28) != (end >> 28)) { 474 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 475 start, end); 476 return -EINVAL; 477 } 478 479 /* TODO: is this still necessary on NI+ ? */ 480 if ((cmd == 0 || cmd == 0x3) && 481 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 482 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 483 start, end); 484 return -EINVAL; 485 } 486 487 if (cmd == 0) { 488 if (*has_msg_cmd) { 489 DRM_ERROR("More than one message in a UVD-IB!\n"); 490 return -EINVAL; 491 } 492 *has_msg_cmd = true; 493 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 494 if (r) 495 return r; 496 } else if (!*has_msg_cmd) { 497 DRM_ERROR("Message needed before other commands are send!\n"); 498 return -EINVAL; 499 } 500 501 return 0; 502 } 503 504 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 505 struct radeon_cs_packet *pkt, 506 int *data0, int *data1, 507 unsigned buf_sizes[], 508 bool *has_msg_cmd) 509 { 510 int i, r; 511 512 p->idx++; 513 for (i = 0; i <= pkt->count; ++i) { 514 switch (pkt->reg + i*4) { 515 case UVD_GPCOM_VCPU_DATA0: 516 *data0 = p->idx; 517 break; 518 case UVD_GPCOM_VCPU_DATA1: 519 *data1 = p->idx; 520 break; 521 case UVD_GPCOM_VCPU_CMD: 522 r = radeon_uvd_cs_reloc(p, *data0, *data1, 523 buf_sizes, has_msg_cmd); 524 if (r) 525 return r; 526 break; 527 case UVD_ENGINE_CNTL: 528 break; 529 default: 530 DRM_ERROR("Invalid reg 0x%X!\n", 531 pkt->reg + i*4); 532 return -EINVAL; 533 } 534 p->idx++; 535 } 536 return 0; 537 } 538 539 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 540 { 541 struct radeon_cs_packet pkt; 542 int r, data0 = 0, data1 = 0; 543 544 /* does the IB has a msg command */ 545 bool has_msg_cmd = false; 546 547 /* minimum buffer sizes */ 548 unsigned buf_sizes[] = { 549 [0x00000000] = 2048, 550 [0x00000001] = 32 * 1024 * 1024, 551 [0x00000002] = 2048 * 1152 * 3, 552 [0x00000003] = 2048, 553 }; 554 555 if (p->chunks[p->chunk_ib_idx].length_dw % 16) { 556 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 557 p->chunks[p->chunk_ib_idx].length_dw); 558 return -EINVAL; 559 } 560 561 if (p->chunk_relocs_idx == -1) { 562 DRM_ERROR("No relocation chunk !\n"); 563 return -EINVAL; 564 } 565 566 567 do { 568 r = radeon_cs_packet_parse(p, &pkt, p->idx); 569 if (r) 570 return r; 571 switch (pkt.type) { 572 case RADEON_PACKET_TYPE0: 573 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 574 buf_sizes, &has_msg_cmd); 575 if (r) 576 return r; 577 break; 578 case RADEON_PACKET_TYPE2: 579 p->idx += pkt.count + 2; 580 break; 581 default: 582 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 583 return -EINVAL; 584 } 585 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 586 587 if (!has_msg_cmd) { 588 DRM_ERROR("UVD-IBs need a msg command!\n"); 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 595 static int radeon_uvd_send_msg(struct radeon_device *rdev, 596 int ring, struct radeon_bo *bo, 597 struct radeon_fence **fence) 598 { 599 struct ttm_validate_buffer tv; 600 struct ww_acquire_ctx ticket; 601 struct list_head head; 602 struct radeon_ib ib; 603 uint64_t addr; 604 int i, r; 605 606 memset(&tv, 0, sizeof(tv)); 607 tv.bo = &bo->tbo; 608 609 INIT_LIST_HEAD(&head); 610 list_add(&tv.head, &head); 611 612 r = ttm_eu_reserve_buffers(&ticket, &head); 613 if (r) 614 return r; 615 616 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM); 617 radeon_uvd_force_into_uvd_segment(bo); 618 619 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 620 if (r) 621 goto err; 622 623 r = radeon_ib_get(rdev, ring, &ib, NULL, 16); 624 if (r) 625 goto err; 626 627 addr = radeon_bo_gpu_offset(bo); 628 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 629 ib.ptr[1] = addr; 630 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 631 ib.ptr[3] = addr >> 32; 632 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 633 ib.ptr[5] = 0; 634 for (i = 6; i < 16; ++i) 635 ib.ptr[i] = PACKET2(0); 636 ib.length_dw = 16; 637 638 r = radeon_ib_schedule(rdev, &ib, NULL); 639 if (r) 640 goto err; 641 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); 642 643 if (fence) 644 *fence = radeon_fence_ref(ib.fence); 645 646 radeon_ib_free(rdev, &ib); 647 radeon_bo_unref(&bo); 648 return 0; 649 650 err: 651 ttm_eu_backoff_reservation(&ticket, &head); 652 return r; 653 } 654 655 /* multiple fence commands without any stream commands in between can 656 crash the vcpu so just try to emmit a dummy create/destroy msg to 657 avoid this */ 658 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 659 uint32_t handle, struct radeon_fence **fence) 660 { 661 struct radeon_bo *bo; 662 uint32_t *msg; 663 int r, i; 664 665 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 666 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 667 if (r) 668 return r; 669 670 r = radeon_bo_reserve(bo, false); 671 if (r) { 672 radeon_bo_unref(&bo); 673 return r; 674 } 675 676 r = radeon_bo_kmap(bo, (void **)&msg); 677 if (r) { 678 radeon_bo_unreserve(bo); 679 radeon_bo_unref(&bo); 680 return r; 681 } 682 683 /* stitch together an UVD create msg */ 684 msg[0] = cpu_to_le32(0x00000de4); 685 msg[1] = cpu_to_le32(0x00000000); 686 msg[2] = cpu_to_le32(handle); 687 msg[3] = cpu_to_le32(0x00000000); 688 msg[4] = cpu_to_le32(0x00000000); 689 msg[5] = cpu_to_le32(0x00000000); 690 msg[6] = cpu_to_le32(0x00000000); 691 msg[7] = cpu_to_le32(0x00000780); 692 msg[8] = cpu_to_le32(0x00000440); 693 msg[9] = cpu_to_le32(0x00000000); 694 msg[10] = cpu_to_le32(0x01b37000); 695 for (i = 11; i < 1024; ++i) 696 msg[i] = cpu_to_le32(0x0); 697 698 radeon_bo_kunmap(bo); 699 radeon_bo_unreserve(bo); 700 701 return radeon_uvd_send_msg(rdev, ring, bo, fence); 702 } 703 704 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 705 uint32_t handle, struct radeon_fence **fence) 706 { 707 struct radeon_bo *bo; 708 uint32_t *msg; 709 int r, i; 710 711 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 712 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 713 if (r) 714 return r; 715 716 r = radeon_bo_reserve(bo, false); 717 if (r) { 718 radeon_bo_unref(&bo); 719 return r; 720 } 721 722 r = radeon_bo_kmap(bo, (void **)&msg); 723 if (r) { 724 radeon_bo_unreserve(bo); 725 radeon_bo_unref(&bo); 726 return r; 727 } 728 729 /* stitch together an UVD destroy msg */ 730 msg[0] = cpu_to_le32(0x00000de4); 731 msg[1] = cpu_to_le32(0x00000002); 732 msg[2] = cpu_to_le32(handle); 733 msg[3] = cpu_to_le32(0x00000000); 734 for (i = 4; i < 1024; ++i) 735 msg[i] = cpu_to_le32(0x0); 736 737 radeon_bo_kunmap(bo); 738 radeon_bo_unreserve(bo); 739 740 return radeon_uvd_send_msg(rdev, ring, bo, fence); 741 } 742 743 /** 744 * radeon_uvd_count_handles - count number of open streams 745 * 746 * @rdev: radeon_device pointer 747 * @sd: number of SD streams 748 * @hd: number of HD streams 749 * 750 * Count the number of open SD/HD streams as a hint for power mangement 751 */ 752 static void radeon_uvd_count_handles(struct radeon_device *rdev, 753 unsigned *sd, unsigned *hd) 754 { 755 unsigned i; 756 757 *sd = 0; 758 *hd = 0; 759 760 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 761 if (!atomic_read(&rdev->uvd.handles[i])) 762 continue; 763 764 if (rdev->uvd.img_size[i] >= 720*576) 765 ++(*hd); 766 else 767 ++(*sd); 768 } 769 } 770 771 static void radeon_uvd_idle_work_handler(struct work_struct *work) 772 { 773 struct radeon_device *rdev = 774 container_of(work, struct radeon_device, uvd.idle_work.work); 775 776 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 777 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 778 radeon_dpm_enable_uvd(rdev, false); 779 } else { 780 radeon_set_uvd_clocks(rdev, 0, 0); 781 } 782 } else { 783 schedule_delayed_work(&rdev->uvd.idle_work, 784 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 785 } 786 } 787 788 void radeon_uvd_note_usage(struct radeon_device *rdev) 789 { 790 bool streams_changed = false; 791 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 792 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 793 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 794 795 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 796 unsigned hd = 0, sd = 0; 797 radeon_uvd_count_handles(rdev, &sd, &hd); 798 if ((rdev->pm.dpm.sd != sd) || 799 (rdev->pm.dpm.hd != hd)) { 800 rdev->pm.dpm.sd = sd; 801 rdev->pm.dpm.hd = hd; 802 /* disable this for now */ 803 /*streams_changed = true;*/ 804 } 805 } 806 807 if (set_clocks || streams_changed) { 808 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 809 radeon_dpm_enable_uvd(rdev, true); 810 } else { 811 radeon_set_uvd_clocks(rdev, 53300, 40000); 812 } 813 } 814 } 815 816 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 817 unsigned target_freq, 818 unsigned pd_min, 819 unsigned pd_even) 820 { 821 unsigned post_div = vco_freq / target_freq; 822 823 /* adjust to post divider minimum value */ 824 if (post_div < pd_min) 825 post_div = pd_min; 826 827 /* we alway need a frequency less than or equal the target */ 828 if ((vco_freq / post_div) > target_freq) 829 post_div += 1; 830 831 /* post dividers above a certain value must be even */ 832 if (post_div > pd_even && post_div % 2) 833 post_div += 1; 834 835 return post_div; 836 } 837 838 /** 839 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 840 * 841 * @rdev: radeon_device pointer 842 * @vclk: wanted VCLK 843 * @dclk: wanted DCLK 844 * @vco_min: minimum VCO frequency 845 * @vco_max: maximum VCO frequency 846 * @fb_factor: factor to multiply vco freq with 847 * @fb_mask: limit and bitmask for feedback divider 848 * @pd_min: post divider minimum 849 * @pd_max: post divider maximum 850 * @pd_even: post divider must be even above this value 851 * @optimal_fb_div: resulting feedback divider 852 * @optimal_vclk_div: resulting vclk post divider 853 * @optimal_dclk_div: resulting dclk post divider 854 * 855 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 856 * Returns zero on success -EINVAL on error. 857 */ 858 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 859 unsigned vclk, unsigned dclk, 860 unsigned vco_min, unsigned vco_max, 861 unsigned fb_factor, unsigned fb_mask, 862 unsigned pd_min, unsigned pd_max, 863 unsigned pd_even, 864 unsigned *optimal_fb_div, 865 unsigned *optimal_vclk_div, 866 unsigned *optimal_dclk_div) 867 { 868 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 869 870 /* start off with something large */ 871 unsigned optimal_score = ~0; 872 873 /* loop through vco from low to high */ 874 vco_min = max(max(vco_min, vclk), dclk); 875 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 876 877 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 878 unsigned vclk_div, dclk_div, score; 879 880 do_div(fb_div, ref_freq); 881 882 /* fb div out of range ? */ 883 if (fb_div > fb_mask) 884 break; /* it can oly get worse */ 885 886 fb_div &= fb_mask; 887 888 /* calc vclk divider with current vco freq */ 889 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 890 pd_min, pd_even); 891 if (vclk_div > pd_max) 892 break; /* vco is too big, it has to stop */ 893 894 /* calc dclk divider with current vco freq */ 895 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 896 pd_min, pd_even); 897 if (vclk_div > pd_max) 898 break; /* vco is too big, it has to stop */ 899 900 /* calc score with current vco freq */ 901 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 902 903 /* determine if this vco setting is better than current optimal settings */ 904 if (score < optimal_score) { 905 *optimal_fb_div = fb_div; 906 *optimal_vclk_div = vclk_div; 907 *optimal_dclk_div = dclk_div; 908 optimal_score = score; 909 if (optimal_score == 0) 910 break; /* it can't get better than this */ 911 } 912 } 913 914 /* did we found a valid setup ? */ 915 if (optimal_score == ~0) 916 return -EINVAL; 917 918 return 0; 919 } 920 921 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 922 unsigned cg_upll_func_cntl) 923 { 924 unsigned i; 925 926 /* make sure UPLL_CTLREQ is deasserted */ 927 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 928 929 mdelay(10); 930 931 /* assert UPLL_CTLREQ */ 932 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 933 934 /* wait for CTLACK and CTLACK2 to get asserted */ 935 for (i = 0; i < 100; ++i) { 936 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 937 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 938 break; 939 mdelay(10); 940 } 941 942 /* deassert UPLL_CTLREQ */ 943 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 944 945 if (i == 100) { 946 DRM_ERROR("Timeout setting UVD clocks!\n"); 947 return -ETIMEDOUT; 948 } 949 950 return 0; 951 } 952