1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "radeon.h" 37 #include "r600d.h" 38 39 /* 1 second timeout */ 40 #define UVD_IDLE_TIMEOUT_MS 1000 41 42 /* Firmware Names */ 43 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 44 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 45 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 46 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 47 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" 48 49 MODULE_FIRMWARE(FIRMWARE_RV710); 50 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 51 MODULE_FIRMWARE(FIRMWARE_SUMO); 52 MODULE_FIRMWARE(FIRMWARE_TAHITI); 53 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 54 55 static void radeon_uvd_idle_work_handler(struct work_struct *work); 56 57 int radeon_uvd_init(struct radeon_device *rdev) 58 { 59 unsigned long bo_size; 60 const char *fw_name; 61 int i, r; 62 63 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 64 65 switch (rdev->family) { 66 case CHIP_RV710: 67 case CHIP_RV730: 68 case CHIP_RV740: 69 fw_name = FIRMWARE_RV710; 70 break; 71 72 case CHIP_CYPRESS: 73 case CHIP_HEMLOCK: 74 case CHIP_JUNIPER: 75 case CHIP_REDWOOD: 76 case CHIP_CEDAR: 77 fw_name = FIRMWARE_CYPRESS; 78 break; 79 80 case CHIP_SUMO: 81 case CHIP_SUMO2: 82 case CHIP_PALM: 83 case CHIP_CAYMAN: 84 case CHIP_BARTS: 85 case CHIP_TURKS: 86 case CHIP_CAICOS: 87 fw_name = FIRMWARE_SUMO; 88 break; 89 90 case CHIP_TAHITI: 91 case CHIP_VERDE: 92 case CHIP_PITCAIRN: 93 case CHIP_ARUBA: 94 fw_name = FIRMWARE_TAHITI; 95 break; 96 97 case CHIP_BONAIRE: 98 case CHIP_KABINI: 99 case CHIP_KAVERI: 100 fw_name = FIRMWARE_BONAIRE; 101 break; 102 103 default: 104 return -EINVAL; 105 } 106 107 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 108 if (r) { 109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 110 fw_name); 111 return r; 112 } 113 114 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 115 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE; 116 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 117 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo); 118 if (r) { 119 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 120 return r; 121 } 122 123 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 124 if (r) { 125 radeon_bo_unref(&rdev->uvd.vcpu_bo); 126 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 127 return r; 128 } 129 130 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 131 &rdev->uvd.gpu_addr); 132 if (r) { 133 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 134 radeon_bo_unref(&rdev->uvd.vcpu_bo); 135 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 136 return r; 137 } 138 139 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 140 if (r) { 141 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 142 return r; 143 } 144 145 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 146 147 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 148 atomic_set(&rdev->uvd.handles[i], 0); 149 rdev->uvd.filp[i] = NULL; 150 } 151 152 return 0; 153 } 154 155 void radeon_uvd_fini(struct radeon_device *rdev) 156 { 157 int r; 158 159 if (rdev->uvd.vcpu_bo == NULL) 160 return; 161 162 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 163 if (!r) { 164 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 165 radeon_bo_unpin(rdev->uvd.vcpu_bo); 166 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 167 } 168 169 radeon_bo_unref(&rdev->uvd.vcpu_bo); 170 171 release_firmware(rdev->uvd_fw); 172 } 173 174 int radeon_uvd_suspend(struct radeon_device *rdev) 175 { 176 unsigned size; 177 void *ptr; 178 int i; 179 180 if (rdev->uvd.vcpu_bo == NULL) 181 return 0; 182 183 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 184 if (atomic_read(&rdev->uvd.handles[i])) 185 break; 186 187 if (i == RADEON_MAX_UVD_HANDLES) 188 return 0; 189 190 size = radeon_bo_size(rdev->uvd.vcpu_bo); 191 size -= rdev->uvd_fw->size; 192 193 ptr = rdev->uvd.cpu_addr; 194 ptr += rdev->uvd_fw->size; 195 196 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 197 memcpy(rdev->uvd.saved_bo, ptr, size); 198 199 return 0; 200 } 201 202 int radeon_uvd_resume(struct radeon_device *rdev) 203 { 204 unsigned size; 205 void *ptr; 206 207 if (rdev->uvd.vcpu_bo == NULL) 208 return -EINVAL; 209 210 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 211 212 size = radeon_bo_size(rdev->uvd.vcpu_bo); 213 size -= rdev->uvd_fw->size; 214 215 ptr = rdev->uvd.cpu_addr; 216 ptr += rdev->uvd_fw->size; 217 218 if (rdev->uvd.saved_bo != NULL) { 219 memcpy(ptr, rdev->uvd.saved_bo, size); 220 kfree(rdev->uvd.saved_bo); 221 rdev->uvd.saved_bo = NULL; 222 } else 223 memset(ptr, 0, size); 224 225 return 0; 226 } 227 228 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo) 229 { 230 rbo->placement.fpfn = 0 >> PAGE_SHIFT; 231 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 232 } 233 234 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 235 { 236 int i, r; 237 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 238 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 239 if (handle != 0 && rdev->uvd.filp[i] == filp) { 240 struct radeon_fence *fence; 241 242 r = radeon_uvd_get_destroy_msg(rdev, 243 R600_RING_TYPE_UVD_INDEX, handle, &fence); 244 if (r) { 245 DRM_ERROR("Error destroying UVD (%d)!\n", r); 246 continue; 247 } 248 249 radeon_fence_wait(fence, false); 250 radeon_fence_unref(&fence); 251 252 rdev->uvd.filp[i] = NULL; 253 atomic_set(&rdev->uvd.handles[i], 0); 254 } 255 } 256 } 257 258 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 259 { 260 unsigned stream_type = msg[4]; 261 unsigned width = msg[6]; 262 unsigned height = msg[7]; 263 unsigned dpb_size = msg[9]; 264 unsigned pitch = msg[28]; 265 266 unsigned width_in_mb = width / 16; 267 unsigned height_in_mb = ALIGN(height / 16, 2); 268 269 unsigned image_size, tmp, min_dpb_size; 270 271 image_size = width * height; 272 image_size += image_size / 2; 273 image_size = ALIGN(image_size, 1024); 274 275 switch (stream_type) { 276 case 0: /* H264 */ 277 278 /* reference picture buffer */ 279 min_dpb_size = image_size * 17; 280 281 /* macroblock context buffer */ 282 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 283 284 /* IT surface buffer */ 285 min_dpb_size += width_in_mb * height_in_mb * 32; 286 break; 287 288 case 1: /* VC1 */ 289 290 /* reference picture buffer */ 291 min_dpb_size = image_size * 3; 292 293 /* CONTEXT_BUFFER */ 294 min_dpb_size += width_in_mb * height_in_mb * 128; 295 296 /* IT surface buffer */ 297 min_dpb_size += width_in_mb * 64; 298 299 /* DB surface buffer */ 300 min_dpb_size += width_in_mb * 128; 301 302 /* BP */ 303 tmp = max(width_in_mb, height_in_mb); 304 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 305 break; 306 307 case 3: /* MPEG2 */ 308 309 /* reference picture buffer */ 310 min_dpb_size = image_size * 3; 311 break; 312 313 case 4: /* MPEG4 */ 314 315 /* reference picture buffer */ 316 min_dpb_size = image_size * 3; 317 318 /* CM */ 319 min_dpb_size += width_in_mb * height_in_mb * 64; 320 321 /* IT surface buffer */ 322 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 323 break; 324 325 default: 326 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 327 return -EINVAL; 328 } 329 330 if (width > pitch) { 331 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 332 return -EINVAL; 333 } 334 335 if (dpb_size < min_dpb_size) { 336 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 337 dpb_size, min_dpb_size); 338 return -EINVAL; 339 } 340 341 buf_sizes[0x1] = dpb_size; 342 buf_sizes[0x2] = image_size; 343 return 0; 344 } 345 346 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 347 unsigned offset, unsigned buf_sizes[]) 348 { 349 int32_t *msg, msg_type, handle; 350 void *ptr; 351 352 int i, r; 353 354 if (offset & 0x3F) { 355 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 356 return -EINVAL; 357 } 358 359 if (bo->tbo.sync_obj) { 360 r = radeon_fence_wait(bo->tbo.sync_obj, false); 361 if (r) { 362 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 363 return r; 364 } 365 } 366 367 r = radeon_bo_kmap(bo, &ptr); 368 if (r) { 369 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 370 return r; 371 } 372 373 msg = ptr + offset; 374 375 msg_type = msg[1]; 376 handle = msg[2]; 377 378 if (handle == 0) { 379 DRM_ERROR("Invalid UVD handle!\n"); 380 return -EINVAL; 381 } 382 383 if (msg_type == 1) { 384 /* it's a decode msg, calc buffer sizes */ 385 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 386 radeon_bo_kunmap(bo); 387 if (r) 388 return r; 389 390 } else if (msg_type == 2) { 391 /* it's a destroy msg, free the handle */ 392 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 393 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 394 radeon_bo_kunmap(bo); 395 return 0; 396 } else { 397 radeon_bo_kunmap(bo); 398 399 if (msg_type != 0) { 400 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 401 return -EINVAL; 402 } 403 404 /* it's a create msg, no special handling needed */ 405 } 406 407 /* create or decode, validate the handle */ 408 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 409 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) 410 return 0; 411 } 412 413 /* handle not found try to alloc a new one */ 414 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 415 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 416 p->rdev->uvd.filp[i] = p->filp; 417 return 0; 418 } 419 } 420 421 DRM_ERROR("No more free UVD handles!\n"); 422 return -EINVAL; 423 } 424 425 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 426 int data0, int data1, 427 unsigned buf_sizes[], bool *has_msg_cmd) 428 { 429 struct radeon_cs_chunk *relocs_chunk; 430 struct radeon_cs_reloc *reloc; 431 unsigned idx, cmd, offset; 432 uint64_t start, end; 433 int r; 434 435 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 436 offset = radeon_get_ib_value(p, data0); 437 idx = radeon_get_ib_value(p, data1); 438 if (idx >= relocs_chunk->length_dw) { 439 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 440 idx, relocs_chunk->length_dw); 441 return -EINVAL; 442 } 443 444 reloc = p->relocs_ptr[(idx / 4)]; 445 start = reloc->lobj.gpu_offset; 446 end = start + radeon_bo_size(reloc->robj); 447 start += offset; 448 449 p->ib.ptr[data0] = start & 0xFFFFFFFF; 450 p->ib.ptr[data1] = start >> 32; 451 452 cmd = radeon_get_ib_value(p, p->idx) >> 1; 453 454 if (cmd < 0x4) { 455 if ((end - start) < buf_sizes[cmd]) { 456 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 457 (unsigned)(end - start), buf_sizes[cmd]); 458 return -EINVAL; 459 } 460 461 } else if (cmd != 0x100) { 462 DRM_ERROR("invalid UVD command %X!\n", cmd); 463 return -EINVAL; 464 } 465 466 if ((start >> 28) != (end >> 28)) { 467 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 468 start, end); 469 return -EINVAL; 470 } 471 472 /* TODO: is this still necessary on NI+ ? */ 473 if ((cmd == 0 || cmd == 0x3) && 474 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 475 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 476 start, end); 477 return -EINVAL; 478 } 479 480 if (cmd == 0) { 481 if (*has_msg_cmd) { 482 DRM_ERROR("More than one message in a UVD-IB!\n"); 483 return -EINVAL; 484 } 485 *has_msg_cmd = true; 486 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 487 if (r) 488 return r; 489 } else if (!*has_msg_cmd) { 490 DRM_ERROR("Message needed before other commands are send!\n"); 491 return -EINVAL; 492 } 493 494 return 0; 495 } 496 497 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 498 struct radeon_cs_packet *pkt, 499 int *data0, int *data1, 500 unsigned buf_sizes[], 501 bool *has_msg_cmd) 502 { 503 int i, r; 504 505 p->idx++; 506 for (i = 0; i <= pkt->count; ++i) { 507 switch (pkt->reg + i*4) { 508 case UVD_GPCOM_VCPU_DATA0: 509 *data0 = p->idx; 510 break; 511 case UVD_GPCOM_VCPU_DATA1: 512 *data1 = p->idx; 513 break; 514 case UVD_GPCOM_VCPU_CMD: 515 r = radeon_uvd_cs_reloc(p, *data0, *data1, 516 buf_sizes, has_msg_cmd); 517 if (r) 518 return r; 519 break; 520 case UVD_ENGINE_CNTL: 521 break; 522 default: 523 DRM_ERROR("Invalid reg 0x%X!\n", 524 pkt->reg + i*4); 525 return -EINVAL; 526 } 527 p->idx++; 528 } 529 return 0; 530 } 531 532 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 533 { 534 struct radeon_cs_packet pkt; 535 int r, data0 = 0, data1 = 0; 536 537 /* does the IB has a msg command */ 538 bool has_msg_cmd = false; 539 540 /* minimum buffer sizes */ 541 unsigned buf_sizes[] = { 542 [0x00000000] = 2048, 543 [0x00000001] = 32 * 1024 * 1024, 544 [0x00000002] = 2048 * 1152 * 3, 545 [0x00000003] = 2048, 546 }; 547 548 if (p->chunks[p->chunk_ib_idx].length_dw % 16) { 549 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 550 p->chunks[p->chunk_ib_idx].length_dw); 551 return -EINVAL; 552 } 553 554 if (p->chunk_relocs_idx == -1) { 555 DRM_ERROR("No relocation chunk !\n"); 556 return -EINVAL; 557 } 558 559 560 do { 561 r = radeon_cs_packet_parse(p, &pkt, p->idx); 562 if (r) 563 return r; 564 switch (pkt.type) { 565 case RADEON_PACKET_TYPE0: 566 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 567 buf_sizes, &has_msg_cmd); 568 if (r) 569 return r; 570 break; 571 case RADEON_PACKET_TYPE2: 572 p->idx += pkt.count + 2; 573 break; 574 default: 575 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 576 return -EINVAL; 577 } 578 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 579 580 if (!has_msg_cmd) { 581 DRM_ERROR("UVD-IBs need a msg command!\n"); 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 588 static int radeon_uvd_send_msg(struct radeon_device *rdev, 589 int ring, struct radeon_bo *bo, 590 struct radeon_fence **fence) 591 { 592 struct ttm_validate_buffer tv; 593 struct ww_acquire_ctx ticket; 594 struct list_head head; 595 struct radeon_ib ib; 596 uint64_t addr; 597 int i, r; 598 599 memset(&tv, 0, sizeof(tv)); 600 tv.bo = &bo->tbo; 601 602 INIT_LIST_HEAD(&head); 603 list_add(&tv.head, &head); 604 605 r = ttm_eu_reserve_buffers(&ticket, &head); 606 if (r) 607 return r; 608 609 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM); 610 radeon_uvd_force_into_uvd_segment(bo); 611 612 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 613 if (r) 614 goto err; 615 616 r = radeon_ib_get(rdev, ring, &ib, NULL, 16); 617 if (r) 618 goto err; 619 620 addr = radeon_bo_gpu_offset(bo); 621 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 622 ib.ptr[1] = addr; 623 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 624 ib.ptr[3] = addr >> 32; 625 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 626 ib.ptr[5] = 0; 627 for (i = 6; i < 16; ++i) 628 ib.ptr[i] = PACKET2(0); 629 ib.length_dw = 16; 630 631 r = radeon_ib_schedule(rdev, &ib, NULL); 632 if (r) 633 goto err; 634 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence); 635 636 if (fence) 637 *fence = radeon_fence_ref(ib.fence); 638 639 radeon_ib_free(rdev, &ib); 640 radeon_bo_unref(&bo); 641 return 0; 642 643 err: 644 ttm_eu_backoff_reservation(&ticket, &head); 645 return r; 646 } 647 648 /* multiple fence commands without any stream commands in between can 649 crash the vcpu so just try to emmit a dummy create/destroy msg to 650 avoid this */ 651 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 652 uint32_t handle, struct radeon_fence **fence) 653 { 654 struct radeon_bo *bo; 655 uint32_t *msg; 656 int r, i; 657 658 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 659 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 660 if (r) 661 return r; 662 663 r = radeon_bo_reserve(bo, false); 664 if (r) { 665 radeon_bo_unref(&bo); 666 return r; 667 } 668 669 r = radeon_bo_kmap(bo, (void **)&msg); 670 if (r) { 671 radeon_bo_unreserve(bo); 672 radeon_bo_unref(&bo); 673 return r; 674 } 675 676 /* stitch together an UVD create msg */ 677 msg[0] = cpu_to_le32(0x00000de4); 678 msg[1] = cpu_to_le32(0x00000000); 679 msg[2] = cpu_to_le32(handle); 680 msg[3] = cpu_to_le32(0x00000000); 681 msg[4] = cpu_to_le32(0x00000000); 682 msg[5] = cpu_to_le32(0x00000000); 683 msg[6] = cpu_to_le32(0x00000000); 684 msg[7] = cpu_to_le32(0x00000780); 685 msg[8] = cpu_to_le32(0x00000440); 686 msg[9] = cpu_to_le32(0x00000000); 687 msg[10] = cpu_to_le32(0x01b37000); 688 for (i = 11; i < 1024; ++i) 689 msg[i] = cpu_to_le32(0x0); 690 691 radeon_bo_kunmap(bo); 692 radeon_bo_unreserve(bo); 693 694 return radeon_uvd_send_msg(rdev, ring, bo, fence); 695 } 696 697 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 698 uint32_t handle, struct radeon_fence **fence) 699 { 700 struct radeon_bo *bo; 701 uint32_t *msg; 702 int r, i; 703 704 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 705 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 706 if (r) 707 return r; 708 709 r = radeon_bo_reserve(bo, false); 710 if (r) { 711 radeon_bo_unref(&bo); 712 return r; 713 } 714 715 r = radeon_bo_kmap(bo, (void **)&msg); 716 if (r) { 717 radeon_bo_unreserve(bo); 718 radeon_bo_unref(&bo); 719 return r; 720 } 721 722 /* stitch together an UVD destroy msg */ 723 msg[0] = cpu_to_le32(0x00000de4); 724 msg[1] = cpu_to_le32(0x00000002); 725 msg[2] = cpu_to_le32(handle); 726 msg[3] = cpu_to_le32(0x00000000); 727 for (i = 4; i < 1024; ++i) 728 msg[i] = cpu_to_le32(0x0); 729 730 radeon_bo_kunmap(bo); 731 radeon_bo_unreserve(bo); 732 733 return radeon_uvd_send_msg(rdev, ring, bo, fence); 734 } 735 736 static void radeon_uvd_idle_work_handler(struct work_struct *work) 737 { 738 struct radeon_device *rdev = 739 container_of(work, struct radeon_device, uvd.idle_work.work); 740 741 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 742 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 743 mutex_lock(&rdev->pm.mutex); 744 rdev->pm.dpm.uvd_active = false; 745 mutex_unlock(&rdev->pm.mutex); 746 radeon_pm_compute_clocks(rdev); 747 } else { 748 radeon_set_uvd_clocks(rdev, 0, 0); 749 } 750 } else { 751 schedule_delayed_work(&rdev->uvd.idle_work, 752 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 753 } 754 } 755 756 void radeon_uvd_note_usage(struct radeon_device *rdev) 757 { 758 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 759 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 760 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 761 if (set_clocks) { 762 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 763 /* XXX pick SD/HD/MVC */ 764 radeon_dpm_enable_power_state(rdev, POWER_STATE_TYPE_INTERNAL_UVD); 765 } else { 766 radeon_set_uvd_clocks(rdev, 53300, 40000); 767 } 768 } 769 } 770 771 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 772 unsigned target_freq, 773 unsigned pd_min, 774 unsigned pd_even) 775 { 776 unsigned post_div = vco_freq / target_freq; 777 778 /* adjust to post divider minimum value */ 779 if (post_div < pd_min) 780 post_div = pd_min; 781 782 /* we alway need a frequency less than or equal the target */ 783 if ((vco_freq / post_div) > target_freq) 784 post_div += 1; 785 786 /* post dividers above a certain value must be even */ 787 if (post_div > pd_even && post_div % 2) 788 post_div += 1; 789 790 return post_div; 791 } 792 793 /** 794 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 795 * 796 * @rdev: radeon_device pointer 797 * @vclk: wanted VCLK 798 * @dclk: wanted DCLK 799 * @vco_min: minimum VCO frequency 800 * @vco_max: maximum VCO frequency 801 * @fb_factor: factor to multiply vco freq with 802 * @fb_mask: limit and bitmask for feedback divider 803 * @pd_min: post divider minimum 804 * @pd_max: post divider maximum 805 * @pd_even: post divider must be even above this value 806 * @optimal_fb_div: resulting feedback divider 807 * @optimal_vclk_div: resulting vclk post divider 808 * @optimal_dclk_div: resulting dclk post divider 809 * 810 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 811 * Returns zero on success -EINVAL on error. 812 */ 813 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 814 unsigned vclk, unsigned dclk, 815 unsigned vco_min, unsigned vco_max, 816 unsigned fb_factor, unsigned fb_mask, 817 unsigned pd_min, unsigned pd_max, 818 unsigned pd_even, 819 unsigned *optimal_fb_div, 820 unsigned *optimal_vclk_div, 821 unsigned *optimal_dclk_div) 822 { 823 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 824 825 /* start off with something large */ 826 unsigned optimal_score = ~0; 827 828 /* loop through vco from low to high */ 829 vco_min = max(max(vco_min, vclk), dclk); 830 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 831 832 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 833 unsigned vclk_div, dclk_div, score; 834 835 do_div(fb_div, ref_freq); 836 837 /* fb div out of range ? */ 838 if (fb_div > fb_mask) 839 break; /* it can oly get worse */ 840 841 fb_div &= fb_mask; 842 843 /* calc vclk divider with current vco freq */ 844 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 845 pd_min, pd_even); 846 if (vclk_div > pd_max) 847 break; /* vco is too big, it has to stop */ 848 849 /* calc dclk divider with current vco freq */ 850 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 851 pd_min, pd_even); 852 if (vclk_div > pd_max) 853 break; /* vco is too big, it has to stop */ 854 855 /* calc score with current vco freq */ 856 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 857 858 /* determine if this vco setting is better than current optimal settings */ 859 if (score < optimal_score) { 860 *optimal_fb_div = fb_div; 861 *optimal_vclk_div = vclk_div; 862 *optimal_dclk_div = dclk_div; 863 optimal_score = score; 864 if (optimal_score == 0) 865 break; /* it can't get better than this */ 866 } 867 } 868 869 /* did we found a valid setup ? */ 870 if (optimal_score == ~0) 871 return -EINVAL; 872 873 return 0; 874 } 875 876 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 877 unsigned cg_upll_func_cntl) 878 { 879 unsigned i; 880 881 /* make sure UPLL_CTLREQ is deasserted */ 882 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 883 884 mdelay(10); 885 886 /* assert UPLL_CTLREQ */ 887 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 888 889 /* wait for CTLACK and CTLACK2 to get asserted */ 890 for (i = 0; i < 100; ++i) { 891 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 892 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 893 break; 894 mdelay(10); 895 } 896 897 /* deassert UPLL_CTLREQ */ 898 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 899 900 if (i == 100) { 901 DRM_ERROR("Timeout setting UVD clocks!\n"); 902 return -ETIMEDOUT; 903 } 904 905 return 0; 906 } 907