1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Christian König <deathsimple@vodafone.de> 29 */ 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <drm/drmP.h> 34 #include <drm/drm.h> 35 36 #include "radeon.h" 37 #include "r600d.h" 38 39 /* 1 second timeout */ 40 #define UVD_IDLE_TIMEOUT_MS 1000 41 42 /* Firmware Names */ 43 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 44 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 45 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 46 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 47 48 MODULE_FIRMWARE(FIRMWARE_RV710); 49 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 50 MODULE_FIRMWARE(FIRMWARE_SUMO); 51 MODULE_FIRMWARE(FIRMWARE_TAHITI); 52 53 static void radeon_uvd_idle_work_handler(struct work_struct *work); 54 55 int radeon_uvd_init(struct radeon_device *rdev) 56 { 57 struct platform_device *pdev; 58 unsigned long bo_size; 59 const char *fw_name; 60 int i, r; 61 62 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 63 64 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0); 65 r = IS_ERR(pdev); 66 if (r) { 67 dev_err(rdev->dev, "radeon_uvd: Failed to register firmware\n"); 68 return -EINVAL; 69 } 70 71 switch (rdev->family) { 72 case CHIP_RV710: 73 case CHIP_RV730: 74 case CHIP_RV740: 75 fw_name = FIRMWARE_RV710; 76 break; 77 78 case CHIP_CYPRESS: 79 case CHIP_HEMLOCK: 80 case CHIP_JUNIPER: 81 case CHIP_REDWOOD: 82 case CHIP_CEDAR: 83 fw_name = FIRMWARE_CYPRESS; 84 break; 85 86 case CHIP_SUMO: 87 case CHIP_SUMO2: 88 case CHIP_PALM: 89 case CHIP_CAYMAN: 90 case CHIP_BARTS: 91 case CHIP_TURKS: 92 case CHIP_CAICOS: 93 fw_name = FIRMWARE_SUMO; 94 break; 95 96 case CHIP_TAHITI: 97 case CHIP_VERDE: 98 case CHIP_PITCAIRN: 99 case CHIP_ARUBA: 100 fw_name = FIRMWARE_TAHITI; 101 break; 102 103 default: 104 return -EINVAL; 105 } 106 107 r = request_firmware(&rdev->uvd_fw, fw_name, &pdev->dev); 108 if (r) { 109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 110 fw_name); 111 platform_device_unregister(pdev); 112 return r; 113 } 114 115 platform_device_unregister(pdev); 116 117 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 118 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE; 119 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 120 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo); 121 if (r) { 122 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 123 return r; 124 } 125 126 r = radeon_uvd_resume(rdev); 127 if (r) 128 return r; 129 130 memset(rdev->uvd.cpu_addr, 0, bo_size); 131 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 132 133 r = radeon_uvd_suspend(rdev); 134 if (r) 135 return r; 136 137 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 138 atomic_set(&rdev->uvd.handles[i], 0); 139 rdev->uvd.filp[i] = NULL; 140 } 141 142 return 0; 143 } 144 145 void radeon_uvd_fini(struct radeon_device *rdev) 146 { 147 radeon_uvd_suspend(rdev); 148 radeon_bo_unref(&rdev->uvd.vcpu_bo); 149 } 150 151 int radeon_uvd_suspend(struct radeon_device *rdev) 152 { 153 int r; 154 155 if (rdev->uvd.vcpu_bo == NULL) 156 return 0; 157 158 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 159 if (!r) { 160 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 161 radeon_bo_unpin(rdev->uvd.vcpu_bo); 162 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 163 } 164 return r; 165 } 166 167 int radeon_uvd_resume(struct radeon_device *rdev) 168 { 169 int r; 170 171 if (rdev->uvd.vcpu_bo == NULL) 172 return -EINVAL; 173 174 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 175 if (r) { 176 radeon_bo_unref(&rdev->uvd.vcpu_bo); 177 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 178 return r; 179 } 180 181 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 182 &rdev->uvd.gpu_addr); 183 if (r) { 184 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 185 radeon_bo_unref(&rdev->uvd.vcpu_bo); 186 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 187 return r; 188 } 189 190 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 191 if (r) { 192 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 193 return r; 194 } 195 196 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 197 198 return 0; 199 } 200 201 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo) 202 { 203 rbo->placement.fpfn = 0 >> PAGE_SHIFT; 204 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 205 } 206 207 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 208 { 209 int i, r; 210 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 211 if (rdev->uvd.filp[i] == filp) { 212 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 213 struct radeon_fence *fence; 214 215 r = radeon_uvd_get_destroy_msg(rdev, 216 R600_RING_TYPE_UVD_INDEX, handle, &fence); 217 if (r) { 218 DRM_ERROR("Error destroying UVD (%d)!\n", r); 219 continue; 220 } 221 222 radeon_fence_wait(fence, false); 223 radeon_fence_unref(&fence); 224 225 rdev->uvd.filp[i] = NULL; 226 atomic_set(&rdev->uvd.handles[i], 0); 227 } 228 } 229 } 230 231 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 232 { 233 unsigned stream_type = msg[4]; 234 unsigned width = msg[6]; 235 unsigned height = msg[7]; 236 unsigned dpb_size = msg[9]; 237 unsigned pitch = msg[28]; 238 239 unsigned width_in_mb = width / 16; 240 unsigned height_in_mb = ALIGN(height / 16, 2); 241 242 unsigned image_size, tmp, min_dpb_size; 243 244 image_size = width * height; 245 image_size += image_size / 2; 246 image_size = ALIGN(image_size, 1024); 247 248 switch (stream_type) { 249 case 0: /* H264 */ 250 251 /* reference picture buffer */ 252 min_dpb_size = image_size * 17; 253 254 /* macroblock context buffer */ 255 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 256 257 /* IT surface buffer */ 258 min_dpb_size += width_in_mb * height_in_mb * 32; 259 break; 260 261 case 1: /* VC1 */ 262 263 /* reference picture buffer */ 264 min_dpb_size = image_size * 3; 265 266 /* CONTEXT_BUFFER */ 267 min_dpb_size += width_in_mb * height_in_mb * 128; 268 269 /* IT surface buffer */ 270 min_dpb_size += width_in_mb * 64; 271 272 /* DB surface buffer */ 273 min_dpb_size += width_in_mb * 128; 274 275 /* BP */ 276 tmp = max(width_in_mb, height_in_mb); 277 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 278 break; 279 280 case 3: /* MPEG2 */ 281 282 /* reference picture buffer */ 283 min_dpb_size = image_size * 3; 284 break; 285 286 case 4: /* MPEG4 */ 287 288 /* reference picture buffer */ 289 min_dpb_size = image_size * 3; 290 291 /* CM */ 292 min_dpb_size += width_in_mb * height_in_mb * 64; 293 294 /* IT surface buffer */ 295 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 296 break; 297 298 default: 299 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 300 return -EINVAL; 301 } 302 303 if (width > pitch) { 304 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 305 return -EINVAL; 306 } 307 308 if (dpb_size < min_dpb_size) { 309 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 310 dpb_size, min_dpb_size); 311 return -EINVAL; 312 } 313 314 buf_sizes[0x1] = dpb_size; 315 buf_sizes[0x2] = image_size; 316 return 0; 317 } 318 319 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 320 unsigned offset, unsigned buf_sizes[]) 321 { 322 int32_t *msg, msg_type, handle; 323 void *ptr; 324 325 int i, r; 326 327 if (offset & 0x3F) { 328 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 329 return -EINVAL; 330 } 331 332 r = radeon_bo_kmap(bo, &ptr); 333 if (r) 334 return r; 335 336 msg = ptr + offset; 337 338 msg_type = msg[1]; 339 handle = msg[2]; 340 341 if (handle == 0) { 342 DRM_ERROR("Invalid UVD handle!\n"); 343 return -EINVAL; 344 } 345 346 if (msg_type == 1) { 347 /* it's a decode msg, calc buffer sizes */ 348 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 349 radeon_bo_kunmap(bo); 350 if (r) 351 return r; 352 353 } else if (msg_type == 2) { 354 /* it's a destroy msg, free the handle */ 355 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 356 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 357 radeon_bo_kunmap(bo); 358 return 0; 359 } else { 360 /* it's a create msg, no special handling needed */ 361 radeon_bo_kunmap(bo); 362 } 363 364 /* create or decode, validate the handle */ 365 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 366 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) 367 return 0; 368 } 369 370 /* handle not found try to alloc a new one */ 371 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 372 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 373 p->rdev->uvd.filp[i] = p->filp; 374 return 0; 375 } 376 } 377 378 DRM_ERROR("No more free UVD handles!\n"); 379 return -EINVAL; 380 } 381 382 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 383 int data0, int data1, 384 unsigned buf_sizes[]) 385 { 386 struct radeon_cs_chunk *relocs_chunk; 387 struct radeon_cs_reloc *reloc; 388 unsigned idx, cmd, offset; 389 uint64_t start, end; 390 int r; 391 392 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 393 offset = radeon_get_ib_value(p, data0); 394 idx = radeon_get_ib_value(p, data1); 395 if (idx >= relocs_chunk->length_dw) { 396 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 397 idx, relocs_chunk->length_dw); 398 return -EINVAL; 399 } 400 401 reloc = p->relocs_ptr[(idx / 4)]; 402 start = reloc->lobj.gpu_offset; 403 end = start + radeon_bo_size(reloc->robj); 404 start += offset; 405 406 p->ib.ptr[data0] = start & 0xFFFFFFFF; 407 p->ib.ptr[data1] = start >> 32; 408 409 cmd = radeon_get_ib_value(p, p->idx) >> 1; 410 411 if (cmd < 0x4) { 412 if ((end - start) < buf_sizes[cmd]) { 413 DRM_ERROR("buffer to small (%d / %d)!\n", 414 (unsigned)(end - start), buf_sizes[cmd]); 415 return -EINVAL; 416 } 417 418 } else if (cmd != 0x100) { 419 DRM_ERROR("invalid UVD command %X!\n", cmd); 420 return -EINVAL; 421 } 422 423 if ((start >> 28) != (end >> 28)) { 424 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 425 start, end); 426 return -EINVAL; 427 } 428 429 /* TODO: is this still necessary on NI+ ? */ 430 if ((cmd == 0 || cmd == 0x3) && 431 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 432 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 433 start, end); 434 return -EINVAL; 435 } 436 437 if (cmd == 0) { 438 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 439 if (r) 440 return r; 441 } 442 443 return 0; 444 } 445 446 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 447 struct radeon_cs_packet *pkt, 448 int *data0, int *data1, 449 unsigned buf_sizes[]) 450 { 451 int i, r; 452 453 p->idx++; 454 for (i = 0; i <= pkt->count; ++i) { 455 switch (pkt->reg + i*4) { 456 case UVD_GPCOM_VCPU_DATA0: 457 *data0 = p->idx; 458 break; 459 case UVD_GPCOM_VCPU_DATA1: 460 *data1 = p->idx; 461 break; 462 case UVD_GPCOM_VCPU_CMD: 463 r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes); 464 if (r) 465 return r; 466 break; 467 case UVD_ENGINE_CNTL: 468 break; 469 default: 470 DRM_ERROR("Invalid reg 0x%X!\n", 471 pkt->reg + i*4); 472 return -EINVAL; 473 } 474 p->idx++; 475 } 476 return 0; 477 } 478 479 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 480 { 481 struct radeon_cs_packet pkt; 482 int r, data0 = 0, data1 = 0; 483 484 /* minimum buffer sizes */ 485 unsigned buf_sizes[] = { 486 [0x00000000] = 2048, 487 [0x00000001] = 32 * 1024 * 1024, 488 [0x00000002] = 2048 * 1152 * 3, 489 [0x00000003] = 2048, 490 }; 491 492 if (p->chunks[p->chunk_ib_idx].length_dw % 16) { 493 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 494 p->chunks[p->chunk_ib_idx].length_dw); 495 return -EINVAL; 496 } 497 498 if (p->chunk_relocs_idx == -1) { 499 DRM_ERROR("No relocation chunk !\n"); 500 return -EINVAL; 501 } 502 503 504 do { 505 r = radeon_cs_packet_parse(p, &pkt, p->idx); 506 if (r) 507 return r; 508 switch (pkt.type) { 509 case RADEON_PACKET_TYPE0: 510 r = radeon_uvd_cs_reg(p, &pkt, &data0, 511 &data1, buf_sizes); 512 if (r) 513 return r; 514 break; 515 case RADEON_PACKET_TYPE2: 516 p->idx += pkt.count + 2; 517 break; 518 default: 519 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 520 return -EINVAL; 521 } 522 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 523 return 0; 524 } 525 526 static int radeon_uvd_send_msg(struct radeon_device *rdev, 527 int ring, struct radeon_bo *bo, 528 struct radeon_fence **fence) 529 { 530 struct ttm_validate_buffer tv; 531 struct list_head head; 532 struct radeon_ib ib; 533 uint64_t addr; 534 int i, r; 535 536 memset(&tv, 0, sizeof(tv)); 537 tv.bo = &bo->tbo; 538 539 INIT_LIST_HEAD(&head); 540 list_add(&tv.head, &head); 541 542 r = ttm_eu_reserve_buffers(&head); 543 if (r) 544 return r; 545 546 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM); 547 radeon_uvd_force_into_uvd_segment(bo); 548 549 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 550 if (r) { 551 ttm_eu_backoff_reservation(&head); 552 return r; 553 } 554 555 r = radeon_ib_get(rdev, ring, &ib, NULL, 16); 556 if (r) { 557 ttm_eu_backoff_reservation(&head); 558 return r; 559 } 560 561 addr = radeon_bo_gpu_offset(bo); 562 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 563 ib.ptr[1] = addr; 564 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 565 ib.ptr[3] = addr >> 32; 566 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 567 ib.ptr[5] = 0; 568 for (i = 6; i < 16; ++i) 569 ib.ptr[i] = PACKET2(0); 570 ib.length_dw = 16; 571 572 r = radeon_ib_schedule(rdev, &ib, NULL); 573 if (r) { 574 ttm_eu_backoff_reservation(&head); 575 return r; 576 } 577 ttm_eu_fence_buffer_objects(&head, ib.fence); 578 579 if (fence) 580 *fence = radeon_fence_ref(ib.fence); 581 582 radeon_ib_free(rdev, &ib); 583 radeon_bo_unref(&bo); 584 return 0; 585 } 586 587 /* multiple fence commands without any stream commands in between can 588 crash the vcpu so just try to emmit a dummy create/destroy msg to 589 avoid this */ 590 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 591 uint32_t handle, struct radeon_fence **fence) 592 { 593 struct radeon_bo *bo; 594 uint32_t *msg; 595 int r, i; 596 597 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 598 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 599 if (r) 600 return r; 601 602 r = radeon_bo_reserve(bo, false); 603 if (r) { 604 radeon_bo_unref(&bo); 605 return r; 606 } 607 608 r = radeon_bo_kmap(bo, (void **)&msg); 609 if (r) { 610 radeon_bo_unreserve(bo); 611 radeon_bo_unref(&bo); 612 return r; 613 } 614 615 /* stitch together an UVD create msg */ 616 msg[0] = 0x00000de4; 617 msg[1] = 0x00000000; 618 msg[2] = handle; 619 msg[3] = 0x00000000; 620 msg[4] = 0x00000000; 621 msg[5] = 0x00000000; 622 msg[6] = 0x00000000; 623 msg[7] = 0x00000780; 624 msg[8] = 0x00000440; 625 msg[9] = 0x00000000; 626 msg[10] = 0x01b37000; 627 for (i = 11; i < 1024; ++i) 628 msg[i] = 0x0; 629 630 radeon_bo_kunmap(bo); 631 radeon_bo_unreserve(bo); 632 633 return radeon_uvd_send_msg(rdev, ring, bo, fence); 634 } 635 636 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 637 uint32_t handle, struct radeon_fence **fence) 638 { 639 struct radeon_bo *bo; 640 uint32_t *msg; 641 int r, i; 642 643 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true, 644 RADEON_GEM_DOMAIN_VRAM, NULL, &bo); 645 if (r) 646 return r; 647 648 r = radeon_bo_reserve(bo, false); 649 if (r) { 650 radeon_bo_unref(&bo); 651 return r; 652 } 653 654 r = radeon_bo_kmap(bo, (void **)&msg); 655 if (r) { 656 radeon_bo_unreserve(bo); 657 radeon_bo_unref(&bo); 658 return r; 659 } 660 661 /* stitch together an UVD destroy msg */ 662 msg[0] = 0x00000de4; 663 msg[1] = 0x00000002; 664 msg[2] = handle; 665 msg[3] = 0x00000000; 666 for (i = 4; i < 1024; ++i) 667 msg[i] = 0x0; 668 669 radeon_bo_kunmap(bo); 670 radeon_bo_unreserve(bo); 671 672 return radeon_uvd_send_msg(rdev, ring, bo, fence); 673 } 674 675 static void radeon_uvd_idle_work_handler(struct work_struct *work) 676 { 677 struct radeon_device *rdev = 678 container_of(work, struct radeon_device, uvd.idle_work.work); 679 680 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) 681 radeon_set_uvd_clocks(rdev, 0, 0); 682 else 683 schedule_delayed_work(&rdev->uvd.idle_work, 684 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 685 } 686 687 void radeon_uvd_note_usage(struct radeon_device *rdev) 688 { 689 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 690 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 691 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 692 if (set_clocks) 693 radeon_set_uvd_clocks(rdev, 53300, 40000); 694 } 695 696 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 697 unsigned target_freq, 698 unsigned pd_min, 699 unsigned pd_even) 700 { 701 unsigned post_div = vco_freq / target_freq; 702 703 /* adjust to post divider minimum value */ 704 if (post_div < pd_min) 705 post_div = pd_min; 706 707 /* we alway need a frequency less than or equal the target */ 708 if ((vco_freq / post_div) > target_freq) 709 post_div += 1; 710 711 /* post dividers above a certain value must be even */ 712 if (post_div > pd_even && post_div % 2) 713 post_div += 1; 714 715 return post_div; 716 } 717 718 /** 719 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 720 * 721 * @rdev: radeon_device pointer 722 * @vclk: wanted VCLK 723 * @dclk: wanted DCLK 724 * @vco_min: minimum VCO frequency 725 * @vco_max: maximum VCO frequency 726 * @fb_factor: factor to multiply vco freq with 727 * @fb_mask: limit and bitmask for feedback divider 728 * @pd_min: post divider minimum 729 * @pd_max: post divider maximum 730 * @pd_even: post divider must be even above this value 731 * @optimal_fb_div: resulting feedback divider 732 * @optimal_vclk_div: resulting vclk post divider 733 * @optimal_dclk_div: resulting dclk post divider 734 * 735 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 736 * Returns zero on success -EINVAL on error. 737 */ 738 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 739 unsigned vclk, unsigned dclk, 740 unsigned vco_min, unsigned vco_max, 741 unsigned fb_factor, unsigned fb_mask, 742 unsigned pd_min, unsigned pd_max, 743 unsigned pd_even, 744 unsigned *optimal_fb_div, 745 unsigned *optimal_vclk_div, 746 unsigned *optimal_dclk_div) 747 { 748 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 749 750 /* start off with something large */ 751 unsigned optimal_score = ~0; 752 753 /* loop through vco from low to high */ 754 vco_min = max(max(vco_min, vclk), dclk); 755 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 756 757 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 758 unsigned vclk_div, dclk_div, score; 759 760 do_div(fb_div, ref_freq); 761 762 /* fb div out of range ? */ 763 if (fb_div > fb_mask) 764 break; /* it can oly get worse */ 765 766 fb_div &= fb_mask; 767 768 /* calc vclk divider with current vco freq */ 769 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 770 pd_min, pd_even); 771 if (vclk_div > pd_max) 772 break; /* vco is too big, it has to stop */ 773 774 /* calc dclk divider with current vco freq */ 775 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 776 pd_min, pd_even); 777 if (vclk_div > pd_max) 778 break; /* vco is too big, it has to stop */ 779 780 /* calc score with current vco freq */ 781 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 782 783 /* determine if this vco setting is better than current optimal settings */ 784 if (score < optimal_score) { 785 *optimal_fb_div = fb_div; 786 *optimal_vclk_div = vclk_div; 787 *optimal_dclk_div = dclk_div; 788 optimal_score = score; 789 if (optimal_score == 0) 790 break; /* it can't get better than this */ 791 } 792 } 793 794 /* did we found a valid setup ? */ 795 if (optimal_score == ~0) 796 return -EINVAL; 797 798 return 0; 799 } 800 801 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 802 unsigned cg_upll_func_cntl) 803 { 804 unsigned i; 805 806 /* make sure UPLL_CTLREQ is deasserted */ 807 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 808 809 mdelay(10); 810 811 /* assert UPLL_CTLREQ */ 812 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 813 814 /* wait for CTLACK and CTLACK2 to get asserted */ 815 for (i = 0; i < 100; ++i) { 816 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 817 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 818 break; 819 mdelay(10); 820 } 821 822 /* deassert UPLL_CTLREQ */ 823 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 824 825 if (i == 100) { 826 DRM_ERROR("Timeout setting UVD clocks!\n"); 827 return -ETIMEDOUT; 828 } 829 830 return 0; 831 } 832