1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <ttm/ttm_bo_api.h> 33 #include <ttm/ttm_bo_driver.h> 34 #include <ttm/ttm_placement.h> 35 #include <ttm/ttm_module.h> 36 #include <ttm/ttm_page_alloc.h> 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swiotlb.h> 42 #include "radeon_reg.h" 43 #include "radeon.h" 44 45 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 46 47 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 48 49 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 50 { 51 struct radeon_mman *mman; 52 struct radeon_device *rdev; 53 54 mman = container_of(bdev, struct radeon_mman, bdev); 55 rdev = container_of(mman, struct radeon_device, mman); 56 return rdev; 57 } 58 59 60 /* 61 * Global memory. 62 */ 63 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 64 { 65 return ttm_mem_global_init(ref->object); 66 } 67 68 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 69 { 70 ttm_mem_global_release(ref->object); 71 } 72 73 static int radeon_ttm_global_init(struct radeon_device *rdev) 74 { 75 struct drm_global_reference *global_ref; 76 int r; 77 78 rdev->mman.mem_global_referenced = false; 79 global_ref = &rdev->mman.mem_global_ref; 80 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 81 global_ref->size = sizeof(struct ttm_mem_global); 82 global_ref->init = &radeon_ttm_mem_global_init; 83 global_ref->release = &radeon_ttm_mem_global_release; 84 r = drm_global_item_ref(global_ref); 85 if (r != 0) { 86 DRM_ERROR("Failed setting up TTM memory accounting " 87 "subsystem.\n"); 88 return r; 89 } 90 91 rdev->mman.bo_global_ref.mem_glob = 92 rdev->mman.mem_global_ref.object; 93 global_ref = &rdev->mman.bo_global_ref.ref; 94 global_ref->global_type = DRM_GLOBAL_TTM_BO; 95 global_ref->size = sizeof(struct ttm_bo_global); 96 global_ref->init = &ttm_bo_global_init; 97 global_ref->release = &ttm_bo_global_release; 98 r = drm_global_item_ref(global_ref); 99 if (r != 0) { 100 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 101 drm_global_item_unref(&rdev->mman.mem_global_ref); 102 return r; 103 } 104 105 rdev->mman.mem_global_referenced = true; 106 return 0; 107 } 108 109 static void radeon_ttm_global_fini(struct radeon_device *rdev) 110 { 111 if (rdev->mman.mem_global_referenced) { 112 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 113 drm_global_item_unref(&rdev->mman.mem_global_ref); 114 rdev->mman.mem_global_referenced = false; 115 } 116 } 117 118 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 119 { 120 return 0; 121 } 122 123 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 124 struct ttm_mem_type_manager *man) 125 { 126 struct radeon_device *rdev; 127 128 rdev = radeon_get_rdev(bdev); 129 130 switch (type) { 131 case TTM_PL_SYSTEM: 132 /* System memory */ 133 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 134 man->available_caching = TTM_PL_MASK_CACHING; 135 man->default_caching = TTM_PL_FLAG_CACHED; 136 break; 137 case TTM_PL_TT: 138 man->func = &ttm_bo_manager_func; 139 man->gpu_offset = rdev->mc.gtt_start; 140 man->available_caching = TTM_PL_MASK_CACHING; 141 man->default_caching = TTM_PL_FLAG_CACHED; 142 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 143 #if __OS_HAS_AGP 144 if (rdev->flags & RADEON_IS_AGP) { 145 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { 146 DRM_ERROR("AGP is not enabled for memory type %u\n", 147 (unsigned)type); 148 return -EINVAL; 149 } 150 if (!rdev->ddev->agp->cant_use_aperture) 151 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 152 man->available_caching = TTM_PL_FLAG_UNCACHED | 153 TTM_PL_FLAG_WC; 154 man->default_caching = TTM_PL_FLAG_WC; 155 } 156 #endif 157 break; 158 case TTM_PL_VRAM: 159 /* "On-card" video ram */ 160 man->func = &ttm_bo_manager_func; 161 man->gpu_offset = rdev->mc.vram_start; 162 man->flags = TTM_MEMTYPE_FLAG_FIXED | 163 TTM_MEMTYPE_FLAG_MAPPABLE; 164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 165 man->default_caching = TTM_PL_FLAG_WC; 166 break; 167 default: 168 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 169 return -EINVAL; 170 } 171 return 0; 172 } 173 174 static void radeon_evict_flags(struct ttm_buffer_object *bo, 175 struct ttm_placement *placement) 176 { 177 struct radeon_bo *rbo; 178 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 179 180 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 181 placement->fpfn = 0; 182 placement->lpfn = 0; 183 placement->placement = &placements; 184 placement->busy_placement = &placements; 185 placement->num_placement = 1; 186 placement->num_busy_placement = 1; 187 return; 188 } 189 rbo = container_of(bo, struct radeon_bo, tbo); 190 switch (bo->mem.mem_type) { 191 case TTM_PL_VRAM: 192 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 193 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 194 else 195 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 196 break; 197 case TTM_PL_TT: 198 default: 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 200 } 201 *placement = rbo->placement; 202 } 203 204 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 205 { 206 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 207 208 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 209 } 210 211 static void radeon_move_null(struct ttm_buffer_object *bo, 212 struct ttm_mem_reg *new_mem) 213 { 214 struct ttm_mem_reg *old_mem = &bo->mem; 215 216 BUG_ON(old_mem->mm_node != NULL); 217 *old_mem = *new_mem; 218 new_mem->mm_node = NULL; 219 } 220 221 static int radeon_move_blit(struct ttm_buffer_object *bo, 222 bool evict, bool no_wait_gpu, 223 struct ttm_mem_reg *new_mem, 224 struct ttm_mem_reg *old_mem) 225 { 226 struct radeon_device *rdev; 227 uint64_t old_start, new_start; 228 struct radeon_fence *fence; 229 int r, ridx; 230 231 rdev = radeon_get_rdev(bo->bdev); 232 ridx = radeon_copy_ring_index(rdev); 233 old_start = old_mem->start << PAGE_SHIFT; 234 new_start = new_mem->start << PAGE_SHIFT; 235 236 switch (old_mem->mem_type) { 237 case TTM_PL_VRAM: 238 old_start += rdev->mc.vram_start; 239 break; 240 case TTM_PL_TT: 241 old_start += rdev->mc.gtt_start; 242 break; 243 default: 244 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 245 return -EINVAL; 246 } 247 switch (new_mem->mem_type) { 248 case TTM_PL_VRAM: 249 new_start += rdev->mc.vram_start; 250 break; 251 case TTM_PL_TT: 252 new_start += rdev->mc.gtt_start; 253 break; 254 default: 255 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 256 return -EINVAL; 257 } 258 if (!rdev->ring[ridx].ready) { 259 DRM_ERROR("Trying to move memory with ring turned off.\n"); 260 return -EINVAL; 261 } 262 263 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 264 265 /* sync other rings */ 266 fence = bo->sync_obj; 267 r = radeon_copy(rdev, old_start, new_start, 268 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 269 &fence); 270 /* FIXME: handle copy error */ 271 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 272 evict, no_wait_gpu, new_mem); 273 radeon_fence_unref(&fence); 274 return r; 275 } 276 277 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 278 bool evict, bool interruptible, 279 bool no_wait_gpu, 280 struct ttm_mem_reg *new_mem) 281 { 282 struct radeon_device *rdev; 283 struct ttm_mem_reg *old_mem = &bo->mem; 284 struct ttm_mem_reg tmp_mem; 285 u32 placements; 286 struct ttm_placement placement; 287 int r; 288 289 rdev = radeon_get_rdev(bo->bdev); 290 tmp_mem = *new_mem; 291 tmp_mem.mm_node = NULL; 292 placement.fpfn = 0; 293 placement.lpfn = 0; 294 placement.num_placement = 1; 295 placement.placement = &placements; 296 placement.num_busy_placement = 1; 297 placement.busy_placement = &placements; 298 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 299 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 300 interruptible, no_wait_gpu); 301 if (unlikely(r)) { 302 return r; 303 } 304 305 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 306 if (unlikely(r)) { 307 goto out_cleanup; 308 } 309 310 r = ttm_tt_bind(bo->ttm, &tmp_mem); 311 if (unlikely(r)) { 312 goto out_cleanup; 313 } 314 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 315 if (unlikely(r)) { 316 goto out_cleanup; 317 } 318 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 319 out_cleanup: 320 ttm_bo_mem_put(bo, &tmp_mem); 321 return r; 322 } 323 324 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 325 bool evict, bool interruptible, 326 bool no_wait_gpu, 327 struct ttm_mem_reg *new_mem) 328 { 329 struct radeon_device *rdev; 330 struct ttm_mem_reg *old_mem = &bo->mem; 331 struct ttm_mem_reg tmp_mem; 332 struct ttm_placement placement; 333 u32 placements; 334 int r; 335 336 rdev = radeon_get_rdev(bo->bdev); 337 tmp_mem = *new_mem; 338 tmp_mem.mm_node = NULL; 339 placement.fpfn = 0; 340 placement.lpfn = 0; 341 placement.num_placement = 1; 342 placement.placement = &placements; 343 placement.num_busy_placement = 1; 344 placement.busy_placement = &placements; 345 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 346 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 347 interruptible, no_wait_gpu); 348 if (unlikely(r)) { 349 return r; 350 } 351 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 352 if (unlikely(r)) { 353 goto out_cleanup; 354 } 355 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 356 if (unlikely(r)) { 357 goto out_cleanup; 358 } 359 out_cleanup: 360 ttm_bo_mem_put(bo, &tmp_mem); 361 return r; 362 } 363 364 static int radeon_bo_move(struct ttm_buffer_object *bo, 365 bool evict, bool interruptible, 366 bool no_wait_gpu, 367 struct ttm_mem_reg *new_mem) 368 { 369 struct radeon_device *rdev; 370 struct ttm_mem_reg *old_mem = &bo->mem; 371 int r; 372 373 rdev = radeon_get_rdev(bo->bdev); 374 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 375 radeon_move_null(bo, new_mem); 376 return 0; 377 } 378 if ((old_mem->mem_type == TTM_PL_TT && 379 new_mem->mem_type == TTM_PL_SYSTEM) || 380 (old_mem->mem_type == TTM_PL_SYSTEM && 381 new_mem->mem_type == TTM_PL_TT)) { 382 /* bind is enough */ 383 radeon_move_null(bo, new_mem); 384 return 0; 385 } 386 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 387 rdev->asic->copy.copy == NULL) { 388 /* use memcpy */ 389 goto memcpy; 390 } 391 392 if (old_mem->mem_type == TTM_PL_VRAM && 393 new_mem->mem_type == TTM_PL_SYSTEM) { 394 r = radeon_move_vram_ram(bo, evict, interruptible, 395 no_wait_gpu, new_mem); 396 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 397 new_mem->mem_type == TTM_PL_VRAM) { 398 r = radeon_move_ram_vram(bo, evict, interruptible, 399 no_wait_gpu, new_mem); 400 } else { 401 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 402 } 403 404 if (r) { 405 memcpy: 406 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 407 } 408 return r; 409 } 410 411 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 412 { 413 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 414 struct radeon_device *rdev = radeon_get_rdev(bdev); 415 416 mem->bus.addr = NULL; 417 mem->bus.offset = 0; 418 mem->bus.size = mem->num_pages << PAGE_SHIFT; 419 mem->bus.base = 0; 420 mem->bus.is_iomem = false; 421 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 422 return -EINVAL; 423 switch (mem->mem_type) { 424 case TTM_PL_SYSTEM: 425 /* system memory */ 426 return 0; 427 case TTM_PL_TT: 428 #if __OS_HAS_AGP 429 if (rdev->flags & RADEON_IS_AGP) { 430 /* RADEON_IS_AGP is set only if AGP is active */ 431 mem->bus.offset = mem->start << PAGE_SHIFT; 432 mem->bus.base = rdev->mc.agp_base; 433 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 434 } 435 #endif 436 break; 437 case TTM_PL_VRAM: 438 mem->bus.offset = mem->start << PAGE_SHIFT; 439 /* check if it's visible */ 440 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 441 return -EINVAL; 442 mem->bus.base = rdev->mc.aper_base; 443 mem->bus.is_iomem = true; 444 #ifdef __alpha__ 445 /* 446 * Alpha: use bus.addr to hold the ioremap() return, 447 * so we can modify bus.base below. 448 */ 449 if (mem->placement & TTM_PL_FLAG_WC) 450 mem->bus.addr = 451 ioremap_wc(mem->bus.base + mem->bus.offset, 452 mem->bus.size); 453 else 454 mem->bus.addr = 455 ioremap_nocache(mem->bus.base + mem->bus.offset, 456 mem->bus.size); 457 458 /* 459 * Alpha: Use just the bus offset plus 460 * the hose/domain memory base for bus.base. 461 * It then can be used to build PTEs for VRAM 462 * access, as done in ttm_bo_vm_fault(). 463 */ 464 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 465 rdev->ddev->hose->dense_mem_base; 466 #endif 467 break; 468 default: 469 return -EINVAL; 470 } 471 return 0; 472 } 473 474 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 475 { 476 } 477 478 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 479 { 480 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 481 } 482 483 static int radeon_sync_obj_flush(void *sync_obj) 484 { 485 return 0; 486 } 487 488 static void radeon_sync_obj_unref(void **sync_obj) 489 { 490 radeon_fence_unref((struct radeon_fence **)sync_obj); 491 } 492 493 static void *radeon_sync_obj_ref(void *sync_obj) 494 { 495 return radeon_fence_ref((struct radeon_fence *)sync_obj); 496 } 497 498 static bool radeon_sync_obj_signaled(void *sync_obj) 499 { 500 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 501 } 502 503 /* 504 * TTM backend functions. 505 */ 506 struct radeon_ttm_tt { 507 struct ttm_dma_tt ttm; 508 struct radeon_device *rdev; 509 u64 offset; 510 }; 511 512 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 513 struct ttm_mem_reg *bo_mem) 514 { 515 struct radeon_ttm_tt *gtt = (void*)ttm; 516 int r; 517 518 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 519 if (!ttm->num_pages) { 520 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 521 ttm->num_pages, bo_mem, ttm); 522 } 523 r = radeon_gart_bind(gtt->rdev, gtt->offset, 524 ttm->num_pages, ttm->pages, gtt->ttm.dma_address); 525 if (r) { 526 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 527 ttm->num_pages, (unsigned)gtt->offset); 528 return r; 529 } 530 return 0; 531 } 532 533 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 534 { 535 struct radeon_ttm_tt *gtt = (void *)ttm; 536 537 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 538 return 0; 539 } 540 541 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 542 { 543 struct radeon_ttm_tt *gtt = (void *)ttm; 544 545 ttm_dma_tt_fini(>t->ttm); 546 kfree(gtt); 547 } 548 549 static struct ttm_backend_func radeon_backend_func = { 550 .bind = &radeon_ttm_backend_bind, 551 .unbind = &radeon_ttm_backend_unbind, 552 .destroy = &radeon_ttm_backend_destroy, 553 }; 554 555 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 556 unsigned long size, uint32_t page_flags, 557 struct page *dummy_read_page) 558 { 559 struct radeon_device *rdev; 560 struct radeon_ttm_tt *gtt; 561 562 rdev = radeon_get_rdev(bdev); 563 #if __OS_HAS_AGP 564 if (rdev->flags & RADEON_IS_AGP) { 565 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, 566 size, page_flags, dummy_read_page); 567 } 568 #endif 569 570 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 571 if (gtt == NULL) { 572 return NULL; 573 } 574 gtt->ttm.ttm.func = &radeon_backend_func; 575 gtt->rdev = rdev; 576 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 577 kfree(gtt); 578 return NULL; 579 } 580 return >t->ttm.ttm; 581 } 582 583 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 584 { 585 struct radeon_device *rdev; 586 struct radeon_ttm_tt *gtt = (void *)ttm; 587 unsigned i; 588 int r; 589 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 590 591 if (ttm->state != tt_unpopulated) 592 return 0; 593 594 if (slave && ttm->sg) { 595 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 596 gtt->ttm.dma_address, ttm->num_pages); 597 ttm->state = tt_unbound; 598 return 0; 599 } 600 601 rdev = radeon_get_rdev(ttm->bdev); 602 #if __OS_HAS_AGP 603 if (rdev->flags & RADEON_IS_AGP) { 604 return ttm_agp_tt_populate(ttm); 605 } 606 #endif 607 608 #ifdef CONFIG_SWIOTLB 609 if (swiotlb_nr_tbl()) { 610 return ttm_dma_populate(>t->ttm, rdev->dev); 611 } 612 #endif 613 614 r = ttm_pool_populate(ttm); 615 if (r) { 616 return r; 617 } 618 619 for (i = 0; i < ttm->num_pages; i++) { 620 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 621 0, PAGE_SIZE, 622 PCI_DMA_BIDIRECTIONAL); 623 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 624 while (--i) { 625 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 626 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 627 gtt->ttm.dma_address[i] = 0; 628 } 629 ttm_pool_unpopulate(ttm); 630 return -EFAULT; 631 } 632 } 633 return 0; 634 } 635 636 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 637 { 638 struct radeon_device *rdev; 639 struct radeon_ttm_tt *gtt = (void *)ttm; 640 unsigned i; 641 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 642 643 if (slave) 644 return; 645 646 rdev = radeon_get_rdev(ttm->bdev); 647 #if __OS_HAS_AGP 648 if (rdev->flags & RADEON_IS_AGP) { 649 ttm_agp_tt_unpopulate(ttm); 650 return; 651 } 652 #endif 653 654 #ifdef CONFIG_SWIOTLB 655 if (swiotlb_nr_tbl()) { 656 ttm_dma_unpopulate(>t->ttm, rdev->dev); 657 return; 658 } 659 #endif 660 661 for (i = 0; i < ttm->num_pages; i++) { 662 if (gtt->ttm.dma_address[i]) { 663 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 664 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 665 } 666 } 667 668 ttm_pool_unpopulate(ttm); 669 } 670 671 static struct ttm_bo_driver radeon_bo_driver = { 672 .ttm_tt_create = &radeon_ttm_tt_create, 673 .ttm_tt_populate = &radeon_ttm_tt_populate, 674 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 675 .invalidate_caches = &radeon_invalidate_caches, 676 .init_mem_type = &radeon_init_mem_type, 677 .evict_flags = &radeon_evict_flags, 678 .move = &radeon_bo_move, 679 .verify_access = &radeon_verify_access, 680 .sync_obj_signaled = &radeon_sync_obj_signaled, 681 .sync_obj_wait = &radeon_sync_obj_wait, 682 .sync_obj_flush = &radeon_sync_obj_flush, 683 .sync_obj_unref = &radeon_sync_obj_unref, 684 .sync_obj_ref = &radeon_sync_obj_ref, 685 .move_notify = &radeon_bo_move_notify, 686 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 687 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 688 .io_mem_free = &radeon_ttm_io_mem_free, 689 }; 690 691 int radeon_ttm_init(struct radeon_device *rdev) 692 { 693 int r; 694 695 r = radeon_ttm_global_init(rdev); 696 if (r) { 697 return r; 698 } 699 /* No others user of address space so set it to 0 */ 700 r = ttm_bo_device_init(&rdev->mman.bdev, 701 rdev->mman.bo_global_ref.ref.object, 702 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, 703 rdev->need_dma32); 704 if (r) { 705 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 706 return r; 707 } 708 rdev->mman.initialized = true; 709 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 710 rdev->mc.real_vram_size >> PAGE_SHIFT); 711 if (r) { 712 DRM_ERROR("Failed initializing VRAM heap.\n"); 713 return r; 714 } 715 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 716 RADEON_GEM_DOMAIN_VRAM, 717 NULL, &rdev->stollen_vga_memory); 718 if (r) { 719 return r; 720 } 721 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 722 if (r) 723 return r; 724 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 725 radeon_bo_unreserve(rdev->stollen_vga_memory); 726 if (r) { 727 radeon_bo_unref(&rdev->stollen_vga_memory); 728 return r; 729 } 730 DRM_INFO("radeon: %uM of VRAM memory ready\n", 731 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 732 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 733 rdev->mc.gtt_size >> PAGE_SHIFT); 734 if (r) { 735 DRM_ERROR("Failed initializing GTT heap.\n"); 736 return r; 737 } 738 DRM_INFO("radeon: %uM of GTT memory ready.\n", 739 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 740 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 741 742 r = radeon_ttm_debugfs_init(rdev); 743 if (r) { 744 DRM_ERROR("Failed to init debugfs\n"); 745 return r; 746 } 747 return 0; 748 } 749 750 void radeon_ttm_fini(struct radeon_device *rdev) 751 { 752 int r; 753 754 if (!rdev->mman.initialized) 755 return; 756 if (rdev->stollen_vga_memory) { 757 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 758 if (r == 0) { 759 radeon_bo_unpin(rdev->stollen_vga_memory); 760 radeon_bo_unreserve(rdev->stollen_vga_memory); 761 } 762 radeon_bo_unref(&rdev->stollen_vga_memory); 763 } 764 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 765 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 766 ttm_bo_device_release(&rdev->mman.bdev); 767 radeon_gart_fini(rdev); 768 radeon_ttm_global_fini(rdev); 769 rdev->mman.initialized = false; 770 DRM_INFO("radeon: ttm finalized\n"); 771 } 772 773 /* this should only be called at bootup or when userspace 774 * isn't running */ 775 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 776 { 777 struct ttm_mem_type_manager *man; 778 779 if (!rdev->mman.initialized) 780 return; 781 782 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 783 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 784 man->size = size >> PAGE_SHIFT; 785 } 786 787 static struct vm_operations_struct radeon_ttm_vm_ops; 788 static const struct vm_operations_struct *ttm_vm_ops = NULL; 789 790 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 791 { 792 struct ttm_buffer_object *bo; 793 struct radeon_device *rdev; 794 int r; 795 796 bo = (struct ttm_buffer_object *)vma->vm_private_data; 797 if (bo == NULL) { 798 return VM_FAULT_NOPAGE; 799 } 800 rdev = radeon_get_rdev(bo->bdev); 801 down_read(&rdev->pm.mclk_lock); 802 r = ttm_vm_ops->fault(vma, vmf); 803 up_read(&rdev->pm.mclk_lock); 804 return r; 805 } 806 807 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 808 { 809 struct drm_file *file_priv; 810 struct radeon_device *rdev; 811 int r; 812 813 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 814 return drm_mmap(filp, vma); 815 } 816 817 file_priv = filp->private_data; 818 rdev = file_priv->minor->dev->dev_private; 819 if (rdev == NULL) { 820 return -EINVAL; 821 } 822 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 823 if (unlikely(r != 0)) { 824 return r; 825 } 826 if (unlikely(ttm_vm_ops == NULL)) { 827 ttm_vm_ops = vma->vm_ops; 828 radeon_ttm_vm_ops = *ttm_vm_ops; 829 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 830 } 831 vma->vm_ops = &radeon_ttm_vm_ops; 832 return 0; 833 } 834 835 836 #define RADEON_DEBUGFS_MEM_TYPES 2 837 838 #if defined(CONFIG_DEBUG_FS) 839 static int radeon_mm_dump_table(struct seq_file *m, void *data) 840 { 841 struct drm_info_node *node = (struct drm_info_node *)m->private; 842 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; 843 struct drm_device *dev = node->minor->dev; 844 struct radeon_device *rdev = dev->dev_private; 845 int ret; 846 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 847 848 spin_lock(&glob->lru_lock); 849 ret = drm_mm_dump_table(m, mm); 850 spin_unlock(&glob->lru_lock); 851 return ret; 852 } 853 #endif 854 855 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 856 { 857 #if defined(CONFIG_DEBUG_FS) 858 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; 859 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; 860 unsigned i; 861 862 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { 863 if (i == 0) 864 sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); 865 else 866 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); 867 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 868 radeon_mem_types_list[i].show = &radeon_mm_dump_table; 869 radeon_mem_types_list[i].driver_features = 0; 870 if (i == 0) 871 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; 872 else 873 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; 874 875 } 876 /* Add ttm page pool to debugfs */ 877 sprintf(radeon_mem_types_names[i], "ttm_page_pool"); 878 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 879 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; 880 radeon_mem_types_list[i].driver_features = 0; 881 radeon_mem_types_list[i++].data = NULL; 882 #ifdef CONFIG_SWIOTLB 883 if (swiotlb_nr_tbl()) { 884 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); 885 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 886 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; 887 radeon_mem_types_list[i].driver_features = 0; 888 radeon_mem_types_list[i++].data = NULL; 889 } 890 #endif 891 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); 892 893 #endif 894 return 0; 895 } 896