1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/pagemap.h> 35 #include <linux/pci.h> 36 #include <linux/seq_file.h> 37 #include <linux/slab.h> 38 #include <linux/swap.h> 39 #include <linux/swiotlb.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_debugfs.h> 43 #include <drm/drm_device.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_prime.h> 46 #include <drm/radeon_drm.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 #include <drm/ttm/ttm_placement.h> 52 53 #include "radeon_reg.h" 54 #include "radeon.h" 55 56 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 57 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 58 59 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 60 { 61 struct radeon_mman *mman; 62 struct radeon_device *rdev; 63 64 mman = container_of(bdev, struct radeon_mman, bdev); 65 rdev = container_of(mman, struct radeon_device, mman); 66 return rdev; 67 } 68 69 static int radeon_ttm_init_vram(struct radeon_device *rdev) 70 { 71 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM, 72 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC, 73 TTM_PL_FLAG_WC, false, 74 rdev->mc.real_vram_size >> PAGE_SHIFT); 75 } 76 77 static int radeon_ttm_init_gtt(struct radeon_device *rdev) 78 { 79 uint32_t available_caching, default_caching; 80 81 available_caching = TTM_PL_MASK_CACHING; 82 default_caching = TTM_PL_FLAG_CACHED; 83 84 #if IS_ENABLED(CONFIG_AGP) 85 if (rdev->flags & RADEON_IS_AGP) { 86 if (!rdev->ddev->agp) { 87 DRM_ERROR("AGP is not enabled\n"); 88 return -EINVAL; 89 } 90 available_caching = TTM_PL_FLAG_UNCACHED | 91 TTM_PL_FLAG_WC; 92 default_caching = TTM_PL_FLAG_WC; 93 } 94 #endif 95 96 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT, 97 available_caching, 98 default_caching, true, 99 rdev->mc.gtt_size >> PAGE_SHIFT); 100 } 101 102 static void radeon_evict_flags(struct ttm_buffer_object *bo, 103 struct ttm_placement *placement) 104 { 105 static const struct ttm_place placements = { 106 .fpfn = 0, 107 .lpfn = 0, 108 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 109 }; 110 111 struct radeon_bo *rbo; 112 113 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 114 placement->placement = &placements; 115 placement->busy_placement = &placements; 116 placement->num_placement = 1; 117 placement->num_busy_placement = 1; 118 return; 119 } 120 rbo = container_of(bo, struct radeon_bo, tbo); 121 switch (bo->mem.mem_type) { 122 case TTM_PL_VRAM: 123 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 124 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 125 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 126 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 127 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 128 int i; 129 130 /* Try evicting to the CPU inaccessible part of VRAM 131 * first, but only set GTT as busy placement, so this 132 * BO will be evicted to GTT rather than causing other 133 * BOs to be evicted from VRAM 134 */ 135 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 136 RADEON_GEM_DOMAIN_GTT); 137 rbo->placement.num_busy_placement = 0; 138 for (i = 0; i < rbo->placement.num_placement; i++) { 139 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 140 if (rbo->placements[i].fpfn < fpfn) 141 rbo->placements[i].fpfn = fpfn; 142 } else { 143 rbo->placement.busy_placement = 144 &rbo->placements[i]; 145 rbo->placement.num_busy_placement = 1; 146 } 147 } 148 } else 149 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 150 break; 151 case TTM_PL_TT: 152 default: 153 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 154 } 155 *placement = rbo->placement; 156 } 157 158 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 159 { 160 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 161 162 if (radeon_ttm_tt_has_userptr(bo->ttm)) 163 return -EPERM; 164 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, 165 filp->private_data); 166 } 167 168 static void radeon_move_null(struct ttm_buffer_object *bo, 169 struct ttm_resource *new_mem) 170 { 171 struct ttm_resource *old_mem = &bo->mem; 172 173 BUG_ON(old_mem->mm_node != NULL); 174 *old_mem = *new_mem; 175 new_mem->mm_node = NULL; 176 } 177 178 static int radeon_move_blit(struct ttm_buffer_object *bo, 179 bool evict, bool no_wait_gpu, 180 struct ttm_resource *new_mem, 181 struct ttm_resource *old_mem) 182 { 183 struct radeon_device *rdev; 184 uint64_t old_start, new_start; 185 struct radeon_fence *fence; 186 unsigned num_pages; 187 int r, ridx; 188 189 rdev = radeon_get_rdev(bo->bdev); 190 ridx = radeon_copy_ring_index(rdev); 191 old_start = (u64)old_mem->start << PAGE_SHIFT; 192 new_start = (u64)new_mem->start << PAGE_SHIFT; 193 194 switch (old_mem->mem_type) { 195 case TTM_PL_VRAM: 196 old_start += rdev->mc.vram_start; 197 break; 198 case TTM_PL_TT: 199 old_start += rdev->mc.gtt_start; 200 break; 201 default: 202 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 203 return -EINVAL; 204 } 205 switch (new_mem->mem_type) { 206 case TTM_PL_VRAM: 207 new_start += rdev->mc.vram_start; 208 break; 209 case TTM_PL_TT: 210 new_start += rdev->mc.gtt_start; 211 break; 212 default: 213 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 214 return -EINVAL; 215 } 216 if (!rdev->ring[ridx].ready) { 217 DRM_ERROR("Trying to move memory with ring turned off.\n"); 218 return -EINVAL; 219 } 220 221 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 222 223 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 224 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); 225 if (IS_ERR(fence)) 226 return PTR_ERR(fence); 227 228 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); 229 radeon_fence_unref(&fence); 230 return r; 231 } 232 233 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 234 bool evict, bool interruptible, 235 bool no_wait_gpu, 236 struct ttm_resource *new_mem) 237 { 238 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 239 struct ttm_resource *old_mem = &bo->mem; 240 struct ttm_resource tmp_mem; 241 struct ttm_place placements; 242 struct ttm_placement placement; 243 int r; 244 245 tmp_mem = *new_mem; 246 tmp_mem.mm_node = NULL; 247 placement.num_placement = 1; 248 placement.placement = &placements; 249 placement.num_busy_placement = 1; 250 placement.busy_placement = &placements; 251 placements.fpfn = 0; 252 placements.lpfn = 0; 253 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 254 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 255 if (unlikely(r)) { 256 return r; 257 } 258 259 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 260 if (unlikely(r)) { 261 goto out_cleanup; 262 } 263 264 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); 265 if (unlikely(r)) { 266 goto out_cleanup; 267 } 268 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 269 if (unlikely(r)) { 270 goto out_cleanup; 271 } 272 r = ttm_bo_move_ttm(bo, &ctx, new_mem); 273 out_cleanup: 274 ttm_bo_mem_put(bo, &tmp_mem); 275 return r; 276 } 277 278 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 279 bool evict, bool interruptible, 280 bool no_wait_gpu, 281 struct ttm_resource *new_mem) 282 { 283 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 284 struct ttm_resource *old_mem = &bo->mem; 285 struct ttm_resource tmp_mem; 286 struct ttm_placement placement; 287 struct ttm_place placements; 288 int r; 289 290 tmp_mem = *new_mem; 291 tmp_mem.mm_node = NULL; 292 placement.num_placement = 1; 293 placement.placement = &placements; 294 placement.num_busy_placement = 1; 295 placement.busy_placement = &placements; 296 placements.fpfn = 0; 297 placements.lpfn = 0; 298 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 299 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 300 if (unlikely(r)) { 301 return r; 302 } 303 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); 304 if (unlikely(r)) { 305 goto out_cleanup; 306 } 307 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 308 if (unlikely(r)) { 309 goto out_cleanup; 310 } 311 out_cleanup: 312 ttm_bo_mem_put(bo, &tmp_mem); 313 return r; 314 } 315 316 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, 317 struct ttm_operation_ctx *ctx, 318 struct ttm_resource *new_mem) 319 { 320 struct radeon_device *rdev; 321 struct radeon_bo *rbo; 322 struct ttm_resource *old_mem = &bo->mem; 323 int r; 324 325 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 326 if (r) 327 return r; 328 329 /* Can't move a pinned BO */ 330 rbo = container_of(bo, struct radeon_bo, tbo); 331 if (WARN_ON_ONCE(rbo->pin_count > 0)) 332 return -EINVAL; 333 334 rdev = radeon_get_rdev(bo->bdev); 335 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 336 radeon_move_null(bo, new_mem); 337 return 0; 338 } 339 if ((old_mem->mem_type == TTM_PL_TT && 340 new_mem->mem_type == TTM_PL_SYSTEM) || 341 (old_mem->mem_type == TTM_PL_SYSTEM && 342 new_mem->mem_type == TTM_PL_TT)) { 343 /* bind is enough */ 344 radeon_move_null(bo, new_mem); 345 return 0; 346 } 347 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 348 rdev->asic->copy.copy == NULL) { 349 /* use memcpy */ 350 goto memcpy; 351 } 352 353 if (old_mem->mem_type == TTM_PL_VRAM && 354 new_mem->mem_type == TTM_PL_SYSTEM) { 355 r = radeon_move_vram_ram(bo, evict, ctx->interruptible, 356 ctx->no_wait_gpu, new_mem); 357 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 358 new_mem->mem_type == TTM_PL_VRAM) { 359 r = radeon_move_ram_vram(bo, evict, ctx->interruptible, 360 ctx->no_wait_gpu, new_mem); 361 } else { 362 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, 363 new_mem, old_mem); 364 } 365 366 if (r) { 367 memcpy: 368 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 369 if (r) { 370 return r; 371 } 372 } 373 374 /* update statistics */ 375 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 376 return 0; 377 } 378 379 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 380 { 381 struct radeon_device *rdev = radeon_get_rdev(bdev); 382 383 mem->bus.addr = NULL; 384 mem->bus.offset = 0; 385 mem->bus.size = mem->num_pages << PAGE_SHIFT; 386 mem->bus.base = 0; 387 mem->bus.is_iomem = false; 388 389 switch (mem->mem_type) { 390 case TTM_PL_SYSTEM: 391 /* system memory */ 392 return 0; 393 case TTM_PL_TT: 394 #if IS_ENABLED(CONFIG_AGP) 395 if (rdev->flags & RADEON_IS_AGP) { 396 /* RADEON_IS_AGP is set only if AGP is active */ 397 mem->bus.offset = mem->start << PAGE_SHIFT; 398 mem->bus.base = rdev->mc.agp_base; 399 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 400 } 401 #endif 402 break; 403 case TTM_PL_VRAM: 404 mem->bus.offset = mem->start << PAGE_SHIFT; 405 /* check if it's visible */ 406 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 407 return -EINVAL; 408 mem->bus.base = rdev->mc.aper_base; 409 mem->bus.is_iomem = true; 410 #ifdef __alpha__ 411 /* 412 * Alpha: use bus.addr to hold the ioremap() return, 413 * so we can modify bus.base below. 414 */ 415 if (mem->placement & TTM_PL_FLAG_WC) 416 mem->bus.addr = 417 ioremap_wc(mem->bus.base + mem->bus.offset, 418 mem->bus.size); 419 else 420 mem->bus.addr = 421 ioremap(mem->bus.base + mem->bus.offset, 422 mem->bus.size); 423 if (!mem->bus.addr) 424 return -ENOMEM; 425 426 /* 427 * Alpha: Use just the bus offset plus 428 * the hose/domain memory base for bus.base. 429 * It then can be used to build PTEs for VRAM 430 * access, as done in ttm_bo_vm_fault(). 431 */ 432 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 433 rdev->ddev->hose->dense_mem_base; 434 #endif 435 break; 436 default: 437 return -EINVAL; 438 } 439 return 0; 440 } 441 442 /* 443 * TTM backend functions. 444 */ 445 struct radeon_ttm_tt { 446 struct ttm_dma_tt ttm; 447 struct radeon_device *rdev; 448 u64 offset; 449 450 uint64_t userptr; 451 struct mm_struct *usermm; 452 uint32_t userflags; 453 }; 454 455 /* prepare the sg table with the user pages */ 456 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) 457 { 458 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 459 struct radeon_ttm_tt *gtt = (void *)ttm; 460 unsigned pinned = 0; 461 int r; 462 463 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 464 enum dma_data_direction direction = write ? 465 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 466 467 if (current->mm != gtt->usermm) 468 return -EPERM; 469 470 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 471 /* check that we only pin down anonymous memory 472 to prevent problems with writeback */ 473 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 474 struct vm_area_struct *vma; 475 vma = find_vma(gtt->usermm, gtt->userptr); 476 if (!vma || vma->vm_file || vma->vm_end < end) 477 return -EPERM; 478 } 479 480 do { 481 unsigned num_pages = ttm->num_pages - pinned; 482 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 483 struct page **pages = ttm->pages + pinned; 484 485 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, 486 pages, NULL); 487 if (r < 0) 488 goto release_pages; 489 490 pinned += r; 491 492 } while (pinned < ttm->num_pages); 493 494 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 495 ttm->num_pages << PAGE_SHIFT, 496 GFP_KERNEL); 497 if (r) 498 goto release_sg; 499 500 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); 501 if (r) 502 goto release_sg; 503 504 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 505 gtt->ttm.dma_address, ttm->num_pages); 506 507 return 0; 508 509 release_sg: 510 kfree(ttm->sg); 511 512 release_pages: 513 release_pages(ttm->pages, pinned); 514 return r; 515 } 516 517 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 518 { 519 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 520 struct radeon_ttm_tt *gtt = (void *)ttm; 521 struct sg_page_iter sg_iter; 522 523 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 524 enum dma_data_direction direction = write ? 525 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 526 527 /* double check that we don't free the table twice */ 528 if (!ttm->sg->sgl) 529 return; 530 531 /* free the sg table and pages again */ 532 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); 533 534 for_each_sgtable_page(ttm->sg, &sg_iter, 0) { 535 struct page *page = sg_page_iter_page(&sg_iter); 536 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) 537 set_page_dirty(page); 538 539 mark_page_accessed(page); 540 put_page(page); 541 } 542 543 sg_free_table(ttm->sg); 544 } 545 546 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 547 struct ttm_resource *bo_mem) 548 { 549 struct radeon_ttm_tt *gtt = (void*)ttm; 550 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 551 RADEON_GART_PAGE_WRITE; 552 int r; 553 554 if (gtt->userptr) { 555 radeon_ttm_tt_pin_userptr(ttm); 556 flags &= ~RADEON_GART_PAGE_WRITE; 557 } 558 559 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 560 if (!ttm->num_pages) { 561 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 562 ttm->num_pages, bo_mem, ttm); 563 } 564 if (ttm->caching_state == tt_cached) 565 flags |= RADEON_GART_PAGE_SNOOP; 566 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 567 ttm->pages, gtt->ttm.dma_address, flags); 568 if (r) { 569 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 570 ttm->num_pages, (unsigned)gtt->offset); 571 return r; 572 } 573 return 0; 574 } 575 576 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 577 { 578 struct radeon_ttm_tt *gtt = (void *)ttm; 579 580 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 581 582 if (gtt->userptr) 583 radeon_ttm_tt_unpin_userptr(ttm); 584 585 return 0; 586 } 587 588 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 589 { 590 struct radeon_ttm_tt *gtt = (void *)ttm; 591 592 ttm_dma_tt_fini(>t->ttm); 593 kfree(gtt); 594 } 595 596 static struct ttm_backend_func radeon_backend_func = { 597 .bind = &radeon_ttm_backend_bind, 598 .unbind = &radeon_ttm_backend_unbind, 599 .destroy = &radeon_ttm_backend_destroy, 600 }; 601 602 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, 603 uint32_t page_flags) 604 { 605 struct radeon_device *rdev; 606 struct radeon_ttm_tt *gtt; 607 608 rdev = radeon_get_rdev(bo->bdev); 609 #if IS_ENABLED(CONFIG_AGP) 610 if (rdev->flags & RADEON_IS_AGP) { 611 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, 612 page_flags); 613 } 614 #endif 615 616 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 617 if (gtt == NULL) { 618 return NULL; 619 } 620 gtt->ttm.ttm.func = &radeon_backend_func; 621 gtt->rdev = rdev; 622 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { 623 kfree(gtt); 624 return NULL; 625 } 626 return >t->ttm.ttm; 627 } 628 629 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) 630 { 631 if (!ttm || ttm->func != &radeon_backend_func) 632 return NULL; 633 return (struct radeon_ttm_tt *)ttm; 634 } 635 636 static int radeon_ttm_tt_populate(struct ttm_tt *ttm, 637 struct ttm_operation_ctx *ctx) 638 { 639 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 640 struct radeon_device *rdev; 641 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 642 643 if (gtt && gtt->userptr) { 644 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 645 if (!ttm->sg) 646 return -ENOMEM; 647 648 ttm->page_flags |= TTM_PAGE_FLAG_SG; 649 ttm->state = tt_unbound; 650 return 0; 651 } 652 653 if (slave && ttm->sg) { 654 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 655 gtt->ttm.dma_address, ttm->num_pages); 656 ttm->state = tt_unbound; 657 return 0; 658 } 659 660 rdev = radeon_get_rdev(ttm->bdev); 661 #if IS_ENABLED(CONFIG_AGP) 662 if (rdev->flags & RADEON_IS_AGP) { 663 return ttm_agp_tt_populate(ttm, ctx); 664 } 665 #endif 666 667 #ifdef CONFIG_SWIOTLB 668 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 669 return ttm_dma_populate(>t->ttm, rdev->dev, ctx); 670 } 671 #endif 672 673 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); 674 } 675 676 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 677 { 678 struct radeon_device *rdev; 679 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 680 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 681 682 if (gtt && gtt->userptr) { 683 kfree(ttm->sg); 684 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 685 return; 686 } 687 688 if (slave) 689 return; 690 691 rdev = radeon_get_rdev(ttm->bdev); 692 #if IS_ENABLED(CONFIG_AGP) 693 if (rdev->flags & RADEON_IS_AGP) { 694 ttm_agp_tt_unpopulate(ttm); 695 return; 696 } 697 #endif 698 699 #ifdef CONFIG_SWIOTLB 700 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 701 ttm_dma_unpopulate(>t->ttm, rdev->dev); 702 return; 703 } 704 #endif 705 706 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); 707 } 708 709 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 710 uint32_t flags) 711 { 712 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 713 714 if (gtt == NULL) 715 return -EINVAL; 716 717 gtt->userptr = addr; 718 gtt->usermm = current->mm; 719 gtt->userflags = flags; 720 return 0; 721 } 722 723 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) 724 { 725 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 726 727 if (gtt == NULL) 728 return false; 729 730 return !!gtt->userptr; 731 } 732 733 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) 734 { 735 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 736 737 if (gtt == NULL) 738 return false; 739 740 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 741 } 742 743 static struct ttm_bo_driver radeon_bo_driver = { 744 .ttm_tt_create = &radeon_ttm_tt_create, 745 .ttm_tt_populate = &radeon_ttm_tt_populate, 746 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 747 .eviction_valuable = ttm_bo_eviction_valuable, 748 .evict_flags = &radeon_evict_flags, 749 .move = &radeon_bo_move, 750 .verify_access = &radeon_verify_access, 751 .move_notify = &radeon_bo_move_notify, 752 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 753 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 754 }; 755 756 int radeon_ttm_init(struct radeon_device *rdev) 757 { 758 int r; 759 760 /* No others user of address space so set it to 0 */ 761 r = ttm_bo_device_init(&rdev->mman.bdev, 762 &radeon_bo_driver, 763 rdev->ddev->anon_inode->i_mapping, 764 rdev->ddev->vma_offset_manager, 765 dma_addressing_limited(&rdev->pdev->dev)); 766 if (r) { 767 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 768 return r; 769 } 770 rdev->mman.initialized = true; 771 772 r = radeon_ttm_init_vram(rdev); 773 if (r) { 774 DRM_ERROR("Failed initializing VRAM heap.\n"); 775 return r; 776 } 777 /* Change the size here instead of the init above so only lpfn is affected */ 778 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 779 780 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 781 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 782 NULL, &rdev->stolen_vga_memory); 783 if (r) { 784 return r; 785 } 786 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 787 if (r) 788 return r; 789 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 790 radeon_bo_unreserve(rdev->stolen_vga_memory); 791 if (r) { 792 radeon_bo_unref(&rdev->stolen_vga_memory); 793 return r; 794 } 795 DRM_INFO("radeon: %uM of VRAM memory ready\n", 796 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 797 798 r = radeon_ttm_init_gtt(rdev); 799 if (r) { 800 DRM_ERROR("Failed initializing GTT heap.\n"); 801 return r; 802 } 803 DRM_INFO("radeon: %uM of GTT memory ready.\n", 804 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 805 806 r = radeon_ttm_debugfs_init(rdev); 807 if (r) { 808 DRM_ERROR("Failed to init debugfs\n"); 809 return r; 810 } 811 return 0; 812 } 813 814 void radeon_ttm_fini(struct radeon_device *rdev) 815 { 816 int r; 817 818 if (!rdev->mman.initialized) 819 return; 820 radeon_ttm_debugfs_fini(rdev); 821 if (rdev->stolen_vga_memory) { 822 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 823 if (r == 0) { 824 radeon_bo_unpin(rdev->stolen_vga_memory); 825 radeon_bo_unreserve(rdev->stolen_vga_memory); 826 } 827 radeon_bo_unref(&rdev->stolen_vga_memory); 828 } 829 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM); 830 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT); 831 ttm_bo_device_release(&rdev->mman.bdev); 832 radeon_gart_fini(rdev); 833 rdev->mman.initialized = false; 834 DRM_INFO("radeon: ttm finalized\n"); 835 } 836 837 /* this should only be called at bootup or when userspace 838 * isn't running */ 839 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 840 { 841 struct ttm_resource_manager *man; 842 843 if (!rdev->mman.initialized) 844 return; 845 846 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 847 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 848 man->size = size >> PAGE_SHIFT; 849 } 850 851 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) 852 { 853 struct ttm_buffer_object *bo; 854 struct radeon_device *rdev; 855 vm_fault_t ret; 856 857 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; 858 if (bo == NULL) 859 return VM_FAULT_NOPAGE; 860 861 rdev = radeon_get_rdev(bo->bdev); 862 down_read(&rdev->pm.mclk_lock); 863 ret = ttm_bo_vm_fault(vmf); 864 up_read(&rdev->pm.mclk_lock); 865 return ret; 866 } 867 868 static struct vm_operations_struct radeon_ttm_vm_ops = { 869 .fault = radeon_ttm_fault, 870 .open = ttm_bo_vm_open, 871 .close = ttm_bo_vm_close, 872 .access = ttm_bo_vm_access 873 }; 874 875 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 876 { 877 int r; 878 struct drm_file *file_priv = filp->private_data; 879 struct radeon_device *rdev = file_priv->minor->dev->dev_private; 880 881 if (rdev == NULL) 882 return -EINVAL; 883 884 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 885 if (unlikely(r != 0)) 886 return r; 887 888 vma->vm_ops = &radeon_ttm_vm_ops; 889 return 0; 890 } 891 892 #if defined(CONFIG_DEBUG_FS) 893 894 static int radeon_mm_dump_table(struct seq_file *m, void *data) 895 { 896 struct drm_info_node *node = (struct drm_info_node *)m->private; 897 unsigned ttm_pl = *(int*)node->info_ent->data; 898 struct drm_device *dev = node->minor->dev; 899 struct radeon_device *rdev = dev->dev_private; 900 struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl); 901 struct drm_printer p = drm_seq_file_printer(m); 902 903 man->func->debug(man, &p); 904 return 0; 905 } 906 907 908 static int ttm_pl_vram = TTM_PL_VRAM; 909 static int ttm_pl_tt = TTM_PL_TT; 910 911 static struct drm_info_list radeon_ttm_debugfs_list[] = { 912 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 913 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 914 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 915 #ifdef CONFIG_SWIOTLB 916 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 917 #endif 918 }; 919 920 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 921 { 922 struct radeon_device *rdev = inode->i_private; 923 i_size_write(inode, rdev->mc.mc_vram_size); 924 filep->private_data = inode->i_private; 925 return 0; 926 } 927 928 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 929 size_t size, loff_t *pos) 930 { 931 struct radeon_device *rdev = f->private_data; 932 ssize_t result = 0; 933 int r; 934 935 if (size & 0x3 || *pos & 0x3) 936 return -EINVAL; 937 938 while (size) { 939 unsigned long flags; 940 uint32_t value; 941 942 if (*pos >= rdev->mc.mc_vram_size) 943 return result; 944 945 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 946 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 947 if (rdev->family >= CHIP_CEDAR) 948 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 949 value = RREG32(RADEON_MM_DATA); 950 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 951 952 r = put_user(value, (uint32_t *)buf); 953 if (r) 954 return r; 955 956 result += 4; 957 buf += 4; 958 *pos += 4; 959 size -= 4; 960 } 961 962 return result; 963 } 964 965 static const struct file_operations radeon_ttm_vram_fops = { 966 .owner = THIS_MODULE, 967 .open = radeon_ttm_vram_open, 968 .read = radeon_ttm_vram_read, 969 .llseek = default_llseek 970 }; 971 972 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 973 { 974 struct radeon_device *rdev = inode->i_private; 975 i_size_write(inode, rdev->mc.gtt_size); 976 filep->private_data = inode->i_private; 977 return 0; 978 } 979 980 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 981 size_t size, loff_t *pos) 982 { 983 struct radeon_device *rdev = f->private_data; 984 ssize_t result = 0; 985 int r; 986 987 while (size) { 988 loff_t p = *pos / PAGE_SIZE; 989 unsigned off = *pos & ~PAGE_MASK; 990 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 991 struct page *page; 992 void *ptr; 993 994 if (p >= rdev->gart.num_cpu_pages) 995 return result; 996 997 page = rdev->gart.pages[p]; 998 if (page) { 999 ptr = kmap(page); 1000 ptr += off; 1001 1002 r = copy_to_user(buf, ptr, cur_size); 1003 kunmap(rdev->gart.pages[p]); 1004 } else 1005 r = clear_user(buf, cur_size); 1006 1007 if (r) 1008 return -EFAULT; 1009 1010 result += cur_size; 1011 buf += cur_size; 1012 *pos += cur_size; 1013 size -= cur_size; 1014 } 1015 1016 return result; 1017 } 1018 1019 static const struct file_operations radeon_ttm_gtt_fops = { 1020 .owner = THIS_MODULE, 1021 .open = radeon_ttm_gtt_open, 1022 .read = radeon_ttm_gtt_read, 1023 .llseek = default_llseek 1024 }; 1025 1026 #endif 1027 1028 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1029 { 1030 #if defined(CONFIG_DEBUG_FS) 1031 unsigned count; 1032 1033 struct drm_minor *minor = rdev->ddev->primary; 1034 struct dentry *root = minor->debugfs_root; 1035 1036 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, 1037 root, rdev, 1038 &radeon_ttm_vram_fops); 1039 1040 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, 1041 root, rdev, &radeon_ttm_gtt_fops); 1042 1043 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1044 1045 #ifdef CONFIG_SWIOTLB 1046 if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) 1047 --count; 1048 #endif 1049 1050 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1051 #else 1052 1053 return 0; 1054 #endif 1055 } 1056 1057 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1058 { 1059 #if defined(CONFIG_DEBUG_FS) 1060 1061 debugfs_remove(rdev->mman.vram); 1062 rdev->mman.vram = NULL; 1063 1064 debugfs_remove(rdev->mman.gtt); 1065 rdev->mman.gtt = NULL; 1066 #endif 1067 } 1068