1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/pagemap.h> 35 #include <linux/pci.h> 36 #include <linux/seq_file.h> 37 #include <linux/slab.h> 38 #include <linux/swap.h> 39 #include <linux/swiotlb.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_debugfs.h> 43 #include <drm/drm_device.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_prime.h> 46 #include <drm/radeon_drm.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 #include <drm/ttm/ttm_placement.h> 52 53 #include "radeon_reg.h" 54 #include "radeon.h" 55 56 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 57 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 58 59 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 60 { 61 struct radeon_mman *mman; 62 struct radeon_device *rdev; 63 64 mman = container_of(bdev, struct radeon_mman, bdev); 65 rdev = container_of(mman, struct radeon_device, mman); 66 return rdev; 67 } 68 69 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 70 struct ttm_mem_type_manager *man) 71 { 72 struct radeon_device *rdev; 73 74 rdev = radeon_get_rdev(bdev); 75 76 switch (type) { 77 case TTM_PL_SYSTEM: 78 /* System memory */ 79 man->flags = 0; 80 man->available_caching = TTM_PL_MASK_CACHING; 81 man->default_caching = TTM_PL_FLAG_CACHED; 82 break; 83 case TTM_PL_TT: 84 man->func = &ttm_bo_manager_func; 85 man->available_caching = TTM_PL_MASK_CACHING; 86 man->default_caching = TTM_PL_FLAG_CACHED; 87 man->flags = 0; 88 #if IS_ENABLED(CONFIG_AGP) 89 if (rdev->flags & RADEON_IS_AGP) { 90 if (!rdev->ddev->agp) { 91 DRM_ERROR("AGP is not enabled for memory type %u\n", 92 (unsigned)type); 93 return -EINVAL; 94 } 95 man->available_caching = TTM_PL_FLAG_UNCACHED | 96 TTM_PL_FLAG_WC; 97 man->default_caching = TTM_PL_FLAG_WC; 98 } 99 #endif 100 break; 101 case TTM_PL_VRAM: 102 /* "On-card" video ram */ 103 man->func = &ttm_bo_manager_func; 104 man->flags = TTM_MEMTYPE_FLAG_FIXED; 105 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 106 man->default_caching = TTM_PL_FLAG_WC; 107 break; 108 default: 109 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 110 return -EINVAL; 111 } 112 return 0; 113 } 114 115 static void radeon_evict_flags(struct ttm_buffer_object *bo, 116 struct ttm_placement *placement) 117 { 118 static const struct ttm_place placements = { 119 .fpfn = 0, 120 .lpfn = 0, 121 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 122 }; 123 124 struct radeon_bo *rbo; 125 126 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 127 placement->placement = &placements; 128 placement->busy_placement = &placements; 129 placement->num_placement = 1; 130 placement->num_busy_placement = 1; 131 return; 132 } 133 rbo = container_of(bo, struct radeon_bo, tbo); 134 switch (bo->mem.mem_type) { 135 case TTM_PL_VRAM: 136 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 137 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 138 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 139 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 140 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 141 int i; 142 143 /* Try evicting to the CPU inaccessible part of VRAM 144 * first, but only set GTT as busy placement, so this 145 * BO will be evicted to GTT rather than causing other 146 * BOs to be evicted from VRAM 147 */ 148 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 149 RADEON_GEM_DOMAIN_GTT); 150 rbo->placement.num_busy_placement = 0; 151 for (i = 0; i < rbo->placement.num_placement; i++) { 152 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 153 if (rbo->placements[i].fpfn < fpfn) 154 rbo->placements[i].fpfn = fpfn; 155 } else { 156 rbo->placement.busy_placement = 157 &rbo->placements[i]; 158 rbo->placement.num_busy_placement = 1; 159 } 160 } 161 } else 162 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 163 break; 164 case TTM_PL_TT: 165 default: 166 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 167 } 168 *placement = rbo->placement; 169 } 170 171 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 172 { 173 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 174 175 if (radeon_ttm_tt_has_userptr(bo->ttm)) 176 return -EPERM; 177 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, 178 filp->private_data); 179 } 180 181 static void radeon_move_null(struct ttm_buffer_object *bo, 182 struct ttm_mem_reg *new_mem) 183 { 184 struct ttm_mem_reg *old_mem = &bo->mem; 185 186 BUG_ON(old_mem->mm_node != NULL); 187 *old_mem = *new_mem; 188 new_mem->mm_node = NULL; 189 } 190 191 static int radeon_move_blit(struct ttm_buffer_object *bo, 192 bool evict, bool no_wait_gpu, 193 struct ttm_mem_reg *new_mem, 194 struct ttm_mem_reg *old_mem) 195 { 196 struct radeon_device *rdev; 197 uint64_t old_start, new_start; 198 struct radeon_fence *fence; 199 unsigned num_pages; 200 int r, ridx; 201 202 rdev = radeon_get_rdev(bo->bdev); 203 ridx = radeon_copy_ring_index(rdev); 204 old_start = (u64)old_mem->start << PAGE_SHIFT; 205 new_start = (u64)new_mem->start << PAGE_SHIFT; 206 207 switch (old_mem->mem_type) { 208 case TTM_PL_VRAM: 209 old_start += rdev->mc.vram_start; 210 break; 211 case TTM_PL_TT: 212 old_start += rdev->mc.gtt_start; 213 break; 214 default: 215 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 216 return -EINVAL; 217 } 218 switch (new_mem->mem_type) { 219 case TTM_PL_VRAM: 220 new_start += rdev->mc.vram_start; 221 break; 222 case TTM_PL_TT: 223 new_start += rdev->mc.gtt_start; 224 break; 225 default: 226 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 227 return -EINVAL; 228 } 229 if (!rdev->ring[ridx].ready) { 230 DRM_ERROR("Trying to move memory with ring turned off.\n"); 231 return -EINVAL; 232 } 233 234 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 235 236 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 237 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); 238 if (IS_ERR(fence)) 239 return PTR_ERR(fence); 240 241 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); 242 radeon_fence_unref(&fence); 243 return r; 244 } 245 246 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 247 bool evict, bool interruptible, 248 bool no_wait_gpu, 249 struct ttm_mem_reg *new_mem) 250 { 251 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 252 struct ttm_mem_reg *old_mem = &bo->mem; 253 struct ttm_mem_reg tmp_mem; 254 struct ttm_place placements; 255 struct ttm_placement placement; 256 int r; 257 258 tmp_mem = *new_mem; 259 tmp_mem.mm_node = NULL; 260 placement.num_placement = 1; 261 placement.placement = &placements; 262 placement.num_busy_placement = 1; 263 placement.busy_placement = &placements; 264 placements.fpfn = 0; 265 placements.lpfn = 0; 266 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 267 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 268 if (unlikely(r)) { 269 return r; 270 } 271 272 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 273 if (unlikely(r)) { 274 goto out_cleanup; 275 } 276 277 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); 278 if (unlikely(r)) { 279 goto out_cleanup; 280 } 281 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 282 if (unlikely(r)) { 283 goto out_cleanup; 284 } 285 r = ttm_bo_move_ttm(bo, &ctx, new_mem); 286 out_cleanup: 287 ttm_bo_mem_put(bo, &tmp_mem); 288 return r; 289 } 290 291 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 292 bool evict, bool interruptible, 293 bool no_wait_gpu, 294 struct ttm_mem_reg *new_mem) 295 { 296 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 297 struct ttm_mem_reg *old_mem = &bo->mem; 298 struct ttm_mem_reg tmp_mem; 299 struct ttm_placement placement; 300 struct ttm_place placements; 301 int r; 302 303 tmp_mem = *new_mem; 304 tmp_mem.mm_node = NULL; 305 placement.num_placement = 1; 306 placement.placement = &placements; 307 placement.num_busy_placement = 1; 308 placement.busy_placement = &placements; 309 placements.fpfn = 0; 310 placements.lpfn = 0; 311 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 312 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 313 if (unlikely(r)) { 314 return r; 315 } 316 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); 317 if (unlikely(r)) { 318 goto out_cleanup; 319 } 320 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 321 if (unlikely(r)) { 322 goto out_cleanup; 323 } 324 out_cleanup: 325 ttm_bo_mem_put(bo, &tmp_mem); 326 return r; 327 } 328 329 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, 330 struct ttm_operation_ctx *ctx, 331 struct ttm_mem_reg *new_mem) 332 { 333 struct radeon_device *rdev; 334 struct radeon_bo *rbo; 335 struct ttm_mem_reg *old_mem = &bo->mem; 336 int r; 337 338 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 339 if (r) 340 return r; 341 342 /* Can't move a pinned BO */ 343 rbo = container_of(bo, struct radeon_bo, tbo); 344 if (WARN_ON_ONCE(rbo->pin_count > 0)) 345 return -EINVAL; 346 347 rdev = radeon_get_rdev(bo->bdev); 348 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 349 radeon_move_null(bo, new_mem); 350 return 0; 351 } 352 if ((old_mem->mem_type == TTM_PL_TT && 353 new_mem->mem_type == TTM_PL_SYSTEM) || 354 (old_mem->mem_type == TTM_PL_SYSTEM && 355 new_mem->mem_type == TTM_PL_TT)) { 356 /* bind is enough */ 357 radeon_move_null(bo, new_mem); 358 return 0; 359 } 360 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 361 rdev->asic->copy.copy == NULL) { 362 /* use memcpy */ 363 goto memcpy; 364 } 365 366 if (old_mem->mem_type == TTM_PL_VRAM && 367 new_mem->mem_type == TTM_PL_SYSTEM) { 368 r = radeon_move_vram_ram(bo, evict, ctx->interruptible, 369 ctx->no_wait_gpu, new_mem); 370 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 371 new_mem->mem_type == TTM_PL_VRAM) { 372 r = radeon_move_ram_vram(bo, evict, ctx->interruptible, 373 ctx->no_wait_gpu, new_mem); 374 } else { 375 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, 376 new_mem, old_mem); 377 } 378 379 if (r) { 380 memcpy: 381 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 382 if (r) { 383 return r; 384 } 385 } 386 387 /* update statistics */ 388 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 389 return 0; 390 } 391 392 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 393 { 394 struct radeon_device *rdev = radeon_get_rdev(bdev); 395 396 mem->bus.addr = NULL; 397 mem->bus.offset = 0; 398 mem->bus.size = mem->num_pages << PAGE_SHIFT; 399 mem->bus.base = 0; 400 mem->bus.is_iomem = false; 401 402 switch (mem->mem_type) { 403 case TTM_PL_SYSTEM: 404 /* system memory */ 405 return 0; 406 case TTM_PL_TT: 407 #if IS_ENABLED(CONFIG_AGP) 408 if (rdev->flags & RADEON_IS_AGP) { 409 /* RADEON_IS_AGP is set only if AGP is active */ 410 mem->bus.offset = mem->start << PAGE_SHIFT; 411 mem->bus.base = rdev->mc.agp_base; 412 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 413 } 414 #endif 415 break; 416 case TTM_PL_VRAM: 417 mem->bus.offset = mem->start << PAGE_SHIFT; 418 /* check if it's visible */ 419 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 420 return -EINVAL; 421 mem->bus.base = rdev->mc.aper_base; 422 mem->bus.is_iomem = true; 423 #ifdef __alpha__ 424 /* 425 * Alpha: use bus.addr to hold the ioremap() return, 426 * so we can modify bus.base below. 427 */ 428 if (mem->placement & TTM_PL_FLAG_WC) 429 mem->bus.addr = 430 ioremap_wc(mem->bus.base + mem->bus.offset, 431 mem->bus.size); 432 else 433 mem->bus.addr = 434 ioremap(mem->bus.base + mem->bus.offset, 435 mem->bus.size); 436 if (!mem->bus.addr) 437 return -ENOMEM; 438 439 /* 440 * Alpha: Use just the bus offset plus 441 * the hose/domain memory base for bus.base. 442 * It then can be used to build PTEs for VRAM 443 * access, as done in ttm_bo_vm_fault(). 444 */ 445 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 446 rdev->ddev->hose->dense_mem_base; 447 #endif 448 break; 449 default: 450 return -EINVAL; 451 } 452 return 0; 453 } 454 455 /* 456 * TTM backend functions. 457 */ 458 struct radeon_ttm_tt { 459 struct ttm_dma_tt ttm; 460 struct radeon_device *rdev; 461 u64 offset; 462 463 uint64_t userptr; 464 struct mm_struct *usermm; 465 uint32_t userflags; 466 }; 467 468 /* prepare the sg table with the user pages */ 469 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) 470 { 471 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 472 struct radeon_ttm_tt *gtt = (void *)ttm; 473 unsigned pinned = 0; 474 int r; 475 476 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 477 enum dma_data_direction direction = write ? 478 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 479 480 if (current->mm != gtt->usermm) 481 return -EPERM; 482 483 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 484 /* check that we only pin down anonymous memory 485 to prevent problems with writeback */ 486 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 487 struct vm_area_struct *vma; 488 vma = find_vma(gtt->usermm, gtt->userptr); 489 if (!vma || vma->vm_file || vma->vm_end < end) 490 return -EPERM; 491 } 492 493 do { 494 unsigned num_pages = ttm->num_pages - pinned; 495 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 496 struct page **pages = ttm->pages + pinned; 497 498 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, 499 pages, NULL); 500 if (r < 0) 501 goto release_pages; 502 503 pinned += r; 504 505 } while (pinned < ttm->num_pages); 506 507 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 508 ttm->num_pages << PAGE_SHIFT, 509 GFP_KERNEL); 510 if (r) 511 goto release_sg; 512 513 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); 514 if (r) 515 goto release_sg; 516 517 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 518 gtt->ttm.dma_address, ttm->num_pages); 519 520 return 0; 521 522 release_sg: 523 kfree(ttm->sg); 524 525 release_pages: 526 release_pages(ttm->pages, pinned); 527 return r; 528 } 529 530 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 531 { 532 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 533 struct radeon_ttm_tt *gtt = (void *)ttm; 534 struct sg_page_iter sg_iter; 535 536 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 537 enum dma_data_direction direction = write ? 538 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 539 540 /* double check that we don't free the table twice */ 541 if (!ttm->sg->sgl) 542 return; 543 544 /* free the sg table and pages again */ 545 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); 546 547 for_each_sgtable_page(ttm->sg, &sg_iter, 0) { 548 struct page *page = sg_page_iter_page(&sg_iter); 549 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) 550 set_page_dirty(page); 551 552 mark_page_accessed(page); 553 put_page(page); 554 } 555 556 sg_free_table(ttm->sg); 557 } 558 559 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 560 struct ttm_mem_reg *bo_mem) 561 { 562 struct radeon_ttm_tt *gtt = (void*)ttm; 563 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 564 RADEON_GART_PAGE_WRITE; 565 int r; 566 567 if (gtt->userptr) { 568 radeon_ttm_tt_pin_userptr(ttm); 569 flags &= ~RADEON_GART_PAGE_WRITE; 570 } 571 572 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 573 if (!ttm->num_pages) { 574 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 575 ttm->num_pages, bo_mem, ttm); 576 } 577 if (ttm->caching_state == tt_cached) 578 flags |= RADEON_GART_PAGE_SNOOP; 579 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 580 ttm->pages, gtt->ttm.dma_address, flags); 581 if (r) { 582 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 583 ttm->num_pages, (unsigned)gtt->offset); 584 return r; 585 } 586 return 0; 587 } 588 589 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 590 { 591 struct radeon_ttm_tt *gtt = (void *)ttm; 592 593 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 594 595 if (gtt->userptr) 596 radeon_ttm_tt_unpin_userptr(ttm); 597 598 return 0; 599 } 600 601 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 602 { 603 struct radeon_ttm_tt *gtt = (void *)ttm; 604 605 ttm_dma_tt_fini(>t->ttm); 606 kfree(gtt); 607 } 608 609 static struct ttm_backend_func radeon_backend_func = { 610 .bind = &radeon_ttm_backend_bind, 611 .unbind = &radeon_ttm_backend_unbind, 612 .destroy = &radeon_ttm_backend_destroy, 613 }; 614 615 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, 616 uint32_t page_flags) 617 { 618 struct radeon_device *rdev; 619 struct radeon_ttm_tt *gtt; 620 621 rdev = radeon_get_rdev(bo->bdev); 622 #if IS_ENABLED(CONFIG_AGP) 623 if (rdev->flags & RADEON_IS_AGP) { 624 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, 625 page_flags); 626 } 627 #endif 628 629 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 630 if (gtt == NULL) { 631 return NULL; 632 } 633 gtt->ttm.ttm.func = &radeon_backend_func; 634 gtt->rdev = rdev; 635 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { 636 kfree(gtt); 637 return NULL; 638 } 639 return >t->ttm.ttm; 640 } 641 642 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) 643 { 644 if (!ttm || ttm->func != &radeon_backend_func) 645 return NULL; 646 return (struct radeon_ttm_tt *)ttm; 647 } 648 649 static int radeon_ttm_tt_populate(struct ttm_tt *ttm, 650 struct ttm_operation_ctx *ctx) 651 { 652 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 653 struct radeon_device *rdev; 654 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 655 656 if (gtt && gtt->userptr) { 657 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 658 if (!ttm->sg) 659 return -ENOMEM; 660 661 ttm->page_flags |= TTM_PAGE_FLAG_SG; 662 ttm->state = tt_unbound; 663 return 0; 664 } 665 666 if (slave && ttm->sg) { 667 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 668 gtt->ttm.dma_address, ttm->num_pages); 669 ttm->state = tt_unbound; 670 return 0; 671 } 672 673 rdev = radeon_get_rdev(ttm->bdev); 674 #if IS_ENABLED(CONFIG_AGP) 675 if (rdev->flags & RADEON_IS_AGP) { 676 return ttm_agp_tt_populate(ttm, ctx); 677 } 678 #endif 679 680 #ifdef CONFIG_SWIOTLB 681 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 682 return ttm_dma_populate(>t->ttm, rdev->dev, ctx); 683 } 684 #endif 685 686 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); 687 } 688 689 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 690 { 691 struct radeon_device *rdev; 692 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 693 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 694 695 if (gtt && gtt->userptr) { 696 kfree(ttm->sg); 697 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 698 return; 699 } 700 701 if (slave) 702 return; 703 704 rdev = radeon_get_rdev(ttm->bdev); 705 #if IS_ENABLED(CONFIG_AGP) 706 if (rdev->flags & RADEON_IS_AGP) { 707 ttm_agp_tt_unpopulate(ttm); 708 return; 709 } 710 #endif 711 712 #ifdef CONFIG_SWIOTLB 713 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 714 ttm_dma_unpopulate(>t->ttm, rdev->dev); 715 return; 716 } 717 #endif 718 719 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); 720 } 721 722 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 723 uint32_t flags) 724 { 725 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 726 727 if (gtt == NULL) 728 return -EINVAL; 729 730 gtt->userptr = addr; 731 gtt->usermm = current->mm; 732 gtt->userflags = flags; 733 return 0; 734 } 735 736 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) 737 { 738 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 739 740 if (gtt == NULL) 741 return false; 742 743 return !!gtt->userptr; 744 } 745 746 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) 747 { 748 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 749 750 if (gtt == NULL) 751 return false; 752 753 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 754 } 755 756 static struct ttm_bo_driver radeon_bo_driver = { 757 .ttm_tt_create = &radeon_ttm_tt_create, 758 .ttm_tt_populate = &radeon_ttm_tt_populate, 759 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 760 .init_mem_type = &radeon_init_mem_type, 761 .eviction_valuable = ttm_bo_eviction_valuable, 762 .evict_flags = &radeon_evict_flags, 763 .move = &radeon_bo_move, 764 .verify_access = &radeon_verify_access, 765 .move_notify = &radeon_bo_move_notify, 766 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 767 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 768 }; 769 770 int radeon_ttm_init(struct radeon_device *rdev) 771 { 772 int r; 773 774 /* No others user of address space so set it to 0 */ 775 r = ttm_bo_device_init(&rdev->mman.bdev, 776 &radeon_bo_driver, 777 rdev->ddev->anon_inode->i_mapping, 778 rdev->ddev->vma_offset_manager, 779 dma_addressing_limited(&rdev->pdev->dev)); 780 if (r) { 781 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 782 return r; 783 } 784 rdev->mman.initialized = true; 785 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 786 rdev->mc.real_vram_size >> PAGE_SHIFT); 787 if (r) { 788 DRM_ERROR("Failed initializing VRAM heap.\n"); 789 return r; 790 } 791 /* Change the size here instead of the init above so only lpfn is affected */ 792 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 793 794 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 795 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 796 NULL, &rdev->stolen_vga_memory); 797 if (r) { 798 return r; 799 } 800 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 801 if (r) 802 return r; 803 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 804 radeon_bo_unreserve(rdev->stolen_vga_memory); 805 if (r) { 806 radeon_bo_unref(&rdev->stolen_vga_memory); 807 return r; 808 } 809 DRM_INFO("radeon: %uM of VRAM memory ready\n", 810 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 811 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 812 rdev->mc.gtt_size >> PAGE_SHIFT); 813 if (r) { 814 DRM_ERROR("Failed initializing GTT heap.\n"); 815 return r; 816 } 817 DRM_INFO("radeon: %uM of GTT memory ready.\n", 818 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 819 820 r = radeon_ttm_debugfs_init(rdev); 821 if (r) { 822 DRM_ERROR("Failed to init debugfs\n"); 823 return r; 824 } 825 return 0; 826 } 827 828 void radeon_ttm_fini(struct radeon_device *rdev) 829 { 830 int r; 831 832 if (!rdev->mman.initialized) 833 return; 834 radeon_ttm_debugfs_fini(rdev); 835 if (rdev->stolen_vga_memory) { 836 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 837 if (r == 0) { 838 radeon_bo_unpin(rdev->stolen_vga_memory); 839 radeon_bo_unreserve(rdev->stolen_vga_memory); 840 } 841 radeon_bo_unref(&rdev->stolen_vga_memory); 842 } 843 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 844 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 845 ttm_bo_device_release(&rdev->mman.bdev); 846 radeon_gart_fini(rdev); 847 rdev->mman.initialized = false; 848 DRM_INFO("radeon: ttm finalized\n"); 849 } 850 851 /* this should only be called at bootup or when userspace 852 * isn't running */ 853 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 854 { 855 struct ttm_mem_type_manager *man; 856 857 if (!rdev->mman.initialized) 858 return; 859 860 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 861 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 862 man->size = size >> PAGE_SHIFT; 863 } 864 865 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) 866 { 867 struct ttm_buffer_object *bo; 868 struct radeon_device *rdev; 869 vm_fault_t ret; 870 871 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; 872 if (bo == NULL) 873 return VM_FAULT_NOPAGE; 874 875 rdev = radeon_get_rdev(bo->bdev); 876 down_read(&rdev->pm.mclk_lock); 877 ret = ttm_bo_vm_fault(vmf); 878 up_read(&rdev->pm.mclk_lock); 879 return ret; 880 } 881 882 static struct vm_operations_struct radeon_ttm_vm_ops = { 883 .fault = radeon_ttm_fault, 884 .open = ttm_bo_vm_open, 885 .close = ttm_bo_vm_close, 886 .access = ttm_bo_vm_access 887 }; 888 889 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 890 { 891 int r; 892 struct drm_file *file_priv = filp->private_data; 893 struct radeon_device *rdev = file_priv->minor->dev->dev_private; 894 895 if (rdev == NULL) 896 return -EINVAL; 897 898 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 899 if (unlikely(r != 0)) 900 return r; 901 902 vma->vm_ops = &radeon_ttm_vm_ops; 903 return 0; 904 } 905 906 #if defined(CONFIG_DEBUG_FS) 907 908 static int radeon_mm_dump_table(struct seq_file *m, void *data) 909 { 910 struct drm_info_node *node = (struct drm_info_node *)m->private; 911 unsigned ttm_pl = *(int*)node->info_ent->data; 912 struct drm_device *dev = node->minor->dev; 913 struct radeon_device *rdev = dev->dev_private; 914 struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; 915 struct drm_printer p = drm_seq_file_printer(m); 916 917 man->func->debug(man, &p); 918 return 0; 919 } 920 921 922 static int ttm_pl_vram = TTM_PL_VRAM; 923 static int ttm_pl_tt = TTM_PL_TT; 924 925 static struct drm_info_list radeon_ttm_debugfs_list[] = { 926 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 927 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 928 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 929 #ifdef CONFIG_SWIOTLB 930 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 931 #endif 932 }; 933 934 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 935 { 936 struct radeon_device *rdev = inode->i_private; 937 i_size_write(inode, rdev->mc.mc_vram_size); 938 filep->private_data = inode->i_private; 939 return 0; 940 } 941 942 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 943 size_t size, loff_t *pos) 944 { 945 struct radeon_device *rdev = f->private_data; 946 ssize_t result = 0; 947 int r; 948 949 if (size & 0x3 || *pos & 0x3) 950 return -EINVAL; 951 952 while (size) { 953 unsigned long flags; 954 uint32_t value; 955 956 if (*pos >= rdev->mc.mc_vram_size) 957 return result; 958 959 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 960 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 961 if (rdev->family >= CHIP_CEDAR) 962 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 963 value = RREG32(RADEON_MM_DATA); 964 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 965 966 r = put_user(value, (uint32_t *)buf); 967 if (r) 968 return r; 969 970 result += 4; 971 buf += 4; 972 *pos += 4; 973 size -= 4; 974 } 975 976 return result; 977 } 978 979 static const struct file_operations radeon_ttm_vram_fops = { 980 .owner = THIS_MODULE, 981 .open = radeon_ttm_vram_open, 982 .read = radeon_ttm_vram_read, 983 .llseek = default_llseek 984 }; 985 986 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 987 { 988 struct radeon_device *rdev = inode->i_private; 989 i_size_write(inode, rdev->mc.gtt_size); 990 filep->private_data = inode->i_private; 991 return 0; 992 } 993 994 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 995 size_t size, loff_t *pos) 996 { 997 struct radeon_device *rdev = f->private_data; 998 ssize_t result = 0; 999 int r; 1000 1001 while (size) { 1002 loff_t p = *pos / PAGE_SIZE; 1003 unsigned off = *pos & ~PAGE_MASK; 1004 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1005 struct page *page; 1006 void *ptr; 1007 1008 if (p >= rdev->gart.num_cpu_pages) 1009 return result; 1010 1011 page = rdev->gart.pages[p]; 1012 if (page) { 1013 ptr = kmap(page); 1014 ptr += off; 1015 1016 r = copy_to_user(buf, ptr, cur_size); 1017 kunmap(rdev->gart.pages[p]); 1018 } else 1019 r = clear_user(buf, cur_size); 1020 1021 if (r) 1022 return -EFAULT; 1023 1024 result += cur_size; 1025 buf += cur_size; 1026 *pos += cur_size; 1027 size -= cur_size; 1028 } 1029 1030 return result; 1031 } 1032 1033 static const struct file_operations radeon_ttm_gtt_fops = { 1034 .owner = THIS_MODULE, 1035 .open = radeon_ttm_gtt_open, 1036 .read = radeon_ttm_gtt_read, 1037 .llseek = default_llseek 1038 }; 1039 1040 #endif 1041 1042 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1043 { 1044 #if defined(CONFIG_DEBUG_FS) 1045 unsigned count; 1046 1047 struct drm_minor *minor = rdev->ddev->primary; 1048 struct dentry *root = minor->debugfs_root; 1049 1050 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, 1051 root, rdev, 1052 &radeon_ttm_vram_fops); 1053 1054 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, 1055 root, rdev, &radeon_ttm_gtt_fops); 1056 1057 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1058 1059 #ifdef CONFIG_SWIOTLB 1060 if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) 1061 --count; 1062 #endif 1063 1064 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1065 #else 1066 1067 return 0; 1068 #endif 1069 } 1070 1071 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1072 { 1073 #if defined(CONFIG_DEBUG_FS) 1074 1075 debugfs_remove(rdev->mman.vram); 1076 rdev->mman.vram = NULL; 1077 1078 debugfs_remove(rdev->mman.gtt); 1079 rdev->mman.gtt = NULL; 1080 #endif 1081 } 1082