1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/pagemap.h> 35 #include <linux/pci.h> 36 #include <linux/seq_file.h> 37 #include <linux/slab.h> 38 #include <linux/swap.h> 39 #include <linux/swiotlb.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_debugfs.h> 43 #include <drm/drm_device.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_prime.h> 46 #include <drm/radeon_drm.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 #include <drm/ttm/ttm_placement.h> 52 53 #include "radeon_reg.h" 54 #include "radeon.h" 55 56 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 57 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 58 59 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 60 { 61 struct radeon_mman *mman; 62 struct radeon_device *rdev; 63 64 mman = container_of(bdev, struct radeon_mman, bdev); 65 rdev = container_of(mman, struct radeon_device, mman); 66 return rdev; 67 } 68 69 static int radeon_ttm_init_vram(struct radeon_device *rdev) 70 { 71 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM, 72 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC, 73 TTM_PL_FLAG_WC, false, 74 rdev->mc.real_vram_size >> PAGE_SHIFT); 75 } 76 77 static int radeon_ttm_init_gtt(struct radeon_device *rdev) 78 { 79 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT, 80 TTM_PL_MASK_CACHING, 81 TTM_PL_FLAG_CACHED, true, 82 rdev->mc.gtt_size >> PAGE_SHIFT); 83 } 84 85 static void radeon_evict_flags(struct ttm_buffer_object *bo, 86 struct ttm_placement *placement) 87 { 88 static const struct ttm_place placements = { 89 .fpfn = 0, 90 .lpfn = 0, 91 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 92 }; 93 94 struct radeon_bo *rbo; 95 96 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 97 placement->placement = &placements; 98 placement->busy_placement = &placements; 99 placement->num_placement = 1; 100 placement->num_busy_placement = 1; 101 return; 102 } 103 rbo = container_of(bo, struct radeon_bo, tbo); 104 switch (bo->mem.mem_type) { 105 case TTM_PL_VRAM: 106 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 107 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 108 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 109 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 110 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 111 int i; 112 113 /* Try evicting to the CPU inaccessible part of VRAM 114 * first, but only set GTT as busy placement, so this 115 * BO will be evicted to GTT rather than causing other 116 * BOs to be evicted from VRAM 117 */ 118 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 119 RADEON_GEM_DOMAIN_GTT); 120 rbo->placement.num_busy_placement = 0; 121 for (i = 0; i < rbo->placement.num_placement; i++) { 122 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 123 if (rbo->placements[i].fpfn < fpfn) 124 rbo->placements[i].fpfn = fpfn; 125 } else { 126 rbo->placement.busy_placement = 127 &rbo->placements[i]; 128 rbo->placement.num_busy_placement = 1; 129 } 130 } 131 } else 132 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 133 break; 134 case TTM_PL_TT: 135 default: 136 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 137 } 138 *placement = rbo->placement; 139 } 140 141 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 142 { 143 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 144 145 if (radeon_ttm_tt_has_userptr(bo->ttm)) 146 return -EPERM; 147 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, 148 filp->private_data); 149 } 150 151 static void radeon_move_null(struct ttm_buffer_object *bo, 152 struct ttm_resource *new_mem) 153 { 154 struct ttm_resource *old_mem = &bo->mem; 155 156 BUG_ON(old_mem->mm_node != NULL); 157 *old_mem = *new_mem; 158 new_mem->mm_node = NULL; 159 } 160 161 static int radeon_move_blit(struct ttm_buffer_object *bo, 162 bool evict, bool no_wait_gpu, 163 struct ttm_resource *new_mem, 164 struct ttm_resource *old_mem) 165 { 166 struct radeon_device *rdev; 167 uint64_t old_start, new_start; 168 struct radeon_fence *fence; 169 unsigned num_pages; 170 int r, ridx; 171 172 rdev = radeon_get_rdev(bo->bdev); 173 ridx = radeon_copy_ring_index(rdev); 174 old_start = (u64)old_mem->start << PAGE_SHIFT; 175 new_start = (u64)new_mem->start << PAGE_SHIFT; 176 177 switch (old_mem->mem_type) { 178 case TTM_PL_VRAM: 179 old_start += rdev->mc.vram_start; 180 break; 181 case TTM_PL_TT: 182 old_start += rdev->mc.gtt_start; 183 break; 184 default: 185 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 186 return -EINVAL; 187 } 188 switch (new_mem->mem_type) { 189 case TTM_PL_VRAM: 190 new_start += rdev->mc.vram_start; 191 break; 192 case TTM_PL_TT: 193 new_start += rdev->mc.gtt_start; 194 break; 195 default: 196 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 197 return -EINVAL; 198 } 199 if (!rdev->ring[ridx].ready) { 200 DRM_ERROR("Trying to move memory with ring turned off.\n"); 201 return -EINVAL; 202 } 203 204 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 205 206 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 207 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); 208 if (IS_ERR(fence)) 209 return PTR_ERR(fence); 210 211 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); 212 radeon_fence_unref(&fence); 213 return r; 214 } 215 216 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 217 bool evict, bool interruptible, 218 bool no_wait_gpu, 219 struct ttm_resource *new_mem) 220 { 221 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 222 struct ttm_resource *old_mem = &bo->mem; 223 struct ttm_resource tmp_mem; 224 struct ttm_place placements; 225 struct ttm_placement placement; 226 int r; 227 228 tmp_mem = *new_mem; 229 tmp_mem.mm_node = NULL; 230 placement.num_placement = 1; 231 placement.placement = &placements; 232 placement.num_busy_placement = 1; 233 placement.busy_placement = &placements; 234 placements.fpfn = 0; 235 placements.lpfn = 0; 236 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 237 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 238 if (unlikely(r)) { 239 return r; 240 } 241 242 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 243 if (unlikely(r)) { 244 goto out_cleanup; 245 } 246 247 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); 248 if (unlikely(r)) { 249 goto out_cleanup; 250 } 251 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 252 if (unlikely(r)) { 253 goto out_cleanup; 254 } 255 r = ttm_bo_move_ttm(bo, &ctx, new_mem); 256 out_cleanup: 257 ttm_resource_free(bo, &tmp_mem); 258 return r; 259 } 260 261 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 262 bool evict, bool interruptible, 263 bool no_wait_gpu, 264 struct ttm_resource *new_mem) 265 { 266 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 267 struct ttm_resource *old_mem = &bo->mem; 268 struct ttm_resource tmp_mem; 269 struct ttm_placement placement; 270 struct ttm_place placements; 271 int r; 272 273 tmp_mem = *new_mem; 274 tmp_mem.mm_node = NULL; 275 placement.num_placement = 1; 276 placement.placement = &placements; 277 placement.num_busy_placement = 1; 278 placement.busy_placement = &placements; 279 placements.fpfn = 0; 280 placements.lpfn = 0; 281 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 282 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 283 if (unlikely(r)) { 284 return r; 285 } 286 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); 287 if (unlikely(r)) { 288 goto out_cleanup; 289 } 290 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 291 if (unlikely(r)) { 292 goto out_cleanup; 293 } 294 out_cleanup: 295 ttm_resource_free(bo, &tmp_mem); 296 return r; 297 } 298 299 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, 300 struct ttm_operation_ctx *ctx, 301 struct ttm_resource *new_mem) 302 { 303 struct radeon_device *rdev; 304 struct radeon_bo *rbo; 305 struct ttm_resource *old_mem = &bo->mem; 306 int r; 307 308 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 309 if (r) 310 return r; 311 312 /* Can't move a pinned BO */ 313 rbo = container_of(bo, struct radeon_bo, tbo); 314 if (WARN_ON_ONCE(rbo->pin_count > 0)) 315 return -EINVAL; 316 317 rdev = radeon_get_rdev(bo->bdev); 318 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 319 radeon_move_null(bo, new_mem); 320 return 0; 321 } 322 if ((old_mem->mem_type == TTM_PL_TT && 323 new_mem->mem_type == TTM_PL_SYSTEM) || 324 (old_mem->mem_type == TTM_PL_SYSTEM && 325 new_mem->mem_type == TTM_PL_TT)) { 326 /* bind is enough */ 327 radeon_move_null(bo, new_mem); 328 return 0; 329 } 330 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 331 rdev->asic->copy.copy == NULL) { 332 /* use memcpy */ 333 goto memcpy; 334 } 335 336 if (old_mem->mem_type == TTM_PL_VRAM && 337 new_mem->mem_type == TTM_PL_SYSTEM) { 338 r = radeon_move_vram_ram(bo, evict, ctx->interruptible, 339 ctx->no_wait_gpu, new_mem); 340 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 341 new_mem->mem_type == TTM_PL_VRAM) { 342 r = radeon_move_ram_vram(bo, evict, ctx->interruptible, 343 ctx->no_wait_gpu, new_mem); 344 } else { 345 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, 346 new_mem, old_mem); 347 } 348 349 if (r) { 350 memcpy: 351 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 352 if (r) { 353 return r; 354 } 355 } 356 357 /* update statistics */ 358 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 359 return 0; 360 } 361 362 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 363 { 364 struct radeon_device *rdev = radeon_get_rdev(bdev); 365 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 366 367 switch (mem->mem_type) { 368 case TTM_PL_SYSTEM: 369 /* system memory */ 370 return 0; 371 case TTM_PL_TT: 372 #if IS_ENABLED(CONFIG_AGP) 373 if (rdev->flags & RADEON_IS_AGP) { 374 /* RADEON_IS_AGP is set only if AGP is active */ 375 mem->bus.offset = mem->start << PAGE_SHIFT; 376 mem->bus.base = rdev->mc.agp_base; 377 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 378 } 379 #endif 380 break; 381 case TTM_PL_VRAM: 382 mem->bus.offset = mem->start << PAGE_SHIFT; 383 /* check if it's visible */ 384 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size) 385 return -EINVAL; 386 mem->bus.base = rdev->mc.aper_base; 387 mem->bus.is_iomem = true; 388 #ifdef __alpha__ 389 /* 390 * Alpha: use bus.addr to hold the ioremap() return, 391 * so we can modify bus.base below. 392 */ 393 if (mem->placement & TTM_PL_FLAG_WC) 394 mem->bus.addr = 395 ioremap_wc(mem->bus.base + mem->bus.offset, 396 bus_size); 397 else 398 mem->bus.addr = 399 ioremap(mem->bus.base + mem->bus.offset, 400 bus_size); 401 if (!mem->bus.addr) 402 return -ENOMEM; 403 404 /* 405 * Alpha: Use just the bus offset plus 406 * the hose/domain memory base for bus.base. 407 * It then can be used to build PTEs for VRAM 408 * access, as done in ttm_bo_vm_fault(). 409 */ 410 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 411 rdev->ddev->hose->dense_mem_base; 412 #endif 413 break; 414 default: 415 return -EINVAL; 416 } 417 return 0; 418 } 419 420 /* 421 * TTM backend functions. 422 */ 423 struct radeon_ttm_tt { 424 struct ttm_dma_tt ttm; 425 u64 offset; 426 427 uint64_t userptr; 428 struct mm_struct *usermm; 429 uint32_t userflags; 430 }; 431 432 /* prepare the sg table with the user pages */ 433 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) 434 { 435 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 436 struct radeon_ttm_tt *gtt = (void *)ttm; 437 unsigned pinned = 0; 438 int r; 439 440 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 441 enum dma_data_direction direction = write ? 442 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 443 444 if (current->mm != gtt->usermm) 445 return -EPERM; 446 447 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 448 /* check that we only pin down anonymous memory 449 to prevent problems with writeback */ 450 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 451 struct vm_area_struct *vma; 452 vma = find_vma(gtt->usermm, gtt->userptr); 453 if (!vma || vma->vm_file || vma->vm_end < end) 454 return -EPERM; 455 } 456 457 do { 458 unsigned num_pages = ttm->num_pages - pinned; 459 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 460 struct page **pages = ttm->pages + pinned; 461 462 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, 463 pages, NULL); 464 if (r < 0) 465 goto release_pages; 466 467 pinned += r; 468 469 } while (pinned < ttm->num_pages); 470 471 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 472 ttm->num_pages << PAGE_SHIFT, 473 GFP_KERNEL); 474 if (r) 475 goto release_sg; 476 477 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); 478 if (r) 479 goto release_sg; 480 481 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 482 gtt->ttm.dma_address, ttm->num_pages); 483 484 return 0; 485 486 release_sg: 487 kfree(ttm->sg); 488 489 release_pages: 490 release_pages(ttm->pages, pinned); 491 return r; 492 } 493 494 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 495 { 496 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 497 struct radeon_ttm_tt *gtt = (void *)ttm; 498 struct sg_page_iter sg_iter; 499 500 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 501 enum dma_data_direction direction = write ? 502 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 503 504 /* double check that we don't free the table twice */ 505 if (!ttm->sg->sgl) 506 return; 507 508 /* free the sg table and pages again */ 509 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); 510 511 for_each_sgtable_page(ttm->sg, &sg_iter, 0) { 512 struct page *page = sg_page_iter_page(&sg_iter); 513 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) 514 set_page_dirty(page); 515 516 mark_page_accessed(page); 517 put_page(page); 518 } 519 520 sg_free_table(ttm->sg); 521 } 522 523 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 524 struct ttm_resource *bo_mem) 525 { 526 struct radeon_ttm_tt *gtt = (void*)ttm; 527 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 528 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 529 RADEON_GART_PAGE_WRITE; 530 int r; 531 532 if (gtt->userptr) { 533 radeon_ttm_tt_pin_userptr(ttm); 534 flags &= ~RADEON_GART_PAGE_WRITE; 535 } 536 537 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 538 if (!ttm->num_pages) { 539 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 540 ttm->num_pages, bo_mem, ttm); 541 } 542 if (ttm->caching_state == tt_cached) 543 flags |= RADEON_GART_PAGE_SNOOP; 544 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages, 545 ttm->pages, gtt->ttm.dma_address, flags); 546 if (r) { 547 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 548 ttm->num_pages, (unsigned)gtt->offset); 549 return r; 550 } 551 return 0; 552 } 553 554 static void radeon_ttm_backend_unbind(struct ttm_tt *ttm) 555 { 556 struct radeon_ttm_tt *gtt = (void *)ttm; 557 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 558 559 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages); 560 561 if (gtt->userptr) 562 radeon_ttm_tt_unpin_userptr(ttm); 563 } 564 565 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 566 { 567 struct radeon_ttm_tt *gtt = (void *)ttm; 568 569 ttm_dma_tt_fini(>t->ttm); 570 kfree(gtt); 571 } 572 573 static struct ttm_backend_func radeon_backend_func = { 574 .bind = &radeon_ttm_backend_bind, 575 .unbind = &radeon_ttm_backend_unbind, 576 .destroy = &radeon_ttm_backend_destroy, 577 }; 578 579 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, 580 uint32_t page_flags) 581 { 582 struct radeon_device *rdev; 583 struct radeon_ttm_tt *gtt; 584 585 rdev = radeon_get_rdev(bo->bdev); 586 #if IS_ENABLED(CONFIG_AGP) 587 if (rdev->flags & RADEON_IS_AGP) { 588 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge, 589 page_flags); 590 } 591 #endif 592 593 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 594 if (gtt == NULL) { 595 return NULL; 596 } 597 gtt->ttm.ttm.func = &radeon_backend_func; 598 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { 599 kfree(gtt); 600 return NULL; 601 } 602 return >t->ttm.ttm; 603 } 604 605 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) 606 { 607 if (!ttm || ttm->func != &radeon_backend_func) 608 return NULL; 609 return (struct radeon_ttm_tt *)ttm; 610 } 611 612 static int radeon_ttm_tt_populate(struct ttm_tt *ttm, 613 struct ttm_operation_ctx *ctx) 614 { 615 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 616 struct radeon_device *rdev; 617 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 618 619 if (gtt && gtt->userptr) { 620 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 621 if (!ttm->sg) 622 return -ENOMEM; 623 624 ttm->page_flags |= TTM_PAGE_FLAG_SG; 625 ttm->state = tt_unbound; 626 return 0; 627 } 628 629 if (slave && ttm->sg) { 630 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 631 gtt->ttm.dma_address, ttm->num_pages); 632 ttm->state = tt_unbound; 633 return 0; 634 } 635 636 rdev = radeon_get_rdev(ttm->bdev); 637 #if IS_ENABLED(CONFIG_AGP) 638 if (rdev->flags & RADEON_IS_AGP) { 639 return ttm_agp_tt_populate(ttm, ctx); 640 } 641 #endif 642 643 #ifdef CONFIG_SWIOTLB 644 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 645 return ttm_dma_populate(>t->ttm, rdev->dev, ctx); 646 } 647 #endif 648 649 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); 650 } 651 652 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 653 { 654 struct radeon_device *rdev; 655 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 656 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 657 658 if (gtt && gtt->userptr) { 659 kfree(ttm->sg); 660 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 661 return; 662 } 663 664 if (slave) 665 return; 666 667 rdev = radeon_get_rdev(ttm->bdev); 668 #if IS_ENABLED(CONFIG_AGP) 669 if (rdev->flags & RADEON_IS_AGP) { 670 ttm_agp_tt_unpopulate(ttm); 671 return; 672 } 673 #endif 674 675 #ifdef CONFIG_SWIOTLB 676 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 677 ttm_dma_unpopulate(>t->ttm, rdev->dev); 678 return; 679 } 680 #endif 681 682 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); 683 } 684 685 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 686 uint32_t flags) 687 { 688 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 689 690 if (gtt == NULL) 691 return -EINVAL; 692 693 gtt->userptr = addr; 694 gtt->usermm = current->mm; 695 gtt->userflags = flags; 696 return 0; 697 } 698 699 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) 700 { 701 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 702 703 if (gtt == NULL) 704 return false; 705 706 return !!gtt->userptr; 707 } 708 709 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) 710 { 711 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 712 713 if (gtt == NULL) 714 return false; 715 716 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 717 } 718 719 static struct ttm_bo_driver radeon_bo_driver = { 720 .ttm_tt_create = &radeon_ttm_tt_create, 721 .ttm_tt_populate = &radeon_ttm_tt_populate, 722 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 723 .eviction_valuable = ttm_bo_eviction_valuable, 724 .evict_flags = &radeon_evict_flags, 725 .move = &radeon_bo_move, 726 .verify_access = &radeon_verify_access, 727 .move_notify = &radeon_bo_move_notify, 728 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 729 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 730 }; 731 732 int radeon_ttm_init(struct radeon_device *rdev) 733 { 734 int r; 735 736 /* No others user of address space so set it to 0 */ 737 r = ttm_bo_device_init(&rdev->mman.bdev, 738 &radeon_bo_driver, 739 rdev->ddev->anon_inode->i_mapping, 740 rdev->ddev->vma_offset_manager, 741 dma_addressing_limited(&rdev->pdev->dev)); 742 if (r) { 743 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 744 return r; 745 } 746 rdev->mman.initialized = true; 747 748 r = radeon_ttm_init_vram(rdev); 749 if (r) { 750 DRM_ERROR("Failed initializing VRAM heap.\n"); 751 return r; 752 } 753 /* Change the size here instead of the init above so only lpfn is affected */ 754 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 755 756 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 757 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 758 NULL, &rdev->stolen_vga_memory); 759 if (r) { 760 return r; 761 } 762 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 763 if (r) 764 return r; 765 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 766 radeon_bo_unreserve(rdev->stolen_vga_memory); 767 if (r) { 768 radeon_bo_unref(&rdev->stolen_vga_memory); 769 return r; 770 } 771 DRM_INFO("radeon: %uM of VRAM memory ready\n", 772 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 773 774 r = radeon_ttm_init_gtt(rdev); 775 if (r) { 776 DRM_ERROR("Failed initializing GTT heap.\n"); 777 return r; 778 } 779 DRM_INFO("radeon: %uM of GTT memory ready.\n", 780 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 781 782 r = radeon_ttm_debugfs_init(rdev); 783 if (r) { 784 DRM_ERROR("Failed to init debugfs\n"); 785 return r; 786 } 787 return 0; 788 } 789 790 void radeon_ttm_fini(struct radeon_device *rdev) 791 { 792 int r; 793 794 if (!rdev->mman.initialized) 795 return; 796 radeon_ttm_debugfs_fini(rdev); 797 if (rdev->stolen_vga_memory) { 798 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 799 if (r == 0) { 800 radeon_bo_unpin(rdev->stolen_vga_memory); 801 radeon_bo_unreserve(rdev->stolen_vga_memory); 802 } 803 radeon_bo_unref(&rdev->stolen_vga_memory); 804 } 805 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM); 806 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT); 807 ttm_bo_device_release(&rdev->mman.bdev); 808 radeon_gart_fini(rdev); 809 rdev->mman.initialized = false; 810 DRM_INFO("radeon: ttm finalized\n"); 811 } 812 813 /* this should only be called at bootup or when userspace 814 * isn't running */ 815 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 816 { 817 struct ttm_resource_manager *man; 818 819 if (!rdev->mman.initialized) 820 return; 821 822 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 823 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 824 man->size = size >> PAGE_SHIFT; 825 } 826 827 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) 828 { 829 struct ttm_buffer_object *bo; 830 struct radeon_device *rdev; 831 vm_fault_t ret; 832 833 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; 834 if (bo == NULL) 835 return VM_FAULT_NOPAGE; 836 837 rdev = radeon_get_rdev(bo->bdev); 838 down_read(&rdev->pm.mclk_lock); 839 ret = ttm_bo_vm_fault(vmf); 840 up_read(&rdev->pm.mclk_lock); 841 return ret; 842 } 843 844 static struct vm_operations_struct radeon_ttm_vm_ops = { 845 .fault = radeon_ttm_fault, 846 .open = ttm_bo_vm_open, 847 .close = ttm_bo_vm_close, 848 .access = ttm_bo_vm_access 849 }; 850 851 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 852 { 853 int r; 854 struct drm_file *file_priv = filp->private_data; 855 struct radeon_device *rdev = file_priv->minor->dev->dev_private; 856 857 if (rdev == NULL) 858 return -EINVAL; 859 860 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 861 if (unlikely(r != 0)) 862 return r; 863 864 vma->vm_ops = &radeon_ttm_vm_ops; 865 return 0; 866 } 867 868 #if defined(CONFIG_DEBUG_FS) 869 870 static int radeon_mm_dump_table(struct seq_file *m, void *data) 871 { 872 struct drm_info_node *node = (struct drm_info_node *)m->private; 873 unsigned ttm_pl = *(int*)node->info_ent->data; 874 struct drm_device *dev = node->minor->dev; 875 struct radeon_device *rdev = dev->dev_private; 876 struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl); 877 struct drm_printer p = drm_seq_file_printer(m); 878 879 man->func->debug(man, &p); 880 return 0; 881 } 882 883 884 static int ttm_pl_vram = TTM_PL_VRAM; 885 static int ttm_pl_tt = TTM_PL_TT; 886 887 static struct drm_info_list radeon_ttm_debugfs_list[] = { 888 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 889 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 890 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 891 #ifdef CONFIG_SWIOTLB 892 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 893 #endif 894 }; 895 896 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 897 { 898 struct radeon_device *rdev = inode->i_private; 899 i_size_write(inode, rdev->mc.mc_vram_size); 900 filep->private_data = inode->i_private; 901 return 0; 902 } 903 904 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 905 size_t size, loff_t *pos) 906 { 907 struct radeon_device *rdev = f->private_data; 908 ssize_t result = 0; 909 int r; 910 911 if (size & 0x3 || *pos & 0x3) 912 return -EINVAL; 913 914 while (size) { 915 unsigned long flags; 916 uint32_t value; 917 918 if (*pos >= rdev->mc.mc_vram_size) 919 return result; 920 921 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 922 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 923 if (rdev->family >= CHIP_CEDAR) 924 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 925 value = RREG32(RADEON_MM_DATA); 926 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 927 928 r = put_user(value, (uint32_t *)buf); 929 if (r) 930 return r; 931 932 result += 4; 933 buf += 4; 934 *pos += 4; 935 size -= 4; 936 } 937 938 return result; 939 } 940 941 static const struct file_operations radeon_ttm_vram_fops = { 942 .owner = THIS_MODULE, 943 .open = radeon_ttm_vram_open, 944 .read = radeon_ttm_vram_read, 945 .llseek = default_llseek 946 }; 947 948 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 949 { 950 struct radeon_device *rdev = inode->i_private; 951 i_size_write(inode, rdev->mc.gtt_size); 952 filep->private_data = inode->i_private; 953 return 0; 954 } 955 956 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 957 size_t size, loff_t *pos) 958 { 959 struct radeon_device *rdev = f->private_data; 960 ssize_t result = 0; 961 int r; 962 963 while (size) { 964 loff_t p = *pos / PAGE_SIZE; 965 unsigned off = *pos & ~PAGE_MASK; 966 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 967 struct page *page; 968 void *ptr; 969 970 if (p >= rdev->gart.num_cpu_pages) 971 return result; 972 973 page = rdev->gart.pages[p]; 974 if (page) { 975 ptr = kmap(page); 976 ptr += off; 977 978 r = copy_to_user(buf, ptr, cur_size); 979 kunmap(rdev->gart.pages[p]); 980 } else 981 r = clear_user(buf, cur_size); 982 983 if (r) 984 return -EFAULT; 985 986 result += cur_size; 987 buf += cur_size; 988 *pos += cur_size; 989 size -= cur_size; 990 } 991 992 return result; 993 } 994 995 static const struct file_operations radeon_ttm_gtt_fops = { 996 .owner = THIS_MODULE, 997 .open = radeon_ttm_gtt_open, 998 .read = radeon_ttm_gtt_read, 999 .llseek = default_llseek 1000 }; 1001 1002 #endif 1003 1004 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1005 { 1006 #if defined(CONFIG_DEBUG_FS) 1007 unsigned count; 1008 1009 struct drm_minor *minor = rdev->ddev->primary; 1010 struct dentry *root = minor->debugfs_root; 1011 1012 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, 1013 root, rdev, 1014 &radeon_ttm_vram_fops); 1015 1016 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, 1017 root, rdev, &radeon_ttm_gtt_fops); 1018 1019 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1020 1021 #ifdef CONFIG_SWIOTLB 1022 if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) 1023 --count; 1024 #endif 1025 1026 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1027 #else 1028 1029 return 0; 1030 #endif 1031 } 1032 1033 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1034 { 1035 #if defined(CONFIG_DEBUG_FS) 1036 1037 debugfs_remove(rdev->mman.vram); 1038 rdev->mman.vram = NULL; 1039 1040 debugfs_remove(rdev->mman.gtt); 1041 rdev->mman.gtt = NULL; 1042 #endif 1043 } 1044