1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <ttm/ttm_bo_api.h> 33 #include <ttm/ttm_bo_driver.h> 34 #include <ttm/ttm_placement.h> 35 #include <ttm/ttm_module.h> 36 #include <ttm/ttm_page_alloc.h> 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swiotlb.h> 42 #include <linux/debugfs.h> 43 #include "radeon_reg.h" 44 #include "radeon.h" 45 46 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 47 48 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 49 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 50 51 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 52 { 53 struct radeon_mman *mman; 54 struct radeon_device *rdev; 55 56 mman = container_of(bdev, struct radeon_mman, bdev); 57 rdev = container_of(mman, struct radeon_device, mman); 58 return rdev; 59 } 60 61 62 /* 63 * Global memory. 64 */ 65 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 66 { 67 return ttm_mem_global_init(ref->object); 68 } 69 70 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 71 { 72 ttm_mem_global_release(ref->object); 73 } 74 75 static int radeon_ttm_global_init(struct radeon_device *rdev) 76 { 77 struct drm_global_reference *global_ref; 78 int r; 79 80 rdev->mman.mem_global_referenced = false; 81 global_ref = &rdev->mman.mem_global_ref; 82 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 83 global_ref->size = sizeof(struct ttm_mem_global); 84 global_ref->init = &radeon_ttm_mem_global_init; 85 global_ref->release = &radeon_ttm_mem_global_release; 86 r = drm_global_item_ref(global_ref); 87 if (r != 0) { 88 DRM_ERROR("Failed setting up TTM memory accounting " 89 "subsystem.\n"); 90 return r; 91 } 92 93 rdev->mman.bo_global_ref.mem_glob = 94 rdev->mman.mem_global_ref.object; 95 global_ref = &rdev->mman.bo_global_ref.ref; 96 global_ref->global_type = DRM_GLOBAL_TTM_BO; 97 global_ref->size = sizeof(struct ttm_bo_global); 98 global_ref->init = &ttm_bo_global_init; 99 global_ref->release = &ttm_bo_global_release; 100 r = drm_global_item_ref(global_ref); 101 if (r != 0) { 102 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 103 drm_global_item_unref(&rdev->mman.mem_global_ref); 104 return r; 105 } 106 107 rdev->mman.mem_global_referenced = true; 108 return 0; 109 } 110 111 static void radeon_ttm_global_fini(struct radeon_device *rdev) 112 { 113 if (rdev->mman.mem_global_referenced) { 114 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 115 drm_global_item_unref(&rdev->mman.mem_global_ref); 116 rdev->mman.mem_global_referenced = false; 117 } 118 } 119 120 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 121 { 122 return 0; 123 } 124 125 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 126 struct ttm_mem_type_manager *man) 127 { 128 struct radeon_device *rdev; 129 130 rdev = radeon_get_rdev(bdev); 131 132 switch (type) { 133 case TTM_PL_SYSTEM: 134 /* System memory */ 135 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 136 man->available_caching = TTM_PL_MASK_CACHING; 137 man->default_caching = TTM_PL_FLAG_CACHED; 138 break; 139 case TTM_PL_TT: 140 man->func = &ttm_bo_manager_func; 141 man->gpu_offset = rdev->mc.gtt_start; 142 man->available_caching = TTM_PL_MASK_CACHING; 143 man->default_caching = TTM_PL_FLAG_CACHED; 144 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 145 #if __OS_HAS_AGP 146 if (rdev->flags & RADEON_IS_AGP) { 147 if (!rdev->ddev->agp) { 148 DRM_ERROR("AGP is not enabled for memory type %u\n", 149 (unsigned)type); 150 return -EINVAL; 151 } 152 if (!rdev->ddev->agp->cant_use_aperture) 153 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 154 man->available_caching = TTM_PL_FLAG_UNCACHED | 155 TTM_PL_FLAG_WC; 156 man->default_caching = TTM_PL_FLAG_WC; 157 } 158 #endif 159 break; 160 case TTM_PL_VRAM: 161 /* "On-card" video ram */ 162 man->func = &ttm_bo_manager_func; 163 man->gpu_offset = rdev->mc.vram_start; 164 man->flags = TTM_MEMTYPE_FLAG_FIXED | 165 TTM_MEMTYPE_FLAG_MAPPABLE; 166 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 167 man->default_caching = TTM_PL_FLAG_WC; 168 break; 169 default: 170 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 171 return -EINVAL; 172 } 173 return 0; 174 } 175 176 static void radeon_evict_flags(struct ttm_buffer_object *bo, 177 struct ttm_placement *placement) 178 { 179 struct radeon_bo *rbo; 180 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 181 182 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 183 placement->fpfn = 0; 184 placement->lpfn = 0; 185 placement->placement = &placements; 186 placement->busy_placement = &placements; 187 placement->num_placement = 1; 188 placement->num_busy_placement = 1; 189 return; 190 } 191 rbo = container_of(bo, struct radeon_bo, tbo); 192 switch (bo->mem.mem_type) { 193 case TTM_PL_VRAM: 194 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 195 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 196 else 197 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 198 break; 199 case TTM_PL_TT: 200 default: 201 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 202 } 203 *placement = rbo->placement; 204 } 205 206 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 207 { 208 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 209 210 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 211 } 212 213 static void radeon_move_null(struct ttm_buffer_object *bo, 214 struct ttm_mem_reg *new_mem) 215 { 216 struct ttm_mem_reg *old_mem = &bo->mem; 217 218 BUG_ON(old_mem->mm_node != NULL); 219 *old_mem = *new_mem; 220 new_mem->mm_node = NULL; 221 } 222 223 static int radeon_move_blit(struct ttm_buffer_object *bo, 224 bool evict, bool no_wait_gpu, 225 struct ttm_mem_reg *new_mem, 226 struct ttm_mem_reg *old_mem) 227 { 228 struct radeon_device *rdev; 229 uint64_t old_start, new_start; 230 struct radeon_fence *fence; 231 int r, ridx; 232 233 rdev = radeon_get_rdev(bo->bdev); 234 ridx = radeon_copy_ring_index(rdev); 235 old_start = old_mem->start << PAGE_SHIFT; 236 new_start = new_mem->start << PAGE_SHIFT; 237 238 switch (old_mem->mem_type) { 239 case TTM_PL_VRAM: 240 old_start += rdev->mc.vram_start; 241 break; 242 case TTM_PL_TT: 243 old_start += rdev->mc.gtt_start; 244 break; 245 default: 246 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 247 return -EINVAL; 248 } 249 switch (new_mem->mem_type) { 250 case TTM_PL_VRAM: 251 new_start += rdev->mc.vram_start; 252 break; 253 case TTM_PL_TT: 254 new_start += rdev->mc.gtt_start; 255 break; 256 default: 257 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 258 return -EINVAL; 259 } 260 if (!rdev->ring[ridx].ready) { 261 DRM_ERROR("Trying to move memory with ring turned off.\n"); 262 return -EINVAL; 263 } 264 265 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 266 267 /* sync other rings */ 268 fence = bo->sync_obj; 269 r = radeon_copy(rdev, old_start, new_start, 270 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 271 &fence); 272 /* FIXME: handle copy error */ 273 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 274 evict, no_wait_gpu, new_mem); 275 radeon_fence_unref(&fence); 276 return r; 277 } 278 279 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 280 bool evict, bool interruptible, 281 bool no_wait_gpu, 282 struct ttm_mem_reg *new_mem) 283 { 284 struct radeon_device *rdev; 285 struct ttm_mem_reg *old_mem = &bo->mem; 286 struct ttm_mem_reg tmp_mem; 287 u32 placements; 288 struct ttm_placement placement; 289 int r; 290 291 rdev = radeon_get_rdev(bo->bdev); 292 tmp_mem = *new_mem; 293 tmp_mem.mm_node = NULL; 294 placement.fpfn = 0; 295 placement.lpfn = 0; 296 placement.num_placement = 1; 297 placement.placement = &placements; 298 placement.num_busy_placement = 1; 299 placement.busy_placement = &placements; 300 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 301 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 302 interruptible, no_wait_gpu); 303 if (unlikely(r)) { 304 return r; 305 } 306 307 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 308 if (unlikely(r)) { 309 goto out_cleanup; 310 } 311 312 r = ttm_tt_bind(bo->ttm, &tmp_mem); 313 if (unlikely(r)) { 314 goto out_cleanup; 315 } 316 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 317 if (unlikely(r)) { 318 goto out_cleanup; 319 } 320 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 321 out_cleanup: 322 ttm_bo_mem_put(bo, &tmp_mem); 323 return r; 324 } 325 326 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 327 bool evict, bool interruptible, 328 bool no_wait_gpu, 329 struct ttm_mem_reg *new_mem) 330 { 331 struct radeon_device *rdev; 332 struct ttm_mem_reg *old_mem = &bo->mem; 333 struct ttm_mem_reg tmp_mem; 334 struct ttm_placement placement; 335 u32 placements; 336 int r; 337 338 rdev = radeon_get_rdev(bo->bdev); 339 tmp_mem = *new_mem; 340 tmp_mem.mm_node = NULL; 341 placement.fpfn = 0; 342 placement.lpfn = 0; 343 placement.num_placement = 1; 344 placement.placement = &placements; 345 placement.num_busy_placement = 1; 346 placement.busy_placement = &placements; 347 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 348 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 349 interruptible, no_wait_gpu); 350 if (unlikely(r)) { 351 return r; 352 } 353 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 354 if (unlikely(r)) { 355 goto out_cleanup; 356 } 357 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 358 if (unlikely(r)) { 359 goto out_cleanup; 360 } 361 out_cleanup: 362 ttm_bo_mem_put(bo, &tmp_mem); 363 return r; 364 } 365 366 static int radeon_bo_move(struct ttm_buffer_object *bo, 367 bool evict, bool interruptible, 368 bool no_wait_gpu, 369 struct ttm_mem_reg *new_mem) 370 { 371 struct radeon_device *rdev; 372 struct ttm_mem_reg *old_mem = &bo->mem; 373 int r; 374 375 rdev = radeon_get_rdev(bo->bdev); 376 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 377 radeon_move_null(bo, new_mem); 378 return 0; 379 } 380 if ((old_mem->mem_type == TTM_PL_TT && 381 new_mem->mem_type == TTM_PL_SYSTEM) || 382 (old_mem->mem_type == TTM_PL_SYSTEM && 383 new_mem->mem_type == TTM_PL_TT)) { 384 /* bind is enough */ 385 radeon_move_null(bo, new_mem); 386 return 0; 387 } 388 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 389 rdev->asic->copy.copy == NULL) { 390 /* use memcpy */ 391 goto memcpy; 392 } 393 394 if (old_mem->mem_type == TTM_PL_VRAM && 395 new_mem->mem_type == TTM_PL_SYSTEM) { 396 r = radeon_move_vram_ram(bo, evict, interruptible, 397 no_wait_gpu, new_mem); 398 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 399 new_mem->mem_type == TTM_PL_VRAM) { 400 r = radeon_move_ram_vram(bo, evict, interruptible, 401 no_wait_gpu, new_mem); 402 } else { 403 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 404 } 405 406 if (r) { 407 memcpy: 408 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 409 if (r) { 410 return r; 411 } 412 } 413 414 /* update statistics */ 415 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 416 return 0; 417 } 418 419 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 420 { 421 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 422 struct radeon_device *rdev = radeon_get_rdev(bdev); 423 424 mem->bus.addr = NULL; 425 mem->bus.offset = 0; 426 mem->bus.size = mem->num_pages << PAGE_SHIFT; 427 mem->bus.base = 0; 428 mem->bus.is_iomem = false; 429 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 430 return -EINVAL; 431 switch (mem->mem_type) { 432 case TTM_PL_SYSTEM: 433 /* system memory */ 434 return 0; 435 case TTM_PL_TT: 436 #if __OS_HAS_AGP 437 if (rdev->flags & RADEON_IS_AGP) { 438 /* RADEON_IS_AGP is set only if AGP is active */ 439 mem->bus.offset = mem->start << PAGE_SHIFT; 440 mem->bus.base = rdev->mc.agp_base; 441 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 442 } 443 #endif 444 break; 445 case TTM_PL_VRAM: 446 mem->bus.offset = mem->start << PAGE_SHIFT; 447 /* check if it's visible */ 448 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 449 return -EINVAL; 450 mem->bus.base = rdev->mc.aper_base; 451 mem->bus.is_iomem = true; 452 #ifdef __alpha__ 453 /* 454 * Alpha: use bus.addr to hold the ioremap() return, 455 * so we can modify bus.base below. 456 */ 457 if (mem->placement & TTM_PL_FLAG_WC) 458 mem->bus.addr = 459 ioremap_wc(mem->bus.base + mem->bus.offset, 460 mem->bus.size); 461 else 462 mem->bus.addr = 463 ioremap_nocache(mem->bus.base + mem->bus.offset, 464 mem->bus.size); 465 466 /* 467 * Alpha: Use just the bus offset plus 468 * the hose/domain memory base for bus.base. 469 * It then can be used to build PTEs for VRAM 470 * access, as done in ttm_bo_vm_fault(). 471 */ 472 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 473 rdev->ddev->hose->dense_mem_base; 474 #endif 475 break; 476 default: 477 return -EINVAL; 478 } 479 return 0; 480 } 481 482 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 483 { 484 } 485 486 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 487 { 488 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 489 } 490 491 static int radeon_sync_obj_flush(void *sync_obj) 492 { 493 return 0; 494 } 495 496 static void radeon_sync_obj_unref(void **sync_obj) 497 { 498 radeon_fence_unref((struct radeon_fence **)sync_obj); 499 } 500 501 static void *radeon_sync_obj_ref(void *sync_obj) 502 { 503 return radeon_fence_ref((struct radeon_fence *)sync_obj); 504 } 505 506 static bool radeon_sync_obj_signaled(void *sync_obj) 507 { 508 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 509 } 510 511 /* 512 * TTM backend functions. 513 */ 514 struct radeon_ttm_tt { 515 struct ttm_dma_tt ttm; 516 struct radeon_device *rdev; 517 u64 offset; 518 }; 519 520 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 521 struct ttm_mem_reg *bo_mem) 522 { 523 struct radeon_ttm_tt *gtt = (void*)ttm; 524 int r; 525 526 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 527 if (!ttm->num_pages) { 528 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 529 ttm->num_pages, bo_mem, ttm); 530 } 531 r = radeon_gart_bind(gtt->rdev, gtt->offset, 532 ttm->num_pages, ttm->pages, gtt->ttm.dma_address); 533 if (r) { 534 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 535 ttm->num_pages, (unsigned)gtt->offset); 536 return r; 537 } 538 return 0; 539 } 540 541 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 542 { 543 struct radeon_ttm_tt *gtt = (void *)ttm; 544 545 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 546 return 0; 547 } 548 549 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 550 { 551 struct radeon_ttm_tt *gtt = (void *)ttm; 552 553 ttm_dma_tt_fini(>t->ttm); 554 kfree(gtt); 555 } 556 557 static struct ttm_backend_func radeon_backend_func = { 558 .bind = &radeon_ttm_backend_bind, 559 .unbind = &radeon_ttm_backend_unbind, 560 .destroy = &radeon_ttm_backend_destroy, 561 }; 562 563 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 564 unsigned long size, uint32_t page_flags, 565 struct page *dummy_read_page) 566 { 567 struct radeon_device *rdev; 568 struct radeon_ttm_tt *gtt; 569 570 rdev = radeon_get_rdev(bdev); 571 #if __OS_HAS_AGP 572 if (rdev->flags & RADEON_IS_AGP) { 573 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, 574 size, page_flags, dummy_read_page); 575 } 576 #endif 577 578 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 579 if (gtt == NULL) { 580 return NULL; 581 } 582 gtt->ttm.ttm.func = &radeon_backend_func; 583 gtt->rdev = rdev; 584 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 585 kfree(gtt); 586 return NULL; 587 } 588 return >t->ttm.ttm; 589 } 590 591 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 592 { 593 struct radeon_device *rdev; 594 struct radeon_ttm_tt *gtt = (void *)ttm; 595 unsigned i; 596 int r; 597 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 598 599 if (ttm->state != tt_unpopulated) 600 return 0; 601 602 if (slave && ttm->sg) { 603 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 604 gtt->ttm.dma_address, ttm->num_pages); 605 ttm->state = tt_unbound; 606 return 0; 607 } 608 609 rdev = radeon_get_rdev(ttm->bdev); 610 #if __OS_HAS_AGP 611 if (rdev->flags & RADEON_IS_AGP) { 612 return ttm_agp_tt_populate(ttm); 613 } 614 #endif 615 616 #ifdef CONFIG_SWIOTLB 617 if (swiotlb_nr_tbl()) { 618 return ttm_dma_populate(>t->ttm, rdev->dev); 619 } 620 #endif 621 622 r = ttm_pool_populate(ttm); 623 if (r) { 624 return r; 625 } 626 627 for (i = 0; i < ttm->num_pages; i++) { 628 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 629 0, PAGE_SIZE, 630 PCI_DMA_BIDIRECTIONAL); 631 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 632 while (--i) { 633 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 634 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 635 gtt->ttm.dma_address[i] = 0; 636 } 637 ttm_pool_unpopulate(ttm); 638 return -EFAULT; 639 } 640 } 641 return 0; 642 } 643 644 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 645 { 646 struct radeon_device *rdev; 647 struct radeon_ttm_tt *gtt = (void *)ttm; 648 unsigned i; 649 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 650 651 if (slave) 652 return; 653 654 rdev = radeon_get_rdev(ttm->bdev); 655 #if __OS_HAS_AGP 656 if (rdev->flags & RADEON_IS_AGP) { 657 ttm_agp_tt_unpopulate(ttm); 658 return; 659 } 660 #endif 661 662 #ifdef CONFIG_SWIOTLB 663 if (swiotlb_nr_tbl()) { 664 ttm_dma_unpopulate(>t->ttm, rdev->dev); 665 return; 666 } 667 #endif 668 669 for (i = 0; i < ttm->num_pages; i++) { 670 if (gtt->ttm.dma_address[i]) { 671 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 672 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 673 } 674 } 675 676 ttm_pool_unpopulate(ttm); 677 } 678 679 static struct ttm_bo_driver radeon_bo_driver = { 680 .ttm_tt_create = &radeon_ttm_tt_create, 681 .ttm_tt_populate = &radeon_ttm_tt_populate, 682 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 683 .invalidate_caches = &radeon_invalidate_caches, 684 .init_mem_type = &radeon_init_mem_type, 685 .evict_flags = &radeon_evict_flags, 686 .move = &radeon_bo_move, 687 .verify_access = &radeon_verify_access, 688 .sync_obj_signaled = &radeon_sync_obj_signaled, 689 .sync_obj_wait = &radeon_sync_obj_wait, 690 .sync_obj_flush = &radeon_sync_obj_flush, 691 .sync_obj_unref = &radeon_sync_obj_unref, 692 .sync_obj_ref = &radeon_sync_obj_ref, 693 .move_notify = &radeon_bo_move_notify, 694 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 695 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 696 .io_mem_free = &radeon_ttm_io_mem_free, 697 }; 698 699 int radeon_ttm_init(struct radeon_device *rdev) 700 { 701 int r; 702 703 r = radeon_ttm_global_init(rdev); 704 if (r) { 705 return r; 706 } 707 /* No others user of address space so set it to 0 */ 708 r = ttm_bo_device_init(&rdev->mman.bdev, 709 rdev->mman.bo_global_ref.ref.object, 710 &radeon_bo_driver, 711 rdev->ddev->anon_inode->i_mapping, 712 DRM_FILE_PAGE_OFFSET, 713 rdev->need_dma32); 714 if (r) { 715 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 716 return r; 717 } 718 rdev->mman.initialized = true; 719 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 720 rdev->mc.real_vram_size >> PAGE_SHIFT); 721 if (r) { 722 DRM_ERROR("Failed initializing VRAM heap.\n"); 723 return r; 724 } 725 /* Change the size here instead of the init above so only lpfn is affected */ 726 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 727 728 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 729 RADEON_GEM_DOMAIN_VRAM, 730 NULL, &rdev->stollen_vga_memory); 731 if (r) { 732 return r; 733 } 734 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 735 if (r) 736 return r; 737 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 738 radeon_bo_unreserve(rdev->stollen_vga_memory); 739 if (r) { 740 radeon_bo_unref(&rdev->stollen_vga_memory); 741 return r; 742 } 743 DRM_INFO("radeon: %uM of VRAM memory ready\n", 744 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 745 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 746 rdev->mc.gtt_size >> PAGE_SHIFT); 747 if (r) { 748 DRM_ERROR("Failed initializing GTT heap.\n"); 749 return r; 750 } 751 DRM_INFO("radeon: %uM of GTT memory ready.\n", 752 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 753 754 r = radeon_ttm_debugfs_init(rdev); 755 if (r) { 756 DRM_ERROR("Failed to init debugfs\n"); 757 return r; 758 } 759 return 0; 760 } 761 762 void radeon_ttm_fini(struct radeon_device *rdev) 763 { 764 int r; 765 766 if (!rdev->mman.initialized) 767 return; 768 radeon_ttm_debugfs_fini(rdev); 769 if (rdev->stollen_vga_memory) { 770 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 771 if (r == 0) { 772 radeon_bo_unpin(rdev->stollen_vga_memory); 773 radeon_bo_unreserve(rdev->stollen_vga_memory); 774 } 775 radeon_bo_unref(&rdev->stollen_vga_memory); 776 } 777 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 778 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 779 ttm_bo_device_release(&rdev->mman.bdev); 780 radeon_gart_fini(rdev); 781 radeon_ttm_global_fini(rdev); 782 rdev->mman.initialized = false; 783 DRM_INFO("radeon: ttm finalized\n"); 784 } 785 786 /* this should only be called at bootup or when userspace 787 * isn't running */ 788 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 789 { 790 struct ttm_mem_type_manager *man; 791 792 if (!rdev->mman.initialized) 793 return; 794 795 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 796 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 797 man->size = size >> PAGE_SHIFT; 798 } 799 800 static struct vm_operations_struct radeon_ttm_vm_ops; 801 static const struct vm_operations_struct *ttm_vm_ops = NULL; 802 803 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 804 { 805 struct ttm_buffer_object *bo; 806 struct radeon_device *rdev; 807 int r; 808 809 bo = (struct ttm_buffer_object *)vma->vm_private_data; 810 if (bo == NULL) { 811 return VM_FAULT_NOPAGE; 812 } 813 rdev = radeon_get_rdev(bo->bdev); 814 down_read(&rdev->pm.mclk_lock); 815 r = ttm_vm_ops->fault(vma, vmf); 816 up_read(&rdev->pm.mclk_lock); 817 return r; 818 } 819 820 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 821 { 822 struct drm_file *file_priv; 823 struct radeon_device *rdev; 824 int r; 825 826 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 827 return drm_mmap(filp, vma); 828 } 829 830 file_priv = filp->private_data; 831 rdev = file_priv->minor->dev->dev_private; 832 if (rdev == NULL) { 833 return -EINVAL; 834 } 835 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 836 if (unlikely(r != 0)) { 837 return r; 838 } 839 if (unlikely(ttm_vm_ops == NULL)) { 840 ttm_vm_ops = vma->vm_ops; 841 radeon_ttm_vm_ops = *ttm_vm_ops; 842 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 843 } 844 vma->vm_ops = &radeon_ttm_vm_ops; 845 return 0; 846 } 847 848 #if defined(CONFIG_DEBUG_FS) 849 850 static int radeon_mm_dump_table(struct seq_file *m, void *data) 851 { 852 struct drm_info_node *node = (struct drm_info_node *)m->private; 853 unsigned ttm_pl = *(int *)node->info_ent->data; 854 struct drm_device *dev = node->minor->dev; 855 struct radeon_device *rdev = dev->dev_private; 856 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; 857 int ret; 858 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 859 860 spin_lock(&glob->lru_lock); 861 ret = drm_mm_dump_table(m, mm); 862 spin_unlock(&glob->lru_lock); 863 return ret; 864 } 865 866 static int ttm_pl_vram = TTM_PL_VRAM; 867 static int ttm_pl_tt = TTM_PL_TT; 868 869 static struct drm_info_list radeon_ttm_debugfs_list[] = { 870 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 871 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 872 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 873 #ifdef CONFIG_SWIOTLB 874 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 875 #endif 876 }; 877 878 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 879 { 880 struct radeon_device *rdev = inode->i_private; 881 i_size_write(inode, rdev->mc.mc_vram_size); 882 filep->private_data = inode->i_private; 883 return 0; 884 } 885 886 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 887 size_t size, loff_t *pos) 888 { 889 struct radeon_device *rdev = f->private_data; 890 ssize_t result = 0; 891 int r; 892 893 if (size & 0x3 || *pos & 0x3) 894 return -EINVAL; 895 896 while (size) { 897 unsigned long flags; 898 uint32_t value; 899 900 if (*pos >= rdev->mc.mc_vram_size) 901 return result; 902 903 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 904 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 905 if (rdev->family >= CHIP_CEDAR) 906 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 907 value = RREG32(RADEON_MM_DATA); 908 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 909 910 r = put_user(value, (uint32_t *)buf); 911 if (r) 912 return r; 913 914 result += 4; 915 buf += 4; 916 *pos += 4; 917 size -= 4; 918 } 919 920 return result; 921 } 922 923 static const struct file_operations radeon_ttm_vram_fops = { 924 .owner = THIS_MODULE, 925 .open = radeon_ttm_vram_open, 926 .read = radeon_ttm_vram_read, 927 .llseek = default_llseek 928 }; 929 930 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 931 { 932 struct radeon_device *rdev = inode->i_private; 933 i_size_write(inode, rdev->mc.gtt_size); 934 filep->private_data = inode->i_private; 935 return 0; 936 } 937 938 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 939 size_t size, loff_t *pos) 940 { 941 struct radeon_device *rdev = f->private_data; 942 ssize_t result = 0; 943 int r; 944 945 while (size) { 946 loff_t p = *pos / PAGE_SIZE; 947 unsigned off = *pos & ~PAGE_MASK; 948 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 949 struct page *page; 950 void *ptr; 951 952 if (p >= rdev->gart.num_cpu_pages) 953 return result; 954 955 page = rdev->gart.pages[p]; 956 if (page) { 957 ptr = kmap(page); 958 ptr += off; 959 960 r = copy_to_user(buf, ptr, cur_size); 961 kunmap(rdev->gart.pages[p]); 962 } else 963 r = clear_user(buf, cur_size); 964 965 if (r) 966 return -EFAULT; 967 968 result += cur_size; 969 buf += cur_size; 970 *pos += cur_size; 971 size -= cur_size; 972 } 973 974 return result; 975 } 976 977 static const struct file_operations radeon_ttm_gtt_fops = { 978 .owner = THIS_MODULE, 979 .open = radeon_ttm_gtt_open, 980 .read = radeon_ttm_gtt_read, 981 .llseek = default_llseek 982 }; 983 984 #endif 985 986 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 987 { 988 #if defined(CONFIG_DEBUG_FS) 989 unsigned count; 990 991 struct drm_minor *minor = rdev->ddev->primary; 992 struct dentry *ent, *root = minor->debugfs_root; 993 994 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, 995 rdev, &radeon_ttm_vram_fops); 996 if (IS_ERR(ent)) 997 return PTR_ERR(ent); 998 rdev->mman.vram = ent; 999 1000 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, 1001 rdev, &radeon_ttm_gtt_fops); 1002 if (IS_ERR(ent)) 1003 return PTR_ERR(ent); 1004 rdev->mman.gtt = ent; 1005 1006 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1007 1008 #ifdef CONFIG_SWIOTLB 1009 if (!swiotlb_nr_tbl()) 1010 --count; 1011 #endif 1012 1013 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1014 #else 1015 1016 return 0; 1017 #endif 1018 } 1019 1020 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1021 { 1022 #if defined(CONFIG_DEBUG_FS) 1023 1024 debugfs_remove(rdev->mman.vram); 1025 rdev->mman.vram = NULL; 1026 1027 debugfs_remove(rdev->mman.gtt); 1028 rdev->mman.gtt = NULL; 1029 #endif 1030 } 1031