1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "radeon_drm.h" 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "atom.h" 34 35 int radeon_debugfs_ib_init(struct radeon_device *rdev); 36 37 /* 38 * IB. 39 */ 40 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) 41 { 42 struct radeon_fence *fence; 43 struct radeon_ib *nib; 44 unsigned long i; 45 int r = 0; 46 47 *ib = NULL; 48 r = radeon_fence_create(rdev, &fence); 49 if (r) { 50 DRM_ERROR("failed to create fence for new IB\n"); 51 return r; 52 } 53 mutex_lock(&rdev->ib_pool.mutex); 54 i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 55 if (i < RADEON_IB_POOL_SIZE) { 56 set_bit(i, rdev->ib_pool.alloc_bm); 57 rdev->ib_pool.ibs[i].length_dw = 0; 58 *ib = &rdev->ib_pool.ibs[i]; 59 goto out; 60 } 61 if (list_empty(&rdev->ib_pool.scheduled_ibs)) { 62 /* we go do nothings here */ 63 DRM_ERROR("all IB allocated none scheduled.\n"); 64 r = -EINVAL; 65 goto out; 66 } 67 /* get the first ib on the scheduled list */ 68 nib = list_entry(rdev->ib_pool.scheduled_ibs.next, 69 struct radeon_ib, list); 70 if (nib->fence == NULL) { 71 /* we go do nothings here */ 72 DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); 73 r = -EINVAL; 74 goto out; 75 } 76 r = radeon_fence_wait(nib->fence, false); 77 if (r) { 78 DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, 79 (unsigned long)nib->gpu_addr, nib->length_dw); 80 DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); 81 goto out; 82 } 83 radeon_fence_unref(&nib->fence); 84 nib->length_dw = 0; 85 list_del(&nib->list); 86 INIT_LIST_HEAD(&nib->list); 87 *ib = nib; 88 out: 89 mutex_unlock(&rdev->ib_pool.mutex); 90 if (r) { 91 radeon_fence_unref(&fence); 92 } else { 93 (*ib)->fence = fence; 94 } 95 return r; 96 } 97 98 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) 99 { 100 struct radeon_ib *tmp = *ib; 101 102 *ib = NULL; 103 if (tmp == NULL) { 104 return; 105 } 106 mutex_lock(&rdev->ib_pool.mutex); 107 if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { 108 /* IB is scheduled & not signaled don't do anythings */ 109 mutex_unlock(&rdev->ib_pool.mutex); 110 return; 111 } 112 list_del(&tmp->list); 113 INIT_LIST_HEAD(&tmp->list); 114 if (tmp->fence) { 115 radeon_fence_unref(&tmp->fence); 116 } 117 tmp->length_dw = 0; 118 clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); 119 mutex_unlock(&rdev->ib_pool.mutex); 120 } 121 122 static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) 123 { 124 while ((ib->length_dw & rdev->cp.align_mask)) { 125 ib->ptr[ib->length_dw++] = PACKET2(0); 126 } 127 } 128 129 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 130 { 131 int r = 0; 132 133 mutex_lock(&rdev->ib_pool.mutex); 134 radeon_ib_align(rdev, ib); 135 if (!ib->length_dw || !rdev->cp.ready) { 136 /* TODO: Nothings in the ib we should report. */ 137 mutex_unlock(&rdev->ib_pool.mutex); 138 DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); 139 return -EINVAL; 140 } 141 /* 64 dwords should be enough for fence too */ 142 r = radeon_ring_lock(rdev, 64); 143 if (r) { 144 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); 145 mutex_unlock(&rdev->ib_pool.mutex); 146 return r; 147 } 148 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 149 radeon_ring_write(rdev, ib->gpu_addr); 150 radeon_ring_write(rdev, ib->length_dw); 151 radeon_fence_emit(rdev, ib->fence); 152 radeon_ring_unlock_commit(rdev); 153 list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); 154 mutex_unlock(&rdev->ib_pool.mutex); 155 return 0; 156 } 157 158 int radeon_ib_pool_init(struct radeon_device *rdev) 159 { 160 void *ptr; 161 uint64_t gpu_addr; 162 int i; 163 int r = 0; 164 165 /* Allocate 1M object buffer */ 166 INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); 167 r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, 168 true, RADEON_GEM_DOMAIN_GTT, 169 false, &rdev->ib_pool.robj); 170 if (r) { 171 DRM_ERROR("radeon: failed to ib pool (%d).\n", r); 172 return r; 173 } 174 r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); 175 if (r) { 176 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); 177 return r; 178 } 179 r = radeon_object_kmap(rdev->ib_pool.robj, &ptr); 180 if (r) { 181 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); 182 return r; 183 } 184 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 185 unsigned offset; 186 187 offset = i * 64 * 1024; 188 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; 189 rdev->ib_pool.ibs[i].ptr = ptr + offset; 190 rdev->ib_pool.ibs[i].idx = i; 191 rdev->ib_pool.ibs[i].length_dw = 0; 192 INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); 193 } 194 bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 195 rdev->ib_pool.ready = true; 196 DRM_INFO("radeon: ib pool ready.\n"); 197 if (radeon_debugfs_ib_init(rdev)) { 198 DRM_ERROR("Failed to register debugfs file for IB !\n"); 199 } 200 return r; 201 } 202 203 void radeon_ib_pool_fini(struct radeon_device *rdev) 204 { 205 if (!rdev->ib_pool.ready) { 206 return; 207 } 208 mutex_lock(&rdev->ib_pool.mutex); 209 bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 210 if (rdev->ib_pool.robj) { 211 radeon_object_kunmap(rdev->ib_pool.robj); 212 radeon_object_unref(&rdev->ib_pool.robj); 213 rdev->ib_pool.robj = NULL; 214 } 215 mutex_unlock(&rdev->ib_pool.mutex); 216 } 217 218 int radeon_ib_test(struct radeon_device *rdev) 219 { 220 struct radeon_ib *ib; 221 uint32_t scratch; 222 uint32_t tmp = 0; 223 unsigned i; 224 int r; 225 226 r = radeon_scratch_get(rdev, &scratch); 227 if (r) { 228 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 229 return r; 230 } 231 WREG32(scratch, 0xCAFEDEAD); 232 r = radeon_ib_get(rdev, &ib); 233 if (r) { 234 return r; 235 } 236 ib->ptr[0] = PACKET0(scratch, 0); 237 ib->ptr[1] = 0xDEADBEEF; 238 ib->ptr[2] = PACKET2(0); 239 ib->ptr[3] = PACKET2(0); 240 ib->ptr[4] = PACKET2(0); 241 ib->ptr[5] = PACKET2(0); 242 ib->ptr[6] = PACKET2(0); 243 ib->ptr[7] = PACKET2(0); 244 ib->length_dw = 8; 245 r = radeon_ib_schedule(rdev, ib); 246 if (r) { 247 radeon_scratch_free(rdev, scratch); 248 radeon_ib_free(rdev, &ib); 249 return r; 250 } 251 r = radeon_fence_wait(ib->fence, false); 252 if (r) { 253 return r; 254 } 255 for (i = 0; i < rdev->usec_timeout; i++) { 256 tmp = RREG32(scratch); 257 if (tmp == 0xDEADBEEF) { 258 break; 259 } 260 DRM_UDELAY(1); 261 } 262 if (i < rdev->usec_timeout) { 263 DRM_INFO("ib test succeeded in %u usecs\n", i); 264 } else { 265 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 266 scratch, tmp); 267 r = -EINVAL; 268 } 269 radeon_scratch_free(rdev, scratch); 270 radeon_ib_free(rdev, &ib); 271 return r; 272 } 273 274 275 /* 276 * Ring. 277 */ 278 void radeon_ring_free_size(struct radeon_device *rdev) 279 { 280 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 281 /* This works because ring_size is a power of 2 */ 282 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); 283 rdev->cp.ring_free_dw -= rdev->cp.wptr; 284 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; 285 if (!rdev->cp.ring_free_dw) { 286 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 287 } 288 } 289 290 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) 291 { 292 int r; 293 294 /* Align requested size with padding so unlock_commit can 295 * pad safely */ 296 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; 297 mutex_lock(&rdev->cp.mutex); 298 while (ndw > (rdev->cp.ring_free_dw - 1)) { 299 radeon_ring_free_size(rdev); 300 if (ndw < rdev->cp.ring_free_dw) { 301 break; 302 } 303 r = radeon_fence_wait_next(rdev); 304 if (r) { 305 mutex_unlock(&rdev->cp.mutex); 306 return r; 307 } 308 } 309 rdev->cp.count_dw = ndw; 310 rdev->cp.wptr_old = rdev->cp.wptr; 311 return 0; 312 } 313 314 void radeon_ring_unlock_commit(struct radeon_device *rdev) 315 { 316 unsigned count_dw_pad; 317 unsigned i; 318 319 /* We pad to match fetch size */ 320 count_dw_pad = (rdev->cp.align_mask + 1) - 321 (rdev->cp.wptr & rdev->cp.align_mask); 322 for (i = 0; i < count_dw_pad; i++) { 323 radeon_ring_write(rdev, PACKET2(0)); 324 } 325 DRM_MEMORYBARRIER(); 326 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 327 (void)RREG32(RADEON_CP_RB_WPTR); 328 mutex_unlock(&rdev->cp.mutex); 329 } 330 331 void radeon_ring_unlock_undo(struct radeon_device *rdev) 332 { 333 rdev->cp.wptr = rdev->cp.wptr_old; 334 mutex_unlock(&rdev->cp.mutex); 335 } 336 337 int radeon_ring_test(struct radeon_device *rdev) 338 { 339 uint32_t scratch; 340 uint32_t tmp = 0; 341 unsigned i; 342 int r; 343 344 r = radeon_scratch_get(rdev, &scratch); 345 if (r) { 346 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 347 return r; 348 } 349 WREG32(scratch, 0xCAFEDEAD); 350 r = radeon_ring_lock(rdev, 2); 351 if (r) { 352 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 353 radeon_scratch_free(rdev, scratch); 354 return r; 355 } 356 radeon_ring_write(rdev, PACKET0(scratch, 0)); 357 radeon_ring_write(rdev, 0xDEADBEEF); 358 radeon_ring_unlock_commit(rdev); 359 for (i = 0; i < rdev->usec_timeout; i++) { 360 tmp = RREG32(scratch); 361 if (tmp == 0xDEADBEEF) { 362 break; 363 } 364 DRM_UDELAY(1); 365 } 366 if (i < rdev->usec_timeout) { 367 DRM_INFO("ring test succeeded in %d usecs\n", i); 368 } else { 369 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", 370 scratch, tmp); 371 r = -EINVAL; 372 } 373 radeon_scratch_free(rdev, scratch); 374 return r; 375 } 376 377 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) 378 { 379 int r; 380 381 rdev->cp.ring_size = ring_size; 382 /* Allocate ring buffer */ 383 if (rdev->cp.ring_obj == NULL) { 384 r = radeon_object_create(rdev, NULL, rdev->cp.ring_size, 385 true, 386 RADEON_GEM_DOMAIN_GTT, 387 false, 388 &rdev->cp.ring_obj); 389 if (r) { 390 DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r); 391 mutex_unlock(&rdev->cp.mutex); 392 return r; 393 } 394 r = radeon_object_pin(rdev->cp.ring_obj, 395 RADEON_GEM_DOMAIN_GTT, 396 &rdev->cp.gpu_addr); 397 if (r) { 398 DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r); 399 mutex_unlock(&rdev->cp.mutex); 400 return r; 401 } 402 r = radeon_object_kmap(rdev->cp.ring_obj, 403 (void **)&rdev->cp.ring); 404 if (r) { 405 DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r); 406 mutex_unlock(&rdev->cp.mutex); 407 return r; 408 } 409 } 410 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; 411 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 412 return 0; 413 } 414 415 void radeon_ring_fini(struct radeon_device *rdev) 416 { 417 mutex_lock(&rdev->cp.mutex); 418 if (rdev->cp.ring_obj) { 419 radeon_object_kunmap(rdev->cp.ring_obj); 420 radeon_object_unpin(rdev->cp.ring_obj); 421 radeon_object_unref(&rdev->cp.ring_obj); 422 rdev->cp.ring = NULL; 423 rdev->cp.ring_obj = NULL; 424 } 425 mutex_unlock(&rdev->cp.mutex); 426 } 427 428 429 /* 430 * Debugfs info 431 */ 432 #if defined(CONFIG_DEBUG_FS) 433 static int radeon_debugfs_ib_info(struct seq_file *m, void *data) 434 { 435 struct drm_info_node *node = (struct drm_info_node *) m->private; 436 struct radeon_ib *ib = node->info_ent->data; 437 unsigned i; 438 439 if (ib == NULL) { 440 return 0; 441 } 442 seq_printf(m, "IB %04lu\n", ib->idx); 443 seq_printf(m, "IB fence %p\n", ib->fence); 444 seq_printf(m, "IB size %05u dwords\n", ib->length_dw); 445 for (i = 0; i < ib->length_dw; i++) { 446 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); 447 } 448 return 0; 449 } 450 451 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; 452 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; 453 #endif 454 455 int radeon_debugfs_ib_init(struct radeon_device *rdev) 456 { 457 #if defined(CONFIG_DEBUG_FS) 458 unsigned i; 459 460 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 461 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); 462 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; 463 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; 464 radeon_debugfs_ib_list[i].driver_features = 0; 465 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; 466 } 467 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, 468 RADEON_IB_POOL_SIZE); 469 #else 470 return 0; 471 #endif 472 } 473