1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/radeon_drm.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "atom.h" 36 37 /* 38 * IB 39 * IBs (Indirect Buffers) and areas of GPU accessible memory where 40 * commands are stored. You can put a pointer to the IB in the 41 * command ring and the hw will fetch the commands from the IB 42 * and execute them. Generally userspace acceleration drivers 43 * produce command buffers which are send to the kernel and 44 * put in IBs for execution by the requested ring. 45 */ 46 static int radeon_debugfs_sa_init(struct radeon_device *rdev); 47 48 /** 49 * radeon_ib_get - request an IB (Indirect Buffer) 50 * 51 * @rdev: radeon_device pointer 52 * @ring: ring index the IB is associated with 53 * @ib: IB object returned 54 * @size: requested IB size 55 * 56 * Request an IB (all asics). IBs are allocated using the 57 * suballocator. 58 * Returns 0 on success, error on failure. 59 */ 60 int radeon_ib_get(struct radeon_device *rdev, int ring, 61 struct radeon_ib *ib, struct radeon_vm *vm, 62 unsigned size) 63 { 64 int i, r; 65 66 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); 67 if (r) { 68 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); 69 return r; 70 } 71 72 r = radeon_semaphore_create(rdev, &ib->semaphore); 73 if (r) { 74 return r; 75 } 76 77 ib->ring = ring; 78 ib->fence = NULL; 79 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); 80 ib->vm = vm; 81 if (vm) { 82 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address 83 * space and soffset is the offset inside the pool bo 84 */ 85 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; 86 } else { 87 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); 88 } 89 ib->is_const_ib = false; 90 for (i = 0; i < RADEON_NUM_RINGS; ++i) 91 ib->sync_to[i] = NULL; 92 93 return 0; 94 } 95 96 /** 97 * radeon_ib_free - free an IB (Indirect Buffer) 98 * 99 * @rdev: radeon_device pointer 100 * @ib: IB object to free 101 * 102 * Free an IB (all asics). 103 */ 104 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) 105 { 106 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); 107 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); 108 radeon_fence_unref(&ib->fence); 109 } 110 111 /** 112 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 113 * 114 * @rdev: radeon_device pointer 115 * @ib: IB object to schedule 116 * @const_ib: Const IB to schedule (SI only) 117 * 118 * Schedule an IB on the associated ring (all asics). 119 * Returns 0 on success, error on failure. 120 * 121 * On SI, there are two parallel engines fed from the primary ring, 122 * the CE (Constant Engine) and the DE (Drawing Engine). Since 123 * resource descriptors have moved to memory, the CE allows you to 124 * prime the caches while the DE is updating register state so that 125 * the resource descriptors will be already in cache when the draw is 126 * processed. To accomplish this, the userspace driver submits two 127 * IBs, one for the CE and one for the DE. If there is a CE IB (called 128 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 129 * to SI there was just a DE IB. 130 */ 131 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 132 struct radeon_ib *const_ib) 133 { 134 struct radeon_ring *ring = &rdev->ring[ib->ring]; 135 bool need_sync = false; 136 int i, r = 0; 137 138 if (!ib->length_dw || !ring->ready) { 139 /* TODO: Nothings in the ib we should report. */ 140 dev_err(rdev->dev, "couldn't schedule ib\n"); 141 return -EINVAL; 142 } 143 144 /* 64 dwords should be enough for fence too */ 145 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); 146 if (r) { 147 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 148 return r; 149 } 150 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 151 struct radeon_fence *fence = ib->sync_to[i]; 152 if (radeon_fence_need_sync(fence, ib->ring)) { 153 need_sync = true; 154 radeon_semaphore_sync_rings(rdev, ib->semaphore, 155 fence->ring, ib->ring); 156 radeon_fence_note_sync(fence, ib->ring); 157 } 158 } 159 /* immediately free semaphore when we don't need to sync */ 160 if (!need_sync) { 161 radeon_semaphore_free(rdev, &ib->semaphore, NULL); 162 } 163 /* if we can't remember our last VM flush then flush now! */ 164 if (ib->vm && !ib->vm->last_flush) { 165 radeon_ring_vm_flush(rdev, ib->ring, ib->vm); 166 } 167 if (const_ib) { 168 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); 169 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); 170 } 171 radeon_ring_ib_execute(rdev, ib->ring, ib); 172 r = radeon_fence_emit(rdev, &ib->fence, ib->ring); 173 if (r) { 174 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); 175 radeon_ring_unlock_undo(rdev, ring); 176 return r; 177 } 178 if (const_ib) { 179 const_ib->fence = radeon_fence_ref(ib->fence); 180 } 181 /* we just flushed the VM, remember that */ 182 if (ib->vm && !ib->vm->last_flush) { 183 ib->vm->last_flush = radeon_fence_ref(ib->fence); 184 } 185 radeon_ring_unlock_commit(rdev, ring); 186 return 0; 187 } 188 189 /** 190 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool 191 * 192 * @rdev: radeon_device pointer 193 * 194 * Initialize the suballocator to manage a pool of memory 195 * for use as IBs (all asics). 196 * Returns 0 on success, error on failure. 197 */ 198 int radeon_ib_pool_init(struct radeon_device *rdev) 199 { 200 int r; 201 202 if (rdev->ib_pool_ready) { 203 return 0; 204 } 205 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 206 RADEON_IB_POOL_SIZE*64*1024, 207 RADEON_GEM_DOMAIN_GTT); 208 if (r) { 209 return r; 210 } 211 212 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); 213 if (r) { 214 return r; 215 } 216 217 rdev->ib_pool_ready = true; 218 if (radeon_debugfs_sa_init(rdev)) { 219 dev_err(rdev->dev, "failed to register debugfs file for SA\n"); 220 } 221 return 0; 222 } 223 224 /** 225 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool 226 * 227 * @rdev: radeon_device pointer 228 * 229 * Tear down the suballocator managing the pool of memory 230 * for use as IBs (all asics). 231 */ 232 void radeon_ib_pool_fini(struct radeon_device *rdev) 233 { 234 if (rdev->ib_pool_ready) { 235 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); 236 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); 237 rdev->ib_pool_ready = false; 238 } 239 } 240 241 /** 242 * radeon_ib_ring_tests - test IBs on the rings 243 * 244 * @rdev: radeon_device pointer 245 * 246 * Test an IB (Indirect Buffer) on each ring. 247 * If the test fails, disable the ring. 248 * Returns 0 on success, error if the primary GFX ring 249 * IB test fails. 250 */ 251 int radeon_ib_ring_tests(struct radeon_device *rdev) 252 { 253 unsigned i; 254 int r; 255 256 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 257 struct radeon_ring *ring = &rdev->ring[i]; 258 259 if (!ring->ready) 260 continue; 261 262 r = radeon_ib_test(rdev, i, ring); 263 if (r) { 264 ring->ready = false; 265 266 if (i == RADEON_RING_TYPE_GFX_INDEX) { 267 /* oh, oh, that's really bad */ 268 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); 269 rdev->accel_working = false; 270 return r; 271 272 } else { 273 /* still not good, but we can live with it */ 274 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); 275 } 276 } 277 } 278 return 0; 279 } 280 281 /* 282 * Rings 283 * Most engines on the GPU are fed via ring buffers. Ring 284 * buffers are areas of GPU accessible memory that the host 285 * writes commands into and the GPU reads commands out of. 286 * There is a rptr (read pointer) that determines where the 287 * GPU is currently reading, and a wptr (write pointer) 288 * which determines where the host has written. When the 289 * pointers are equal, the ring is idle. When the host 290 * writes commands to the ring buffer, it increments the 291 * wptr. The GPU then starts fetching commands and executes 292 * them until the pointers are equal again. 293 */ 294 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); 295 296 /** 297 * radeon_ring_write - write a value to the ring 298 * 299 * @ring: radeon_ring structure holding ring information 300 * @v: dword (dw) value to write 301 * 302 * Write a value to the requested ring buffer (all asics). 303 */ 304 void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 305 { 306 #if DRM_DEBUG_CODE 307 if (ring->count_dw <= 0) { 308 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 309 } 310 #endif 311 ring->ring[ring->wptr++] = v; 312 ring->wptr &= ring->ptr_mask; 313 ring->count_dw--; 314 ring->ring_free_dw--; 315 } 316 317 /** 318 * radeon_ring_supports_scratch_reg - check if the ring supports 319 * writing to scratch registers 320 * 321 * @rdev: radeon_device pointer 322 * @ring: radeon_ring structure holding ring information 323 * 324 * Check if a specific ring supports writing to scratch registers (all asics). 325 * Returns true if the ring supports writing to scratch regs, false if not. 326 */ 327 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 328 struct radeon_ring *ring) 329 { 330 switch (ring->idx) { 331 case RADEON_RING_TYPE_GFX_INDEX: 332 case CAYMAN_RING_TYPE_CP1_INDEX: 333 case CAYMAN_RING_TYPE_CP2_INDEX: 334 return true; 335 default: 336 return false; 337 } 338 } 339 340 /** 341 * radeon_ring_free_size - update the free size 342 * 343 * @rdev: radeon_device pointer 344 * @ring: radeon_ring structure holding ring information 345 * 346 * Update the free dw slots in the ring buffer (all asics). 347 */ 348 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) 349 { 350 u32 rptr; 351 352 if (rdev->wb.enabled) 353 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 354 else 355 rptr = RREG32(ring->rptr_reg); 356 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 357 /* This works because ring_size is a power of 2 */ 358 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); 359 ring->ring_free_dw -= ring->wptr; 360 ring->ring_free_dw &= ring->ptr_mask; 361 if (!ring->ring_free_dw) { 362 ring->ring_free_dw = ring->ring_size / 4; 363 } 364 } 365 366 /** 367 * radeon_ring_alloc - allocate space on the ring buffer 368 * 369 * @rdev: radeon_device pointer 370 * @ring: radeon_ring structure holding ring information 371 * @ndw: number of dwords to allocate in the ring buffer 372 * 373 * Allocate @ndw dwords in the ring buffer (all asics). 374 * Returns 0 on success, error on failure. 375 */ 376 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 377 { 378 int r; 379 380 /* make sure we aren't trying to allocate more space than there is on the ring */ 381 if (ndw > (ring->ring_size / 4)) 382 return -ENOMEM; 383 /* Align requested size with padding so unlock_commit can 384 * pad safely */ 385 ndw = (ndw + ring->align_mask) & ~ring->align_mask; 386 while (ndw > (ring->ring_free_dw - 1)) { 387 radeon_ring_free_size(rdev, ring); 388 if (ndw < ring->ring_free_dw) { 389 break; 390 } 391 r = radeon_fence_wait_next_locked(rdev, ring->idx); 392 if (r) 393 return r; 394 } 395 ring->count_dw = ndw; 396 ring->wptr_old = ring->wptr; 397 return 0; 398 } 399 400 /** 401 * radeon_ring_lock - lock the ring and allocate space on it 402 * 403 * @rdev: radeon_device pointer 404 * @ring: radeon_ring structure holding ring information 405 * @ndw: number of dwords to allocate in the ring buffer 406 * 407 * Lock the ring and allocate @ndw dwords in the ring buffer 408 * (all asics). 409 * Returns 0 on success, error on failure. 410 */ 411 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 412 { 413 int r; 414 415 mutex_lock(&rdev->ring_lock); 416 r = radeon_ring_alloc(rdev, ring, ndw); 417 if (r) { 418 mutex_unlock(&rdev->ring_lock); 419 return r; 420 } 421 return 0; 422 } 423 424 /** 425 * radeon_ring_commit - tell the GPU to execute the new 426 * commands on the ring buffer 427 * 428 * @rdev: radeon_device pointer 429 * @ring: radeon_ring structure holding ring information 430 * 431 * Update the wptr (write pointer) to tell the GPU to 432 * execute new commands on the ring buffer (all asics). 433 */ 434 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) 435 { 436 /* We pad to match fetch size */ 437 while (ring->wptr & ring->align_mask) { 438 radeon_ring_write(ring, ring->nop); 439 } 440 DRM_MEMORYBARRIER(); 441 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); 442 (void)RREG32(ring->wptr_reg); 443 } 444 445 /** 446 * radeon_ring_unlock_commit - tell the GPU to execute the new 447 * commands on the ring buffer and unlock it 448 * 449 * @rdev: radeon_device pointer 450 * @ring: radeon_ring structure holding ring information 451 * 452 * Call radeon_ring_commit() then unlock the ring (all asics). 453 */ 454 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) 455 { 456 radeon_ring_commit(rdev, ring); 457 mutex_unlock(&rdev->ring_lock); 458 } 459 460 /** 461 * radeon_ring_undo - reset the wptr 462 * 463 * @ring: radeon_ring structure holding ring information 464 * 465 * Reset the driver's copy of the wptr (all asics). 466 */ 467 void radeon_ring_undo(struct radeon_ring *ring) 468 { 469 ring->wptr = ring->wptr_old; 470 } 471 472 /** 473 * radeon_ring_unlock_undo - reset the wptr and unlock the ring 474 * 475 * @ring: radeon_ring structure holding ring information 476 * 477 * Call radeon_ring_undo() then unlock the ring (all asics). 478 */ 479 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) 480 { 481 radeon_ring_undo(ring); 482 mutex_unlock(&rdev->ring_lock); 483 } 484 485 /** 486 * radeon_ring_force_activity - add some nop packets to the ring 487 * 488 * @rdev: radeon_device pointer 489 * @ring: radeon_ring structure holding ring information 490 * 491 * Add some nop packets to the ring to force activity (all asics). 492 * Used for lockup detection to see if the rptr is advancing. 493 */ 494 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) 495 { 496 int r; 497 498 radeon_ring_free_size(rdev, ring); 499 if (ring->rptr == ring->wptr) { 500 r = radeon_ring_alloc(rdev, ring, 1); 501 if (!r) { 502 radeon_ring_write(ring, ring->nop); 503 radeon_ring_commit(rdev, ring); 504 } 505 } 506 } 507 508 /** 509 * radeon_ring_lockup_update - update lockup variables 510 * 511 * @ring: radeon_ring structure holding ring information 512 * 513 * Update the last rptr value and timestamp (all asics). 514 */ 515 void radeon_ring_lockup_update(struct radeon_ring *ring) 516 { 517 ring->last_rptr = ring->rptr; 518 ring->last_activity = jiffies; 519 } 520 521 /** 522 * radeon_ring_test_lockup() - check if ring is lockedup by recording information 523 * @rdev: radeon device structure 524 * @ring: radeon_ring structure holding ring information 525 * 526 * We don't need to initialize the lockup tracking information as we will either 527 * have CP rptr to a different value of jiffies wrap around which will force 528 * initialization of the lockup tracking informations. 529 * 530 * A possible false positivie is if we get call after while and last_cp_rptr == 531 * the current CP rptr, even if it's unlikely it might happen. To avoid this 532 * if the elapsed time since last call is bigger than 2 second than we return 533 * false and update the tracking information. Due to this the caller must call 534 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported 535 * the fencing code should be cautious about that. 536 * 537 * Caller should write to the ring to force CP to do something so we don't get 538 * false positive when CP is just gived nothing to do. 539 * 540 **/ 541 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 542 { 543 unsigned long cjiffies, elapsed; 544 uint32_t rptr; 545 546 cjiffies = jiffies; 547 if (!time_after(cjiffies, ring->last_activity)) { 548 /* likely a wrap around */ 549 radeon_ring_lockup_update(ring); 550 return false; 551 } 552 rptr = RREG32(ring->rptr_reg); 553 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 554 if (ring->rptr != ring->last_rptr) { 555 /* CP is still working no lockup */ 556 radeon_ring_lockup_update(ring); 557 return false; 558 } 559 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); 560 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { 561 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 562 return true; 563 } 564 /* give a chance to the GPU ... */ 565 return false; 566 } 567 568 /** 569 * radeon_ring_backup - Back up the content of a ring 570 * 571 * @rdev: radeon_device pointer 572 * @ring: the ring we want to back up 573 * 574 * Saves all unprocessed commits from a ring, returns the number of dwords saved. 575 */ 576 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 577 uint32_t **data) 578 { 579 unsigned size, ptr, i; 580 581 /* just in case lock the ring */ 582 mutex_lock(&rdev->ring_lock); 583 *data = NULL; 584 585 if (ring->ring_obj == NULL) { 586 mutex_unlock(&rdev->ring_lock); 587 return 0; 588 } 589 590 /* it doesn't make sense to save anything if all fences are signaled */ 591 if (!radeon_fence_count_emitted(rdev, ring->idx)) { 592 mutex_unlock(&rdev->ring_lock); 593 return 0; 594 } 595 596 /* calculate the number of dw on the ring */ 597 if (ring->rptr_save_reg) 598 ptr = RREG32(ring->rptr_save_reg); 599 else if (rdev->wb.enabled) 600 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); 601 else { 602 /* no way to read back the next rptr */ 603 mutex_unlock(&rdev->ring_lock); 604 return 0; 605 } 606 607 size = ring->wptr + (ring->ring_size / 4); 608 size -= ptr; 609 size &= ring->ptr_mask; 610 if (size == 0) { 611 mutex_unlock(&rdev->ring_lock); 612 return 0; 613 } 614 615 /* and then save the content of the ring */ 616 *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); 617 if (!*data) { 618 mutex_unlock(&rdev->ring_lock); 619 return 0; 620 } 621 for (i = 0; i < size; ++i) { 622 (*data)[i] = ring->ring[ptr++]; 623 ptr &= ring->ptr_mask; 624 } 625 626 mutex_unlock(&rdev->ring_lock); 627 return size; 628 } 629 630 /** 631 * radeon_ring_restore - append saved commands to the ring again 632 * 633 * @rdev: radeon_device pointer 634 * @ring: ring to append commands to 635 * @size: number of dwords we want to write 636 * @data: saved commands 637 * 638 * Allocates space on the ring and restore the previously saved commands. 639 */ 640 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 641 unsigned size, uint32_t *data) 642 { 643 int i, r; 644 645 if (!size || !data) 646 return 0; 647 648 /* restore the saved ring content */ 649 r = radeon_ring_lock(rdev, ring, size); 650 if (r) 651 return r; 652 653 for (i = 0; i < size; ++i) { 654 radeon_ring_write(ring, data[i]); 655 } 656 657 radeon_ring_unlock_commit(rdev, ring); 658 kfree(data); 659 return 0; 660 } 661 662 /** 663 * radeon_ring_init - init driver ring struct. 664 * 665 * @rdev: radeon_device pointer 666 * @ring: radeon_ring structure holding ring information 667 * @ring_size: size of the ring 668 * @rptr_offs: offset of the rptr writeback location in the WB buffer 669 * @rptr_reg: MMIO offset of the rptr register 670 * @wptr_reg: MMIO offset of the wptr register 671 * @ptr_reg_shift: bit offset of the rptr/wptr values 672 * @ptr_reg_mask: bit mask of the rptr/wptr values 673 * @nop: nop packet for this ring 674 * 675 * Initialize the driver information for the selected ring (all asics). 676 * Returns 0 on success, error on failure. 677 */ 678 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 679 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 680 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) 681 { 682 int r; 683 684 ring->ring_size = ring_size; 685 ring->rptr_offs = rptr_offs; 686 ring->rptr_reg = rptr_reg; 687 ring->wptr_reg = wptr_reg; 688 ring->ptr_reg_shift = ptr_reg_shift; 689 ring->ptr_reg_mask = ptr_reg_mask; 690 ring->nop = nop; 691 /* Allocate ring buffer */ 692 if (ring->ring_obj == NULL) { 693 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 694 RADEON_GEM_DOMAIN_GTT, 695 NULL, &ring->ring_obj); 696 if (r) { 697 dev_err(rdev->dev, "(%d) ring create failed\n", r); 698 return r; 699 } 700 r = radeon_bo_reserve(ring->ring_obj, false); 701 if (unlikely(r != 0)) 702 return r; 703 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, 704 &ring->gpu_addr); 705 if (r) { 706 radeon_bo_unreserve(ring->ring_obj); 707 dev_err(rdev->dev, "(%d) ring pin failed\n", r); 708 return r; 709 } 710 r = radeon_bo_kmap(ring->ring_obj, 711 (void **)&ring->ring); 712 radeon_bo_unreserve(ring->ring_obj); 713 if (r) { 714 dev_err(rdev->dev, "(%d) ring map failed\n", r); 715 return r; 716 } 717 } 718 ring->ptr_mask = (ring->ring_size / 4) - 1; 719 ring->ring_free_dw = ring->ring_size / 4; 720 if (rdev->wb.enabled) { 721 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); 722 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; 723 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; 724 } 725 if (radeon_debugfs_ring_init(rdev, ring)) { 726 DRM_ERROR("Failed to register debugfs file for rings !\n"); 727 } 728 radeon_ring_lockup_update(ring); 729 return 0; 730 } 731 732 /** 733 * radeon_ring_fini - tear down the driver ring struct. 734 * 735 * @rdev: radeon_device pointer 736 * @ring: radeon_ring structure holding ring information 737 * 738 * Tear down the driver information for the selected ring (all asics). 739 */ 740 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) 741 { 742 int r; 743 struct radeon_bo *ring_obj; 744 745 mutex_lock(&rdev->ring_lock); 746 ring_obj = ring->ring_obj; 747 ring->ready = false; 748 ring->ring = NULL; 749 ring->ring_obj = NULL; 750 mutex_unlock(&rdev->ring_lock); 751 752 if (ring_obj) { 753 r = radeon_bo_reserve(ring_obj, false); 754 if (likely(r == 0)) { 755 radeon_bo_kunmap(ring_obj); 756 radeon_bo_unpin(ring_obj); 757 radeon_bo_unreserve(ring_obj); 758 } 759 radeon_bo_unref(&ring_obj); 760 } 761 } 762 763 /* 764 * Debugfs info 765 */ 766 #if defined(CONFIG_DEBUG_FS) 767 768 static int radeon_debugfs_ring_info(struct seq_file *m, void *data) 769 { 770 struct drm_info_node *node = (struct drm_info_node *) m->private; 771 struct drm_device *dev = node->minor->dev; 772 struct radeon_device *rdev = dev->dev_private; 773 int ridx = *(int*)node->info_ent->data; 774 struct radeon_ring *ring = &rdev->ring[ridx]; 775 unsigned count, i, j; 776 u32 tmp; 777 778 radeon_ring_free_size(rdev, ring); 779 count = (ring->ring_size / 4) - ring->ring_free_dw; 780 tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; 781 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); 782 tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; 783 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); 784 if (ring->rptr_save_reg) { 785 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, 786 RREG32(ring->rptr_save_reg)); 787 } 788 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); 789 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); 790 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); 791 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); 792 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 793 seq_printf(m, "%u dwords in ring\n", count); 794 /* print 8 dw before current rptr as often it's the last executed 795 * packet that is the root issue 796 */ 797 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 798 for (j = 0; j <= (count + 32); j++) { 799 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); 800 i = (i + 1) & ring->ptr_mask; 801 } 802 return 0; 803 } 804 805 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 806 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 807 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 808 static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; 809 static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 810 811 static struct drm_info_list radeon_debugfs_ring_info_list[] = { 812 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, 813 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, 814 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, 815 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, 816 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, 817 }; 818 819 static int radeon_debugfs_sa_info(struct seq_file *m, void *data) 820 { 821 struct drm_info_node *node = (struct drm_info_node *) m->private; 822 struct drm_device *dev = node->minor->dev; 823 struct radeon_device *rdev = dev->dev_private; 824 825 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); 826 827 return 0; 828 829 } 830 831 static struct drm_info_list radeon_debugfs_sa_list[] = { 832 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, 833 }; 834 835 #endif 836 837 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) 838 { 839 #if defined(CONFIG_DEBUG_FS) 840 unsigned i; 841 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { 842 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; 843 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; 844 unsigned r; 845 846 if (&rdev->ring[ridx] != ring) 847 continue; 848 849 r = radeon_debugfs_add_files(rdev, info, 1); 850 if (r) 851 return r; 852 } 853 #endif 854 return 0; 855 } 856 857 static int radeon_debugfs_sa_init(struct radeon_device *rdev) 858 { 859 #if defined(CONFIG_DEBUG_FS) 860 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); 861 #else 862 return 0; 863 #endif 864 } 865