1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * 5771fe6b9SJerome Glisse * All Rights Reserved. 6771fe6b9SJerome Glisse * 7771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining 8771fe6b9SJerome Glisse * a copy of this software and associated documentation files (the 9771fe6b9SJerome Glisse * "Software"), to deal in the Software without restriction, including 10771fe6b9SJerome Glisse * without limitation on the rights to use, copy, modify, merge, 11771fe6b9SJerome Glisse * publish, distribute, sublicense, and/or sell copies of the Software, 12771fe6b9SJerome Glisse * and to permit persons to whom the Software is furnished to do so, 13771fe6b9SJerome Glisse * subject to the following conditions: 14771fe6b9SJerome Glisse * 15771fe6b9SJerome Glisse * The above copyright notice and this permission notice (including the 16771fe6b9SJerome Glisse * next paragraph) shall be included in all copies or substantial 17771fe6b9SJerome Glisse * portions of the Software. 18771fe6b9SJerome Glisse * 19771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20771fe6b9SJerome Glisse * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21771fe6b9SJerome Glisse * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22771fe6b9SJerome Glisse * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23771fe6b9SJerome Glisse * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24771fe6b9SJerome Glisse * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25771fe6b9SJerome Glisse * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26771fe6b9SJerome Glisse * DEALINGS IN THE SOFTWARE. 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse 29771fe6b9SJerome Glisse /* 30771fe6b9SJerome Glisse * Authors: 31771fe6b9SJerome Glisse * Kevin E. Martin <martin@xfree86.org> 32771fe6b9SJerome Glisse * Rickard E. Faith <faith@valinux.com> 33771fe6b9SJerome Glisse * Alan Hourihane <alanh@fairlite.demon.co.uk> 34771fe6b9SJerome Glisse * 35771fe6b9SJerome Glisse * References: 36771fe6b9SJerome Glisse * 37771fe6b9SJerome Glisse * !!!! FIXME !!!! 38771fe6b9SJerome Glisse * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 39771fe6b9SJerome Glisse * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 40771fe6b9SJerome Glisse * 1999. 41771fe6b9SJerome Glisse * 42771fe6b9SJerome Glisse * !!!! FIXME !!!! 43771fe6b9SJerome Glisse * RAGE 128 Software Development Manual (Technical Reference Manual P/N 44771fe6b9SJerome Glisse * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 45771fe6b9SJerome Glisse * 46771fe6b9SJerome Glisse */ 47771fe6b9SJerome Glisse 48771fe6b9SJerome Glisse /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h 49771fe6b9SJerome Glisse * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT 50771fe6b9SJerome Glisse * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ 51771fe6b9SJerome Glisse #ifndef _RADEON_REG_H_ 52771fe6b9SJerome Glisse #define _RADEON_REG_H_ 53771fe6b9SJerome Glisse 54771fe6b9SJerome Glisse #include "r300_reg.h" 55771fe6b9SJerome Glisse #include "r500_reg.h" 56771fe6b9SJerome Glisse #include "r600_reg.h" 57bcc1c2a1SAlex Deucher #include "evergreen_reg.h" 58771fe6b9SJerome Glisse 59771fe6b9SJerome Glisse #define RADEON_MC_AGP_LOCATION 0x014c 60771fe6b9SJerome Glisse #define RADEON_MC_AGP_START_MASK 0x0000FFFF 61771fe6b9SJerome Glisse #define RADEON_MC_AGP_START_SHIFT 0 62771fe6b9SJerome Glisse #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000 63771fe6b9SJerome Glisse #define RADEON_MC_AGP_TOP_SHIFT 16 64771fe6b9SJerome Glisse #define RADEON_MC_FB_LOCATION 0x0148 65771fe6b9SJerome Glisse #define RADEON_MC_FB_START_MASK 0x0000FFFF 66771fe6b9SJerome Glisse #define RADEON_MC_FB_START_SHIFT 0 67771fe6b9SJerome Glisse #define RADEON_MC_FB_TOP_MASK 0xFFFF0000 68771fe6b9SJerome Glisse #define RADEON_MC_FB_TOP_SHIFT 16 69771fe6b9SJerome Glisse #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 70771fe6b9SJerome Glisse #define RADEON_AGP_BASE 0x0170 71771fe6b9SJerome Glisse 72771fe6b9SJerome Glisse #define ATI_DATATYPE_VQ 0 73771fe6b9SJerome Glisse #define ATI_DATATYPE_CI4 1 74771fe6b9SJerome Glisse #define ATI_DATATYPE_CI8 2 75771fe6b9SJerome Glisse #define ATI_DATATYPE_ARGB1555 3 76771fe6b9SJerome Glisse #define ATI_DATATYPE_RGB565 4 77771fe6b9SJerome Glisse #define ATI_DATATYPE_RGB888 5 78771fe6b9SJerome Glisse #define ATI_DATATYPE_ARGB8888 6 79771fe6b9SJerome Glisse #define ATI_DATATYPE_RGB332 7 80771fe6b9SJerome Glisse #define ATI_DATATYPE_Y8 8 81771fe6b9SJerome Glisse #define ATI_DATATYPE_RGB8 9 82771fe6b9SJerome Glisse #define ATI_DATATYPE_CI16 10 83771fe6b9SJerome Glisse #define ATI_DATATYPE_VYUY_422 11 84771fe6b9SJerome Glisse #define ATI_DATATYPE_YVYU_422 12 85771fe6b9SJerome Glisse #define ATI_DATATYPE_AYUV_444 14 86771fe6b9SJerome Glisse #define ATI_DATATYPE_ARGB4444 15 87771fe6b9SJerome Glisse 88771fe6b9SJerome Glisse /* Registers for 2D/Video/Overlay */ 89771fe6b9SJerome Glisse #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ 90771fe6b9SJerome Glisse #define RADEON_AGP_BASE 0x0170 91771fe6b9SJerome Glisse #define RADEON_AGP_CNTL 0x0174 92771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) 93771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) 94771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) 95771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) 96771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) 97771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) 98771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) 99771fe6b9SJerome Glisse # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) 100771fe6b9SJerome Glisse #define RADEON_STATUS_PCI_CONFIG 0x06 101771fe6b9SJerome Glisse # define RADEON_CAP_LIST 0x100000 102771fe6b9SJerome Glisse #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ 103771fe6b9SJerome Glisse # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ 104771fe6b9SJerome Glisse # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ 105771fe6b9SJerome Glisse # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ 106771fe6b9SJerome Glisse # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ 107771fe6b9SJerome Glisse #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ 108771fe6b9SJerome Glisse #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ 109771fe6b9SJerome Glisse # define RADEON_AGP_ENABLE (1<<8) 110771fe6b9SJerome Glisse #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ 111771fe6b9SJerome Glisse #define RADEON_AGP_STATUS 0x0f5c /* PCI */ 112771fe6b9SJerome Glisse # define RADEON_AGP_1X_MODE 0x01 113771fe6b9SJerome Glisse # define RADEON_AGP_2X_MODE 0x02 114771fe6b9SJerome Glisse # define RADEON_AGP_4X_MODE 0x04 115771fe6b9SJerome Glisse # define RADEON_AGP_FW_MODE 0x10 116771fe6b9SJerome Glisse # define RADEON_AGP_MODE_MASK 0x17 117771fe6b9SJerome Glisse # define RADEON_AGPv3_MODE 0x08 118771fe6b9SJerome Glisse # define RADEON_AGPv3_4X_MODE 0x01 119771fe6b9SJerome Glisse # define RADEON_AGPv3_8X_MODE 0x02 120771fe6b9SJerome Glisse #define RADEON_ATTRDR 0x03c1 /* VGA */ 121771fe6b9SJerome Glisse #define RADEON_ATTRDW 0x03c0 /* VGA */ 122771fe6b9SJerome Glisse #define RADEON_ATTRX 0x03c0 /* VGA */ 123771fe6b9SJerome Glisse #define RADEON_AUX_SC_CNTL 0x1660 124771fe6b9SJerome Glisse # define RADEON_AUX1_SC_EN (1 << 0) 125771fe6b9SJerome Glisse # define RADEON_AUX1_SC_MODE_OR (0 << 1) 126771fe6b9SJerome Glisse # define RADEON_AUX1_SC_MODE_NAND (1 << 1) 127771fe6b9SJerome Glisse # define RADEON_AUX2_SC_EN (1 << 2) 128771fe6b9SJerome Glisse # define RADEON_AUX2_SC_MODE_OR (0 << 3) 129771fe6b9SJerome Glisse # define RADEON_AUX2_SC_MODE_NAND (1 << 3) 130771fe6b9SJerome Glisse # define RADEON_AUX3_SC_EN (1 << 4) 131771fe6b9SJerome Glisse # define RADEON_AUX3_SC_MODE_OR (0 << 5) 132771fe6b9SJerome Glisse # define RADEON_AUX3_SC_MODE_NAND (1 << 5) 133771fe6b9SJerome Glisse #define RADEON_AUX1_SC_BOTTOM 0x1670 134771fe6b9SJerome Glisse #define RADEON_AUX1_SC_LEFT 0x1664 135771fe6b9SJerome Glisse #define RADEON_AUX1_SC_RIGHT 0x1668 136771fe6b9SJerome Glisse #define RADEON_AUX1_SC_TOP 0x166c 137771fe6b9SJerome Glisse #define RADEON_AUX2_SC_BOTTOM 0x1680 138771fe6b9SJerome Glisse #define RADEON_AUX2_SC_LEFT 0x1674 139771fe6b9SJerome Glisse #define RADEON_AUX2_SC_RIGHT 0x1678 140771fe6b9SJerome Glisse #define RADEON_AUX2_SC_TOP 0x167c 141771fe6b9SJerome Glisse #define RADEON_AUX3_SC_BOTTOM 0x1690 142771fe6b9SJerome Glisse #define RADEON_AUX3_SC_LEFT 0x1684 143771fe6b9SJerome Glisse #define RADEON_AUX3_SC_RIGHT 0x1688 144771fe6b9SJerome Glisse #define RADEON_AUX3_SC_TOP 0x168c 145771fe6b9SJerome Glisse #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 146771fe6b9SJerome Glisse #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc 147771fe6b9SJerome Glisse 148771fe6b9SJerome Glisse #define RADEON_BASE_CODE 0x0f0b 149771fe6b9SJerome Glisse #define RADEON_BIOS_0_SCRATCH 0x0010 150771fe6b9SJerome Glisse # define RADEON_FP_PANEL_SCALABLE (1 << 16) 151771fe6b9SJerome Glisse # define RADEON_FP_PANEL_SCALE_EN (1 << 17) 152771fe6b9SJerome Glisse # define RADEON_FP_CHIP_SCALE_EN (1 << 18) 153771fe6b9SJerome Glisse # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) 154771fe6b9SJerome Glisse # define RADEON_DISPLAY_ROT_MASK (3 << 28) 155771fe6b9SJerome Glisse # define RADEON_DISPLAY_ROT_00 (0 << 28) 156771fe6b9SJerome Glisse # define RADEON_DISPLAY_ROT_90 (1 << 28) 157771fe6b9SJerome Glisse # define RADEON_DISPLAY_ROT_180 (2 << 28) 158771fe6b9SJerome Glisse # define RADEON_DISPLAY_ROT_270 (3 << 28) 159771fe6b9SJerome Glisse #define RADEON_BIOS_1_SCRATCH 0x0014 160771fe6b9SJerome Glisse #define RADEON_BIOS_2_SCRATCH 0x0018 161771fe6b9SJerome Glisse #define RADEON_BIOS_3_SCRATCH 0x001c 162771fe6b9SJerome Glisse #define RADEON_BIOS_4_SCRATCH 0x0020 163771fe6b9SJerome Glisse # define RADEON_CRT1_ATTACHED_MASK (3 << 0) 164771fe6b9SJerome Glisse # define RADEON_CRT1_ATTACHED_MONO (1 << 0) 165771fe6b9SJerome Glisse # define RADEON_CRT1_ATTACHED_COLOR (2 << 0) 166771fe6b9SJerome Glisse # define RADEON_LCD1_ATTACHED (1 << 2) 167771fe6b9SJerome Glisse # define RADEON_DFP1_ATTACHED (1 << 3) 168771fe6b9SJerome Glisse # define RADEON_TV1_ATTACHED_MASK (3 << 4) 169771fe6b9SJerome Glisse # define RADEON_TV1_ATTACHED_COMP (1 << 4) 170771fe6b9SJerome Glisse # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) 171771fe6b9SJerome Glisse # define RADEON_CRT2_ATTACHED_MASK (3 << 8) 172771fe6b9SJerome Glisse # define RADEON_CRT2_ATTACHED_MONO (1 << 8) 173771fe6b9SJerome Glisse # define RADEON_CRT2_ATTACHED_COLOR (2 << 8) 174771fe6b9SJerome Glisse # define RADEON_DFP2_ATTACHED (1 << 11) 175771fe6b9SJerome Glisse #define RADEON_BIOS_5_SCRATCH 0x0024 176771fe6b9SJerome Glisse # define RADEON_LCD1_ON (1 << 0) 177771fe6b9SJerome Glisse # define RADEON_CRT1_ON (1 << 1) 178771fe6b9SJerome Glisse # define RADEON_TV1_ON (1 << 2) 179771fe6b9SJerome Glisse # define RADEON_DFP1_ON (1 << 3) 180771fe6b9SJerome Glisse # define RADEON_CRT2_ON (1 << 5) 181771fe6b9SJerome Glisse # define RADEON_CV1_ON (1 << 6) 182771fe6b9SJerome Glisse # define RADEON_DFP2_ON (1 << 7) 183771fe6b9SJerome Glisse # define RADEON_LCD1_CRTC_MASK (1 << 8) 184771fe6b9SJerome Glisse # define RADEON_LCD1_CRTC_SHIFT 8 185771fe6b9SJerome Glisse # define RADEON_CRT1_CRTC_MASK (1 << 9) 186771fe6b9SJerome Glisse # define RADEON_CRT1_CRTC_SHIFT 9 187771fe6b9SJerome Glisse # define RADEON_TV1_CRTC_MASK (1 << 10) 188771fe6b9SJerome Glisse # define RADEON_TV1_CRTC_SHIFT 10 189771fe6b9SJerome Glisse # define RADEON_DFP1_CRTC_MASK (1 << 11) 190771fe6b9SJerome Glisse # define RADEON_DFP1_CRTC_SHIFT 11 191771fe6b9SJerome Glisse # define RADEON_CRT2_CRTC_MASK (1 << 12) 192771fe6b9SJerome Glisse # define RADEON_CRT2_CRTC_SHIFT 12 193771fe6b9SJerome Glisse # define RADEON_CV1_CRTC_MASK (1 << 13) 194771fe6b9SJerome Glisse # define RADEON_CV1_CRTC_SHIFT 13 195771fe6b9SJerome Glisse # define RADEON_DFP2_CRTC_MASK (1 << 14) 196771fe6b9SJerome Glisse # define RADEON_DFP2_CRTC_SHIFT 14 197771fe6b9SJerome Glisse # define RADEON_ACC_REQ_LCD1 (1 << 16) 198771fe6b9SJerome Glisse # define RADEON_ACC_REQ_CRT1 (1 << 17) 199771fe6b9SJerome Glisse # define RADEON_ACC_REQ_TV1 (1 << 18) 200771fe6b9SJerome Glisse # define RADEON_ACC_REQ_DFP1 (1 << 19) 201771fe6b9SJerome Glisse # define RADEON_ACC_REQ_CRT2 (1 << 21) 202771fe6b9SJerome Glisse # define RADEON_ACC_REQ_TV2 (1 << 22) 203771fe6b9SJerome Glisse # define RADEON_ACC_REQ_DFP2 (1 << 23) 204771fe6b9SJerome Glisse #define RADEON_BIOS_6_SCRATCH 0x0028 205771fe6b9SJerome Glisse # define RADEON_ACC_MODE_CHANGE (1 << 2) 206771fe6b9SJerome Glisse # define RADEON_EXT_DESKTOP_MODE (1 << 3) 207771fe6b9SJerome Glisse # define RADEON_LCD_DPMS_ON (1 << 20) 208771fe6b9SJerome Glisse # define RADEON_CRT_DPMS_ON (1 << 21) 209771fe6b9SJerome Glisse # define RADEON_TV_DPMS_ON (1 << 22) 210771fe6b9SJerome Glisse # define RADEON_DFP_DPMS_ON (1 << 23) 211771fe6b9SJerome Glisse # define RADEON_DPMS_MASK (3 << 24) 212771fe6b9SJerome Glisse # define RADEON_DPMS_ON (0 << 24) 213771fe6b9SJerome Glisse # define RADEON_DPMS_STANDBY (1 << 24) 214771fe6b9SJerome Glisse # define RADEON_DPMS_SUSPEND (2 << 24) 215771fe6b9SJerome Glisse # define RADEON_DPMS_OFF (3 << 24) 216771fe6b9SJerome Glisse # define RADEON_SCREEN_BLANKING (1 << 26) 217771fe6b9SJerome Glisse # define RADEON_DRIVER_CRITICAL (1 << 27) 218771fe6b9SJerome Glisse # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) 219771fe6b9SJerome Glisse #define RADEON_BIOS_7_SCRATCH 0x002c 220771fe6b9SJerome Glisse # define RADEON_SYS_HOTKEY (1 << 10) 221771fe6b9SJerome Glisse # define RADEON_DRV_LOADED (1 << 12) 222771fe6b9SJerome Glisse #define RADEON_BIOS_ROM 0x0f30 /* PCI */ 223771fe6b9SJerome Glisse #define RADEON_BIST 0x0f0f /* PCI */ 224771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA0 0x1480 225771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA1 0x1484 226771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA10 0x14a8 227771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA11 0x14ac 228771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA12 0x14b0 229771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA13 0x14b4 230771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA14 0x14b8 231771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA15 0x14bc 232771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA16 0x14c0 233771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA17 0x14c4 234771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA18 0x14c8 235771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA19 0x14cc 236771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA2 0x1488 237771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA20 0x14d0 238771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA21 0x14d4 239771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA22 0x14d8 240771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA23 0x14dc 241771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA24 0x14e0 242771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA25 0x14e4 243771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA26 0x14e8 244771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA27 0x14ec 245771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA28 0x14f0 246771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA29 0x14f4 247771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA3 0x148c 248771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA30 0x14f8 249771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA31 0x14fc 250771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA32 0x1500 251771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA33 0x1504 252771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA34 0x1508 253771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA35 0x150c 254771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA36 0x1510 255771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA37 0x1514 256771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA38 0x1518 257771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA39 0x151c 258771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA4 0x1490 259771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA40 0x1520 260771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA41 0x1524 261771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA42 0x1528 262771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA43 0x152c 263771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA44 0x1530 264771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA45 0x1534 265771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA46 0x1538 266771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA47 0x153c 267771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA48 0x1540 268771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA49 0x1544 269771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA5 0x1494 270771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA50 0x1548 271771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA51 0x154c 272771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA52 0x1550 273771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA53 0x1554 274771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA54 0x1558 275771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA55 0x155c 276771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA56 0x1560 277771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA57 0x1564 278771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA58 0x1568 279771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA59 0x156c 280771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA6 0x1498 281771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA60 0x1570 282771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA61 0x1574 283771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA62 0x1578 284771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA63 0x157c 285771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA7 0x149c 286771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA8 0x14a0 287771fe6b9SJerome Glisse #define RADEON_BRUSH_DATA9 0x14a4 288771fe6b9SJerome Glisse #define RADEON_BRUSH_SCALE 0x1470 289771fe6b9SJerome Glisse #define RADEON_BRUSH_Y_X 0x1474 290771fe6b9SJerome Glisse #define RADEON_BUS_CNTL 0x0030 291771fe6b9SJerome Glisse # define RADEON_BUS_MASTER_DIS (1 << 6) 292771fe6b9SJerome Glisse # define RADEON_BUS_BIOS_DIS_ROM (1 << 12) 2933e5cb98dSAlex Deucher # define RS600_BUS_MASTER_DIS (1 << 14) 2943e5cb98dSAlex Deucher # define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */ 295771fe6b9SJerome Glisse # define RADEON_BUS_RD_DISCARD_EN (1 << 24) 296771fe6b9SJerome Glisse # define RADEON_BUS_RD_ABORT_EN (1 << 25) 297771fe6b9SJerome Glisse # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) 298771fe6b9SJerome Glisse # define RADEON_BUS_WRT_BURST (1 << 29) 299771fe6b9SJerome Glisse # define RADEON_BUS_READ_BURST (1 << 30) 300771fe6b9SJerome Glisse #define RADEON_BUS_CNTL1 0x0034 301771fe6b9SJerome Glisse # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 3023e5cb98dSAlex Deucher /* rv370/rv380, rv410, r423/r430/r480, r5xx */ 3033e5cb98dSAlex Deucher #define RADEON_MSI_REARM_EN 0x0160 3043e5cb98dSAlex Deucher # define RV370_MSI_REARM_EN (1 << 0) 305771fe6b9SJerome Glisse 306771fe6b9SJerome Glisse /* #define RADEON_PCIE_INDEX 0x0030 */ 307771fe6b9SJerome Glisse /* #define RADEON_PCIE_DATA 0x0034 */ 308771fe6b9SJerome Glisse #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ 309771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 310771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 311771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X0 0 312771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X1 1 313771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X2 2 314771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X4 3 315771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X8 4 316771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X12 5 317771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_X16 6 318771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 319771fe6b9SJerome Glisse # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 320771fe6b9SJerome Glisse # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) 321771fe6b9SJerome Glisse # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) 322771fe6b9SJerome Glisse # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) 323771fe6b9SJerome Glisse 324771fe6b9SJerome Glisse #define RADEON_CACHE_CNTL 0x1724 325771fe6b9SJerome Glisse #define RADEON_CACHE_LINE 0x0f0c /* PCI */ 326771fe6b9SJerome Glisse #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ 327771fe6b9SJerome Glisse #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ 328771fe6b9SJerome Glisse #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ 329771fe6b9SJerome Glisse # define RADEON_DONT_USE_XTALIN (1 << 4) 330771fe6b9SJerome Glisse # define RADEON_SCLK_DYN_START_CNTL (1 << 15) 331771fe6b9SJerome Glisse #define RADEON_CLOCK_CNTL_DATA 0x000c 332771fe6b9SJerome Glisse #define RADEON_CLOCK_CNTL_INDEX 0x0008 333771fe6b9SJerome Glisse # define RADEON_PLL_WR_EN (1 << 7) 334771fe6b9SJerome Glisse # define RADEON_PLL_DIV_SEL (3 << 8) 335771fe6b9SJerome Glisse # define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8)) 336771fe6b9SJerome Glisse #define RADEON_CLK_PWRMGT_CNTL 0x0014 337771fe6b9SJerome Glisse # define RADEON_ENGIN_DYNCLK_MODE (1 << 12) 338771fe6b9SJerome Glisse # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) 339771fe6b9SJerome Glisse # define RADEON_ACTIVE_HILO_LAT_SHIFT 13 340771fe6b9SJerome Glisse # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) 341771fe6b9SJerome Glisse # define RADEON_MC_BUSY (1 << 16) 342771fe6b9SJerome Glisse # define RADEON_DLL_READY (1 << 19) 343771fe6b9SJerome Glisse # define RADEON_CG_NO1_DEBUG_0 (1 << 24) 344771fe6b9SJerome Glisse # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) 345771fe6b9SJerome Glisse # define RADEON_DYN_STOP_MODE_MASK (7 << 21) 346771fe6b9SJerome Glisse # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) 347771fe6b9SJerome Glisse # define RADEON_TVCLK_TURNOFF (1 << 31) 348771fe6b9SJerome Glisse #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ 349d668046cSDave Airlie # define RADEON_PM_MODE_SEL (1 << 13) 350771fe6b9SJerome Glisse # define RADEON_TCL_BYPASS_DISABLE (1 << 20) 351771fe6b9SJerome Glisse #define RADEON_CLR_CMP_CLR_3D 0x1a24 352771fe6b9SJerome Glisse #define RADEON_CLR_CMP_CLR_DST 0x15c8 353771fe6b9SJerome Glisse #define RADEON_CLR_CMP_CLR_SRC 0x15c4 354771fe6b9SJerome Glisse #define RADEON_CLR_CMP_CNTL 0x15c0 355771fe6b9SJerome Glisse # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) 356771fe6b9SJerome Glisse # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) 357771fe6b9SJerome Glisse # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) 358771fe6b9SJerome Glisse #define RADEON_CLR_CMP_MASK 0x15cc 359771fe6b9SJerome Glisse # define RADEON_CLR_CMP_MSK 0xffffffff 360771fe6b9SJerome Glisse #define RADEON_CLR_CMP_MASK_3D 0x1A28 361771fe6b9SJerome Glisse #define RADEON_COMMAND 0x0f04 /* PCI */ 362771fe6b9SJerome Glisse #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c 363771fe6b9SJerome Glisse #define RADEON_CONFIG_APER_0_BASE 0x0100 364771fe6b9SJerome Glisse #define RADEON_CONFIG_APER_1_BASE 0x0104 365771fe6b9SJerome Glisse #define RADEON_CONFIG_APER_SIZE 0x0108 366771fe6b9SJerome Glisse #define RADEON_CONFIG_BONDS 0x00e8 367771fe6b9SJerome Glisse #define RADEON_CONFIG_CNTL 0x00e0 368771fe6b9SJerome Glisse # define RADEON_CFG_ATI_REV_A11 (0 << 16) 369771fe6b9SJerome Glisse # define RADEON_CFG_ATI_REV_A12 (1 << 16) 370771fe6b9SJerome Glisse # define RADEON_CFG_ATI_REV_A13 (2 << 16) 371771fe6b9SJerome Glisse # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) 372771fe6b9SJerome Glisse #define RADEON_CONFIG_MEMSIZE 0x00f8 373771fe6b9SJerome Glisse #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 374771fe6b9SJerome Glisse #define RADEON_CONFIG_REG_1_BASE 0x010c 375771fe6b9SJerome Glisse #define RADEON_CONFIG_REG_APER_SIZE 0x0110 376771fe6b9SJerome Glisse #define RADEON_CONFIG_XSTRAP 0x00e4 377771fe6b9SJerome Glisse #define RADEON_CONSTANT_COLOR_C 0x1d34 378771fe6b9SJerome Glisse # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff 379771fe6b9SJerome Glisse # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff 380771fe6b9SJerome Glisse # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 381771fe6b9SJerome Glisse #define RADEON_CRC_CMDFIFO_ADDR 0x0740 382771fe6b9SJerome Glisse #define RADEON_CRC_CMDFIFO_DOUT 0x0744 383771fe6b9SJerome Glisse #define RADEON_GRPH_BUFFER_CNTL 0x02f0 384771fe6b9SJerome Glisse # define RADEON_GRPH_START_REQ_MASK (0x7f) 385771fe6b9SJerome Glisse # define RADEON_GRPH_START_REQ_SHIFT 0 386771fe6b9SJerome Glisse # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) 387771fe6b9SJerome Glisse # define RADEON_GRPH_STOP_REQ_SHIFT 8 388771fe6b9SJerome Glisse # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) 389771fe6b9SJerome Glisse # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 390771fe6b9SJerome Glisse # define RADEON_GRPH_CRITICAL_CNTL (1<<28) 391771fe6b9SJerome Glisse # define RADEON_GRPH_BUFFER_SIZE (1<<29) 392771fe6b9SJerome Glisse # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) 393771fe6b9SJerome Glisse # define RADEON_GRPH_STOP_CNTL (1<<31) 394771fe6b9SJerome Glisse #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 395771fe6b9SJerome Glisse # define RADEON_GRPH2_START_REQ_MASK (0x7f) 396771fe6b9SJerome Glisse # define RADEON_GRPH2_START_REQ_SHIFT 0 397771fe6b9SJerome Glisse # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) 398771fe6b9SJerome Glisse # define RADEON_GRPH2_STOP_REQ_SHIFT 8 399771fe6b9SJerome Glisse # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) 400771fe6b9SJerome Glisse # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 401771fe6b9SJerome Glisse # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) 402771fe6b9SJerome Glisse # define RADEON_GRPH2_BUFFER_SIZE (1<<29) 403771fe6b9SJerome Glisse # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) 404771fe6b9SJerome Glisse # define RADEON_GRPH2_STOP_CNTL (1<<31) 405771fe6b9SJerome Glisse #define RADEON_CRTC_CRNT_FRAME 0x0214 406771fe6b9SJerome Glisse #define RADEON_CRTC_EXT_CNTL 0x0054 407771fe6b9SJerome Glisse # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) 408771fe6b9SJerome Glisse # define RADEON_VGA_ATI_LINEAR (1 << 3) 409771fe6b9SJerome Glisse # define RADEON_XCRT_CNT_EN (1 << 6) 410771fe6b9SJerome Glisse # define RADEON_CRTC_HSYNC_DIS (1 << 8) 411771fe6b9SJerome Glisse # define RADEON_CRTC_VSYNC_DIS (1 << 9) 412771fe6b9SJerome Glisse # define RADEON_CRTC_DISPLAY_DIS (1 << 10) 413771fe6b9SJerome Glisse # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) 414771fe6b9SJerome Glisse # define RADEON_CRTC_CRT_ON (1 << 15) 415771fe6b9SJerome Glisse #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 416771fe6b9SJerome Glisse # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) 417771fe6b9SJerome Glisse # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) 418771fe6b9SJerome Glisse # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) 419771fe6b9SJerome Glisse #define RADEON_CRTC_GEN_CNTL 0x0050 420771fe6b9SJerome Glisse # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) 421771fe6b9SJerome Glisse # define RADEON_CRTC_INTERLACE_EN (1 << 1) 422771fe6b9SJerome Glisse # define RADEON_CRTC_CSYNC_EN (1 << 4) 423771fe6b9SJerome Glisse # define RADEON_CRTC_ICON_EN (1 << 15) 424771fe6b9SJerome Glisse # define RADEON_CRTC_CUR_EN (1 << 16) 425771fe6b9SJerome Glisse # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) 426771fe6b9SJerome Glisse # define RADEON_CRTC_CUR_MODE_SHIFT 20 427771fe6b9SJerome Glisse # define RADEON_CRTC_CUR_MODE_MONO 0 428771fe6b9SJerome Glisse # define RADEON_CRTC_CUR_MODE_24BPP 2 429771fe6b9SJerome Glisse # define RADEON_CRTC_EXT_DISP_EN (1 << 24) 430771fe6b9SJerome Glisse # define RADEON_CRTC_EN (1 << 25) 431771fe6b9SJerome Glisse # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) 432771fe6b9SJerome Glisse #define RADEON_CRTC2_GEN_CNTL 0x03f8 433771fe6b9SJerome Glisse # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) 434771fe6b9SJerome Glisse # define RADEON_CRTC2_INTERLACE_EN (1 << 1) 435771fe6b9SJerome Glisse # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) 436771fe6b9SJerome Glisse # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) 437771fe6b9SJerome Glisse # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) 438771fe6b9SJerome Glisse # define RADEON_CRTC2_CRT2_ON (1 << 7) 439771fe6b9SJerome Glisse # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 440771fe6b9SJerome Glisse # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) 441771fe6b9SJerome Glisse # define RADEON_CRTC2_ICON_EN (1 << 15) 442771fe6b9SJerome Glisse # define RADEON_CRTC2_CUR_EN (1 << 16) 443771fe6b9SJerome Glisse # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) 444771fe6b9SJerome Glisse # define RADEON_CRTC2_DISP_DIS (1 << 23) 445771fe6b9SJerome Glisse # define RADEON_CRTC2_EN (1 << 25) 446771fe6b9SJerome Glisse # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) 447771fe6b9SJerome Glisse # define RADEON_CRTC2_CSYNC_EN (1 << 27) 448771fe6b9SJerome Glisse # define RADEON_CRTC2_HSYNC_DIS (1 << 28) 449771fe6b9SJerome Glisse # define RADEON_CRTC2_VSYNC_DIS (1 << 29) 450771fe6b9SJerome Glisse #define RADEON_CRTC_MORE_CNTL 0x27c 451771fe6b9SJerome Glisse # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) 452771fe6b9SJerome Glisse # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) 453771fe6b9SJerome Glisse # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 454771fe6b9SJerome Glisse # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 455771fe6b9SJerome Glisse #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 456771fe6b9SJerome Glisse #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 457771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) 458771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) 459771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 460771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) 461771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 462771fe6b9SJerome Glisse # define RADEON_CRTC_H_SYNC_POL (1 << 23) 463771fe6b9SJerome Glisse #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 464771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 465771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) 466771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 467771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) 468771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 469771fe6b9SJerome Glisse # define RADEON_CRTC2_H_SYNC_POL (1 << 23) 470771fe6b9SJerome Glisse #define RADEON_CRTC_H_TOTAL_DISP 0x0200 471771fe6b9SJerome Glisse # define RADEON_CRTC_H_TOTAL (0x03ff << 0) 472771fe6b9SJerome Glisse # define RADEON_CRTC_H_TOTAL_SHIFT 0 473771fe6b9SJerome Glisse # define RADEON_CRTC_H_DISP (0x01ff << 16) 474771fe6b9SJerome Glisse # define RADEON_CRTC_H_DISP_SHIFT 16 475771fe6b9SJerome Glisse #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 476771fe6b9SJerome Glisse # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) 477771fe6b9SJerome Glisse # define RADEON_CRTC2_H_TOTAL_SHIFT 0 478771fe6b9SJerome Glisse # define RADEON_CRTC2_H_DISP (0x01ff << 16) 479771fe6b9SJerome Glisse # define RADEON_CRTC2_H_DISP_SHIFT 16 480771fe6b9SJerome Glisse 481771fe6b9SJerome Glisse #define RADEON_CRTC_OFFSET_RIGHT 0x0220 482771fe6b9SJerome Glisse #define RADEON_CRTC_OFFSET 0x0224 483771fe6b9SJerome Glisse # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) 484771fe6b9SJerome Glisse # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) 485771fe6b9SJerome Glisse 486771fe6b9SJerome Glisse #define RADEON_CRTC2_OFFSET 0x0324 487771fe6b9SJerome Glisse # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) 488771fe6b9SJerome Glisse # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) 489771fe6b9SJerome Glisse #define RADEON_CRTC_OFFSET_CNTL 0x0228 490771fe6b9SJerome Glisse # define RADEON_CRTC_TILE_LINE_SHIFT 0 491771fe6b9SJerome Glisse # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 492771fe6b9SJerome Glisse # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) 493771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) 494771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) 495771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) 496771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) 497771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) 498771fe6b9SJerome Glisse # define R300_CRTC_X_Y_MODE_EN (1 << 9) 499771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) 500771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) 501771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) 502771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) 503771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) 504771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) 505771fe6b9SJerome Glisse # define R300_CRTC_MICRO_TILE_EN (1 << 13) 506771fe6b9SJerome Glisse # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) 507771fe6b9SJerome Glisse # define R300_CRTC_MACRO_TILE_EN (1 << 15) 508771fe6b9SJerome Glisse # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) 509771fe6b9SJerome Glisse # define RADEON_CRTC_TILE_EN (1 << 15) 510771fe6b9SJerome Glisse # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 511771fe6b9SJerome Glisse # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) 512771fe6b9SJerome Glisse 513771fe6b9SJerome Glisse #define R300_CRTC_TILE_X0_Y0 0x0350 514771fe6b9SJerome Glisse #define R300_CRTC2_TILE_X0_Y0 0x0358 515771fe6b9SJerome Glisse 516771fe6b9SJerome Glisse #define RADEON_CRTC2_OFFSET_CNTL 0x0328 517771fe6b9SJerome Glisse # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) 518771fe6b9SJerome Glisse # define RADEON_CRTC2_TILE_EN (1 << 15) 519771fe6b9SJerome Glisse #define RADEON_CRTC_PITCH 0x022c 520771fe6b9SJerome Glisse # define RADEON_CRTC_PITCH__SHIFT 0 521771fe6b9SJerome Glisse # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 522771fe6b9SJerome Glisse 523771fe6b9SJerome Glisse #define RADEON_CRTC2_PITCH 0x032c 524771fe6b9SJerome Glisse #define RADEON_CRTC_STATUS 0x005c 525771fe6b9SJerome Glisse # define RADEON_CRTC_VBLANK_SAVE (1 << 1) 526771fe6b9SJerome Glisse # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) 527771fe6b9SJerome Glisse #define RADEON_CRTC2_STATUS 0x03fc 528771fe6b9SJerome Glisse # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) 529771fe6b9SJerome Glisse # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) 530771fe6b9SJerome Glisse #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c 531771fe6b9SJerome Glisse # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) 532771fe6b9SJerome Glisse # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 533771fe6b9SJerome Glisse # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) 534771fe6b9SJerome Glisse # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 535771fe6b9SJerome Glisse # define RADEON_CRTC_V_SYNC_POL (1 << 23) 536771fe6b9SJerome Glisse #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c 537771fe6b9SJerome Glisse # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) 538771fe6b9SJerome Glisse # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 539771fe6b9SJerome Glisse # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) 540771fe6b9SJerome Glisse # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 541771fe6b9SJerome Glisse # define RADEON_CRTC2_V_SYNC_POL (1 << 23) 542771fe6b9SJerome Glisse #define RADEON_CRTC_V_TOTAL_DISP 0x0208 543771fe6b9SJerome Glisse # define RADEON_CRTC_V_TOTAL (0x07ff << 0) 544771fe6b9SJerome Glisse # define RADEON_CRTC_V_TOTAL_SHIFT 0 545771fe6b9SJerome Glisse # define RADEON_CRTC_V_DISP (0x07ff << 16) 546771fe6b9SJerome Glisse # define RADEON_CRTC_V_DISP_SHIFT 16 547771fe6b9SJerome Glisse #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 548771fe6b9SJerome Glisse # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) 549771fe6b9SJerome Glisse # define RADEON_CRTC2_V_TOTAL_SHIFT 0 550771fe6b9SJerome Glisse # define RADEON_CRTC2_V_DISP (0x07ff << 16) 551771fe6b9SJerome Glisse # define RADEON_CRTC2_V_DISP_SHIFT 16 552771fe6b9SJerome Glisse #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 553771fe6b9SJerome Glisse # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) 554771fe6b9SJerome Glisse #define RADEON_CRTC2_CRNT_FRAME 0x0314 555771fe6b9SJerome Glisse #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 556771fe6b9SJerome Glisse #define RADEON_CRTC2_STATUS 0x03fc 557771fe6b9SJerome Glisse #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 558771fe6b9SJerome Glisse #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 559771fe6b9SJerome Glisse #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 560771fe6b9SJerome Glisse #define RADEON_CUR_CLR0 0x026c 561771fe6b9SJerome Glisse #define RADEON_CUR_CLR1 0x0270 562771fe6b9SJerome Glisse #define RADEON_CUR_HORZ_VERT_OFF 0x0268 563771fe6b9SJerome Glisse #define RADEON_CUR_HORZ_VERT_POSN 0x0264 564771fe6b9SJerome Glisse #define RADEON_CUR_OFFSET 0x0260 565771fe6b9SJerome Glisse # define RADEON_CUR_LOCK (1 << 31) 566771fe6b9SJerome Glisse #define RADEON_CUR2_CLR0 0x036c 567771fe6b9SJerome Glisse #define RADEON_CUR2_CLR1 0x0370 568771fe6b9SJerome Glisse #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 569771fe6b9SJerome Glisse #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 570771fe6b9SJerome Glisse #define RADEON_CUR2_OFFSET 0x0360 571771fe6b9SJerome Glisse # define RADEON_CUR2_LOCK (1 << 31) 572771fe6b9SJerome Glisse 573771fe6b9SJerome Glisse #define RADEON_DAC_CNTL 0x0058 574771fe6b9SJerome Glisse # define RADEON_DAC_RANGE_CNTL (3 << 0) 575771fe6b9SJerome Glisse # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) 576771fe6b9SJerome Glisse # define RADEON_DAC_RANGE_CNTL_MASK 0x03 577771fe6b9SJerome Glisse # define RADEON_DAC_BLANKING (1 << 2) 578771fe6b9SJerome Glisse # define RADEON_DAC_CMP_EN (1 << 3) 579771fe6b9SJerome Glisse # define RADEON_DAC_CMP_OUTPUT (1 << 7) 580771fe6b9SJerome Glisse # define RADEON_DAC_8BIT_EN (1 << 8) 581771fe6b9SJerome Glisse # define RADEON_DAC_TVO_EN (1 << 10) 582771fe6b9SJerome Glisse # define RADEON_DAC_VGA_ADR_EN (1 << 13) 583771fe6b9SJerome Glisse # define RADEON_DAC_PDWN (1 << 15) 584771fe6b9SJerome Glisse # define RADEON_DAC_MASK_ALL (0xff << 24) 585771fe6b9SJerome Glisse #define RADEON_DAC_CNTL2 0x007c 586771fe6b9SJerome Glisse # define RADEON_DAC2_TV_CLK_SEL (0 << 1) 587771fe6b9SJerome Glisse # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) 588771fe6b9SJerome Glisse # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) 589771fe6b9SJerome Glisse # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) 590771fe6b9SJerome Glisse # define RADEON_DAC2_CMP_EN (1 << 7) 591771fe6b9SJerome Glisse # define RADEON_DAC2_CMP_OUT_R (1 << 8) 592771fe6b9SJerome Glisse # define RADEON_DAC2_CMP_OUT_G (1 << 9) 593771fe6b9SJerome Glisse # define RADEON_DAC2_CMP_OUT_B (1 << 10) 594771fe6b9SJerome Glisse # define RADEON_DAC2_CMP_OUTPUT (1 << 11) 595771fe6b9SJerome Glisse #define RADEON_DAC_EXT_CNTL 0x0280 596771fe6b9SJerome Glisse # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) 597771fe6b9SJerome Glisse # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) 598771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) 599771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_EN (1 << 5) 600771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) 601771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) 602771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) 603771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) 604771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) 605771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 606771fe6b9SJerome Glisse # define RADEON_DAC_FORCE_DATA_SHIFT 8 607771fe6b9SJerome Glisse #define RADEON_DAC_MACRO_CNTL 0x0d04 608771fe6b9SJerome Glisse # define RADEON_DAC_PDWN_R (1 << 16) 609771fe6b9SJerome Glisse # define RADEON_DAC_PDWN_G (1 << 17) 610771fe6b9SJerome Glisse # define RADEON_DAC_PDWN_B (1 << 18) 611771fe6b9SJerome Glisse #define RADEON_DISP_PWR_MAN 0x0d08 612771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) 613771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4) 614771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8) 615771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8) 616771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8) 617771fe6b9SJerome Glisse # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8) 618771fe6b9SJerome Glisse # define RADEON_DISP_D3_RST (1 << 16) 619771fe6b9SJerome Glisse # define RADEON_DISP_D3_REG_RST (1 << 17) 620771fe6b9SJerome Glisse # define RADEON_DISP_D3_GRPH_RST (1 << 18) 621771fe6b9SJerome Glisse # define RADEON_DISP_D3_SUBPIC_RST (1 << 19) 622771fe6b9SJerome Glisse # define RADEON_DISP_D3_OV0_RST (1 << 20) 623771fe6b9SJerome Glisse # define RADEON_DISP_D1D2_GRPH_RST (1 << 21) 624771fe6b9SJerome Glisse # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22) 625771fe6b9SJerome Glisse # define RADEON_DISP_D1D2_OV0_RST (1 << 23) 626771fe6b9SJerome Glisse # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24) 627771fe6b9SJerome Glisse # define RADEON_TV_ENABLE_RST (1 << 25) 628771fe6b9SJerome Glisse # define RADEON_AUTO_PWRUP_EN (1 << 26) 629771fe6b9SJerome Glisse #define RADEON_TV_DAC_CNTL 0x088c 630771fe6b9SJerome Glisse # define RADEON_TV_DAC_NBLANK (1 << 0) 631771fe6b9SJerome Glisse # define RADEON_TV_DAC_NHOLD (1 << 1) 632771fe6b9SJerome Glisse # define RADEON_TV_DAC_PEDESTAL (1 << 2) 633771fe6b9SJerome Glisse # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) 634771fe6b9SJerome Glisse # define RADEON_TV_DAC_CMPOUT (1 << 5) 635771fe6b9SJerome Glisse # define RADEON_TV_DAC_STD_MASK (3 << 8) 636771fe6b9SJerome Glisse # define RADEON_TV_DAC_STD_PAL (0 << 8) 637771fe6b9SJerome Glisse # define RADEON_TV_DAC_STD_NTSC (1 << 8) 638771fe6b9SJerome Glisse # define RADEON_TV_DAC_STD_PS2 (2 << 8) 639771fe6b9SJerome Glisse # define RADEON_TV_DAC_STD_RS343 (3 << 8) 640771fe6b9SJerome Glisse # define RADEON_TV_DAC_BGSLEEP (1 << 6) 641771fe6b9SJerome Glisse # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) 642771fe6b9SJerome Glisse # define RADEON_TV_DAC_BGADJ_SHIFT 16 643771fe6b9SJerome Glisse # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) 644771fe6b9SJerome Glisse # define RADEON_TV_DAC_DACADJ_SHIFT 20 645771fe6b9SJerome Glisse # define RADEON_TV_DAC_RDACPD (1 << 24) 646771fe6b9SJerome Glisse # define RADEON_TV_DAC_GDACPD (1 << 25) 647771fe6b9SJerome Glisse # define RADEON_TV_DAC_BDACPD (1 << 26) 648771fe6b9SJerome Glisse # define RADEON_TV_DAC_RDACDET (1 << 29) 649771fe6b9SJerome Glisse # define RADEON_TV_DAC_GDACDET (1 << 30) 650771fe6b9SJerome Glisse # define RADEON_TV_DAC_BDACDET (1 << 31) 651771fe6b9SJerome Glisse # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) 652771fe6b9SJerome Glisse # define R420_TV_DAC_RDACPD (1 << 25) 653771fe6b9SJerome Glisse # define R420_TV_DAC_GDACPD (1 << 26) 654771fe6b9SJerome Glisse # define R420_TV_DAC_BDACPD (1 << 27) 655771fe6b9SJerome Glisse # define R420_TV_DAC_TVENABLE (1 << 28) 656771fe6b9SJerome Glisse #define RADEON_DISP_HW_DEBUG 0x0d14 657771fe6b9SJerome Glisse # define RADEON_CRT2_DISP1_SEL (1 << 5) 658771fe6b9SJerome Glisse #define RADEON_DISP_OUTPUT_CNTL 0x0d64 659771fe6b9SJerome Glisse # define RADEON_DISP_DAC_SOURCE_MASK 0x03 660771fe6b9SJerome Glisse # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c 661771fe6b9SJerome Glisse # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 662771fe6b9SJerome Glisse # define RADEON_DISP_DAC_SOURCE_RMX 0x02 663771fe6b9SJerome Glisse # define RADEON_DISP_DAC_SOURCE_LTU 0x03 664771fe6b9SJerome Glisse # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 665771fe6b9SJerome Glisse # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) 666771fe6b9SJerome Glisse # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 667771fe6b9SJerome Glisse # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) 668771fe6b9SJerome Glisse # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) 669771fe6b9SJerome Glisse # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) 670771fe6b9SJerome Glisse # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) 671771fe6b9SJerome Glisse # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) 672771fe6b9SJerome Glisse # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) 673771fe6b9SJerome Glisse # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) 674771fe6b9SJerome Glisse # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ 675771fe6b9SJerome Glisse # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ 676771fe6b9SJerome Glisse #define RADEON_DISP_TV_OUT_CNTL 0x0d6c 677771fe6b9SJerome Glisse # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) 678771fe6b9SJerome Glisse # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) 679771fe6b9SJerome Glisse #define RADEON_DAC_CRC_SIG 0x02cc 680771fe6b9SJerome Glisse #define RADEON_DAC_DATA 0x03c9 /* VGA */ 681771fe6b9SJerome Glisse #define RADEON_DAC_MASK 0x03c6 /* VGA */ 682771fe6b9SJerome Glisse #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ 683771fe6b9SJerome Glisse #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ 684771fe6b9SJerome Glisse #define RADEON_DDA_CONFIG 0x02e0 685771fe6b9SJerome Glisse #define RADEON_DDA_ON_OFF 0x02e4 686771fe6b9SJerome Glisse #define RADEON_DEFAULT_OFFSET 0x16e0 687771fe6b9SJerome Glisse #define RADEON_DEFAULT_PITCH 0x16e4 688771fe6b9SJerome Glisse #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 689771fe6b9SJerome Glisse # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 690771fe6b9SJerome Glisse # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 691771fe6b9SJerome Glisse #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 692771fe6b9SJerome Glisse #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 693771fe6b9SJerome Glisse #define RADEON_DEVICE_ID 0x0f02 /* PCI */ 694771fe6b9SJerome Glisse #define RADEON_DISP_MISC_CNTL 0x0d00 695771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) 696771fe6b9SJerome Glisse #define RADEON_DISP_MERGE_CNTL 0x0d60 697771fe6b9SJerome Glisse # define RADEON_DISP_ALPHA_MODE_MASK 0x03 698771fe6b9SJerome Glisse # define RADEON_DISP_ALPHA_MODE_KEY 0 699771fe6b9SJerome Glisse # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 700771fe6b9SJerome Glisse # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 701771fe6b9SJerome Glisse # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) 702771fe6b9SJerome Glisse # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) 703771fe6b9SJerome Glisse # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) 704771fe6b9SJerome Glisse # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) 705771fe6b9SJerome Glisse #define RADEON_DISP2_MERGE_CNTL 0x0d68 706771fe6b9SJerome Glisse # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) 707771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 708771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 709771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 710771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c 711771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 712771fe6b9SJerome Glisse #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 713771fe6b9SJerome Glisse #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 714771fe6b9SJerome Glisse #define RADEON_DP_BRUSH_FRGD_CLR 0x147c 715771fe6b9SJerome Glisse #define RADEON_DP_CNTL 0x16c0 716771fe6b9SJerome Glisse # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) 717771fe6b9SJerome Glisse # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) 718771fe6b9SJerome Glisse # define RADEON_DP_DST_TILE_LINEAR (0 << 3) 719771fe6b9SJerome Glisse # define RADEON_DP_DST_TILE_MACRO (1 << 3) 720771fe6b9SJerome Glisse # define RADEON_DP_DST_TILE_MICRO (2 << 3) 721771fe6b9SJerome Glisse # define RADEON_DP_DST_TILE_BOTH (3 << 3) 722771fe6b9SJerome Glisse #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 723771fe6b9SJerome Glisse # define RADEON_DST_Y_MAJOR (1 << 2) 724771fe6b9SJerome Glisse # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 725771fe6b9SJerome Glisse # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 726771fe6b9SJerome Glisse #define RADEON_DP_DATATYPE 0x16c4 727771fe6b9SJerome Glisse # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) 728771fe6b9SJerome Glisse #define RADEON_DP_GUI_MASTER_CNTL 0x146c 729771fe6b9SJerome Glisse # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 730771fe6b9SJerome Glisse # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 731771fe6b9SJerome Glisse # define RADEON_GMC_SRC_CLIPPING (1 << 2) 732771fe6b9SJerome Glisse # define RADEON_GMC_DST_CLIPPING (1 << 3) 733771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 734771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 735771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 736771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 737771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 738771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 739771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 740771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 741771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 742771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) 743771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) 744771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 745771fe6b9SJerome Glisse # define RADEON_GMC_BRUSH_NONE (15 << 4) 746771fe6b9SJerome Glisse # define RADEON_GMC_DST_8BPP_CI (2 << 8) 747771fe6b9SJerome Glisse # define RADEON_GMC_DST_15BPP (3 << 8) 748771fe6b9SJerome Glisse # define RADEON_GMC_DST_16BPP (4 << 8) 749771fe6b9SJerome Glisse # define RADEON_GMC_DST_24BPP (5 << 8) 750771fe6b9SJerome Glisse # define RADEON_GMC_DST_32BPP (6 << 8) 751771fe6b9SJerome Glisse # define RADEON_GMC_DST_8BPP_RGB (7 << 8) 752771fe6b9SJerome Glisse # define RADEON_GMC_DST_Y8 (8 << 8) 753771fe6b9SJerome Glisse # define RADEON_GMC_DST_RGB8 (9 << 8) 754771fe6b9SJerome Glisse # define RADEON_GMC_DST_VYUY (11 << 8) 755771fe6b9SJerome Glisse # define RADEON_GMC_DST_YVYU (12 << 8) 756771fe6b9SJerome Glisse # define RADEON_GMC_DST_AYUV444 (14 << 8) 757771fe6b9SJerome Glisse # define RADEON_GMC_DST_ARGB4444 (15 << 8) 758771fe6b9SJerome Glisse # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) 759771fe6b9SJerome Glisse # define RADEON_GMC_DST_DATATYPE_SHIFT 8 760771fe6b9SJerome Glisse # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) 761771fe6b9SJerome Glisse # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 762771fe6b9SJerome Glisse # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 763771fe6b9SJerome Glisse # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 764771fe6b9SJerome Glisse # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) 765771fe6b9SJerome Glisse # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) 766771fe6b9SJerome Glisse # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) 767771fe6b9SJerome Glisse # define RADEON_GMC_CONVERSION_TEMP (1 << 15) 768771fe6b9SJerome Glisse # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) 769771fe6b9SJerome Glisse # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) 770771fe6b9SJerome Glisse # define RADEON_GMC_ROP3_MASK (0xff << 16) 771771fe6b9SJerome Glisse # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) 772771fe6b9SJerome Glisse # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 773771fe6b9SJerome Glisse # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 774771fe6b9SJerome Glisse # define RADEON_GMC_3D_FCN_EN (1 << 27) 775771fe6b9SJerome Glisse # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 776771fe6b9SJerome Glisse # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) 777771fe6b9SJerome Glisse # define RADEON_GMC_WR_MSK_DIS (1 << 30) 778771fe6b9SJerome Glisse # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) 779771fe6b9SJerome Glisse # define RADEON_ROP3_ZERO 0x00000000 780771fe6b9SJerome Glisse # define RADEON_ROP3_DSa 0x00880000 781771fe6b9SJerome Glisse # define RADEON_ROP3_SDna 0x00440000 782771fe6b9SJerome Glisse # define RADEON_ROP3_S 0x00cc0000 783771fe6b9SJerome Glisse # define RADEON_ROP3_DSna 0x00220000 784771fe6b9SJerome Glisse # define RADEON_ROP3_D 0x00aa0000 785771fe6b9SJerome Glisse # define RADEON_ROP3_DSx 0x00660000 786771fe6b9SJerome Glisse # define RADEON_ROP3_DSo 0x00ee0000 787771fe6b9SJerome Glisse # define RADEON_ROP3_DSon 0x00110000 788771fe6b9SJerome Glisse # define RADEON_ROP3_DSxn 0x00990000 789771fe6b9SJerome Glisse # define RADEON_ROP3_Dn 0x00550000 790771fe6b9SJerome Glisse # define RADEON_ROP3_SDno 0x00dd0000 791771fe6b9SJerome Glisse # define RADEON_ROP3_Sn 0x00330000 792771fe6b9SJerome Glisse # define RADEON_ROP3_DSno 0x00bb0000 793771fe6b9SJerome Glisse # define RADEON_ROP3_DSan 0x00770000 794771fe6b9SJerome Glisse # define RADEON_ROP3_ONE 0x00ff0000 795771fe6b9SJerome Glisse # define RADEON_ROP3_DPa 0x00a00000 796771fe6b9SJerome Glisse # define RADEON_ROP3_PDna 0x00500000 797771fe6b9SJerome Glisse # define RADEON_ROP3_P 0x00f00000 798771fe6b9SJerome Glisse # define RADEON_ROP3_DPna 0x000a0000 799771fe6b9SJerome Glisse # define RADEON_ROP3_D 0x00aa0000 800771fe6b9SJerome Glisse # define RADEON_ROP3_DPx 0x005a0000 801771fe6b9SJerome Glisse # define RADEON_ROP3_DPo 0x00fa0000 802771fe6b9SJerome Glisse # define RADEON_ROP3_DPon 0x00050000 803771fe6b9SJerome Glisse # define RADEON_ROP3_PDxn 0x00a50000 804771fe6b9SJerome Glisse # define RADEON_ROP3_PDno 0x00f50000 805771fe6b9SJerome Glisse # define RADEON_ROP3_Pn 0x000f0000 806771fe6b9SJerome Glisse # define RADEON_ROP3_DPno 0x00af0000 807771fe6b9SJerome Glisse # define RADEON_ROP3_DPan 0x005f0000 808771fe6b9SJerome Glisse #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 809771fe6b9SJerome Glisse #define RADEON_DP_MIX 0x16c8 810771fe6b9SJerome Glisse #define RADEON_DP_SRC_BKGD_CLR 0x15dc 811771fe6b9SJerome Glisse #define RADEON_DP_SRC_FRGD_CLR 0x15d8 812771fe6b9SJerome Glisse #define RADEON_DP_WRITE_MASK 0x16cc 813771fe6b9SJerome Glisse #define RADEON_DST_BRES_DEC 0x1630 814771fe6b9SJerome Glisse #define RADEON_DST_BRES_ERR 0x1628 815771fe6b9SJerome Glisse #define RADEON_DST_BRES_INC 0x162c 816771fe6b9SJerome Glisse #define RADEON_DST_BRES_LNTH 0x1634 817771fe6b9SJerome Glisse #define RADEON_DST_BRES_LNTH_SUB 0x1638 818771fe6b9SJerome Glisse #define RADEON_DST_HEIGHT 0x1410 819771fe6b9SJerome Glisse #define RADEON_DST_HEIGHT_WIDTH 0x143c 820771fe6b9SJerome Glisse #define RADEON_DST_HEIGHT_WIDTH_8 0x158c 821771fe6b9SJerome Glisse #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 822771fe6b9SJerome Glisse #define RADEON_DST_HEIGHT_Y 0x15a0 823771fe6b9SJerome Glisse #define RADEON_DST_LINE_START 0x1600 824771fe6b9SJerome Glisse #define RADEON_DST_LINE_END 0x1604 825771fe6b9SJerome Glisse #define RADEON_DST_LINE_PATCOUNT 0x1608 826771fe6b9SJerome Glisse # define RADEON_BRES_CNTL_SHIFT 8 827771fe6b9SJerome Glisse #define RADEON_DST_OFFSET 0x1404 828771fe6b9SJerome Glisse #define RADEON_DST_PITCH 0x1408 829771fe6b9SJerome Glisse #define RADEON_DST_PITCH_OFFSET 0x142c 830771fe6b9SJerome Glisse #define RADEON_DST_PITCH_OFFSET_C 0x1c80 831771fe6b9SJerome Glisse # define RADEON_PITCH_SHIFT 21 832771fe6b9SJerome Glisse # define RADEON_DST_TILE_LINEAR (0 << 30) 833771fe6b9SJerome Glisse # define RADEON_DST_TILE_MACRO (1 << 30) 834771fe6b9SJerome Glisse # define RADEON_DST_TILE_MICRO (2 << 30) 835771fe6b9SJerome Glisse # define RADEON_DST_TILE_BOTH (3 << 30) 836771fe6b9SJerome Glisse #define RADEON_DST_WIDTH 0x140c 837771fe6b9SJerome Glisse #define RADEON_DST_WIDTH_HEIGHT 0x1598 838771fe6b9SJerome Glisse #define RADEON_DST_WIDTH_X 0x1588 839771fe6b9SJerome Glisse #define RADEON_DST_WIDTH_X_INCY 0x159c 840771fe6b9SJerome Glisse #define RADEON_DST_X 0x141c 841771fe6b9SJerome Glisse #define RADEON_DST_X_SUB 0x15a4 842771fe6b9SJerome Glisse #define RADEON_DST_X_Y 0x1594 843771fe6b9SJerome Glisse #define RADEON_DST_Y 0x1420 844771fe6b9SJerome Glisse #define RADEON_DST_Y_SUB 0x15a8 845771fe6b9SJerome Glisse #define RADEON_DST_Y_X 0x1438 846771fe6b9SJerome Glisse 847771fe6b9SJerome Glisse #define RADEON_FCP_CNTL 0x0910 848771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_PCICLK 0 849771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_PCLK 1 850771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_PCLKb 2 851771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_HREF 3 852771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_GND 4 853771fe6b9SJerome Glisse # define RADEON_FCP0_SRC_HREFb 5 854771fe6b9SJerome Glisse #define RADEON_FLUSH_1 0x1704 855771fe6b9SJerome Glisse #define RADEON_FLUSH_2 0x1708 856771fe6b9SJerome Glisse #define RADEON_FLUSH_3 0x170c 857771fe6b9SJerome Glisse #define RADEON_FLUSH_4 0x1710 858771fe6b9SJerome Glisse #define RADEON_FLUSH_5 0x1714 859771fe6b9SJerome Glisse #define RADEON_FLUSH_6 0x1718 860771fe6b9SJerome Glisse #define RADEON_FLUSH_7 0x171c 861771fe6b9SJerome Glisse #define RADEON_FOG_3D_TABLE_START 0x1810 862771fe6b9SJerome Glisse #define RADEON_FOG_3D_TABLE_END 0x1814 863771fe6b9SJerome Glisse #define RADEON_FOG_3D_TABLE_DENSITY 0x181c 864771fe6b9SJerome Glisse #define RADEON_FOG_TABLE_INDEX 0x1a14 865771fe6b9SJerome Glisse #define RADEON_FOG_TABLE_DATA 0x1a18 866771fe6b9SJerome Glisse #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 867771fe6b9SJerome Glisse #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 868771fe6b9SJerome Glisse # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff 869771fe6b9SJerome Glisse # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 870771fe6b9SJerome Glisse # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff 871771fe6b9SJerome Glisse # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 872771fe6b9SJerome Glisse # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 873771fe6b9SJerome Glisse # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 874771fe6b9SJerome Glisse # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff 875771fe6b9SJerome Glisse # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 876771fe6b9SJerome Glisse # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 877771fe6b9SJerome Glisse # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 878771fe6b9SJerome Glisse # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 879771fe6b9SJerome Glisse # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 880771fe6b9SJerome Glisse # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 881771fe6b9SJerome Glisse # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 882771fe6b9SJerome Glisse # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 883771fe6b9SJerome Glisse # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 884771fe6b9SJerome Glisse #define RADEON_FP_GEN_CNTL 0x0284 885771fe6b9SJerome Glisse # define RADEON_FP_FPON (1 << 0) 886771fe6b9SJerome Glisse # define RADEON_FP_BLANK_EN (1 << 1) 887771fe6b9SJerome Glisse # define RADEON_FP_TMDS_EN (1 << 2) 888771fe6b9SJerome Glisse # define RADEON_FP_PANEL_FORMAT (1 << 3) 889771fe6b9SJerome Glisse # define RADEON_FP_EN_TMDS (1 << 7) 890771fe6b9SJerome Glisse # define RADEON_FP_DETECT_SENSE (1 << 8) 891b500f680SAlex Deucher # define RADEON_FP_DETECT_INT_POL (1 << 9) 892771fe6b9SJerome Glisse # define R200_FP_SOURCE_SEL_MASK (3 << 10) 893771fe6b9SJerome Glisse # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) 894771fe6b9SJerome Glisse # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) 895771fe6b9SJerome Glisse # define R200_FP_SOURCE_SEL_RMX (2 << 10) 896771fe6b9SJerome Glisse # define R200_FP_SOURCE_SEL_TRANS (3 << 10) 897771fe6b9SJerome Glisse # define RADEON_FP_SEL_CRTC1 (0 << 13) 898771fe6b9SJerome Glisse # define RADEON_FP_SEL_CRTC2 (1 << 13) 899b500f680SAlex Deucher # define R300_HPD_SEL(x) ((x) << 13) 900771fe6b9SJerome Glisse # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 901771fe6b9SJerome Glisse # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 902771fe6b9SJerome Glisse # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) 903771fe6b9SJerome Glisse # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) 904771fe6b9SJerome Glisse # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 905771fe6b9SJerome Glisse # define RADEON_FP_DFP_SYNC_SEL (1 << 21) 906771fe6b9SJerome Glisse # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) 907771fe6b9SJerome Glisse # define RADEON_FP_CRT_SYNC_SEL (1 << 23) 908771fe6b9SJerome Glisse # define RADEON_FP_USE_SHADOW_EN (1 << 24) 909771fe6b9SJerome Glisse # define RADEON_FP_CRT_SYNC_ALT (1 << 26) 910771fe6b9SJerome Glisse #define RADEON_FP2_GEN_CNTL 0x0288 911771fe6b9SJerome Glisse # define RADEON_FP2_BLANK_EN (1 << 1) 912771fe6b9SJerome Glisse # define RADEON_FP2_ON (1 << 2) 913771fe6b9SJerome Glisse # define RADEON_FP2_PANEL_FORMAT (1 << 3) 914771fe6b9SJerome Glisse # define RADEON_FP2_DETECT_SENSE (1 << 8) 915b500f680SAlex Deucher # define RADEON_FP2_DETECT_INT_POL (1 << 9) 916771fe6b9SJerome Glisse # define R200_FP2_SOURCE_SEL_MASK (3 << 10) 917771fe6b9SJerome Glisse # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) 918771fe6b9SJerome Glisse # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) 919771fe6b9SJerome Glisse # define R200_FP2_SOURCE_SEL_RMX (2 << 10) 920771fe6b9SJerome Glisse # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) 921771fe6b9SJerome Glisse # define RADEON_FP2_SRC_SEL_MASK (3 << 13) 922771fe6b9SJerome Glisse # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) 923771fe6b9SJerome Glisse # define RADEON_FP2_FP_POL (1 << 16) 924771fe6b9SJerome Glisse # define RADEON_FP2_LP_POL (1 << 17) 925771fe6b9SJerome Glisse # define RADEON_FP2_SCK_POL (1 << 18) 926771fe6b9SJerome Glisse # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) 927771fe6b9SJerome Glisse # define RADEON_FP2_PAD_FLOP_EN (1 << 22) 928771fe6b9SJerome Glisse # define RADEON_FP2_CRC_EN (1 << 23) 929771fe6b9SJerome Glisse # define RADEON_FP2_CRC_READ_EN (1 << 24) 930771fe6b9SJerome Glisse # define RADEON_FP2_DVO_EN (1 << 25) 931771fe6b9SJerome Glisse # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) 932771fe6b9SJerome Glisse # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) 933771fe6b9SJerome Glisse # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) 934771fe6b9SJerome Glisse # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) 935771fe6b9SJerome Glisse #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 936771fe6b9SJerome Glisse #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 937771fe6b9SJerome Glisse #define RADEON_FP_HORZ_STRETCH 0x028c 938771fe6b9SJerome Glisse #define RADEON_FP_HORZ2_STRETCH 0x038c 939771fe6b9SJerome Glisse # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff 940771fe6b9SJerome Glisse # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 941771fe6b9SJerome Glisse # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) 942771fe6b9SJerome Glisse # define RADEON_HORZ_PANEL_SHIFT 16 943771fe6b9SJerome Glisse # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) 944771fe6b9SJerome Glisse # define RADEON_HORZ_STRETCH_BLEND (1 << 26) 945771fe6b9SJerome Glisse # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) 946771fe6b9SJerome Glisse # define RADEON_HORZ_AUTO_RATIO (1 << 27) 947771fe6b9SJerome Glisse # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) 948771fe6b9SJerome Glisse # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) 949771fe6b9SJerome Glisse #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 950771fe6b9SJerome Glisse #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 951771fe6b9SJerome Glisse #define RADEON_FP_VERT_STRETCH 0x0290 952771fe6b9SJerome Glisse #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 953771fe6b9SJerome Glisse #define RADEON_FP_VERT2_STRETCH 0x0390 954771fe6b9SJerome Glisse # define RADEON_VERT_PANEL_SIZE (0xfff << 12) 955771fe6b9SJerome Glisse # define RADEON_VERT_PANEL_SHIFT 12 956771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff 957771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 958771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_RATIO_MAX 4096 959771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_ENABLE (1 << 25) 960771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_LINEREP (0 << 26) 961771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_BLEND (1 << 26) 962771fe6b9SJerome Glisse # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) 963771fe6b9SJerome Glisse # define RADEON_VERT_AUTO_RATIO_INC (1 << 31) 964771fe6b9SJerome Glisse # define RADEON_VERT_STRETCH_RESERVED 0x71000000 965771fe6b9SJerome Glisse #define RS400_FP_2ND_GEN_CNTL 0x0384 966771fe6b9SJerome Glisse # define RS400_FP_2ND_ON (1 << 0) 967771fe6b9SJerome Glisse # define RS400_FP_2ND_BLANK_EN (1 << 1) 968771fe6b9SJerome Glisse # define RS400_TMDS_2ND_EN (1 << 2) 969771fe6b9SJerome Glisse # define RS400_PANEL_FORMAT_2ND (1 << 3) 970771fe6b9SJerome Glisse # define RS400_FP_2ND_EN_TMDS (1 << 7) 971771fe6b9SJerome Glisse # define RS400_FP_2ND_DETECT_SENSE (1 << 8) 972771fe6b9SJerome Glisse # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) 973771fe6b9SJerome Glisse # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) 974771fe6b9SJerome Glisse # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) 975771fe6b9SJerome Glisse # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) 976771fe6b9SJerome Glisse # define RS400_FP_2ND_DETECT_EN (1 << 12) 977771fe6b9SJerome Glisse # define RS400_HPD_2ND_SEL (1 << 13) 978771fe6b9SJerome Glisse #define RS400_FP2_2_GEN_CNTL 0x0388 979771fe6b9SJerome Glisse # define RS400_FP2_2_BLANK_EN (1 << 1) 980771fe6b9SJerome Glisse # define RS400_FP2_2_ON (1 << 2) 981771fe6b9SJerome Glisse # define RS400_FP2_2_PANEL_FORMAT (1 << 3) 982771fe6b9SJerome Glisse # define RS400_FP2_2_DETECT_SENSE (1 << 8) 983771fe6b9SJerome Glisse # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) 984771fe6b9SJerome Glisse # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) 985771fe6b9SJerome Glisse # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) 986771fe6b9SJerome Glisse # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) 987771fe6b9SJerome Glisse # define RS400_FP2_2_DVO2_EN (1 << 25) 988771fe6b9SJerome Glisse #define RS400_TMDS2_CNTL 0x0394 989771fe6b9SJerome Glisse #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 990771fe6b9SJerome Glisse # define RS400_TMDS2_PLLEN (1 << 0) 991771fe6b9SJerome Glisse # define RS400_TMDS2_PLLRST (1 << 1) 992771fe6b9SJerome Glisse 993771fe6b9SJerome Glisse #define RADEON_GEN_INT_CNTL 0x0040 9947ed220d7SMichel Dänzer # define RADEON_CRTC_VBLANK_MASK (1 << 0) 995b500f680SAlex Deucher # define RADEON_FP_DETECT_MASK (1 << 4) 9967ed220d7SMichel Dänzer # define RADEON_CRTC2_VBLANK_MASK (1 << 9) 997b500f680SAlex Deucher # define RADEON_FP2_DETECT_MASK (1 << 10) 998771fe6b9SJerome Glisse # define RADEON_SW_INT_ENABLE (1 << 25) 999771fe6b9SJerome Glisse #define RADEON_GEN_INT_STATUS 0x0044 10007ed220d7SMichel Dänzer # define AVIVO_DISPLAY_INT_STATUS (1 << 0) 10017ed220d7SMichel Dänzer # define RADEON_CRTC_VBLANK_STAT (1 << 0) 10027ed220d7SMichel Dänzer # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 1003b500f680SAlex Deucher # define RADEON_FP_DETECT_STAT (1 << 4) 1004b500f680SAlex Deucher # define RADEON_FP_DETECT_STAT_ACK (1 << 4) 10057ed220d7SMichel Dänzer # define RADEON_CRTC2_VBLANK_STAT (1 << 9) 10067ed220d7SMichel Dänzer # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 1007b500f680SAlex Deucher # define RADEON_FP2_DETECT_STAT (1 << 10) 1008b500f680SAlex Deucher # define RADEON_FP2_DETECT_STAT_ACK (1 << 10) 1009771fe6b9SJerome Glisse # define RADEON_SW_INT_FIRE (1 << 26) 1010771fe6b9SJerome Glisse # define RADEON_SW_INT_TEST (1 << 25) 1011771fe6b9SJerome Glisse # define RADEON_SW_INT_TEST_ACK (1 << 25) 1012771fe6b9SJerome Glisse #define RADEON_GENENB 0x03c3 /* VGA */ 1013771fe6b9SJerome Glisse #define RADEON_GENFC_RD 0x03ca /* VGA */ 1014771fe6b9SJerome Glisse #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ 1015771fe6b9SJerome Glisse #define RADEON_GENMO_RD 0x03cc /* VGA */ 1016771fe6b9SJerome Glisse #define RADEON_GENMO_WT 0x03c2 /* VGA */ 1017771fe6b9SJerome Glisse #define RADEON_GENS0 0x03c2 /* VGA */ 1018771fe6b9SJerome Glisse #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ 1019771fe6b9SJerome Glisse #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ 1020771fe6b9SJerome Glisse #define RADEON_GPIO_MONIDB 0x006c 1021771fe6b9SJerome Glisse #define RADEON_GPIO_CRT2_DDC 0x006c 1022771fe6b9SJerome Glisse #define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ 1023771fe6b9SJerome Glisse #define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ 1024771fe6b9SJerome Glisse # define RADEON_GPIO_A_0 (1 << 0) 1025771fe6b9SJerome Glisse # define RADEON_GPIO_A_1 (1 << 1) 1026771fe6b9SJerome Glisse # define RADEON_GPIO_Y_0 (1 << 8) 1027771fe6b9SJerome Glisse # define RADEON_GPIO_Y_1 (1 << 9) 1028771fe6b9SJerome Glisse # define RADEON_GPIO_Y_SHIFT_0 8 1029771fe6b9SJerome Glisse # define RADEON_GPIO_Y_SHIFT_1 9 1030771fe6b9SJerome Glisse # define RADEON_GPIO_EN_0 (1 << 16) 1031771fe6b9SJerome Glisse # define RADEON_GPIO_EN_1 (1 << 17) 1032771fe6b9SJerome Glisse # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ 1033771fe6b9SJerome Glisse # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ 1034771fe6b9SJerome Glisse #define RADEON_GRPH8_DATA 0x03cf /* VGA */ 1035771fe6b9SJerome Glisse #define RADEON_GRPH8_IDX 0x03ce /* VGA */ 1036771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG0 0x15e0 1037771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG1 0x15e4 1038771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG2 0x15e8 1039771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG3 0x15ec 1040771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG4 0x15f0 1041771fe6b9SJerome Glisse #define RADEON_GUI_SCRATCH_REG5 0x15f4 1042771fe6b9SJerome Glisse 1043771fe6b9SJerome Glisse #define RADEON_HEADER 0x0f0e /* PCI */ 1044771fe6b9SJerome Glisse #define RADEON_HOST_DATA0 0x17c0 1045771fe6b9SJerome Glisse #define RADEON_HOST_DATA1 0x17c4 1046771fe6b9SJerome Glisse #define RADEON_HOST_DATA2 0x17c8 1047771fe6b9SJerome Glisse #define RADEON_HOST_DATA3 0x17cc 1048771fe6b9SJerome Glisse #define RADEON_HOST_DATA4 0x17d0 1049771fe6b9SJerome Glisse #define RADEON_HOST_DATA5 0x17d4 1050771fe6b9SJerome Glisse #define RADEON_HOST_DATA6 0x17d8 1051771fe6b9SJerome Glisse #define RADEON_HOST_DATA7 0x17dc 1052771fe6b9SJerome Glisse #define RADEON_HOST_DATA_LAST 0x17e0 1053771fe6b9SJerome Glisse #define RADEON_HOST_PATH_CNTL 0x0130 1054771fe6b9SJerome Glisse # define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24) 1055771fe6b9SJerome Glisse # define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27) 1056771fe6b9SJerome Glisse # define RADEON_HDP_SOFT_RESET (1 << 26) 1057771fe6b9SJerome Glisse # define RADEON_HDP_APER_CNTL (1 << 23) 1058771fe6b9SJerome Glisse #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ 1059771fe6b9SJerome Glisse # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) 1060771fe6b9SJerome Glisse #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ 1061771fe6b9SJerome Glisse 1062771fe6b9SJerome Glisse /* Multimedia I2C bus */ 1063771fe6b9SJerome Glisse #define RADEON_I2C_CNTL_0 0x0090 1064771fe6b9SJerome Glisse # define RADEON_I2C_DONE (1 << 0) 1065771fe6b9SJerome Glisse # define RADEON_I2C_NACK (1 << 1) 1066771fe6b9SJerome Glisse # define RADEON_I2C_HALT (1 << 2) 1067771fe6b9SJerome Glisse # define RADEON_I2C_SOFT_RST (1 << 5) 1068771fe6b9SJerome Glisse # define RADEON_I2C_DRIVE_EN (1 << 6) 1069771fe6b9SJerome Glisse # define RADEON_I2C_DRIVE_SEL (1 << 7) 1070771fe6b9SJerome Glisse # define RADEON_I2C_START (1 << 8) 1071771fe6b9SJerome Glisse # define RADEON_I2C_STOP (1 << 9) 1072771fe6b9SJerome Glisse # define RADEON_I2C_RECEIVE (1 << 10) 1073771fe6b9SJerome Glisse # define RADEON_I2C_ABORT (1 << 11) 1074771fe6b9SJerome Glisse # define RADEON_I2C_GO (1 << 12) 1075fcec570bSAlex Deucher # define RADEON_I2C_PRESCALE_SHIFT 16 1076771fe6b9SJerome Glisse #define RADEON_I2C_CNTL_1 0x0094 1077fcec570bSAlex Deucher # define RADEON_I2C_DATA_COUNT_SHIFT 0 1078fcec570bSAlex Deucher # define RADEON_I2C_ADDR_COUNT_SHIFT 4 1079fcec570bSAlex Deucher # define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8 1080771fe6b9SJerome Glisse # define RADEON_I2C_SEL (1 << 16) 1081771fe6b9SJerome Glisse # define RADEON_I2C_EN (1 << 17) 1082fcec570bSAlex Deucher # define RADEON_I2C_TIME_LIMIT_SHIFT 24 1083771fe6b9SJerome Glisse #define RADEON_I2C_DATA 0x0098 1084771fe6b9SJerome Glisse 1085771fe6b9SJerome Glisse #define RADEON_DVI_I2C_CNTL_0 0x02e0 1086771fe6b9SJerome Glisse # define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) 108740bacf16SAlex Deucher # define R200_SEL_DDC1 0 /* depends on asic */ 108840bacf16SAlex Deucher # define R200_SEL_DDC2 1 /* depends on asic */ 108940bacf16SAlex Deucher # define R200_SEL_DDC3 2 /* depends on asic */ 109040bacf16SAlex Deucher # define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13) 109140bacf16SAlex Deucher # define RADEON_SW_CAN_USE_DVI_I2C (1 << 13) 109240bacf16SAlex Deucher # define RADEON_SW_DONE_USING_DVI_I2C (1 << 14) 109340bacf16SAlex Deucher # define RADEON_HW_NEEDS_DVI_I2C (1 << 14) 109440bacf16SAlex Deucher # define RADEON_ABORT_HW_DVI_I2C (1 << 15) 109540bacf16SAlex Deucher # define RADEON_HW_USING_DVI_I2C (1 << 15) 1096fcec570bSAlex Deucher #define RADEON_DVI_I2C_CNTL_1 0x02e4 1097771fe6b9SJerome Glisse #define RADEON_DVI_I2C_DATA 0x02e8 1098771fe6b9SJerome Glisse 1099771fe6b9SJerome Glisse #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ 1100771fe6b9SJerome Glisse #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ 1101771fe6b9SJerome Glisse #define RADEON_IO_BASE 0x0f14 /* PCI */ 1102771fe6b9SJerome Glisse 1103771fe6b9SJerome Glisse #define RADEON_LATENCY 0x0f0d /* PCI */ 1104771fe6b9SJerome Glisse #define RADEON_LEAD_BRES_DEC 0x1608 1105771fe6b9SJerome Glisse #define RADEON_LEAD_BRES_LNTH 0x161c 1106771fe6b9SJerome Glisse #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 1107771fe6b9SJerome Glisse #define RADEON_LVDS_GEN_CNTL 0x02d0 1108771fe6b9SJerome Glisse # define RADEON_LVDS_ON (1 << 0) 1109771fe6b9SJerome Glisse # define RADEON_LVDS_DISPLAY_DIS (1 << 1) 1110771fe6b9SJerome Glisse # define RADEON_LVDS_PANEL_TYPE (1 << 2) 1111771fe6b9SJerome Glisse # define RADEON_LVDS_PANEL_FORMAT (1 << 3) 1112771fe6b9SJerome Glisse # define RADEON_LVDS_NO_FM (0 << 4) 1113771fe6b9SJerome Glisse # define RADEON_LVDS_2_GREY (1 << 4) 1114771fe6b9SJerome Glisse # define RADEON_LVDS_4_GREY (2 << 4) 1115771fe6b9SJerome Glisse # define RADEON_LVDS_RST_FM (1 << 6) 1116771fe6b9SJerome Glisse # define RADEON_LVDS_EN (1 << 7) 1117771fe6b9SJerome Glisse # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 1118771fe6b9SJerome Glisse # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) 1119771fe6b9SJerome Glisse # define RADEON_LVDS_BL_MOD_EN (1 << 16) 1120771fe6b9SJerome Glisse # define RADEON_LVDS_BL_CLK_SEL (1 << 17) 1121771fe6b9SJerome Glisse # define RADEON_LVDS_DIGON (1 << 18) 1122771fe6b9SJerome Glisse # define RADEON_LVDS_BLON (1 << 19) 1123771fe6b9SJerome Glisse # define RADEON_LVDS_FP_POL_LOW (1 << 20) 1124771fe6b9SJerome Glisse # define RADEON_LVDS_LP_POL_LOW (1 << 21) 1125771fe6b9SJerome Glisse # define RADEON_LVDS_DTM_POL_LOW (1 << 22) 1126771fe6b9SJerome Glisse # define RADEON_LVDS_SEL_CRTC2 (1 << 23) 1127771fe6b9SJerome Glisse # define RADEON_LVDS_FPDI_EN (1 << 27) 1128771fe6b9SJerome Glisse # define RADEON_LVDS_HSYNC_DELAY_SHIFT 28 1129771fe6b9SJerome Glisse #define RADEON_LVDS_PLL_CNTL 0x02d4 1130771fe6b9SJerome Glisse # define RADEON_HSYNC_DELAY_SHIFT 28 1131771fe6b9SJerome Glisse # define RADEON_HSYNC_DELAY_MASK (0xf << 28) 1132771fe6b9SJerome Glisse # define RADEON_LVDS_PLL_EN (1 << 16) 1133771fe6b9SJerome Glisse # define RADEON_LVDS_PLL_RESET (1 << 17) 1134771fe6b9SJerome Glisse # define R300_LVDS_SRC_SEL_MASK (3 << 18) 1135771fe6b9SJerome Glisse # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) 1136771fe6b9SJerome Glisse # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) 1137771fe6b9SJerome Glisse # define R300_LVDS_SRC_SEL_RMX (2 << 18) 1138771fe6b9SJerome Glisse #define RADEON_LVDS_SS_GEN_CNTL 0x02ec 1139771fe6b9SJerome Glisse # define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16 1140771fe6b9SJerome Glisse # define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20 1141771fe6b9SJerome Glisse 1142771fe6b9SJerome Glisse #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ 1143771fe6b9SJerome Glisse #define RADEON_DISPLAY_BASE_ADDR 0x23c 1144771fe6b9SJerome Glisse #define RADEON_DISPLAY2_BASE_ADDR 0x33c 1145771fe6b9SJerome Glisse #define RADEON_OV0_BASE_ADDR 0x43c 1146771fe6b9SJerome Glisse #define RADEON_NB_TOM 0x15c 1147771fe6b9SJerome Glisse #define R300_MC_INIT_MISC_LAT_TIMER 0x180 1148771fe6b9SJerome Glisse # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 1149771fe6b9SJerome Glisse # define R300_MC_DISP0R_INIT_LAT_MASK 0xf 1150771fe6b9SJerome Glisse # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 1151771fe6b9SJerome Glisse # define R300_MC_DISP1R_INIT_LAT_MASK 0xf 1152771fe6b9SJerome Glisse #define RADEON_MCLK_CNTL 0x0012 /* PLL */ 1153771fe6b9SJerome Glisse # define RADEON_MCLKA_SRC_SEL_MASK 0x7 1154771fe6b9SJerome Glisse # define RADEON_FORCEON_MCLKA (1 << 16) 1155771fe6b9SJerome Glisse # define RADEON_FORCEON_MCLKB (1 << 17) 1156771fe6b9SJerome Glisse # define RADEON_FORCEON_YCLKA (1 << 18) 1157771fe6b9SJerome Glisse # define RADEON_FORCEON_YCLKB (1 << 19) 1158771fe6b9SJerome Glisse # define RADEON_FORCEON_MC (1 << 20) 1159771fe6b9SJerome Glisse # define RADEON_FORCEON_AIC (1 << 21) 1160771fe6b9SJerome Glisse # define R300_DISABLE_MC_MCLKA (1 << 21) 1161771fe6b9SJerome Glisse # define R300_DISABLE_MC_MCLKB (1 << 21) 1162771fe6b9SJerome Glisse #define RADEON_MCLK_MISC 0x001f /* PLL */ 1163771fe6b9SJerome Glisse # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) 1164771fe6b9SJerome Glisse # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) 1165771fe6b9SJerome Glisse # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) 1166771fe6b9SJerome Glisse # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) 11676a93cb25SAlex Deucher 1168fcec570bSAlex Deucher #define RADEON_GPIOPAD_MASK 0x0198 1169fcec570bSAlex Deucher #define RADEON_GPIOPAD_A 0x019c 1170771fe6b9SJerome Glisse #define RADEON_GPIOPAD_EN 0x01a0 1171fcec570bSAlex Deucher #define RADEON_GPIOPAD_Y 0x01a4 11726a93cb25SAlex Deucher #define RADEON_MDGPIO_MASK 0x01a8 11736a93cb25SAlex Deucher #define RADEON_MDGPIO_A 0x01ac 11746a93cb25SAlex Deucher #define RADEON_MDGPIO_EN 0x01b0 11756a93cb25SAlex Deucher #define RADEON_MDGPIO_Y 0x01b4 11766a93cb25SAlex Deucher 1177771fe6b9SJerome Glisse #define RADEON_MEM_ADDR_CONFIG 0x0148 1178771fe6b9SJerome Glisse #define RADEON_MEM_BASE 0x0f10 /* PCI */ 1179771fe6b9SJerome Glisse #define RADEON_MEM_CNTL 0x0140 1180771fe6b9SJerome Glisse # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 1181771fe6b9SJerome Glisse # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) 1182771fe6b9SJerome Glisse # define RV100_HALF_MODE (1 << 3) 1183771fe6b9SJerome Glisse # define R300_MEM_NUM_CHANNELS_MASK 0x03 1184771fe6b9SJerome Glisse # define R300_MEM_USE_CD_CH_ONLY (1 << 2) 1185771fe6b9SJerome Glisse #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ 1186771fe6b9SJerome Glisse #define RADEON_MEM_INIT_LAT_TIMER 0x0154 1187771fe6b9SJerome Glisse #define RADEON_MEM_INTF_CNTL 0x014c 1188771fe6b9SJerome Glisse #define RADEON_MEM_SDRAM_MODE_REG 0x0158 1189771fe6b9SJerome Glisse # define RADEON_SDRAM_MODE_MASK 0xffff0000 1190771fe6b9SJerome Glisse # define RADEON_B3MEM_RESET_MASK 0x6fffffff 1191771fe6b9SJerome Glisse # define RADEON_MEM_CFG_TYPE_DDR (1 << 30) 1192771fe6b9SJerome Glisse #define RADEON_MEM_STR_CNTL 0x0150 1193771fe6b9SJerome Glisse # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) 1194771fe6b9SJerome Glisse # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) 1195771fe6b9SJerome Glisse # define R300_MEM_PWRUP_COMPL_C (1 << 2) 1196771fe6b9SJerome Glisse # define R300_MEM_PWRUP_COMPL_D (1 << 3) 1197771fe6b9SJerome Glisse # define RADEON_MEM_PWRUP_COMPLETE 0x03 1198771fe6b9SJerome Glisse # define R300_MEM_PWRUP_COMPLETE 0x0f 1199771fe6b9SJerome Glisse #define RADEON_MC_STATUS 0x0150 1200771fe6b9SJerome Glisse # define RADEON_MC_IDLE (1 << 2) 1201771fe6b9SJerome Glisse # define R300_MC_IDLE (1 << 4) 1202771fe6b9SJerome Glisse #define RADEON_MEM_VGA_RP_SEL 0x003c 1203771fe6b9SJerome Glisse #define RADEON_MEM_VGA_WP_SEL 0x0038 1204771fe6b9SJerome Glisse #define RADEON_MIN_GRANT 0x0f3e /* PCI */ 1205771fe6b9SJerome Glisse #define RADEON_MM_DATA 0x0004 1206771fe6b9SJerome Glisse #define RADEON_MM_INDEX 0x0000 1207771fe6b9SJerome Glisse # define RADEON_MM_APER (1 << 31) 1208771fe6b9SJerome Glisse #define RADEON_MPLL_CNTL 0x000e /* PLL */ 1209771fe6b9SJerome Glisse #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ 1210771fe6b9SJerome Glisse #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ 1211771fe6b9SJerome Glisse #define RADEON_SEPROM_CNTL1 0x01c0 1212771fe6b9SJerome Glisse # define RADEON_SCK_PRESCALE_SHIFT 24 1213771fe6b9SJerome Glisse # define RADEON_SCK_PRESCALE_MASK (0xff << 24) 1214771fe6b9SJerome Glisse #define R300_MC_IND_INDEX 0x01f8 1215771fe6b9SJerome Glisse # define R300_MC_IND_ADDR_MASK 0x3f 1216771fe6b9SJerome Glisse # define R300_MC_IND_WR_EN (1 << 8) 1217771fe6b9SJerome Glisse #define R300_MC_IND_DATA 0x01fc 1218771fe6b9SJerome Glisse #define R300_MC_READ_CNTL_AB 0x017c 1219771fe6b9SJerome Glisse # define R300_MEM_RBS_POSITION_A_MASK 0x03 1220771fe6b9SJerome Glisse #define R300_MC_READ_CNTL_CD_mcind 0x24 1221771fe6b9SJerome Glisse # define R300_MEM_RBS_POSITION_C_MASK 0x03 1222771fe6b9SJerome Glisse 1223771fe6b9SJerome Glisse #define RADEON_N_VIF_COUNT 0x0248 1224771fe6b9SJerome Glisse 1225771fe6b9SJerome Glisse #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 1226771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 1227771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 1228771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 1229771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 1230771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 1231771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 1232771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 1233771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 1234771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 1235771fe6b9SJerome Glisse # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 1236771fe6b9SJerome Glisse 1237771fe6b9SJerome Glisse #define RADEON_OV0_COLOUR_CNTL 0x04E0 1238771fe6b9SJerome Glisse #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 1239771fe6b9SJerome Glisse #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 1240771fe6b9SJerome Glisse # define RADEON_EXCL_HORZ_START_MASK 0x000000ff 1241771fe6b9SJerome Glisse # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 1242771fe6b9SJerome Glisse # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 1243771fe6b9SJerome Glisse # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 1244771fe6b9SJerome Glisse #define RADEON_OV0_EXCLUSIVE_VERT 0x040C 1245771fe6b9SJerome Glisse # define RADEON_EXCL_VERT_START_MASK 0x000003ff 1246771fe6b9SJerome Glisse # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 1247771fe6b9SJerome Glisse #define RADEON_OV0_FILTER_CNTL 0x04A0 1248771fe6b9SJerome Glisse # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 1249771fe6b9SJerome Glisse # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 1250771fe6b9SJerome Glisse # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 1251771fe6b9SJerome Glisse # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 1252771fe6b9SJerome Glisse # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 1253771fe6b9SJerome Glisse # define RADEON_FILTER_HARDCODED_COEF 0xf 1254771fe6b9SJerome Glisse # define RADEON_FILTER_COEF_MASK 0xf 1255771fe6b9SJerome Glisse 1256771fe6b9SJerome Glisse #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 1257771fe6b9SJerome Glisse #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 1258771fe6b9SJerome Glisse #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 1259771fe6b9SJerome Glisse #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC 1260771fe6b9SJerome Glisse #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 1261771fe6b9SJerome Glisse #define RADEON_OV0_FLAG_CNTL 0x04DC 1262771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_000_00F 0x0d40 1263771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_010_01F 0x0d44 1264771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_020_03F 0x0d48 1265771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_040_07F 0x0d4c 1266771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_080_0BF 0x0e00 1267771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 1268771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_100_13F 0x0e08 1269771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_140_17F 0x0e0c 1270771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_180_1BF 0x0e10 1271771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 1272771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_200_23F 0x0e18 1273771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_240_27F 0x0e1c 1274771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_280_2BF 0x0e20 1275771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 1276771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_300_33F 0x0e28 1277771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_340_37F 0x0e2c 1278771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_380_3BF 0x0d50 1279771fe6b9SJerome Glisse #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 1280771fe6b9SJerome Glisse #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 1281771fe6b9SJerome Glisse #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 1282771fe6b9SJerome Glisse #define RADEON_OV0_H_INC 0x0480 1283771fe6b9SJerome Glisse #define RADEON_OV0_KEY_CNTL 0x04F4 1284771fe6b9SJerome Glisse # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L 1285771fe6b9SJerome Glisse # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L 1286771fe6b9SJerome Glisse # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L 1287771fe6b9SJerome Glisse # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L 1288771fe6b9SJerome Glisse # define RADEON_VIDEO_KEY_FN_NE 0x00000003L 1289771fe6b9SJerome Glisse # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L 1290771fe6b9SJerome Glisse # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L 1291771fe6b9SJerome Glisse # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L 1292771fe6b9SJerome Glisse # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L 1293771fe6b9SJerome Glisse # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L 1294771fe6b9SJerome Glisse # define RADEON_CMP_MIX_MASK 0x00000100L 1295771fe6b9SJerome Glisse # define RADEON_CMP_MIX_OR 0x00000000L 1296771fe6b9SJerome Glisse # define RADEON_CMP_MIX_AND 0x00000100L 1297771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_A 0x0d20 1298771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_B 0x0d24 1299771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_C 0x0d28 1300771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_D 0x0d2c 1301771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_E 0x0d30 1302771fe6b9SJerome Glisse #define RADEON_OV0_LIN_TRANS_F 0x0d34 1303771fe6b9SJerome Glisse #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 1304771fe6b9SJerome Glisse # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 1305771fe6b9SJerome Glisse # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L 1306771fe6b9SJerome Glisse #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 1307771fe6b9SJerome Glisse #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 1308771fe6b9SJerome Glisse # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 1309771fe6b9SJerome Glisse # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 1310771fe6b9SJerome Glisse #define RADEON_OV0_P1_X_START_END 0x0494 1311771fe6b9SJerome Glisse #define RADEON_OV0_P2_X_START_END 0x0498 1312771fe6b9SJerome Glisse #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 1313771fe6b9SJerome Glisse # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 1314771fe6b9SJerome Glisse # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L 1315771fe6b9SJerome Glisse #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C 1316771fe6b9SJerome Glisse #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C 1317771fe6b9SJerome Glisse #define RADEON_OV0_P3_X_START_END 0x049C 1318771fe6b9SJerome Glisse #define RADEON_OV0_REG_LOAD_CNTL 0x0410 1319771fe6b9SJerome Glisse # define RADEON_REG_LD_CTL_LOCK 0x00000001L 1320771fe6b9SJerome Glisse # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 1321771fe6b9SJerome Glisse # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 1322771fe6b9SJerome Glisse # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L 1323771fe6b9SJerome Glisse # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L 1324771fe6b9SJerome Glisse #define RADEON_OV0_SCALE_CNTL 0x0420 1325771fe6b9SJerome Glisse # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L 1326771fe6b9SJerome Glisse # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L 1327771fe6b9SJerome Glisse # define RADEON_SCALER_SIGNED_UV 0x00000010L 1328771fe6b9SJerome Glisse # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L 1329771fe6b9SJerome Glisse # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 1330771fe6b9SJerome Glisse # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L 1331771fe6b9SJerome Glisse # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L 1332771fe6b9SJerome Glisse # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L 1333771fe6b9SJerome Glisse # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 1334771fe6b9SJerome Glisse # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L 1335771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_15BPP 0x00000300L 1336771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_16BPP 0x00000400L 1337771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_32BPP 0x00000600L 1338771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_YUV9 0x00000900L 1339771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L 1340771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L 1341771fe6b9SJerome Glisse # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L 1342771fe6b9SJerome Glisse # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 1343771fe6b9SJerome Glisse # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L 1344771fe6b9SJerome Glisse # define RADEON_SCALER_CRTC_SEL 0x00004000L 1345771fe6b9SJerome Glisse # define RADEON_SCALER_SMART_SWITCH 0x00008000L 1346771fe6b9SJerome Glisse # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L 1347771fe6b9SJerome Glisse # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L 1348771fe6b9SJerome Glisse # define RADEON_SCALER_DIS_LIMIT 0x08000000L 1349771fe6b9SJerome Glisse # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L 1350771fe6b9SJerome Glisse # define RADEON_SCALER_INT_EMU 0x20000000L 1351771fe6b9SJerome Glisse # define RADEON_SCALER_ENABLE 0x40000000L 1352771fe6b9SJerome Glisse # define RADEON_SCALER_SOFT_RESET 0x80000000L 1353771fe6b9SJerome Glisse #define RADEON_OV0_STEP_BY 0x0484 1354771fe6b9SJerome Glisse #define RADEON_OV0_TEST 0x04F8 1355771fe6b9SJerome Glisse #define RADEON_OV0_V_INC 0x0424 1356771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 1357771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 1358771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 1359771fe6b9SJerome Glisse # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L 1360771fe6b9SJerome Glisse # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L 1361771fe6b9SJerome Glisse # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 1362771fe6b9SJerome Glisse # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 1363771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 1364771fe6b9SJerome Glisse # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L 1365771fe6b9SJerome Glisse # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L 1366771fe6b9SJerome Glisse # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 1367771fe6b9SJerome Glisse # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 1368771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 1369771fe6b9SJerome Glisse # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L 1370771fe6b9SJerome Glisse # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L 1371771fe6b9SJerome Glisse # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 1372771fe6b9SJerome Glisse # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 1373771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C 1374771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 1375771fe6b9SJerome Glisse #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 1376771fe6b9SJerome Glisse #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 1377771fe6b9SJerome Glisse #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 1378771fe6b9SJerome Glisse #define RADEON_OV0_Y_X_START 0x0400 1379771fe6b9SJerome Glisse #define RADEON_OV0_Y_X_END 0x0404 1380771fe6b9SJerome Glisse #define RADEON_OV1_Y_X_START 0x0600 1381771fe6b9SJerome Glisse #define RADEON_OV1_Y_X_END 0x0604 1382771fe6b9SJerome Glisse #define RADEON_OVR_CLR 0x0230 1383771fe6b9SJerome Glisse #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 1384771fe6b9SJerome Glisse #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 13856b02af1cSAlex Deucher #define RADEON_OVR2_CLR 0x0330 13866b02af1cSAlex Deucher #define RADEON_OVR2_WID_LEFT_RIGHT 0x0334 13876b02af1cSAlex Deucher #define RADEON_OVR2_WID_TOP_BOTTOM 0x0338 1388771fe6b9SJerome Glisse 1389771fe6b9SJerome Glisse /* first capture unit */ 1390771fe6b9SJerome Glisse 1391771fe6b9SJerome Glisse #define RADEON_CAP0_BUF0_OFFSET 0x0920 1392771fe6b9SJerome Glisse #define RADEON_CAP0_BUF1_OFFSET 0x0924 1393771fe6b9SJerome Glisse #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 1394771fe6b9SJerome Glisse #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C 1395771fe6b9SJerome Glisse 1396771fe6b9SJerome Glisse #define RADEON_CAP0_BUF_PITCH 0x0930 1397771fe6b9SJerome Glisse #define RADEON_CAP0_V_WINDOW 0x0934 1398771fe6b9SJerome Glisse #define RADEON_CAP0_H_WINDOW 0x0938 1399771fe6b9SJerome Glisse #define RADEON_CAP0_VBI0_OFFSET 0x093C 1400771fe6b9SJerome Glisse #define RADEON_CAP0_VBI1_OFFSET 0x0940 1401771fe6b9SJerome Glisse #define RADEON_CAP0_VBI_V_WINDOW 0x0944 1402771fe6b9SJerome Glisse #define RADEON_CAP0_VBI_H_WINDOW 0x0948 1403771fe6b9SJerome Glisse #define RADEON_CAP0_PORT_MODE_CNTL 0x094C 1404771fe6b9SJerome Glisse #define RADEON_CAP0_TRIG_CNTL 0x0950 1405771fe6b9SJerome Glisse #define RADEON_CAP0_DEBUG 0x0954 1406771fe6b9SJerome Glisse #define RADEON_CAP0_CONFIG 0x0958 1407771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 1408771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 1409771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 1410771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 1411771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 1412771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 1413771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 1414771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 1415771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 1416771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 1417771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 1418771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 1419771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 1420771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 1421771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 1422771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 1423771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 1424771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 1425771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 1426771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 1427771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 1428771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 1429771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 1430771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 1431771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 1432771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 1433771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 1434771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 1435771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 1436771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 1437771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 1438771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 1439771fe6b9SJerome Glisse # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 1440771fe6b9SJerome Glisse #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C 1441771fe6b9SJerome Glisse #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 1442771fe6b9SJerome Glisse #define RADEON_CAP0_ANC_H_WINDOW 0x0964 1443771fe6b9SJerome Glisse #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 1444771fe6b9SJerome Glisse #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C 1445771fe6b9SJerome Glisse #define RADEON_CAP0_BUF_STATUS 0x0970 1446771fe6b9SJerome Glisse /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ 1447771fe6b9SJerome Glisse /* #define RADEON_CAP0_XSHARPNESS 0x097C */ 1448771fe6b9SJerome Glisse #define RADEON_CAP0_VBI2_OFFSET 0x0980 1449771fe6b9SJerome Glisse #define RADEON_CAP0_VBI3_OFFSET 0x0984 1450771fe6b9SJerome Glisse #define RADEON_CAP0_ANC2_OFFSET 0x0988 1451771fe6b9SJerome Glisse #define RADEON_CAP0_ANC3_OFFSET 0x098C 1452771fe6b9SJerome Glisse #define RADEON_VID_BUFFER_CONTROL 0x0900 1453771fe6b9SJerome Glisse 1454771fe6b9SJerome Glisse /* second capture unit */ 1455771fe6b9SJerome Glisse 1456771fe6b9SJerome Glisse #define RADEON_CAP1_BUF0_OFFSET 0x0990 1457771fe6b9SJerome Glisse #define RADEON_CAP1_BUF1_OFFSET 0x0994 1458771fe6b9SJerome Glisse #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 1459771fe6b9SJerome Glisse #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C 1460771fe6b9SJerome Glisse 1461771fe6b9SJerome Glisse #define RADEON_CAP1_BUF_PITCH 0x09A0 1462771fe6b9SJerome Glisse #define RADEON_CAP1_V_WINDOW 0x09A4 1463771fe6b9SJerome Glisse #define RADEON_CAP1_H_WINDOW 0x09A8 1464771fe6b9SJerome Glisse #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC 1465771fe6b9SJerome Glisse #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 1466771fe6b9SJerome Glisse #define RADEON_CAP1_VBI_V_WINDOW 0x09B4 1467771fe6b9SJerome Glisse #define RADEON_CAP1_VBI_H_WINDOW 0x09B8 1468771fe6b9SJerome Glisse #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC 1469771fe6b9SJerome Glisse #define RADEON_CAP1_TRIG_CNTL 0x09C0 1470771fe6b9SJerome Glisse #define RADEON_CAP1_DEBUG 0x09C4 1471771fe6b9SJerome Glisse #define RADEON_CAP1_CONFIG 0x09C8 1472771fe6b9SJerome Glisse #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC 1473771fe6b9SJerome Glisse #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 1474771fe6b9SJerome Glisse #define RADEON_CAP1_ANC_H_WINDOW 0x09D4 1475771fe6b9SJerome Glisse #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 1476771fe6b9SJerome Glisse #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC 1477771fe6b9SJerome Glisse #define RADEON_CAP1_BUF_STATUS 0x09E0 1478771fe6b9SJerome Glisse #define RADEON_CAP1_DWNSC_XRATIO 0x09E8 1479771fe6b9SJerome Glisse #define RADEON_CAP1_XSHARPNESS 0x09EC 1480771fe6b9SJerome Glisse 1481771fe6b9SJerome Glisse /* misc multimedia registers */ 1482771fe6b9SJerome Glisse 1483771fe6b9SJerome Glisse #define RADEON_IDCT_RUNS 0x1F80 1484771fe6b9SJerome Glisse #define RADEON_IDCT_LEVELS 0x1F84 1485771fe6b9SJerome Glisse #define RADEON_IDCT_CONTROL 0x1FBC 1486771fe6b9SJerome Glisse #define RADEON_IDCT_AUTH_CONTROL 0x1F88 1487771fe6b9SJerome Glisse #define RADEON_IDCT_AUTH 0x1F8C 1488771fe6b9SJerome Glisse 1489771fe6b9SJerome Glisse #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ 1490771fe6b9SJerome Glisse # define RADEON_P2PLL_RESET (1 << 0) 1491771fe6b9SJerome Glisse # define RADEON_P2PLL_SLEEP (1 << 1) 1492771fe6b9SJerome Glisse # define RADEON_P2PLL_PVG_MASK (7 << 11) 1493771fe6b9SJerome Glisse # define RADEON_P2PLL_PVG_SHIFT 11 1494771fe6b9SJerome Glisse # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 1495771fe6b9SJerome Glisse # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 1496771fe6b9SJerome Glisse # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 1497771fe6b9SJerome Glisse #define RADEON_P2PLL_DIV_0 0x002c 1498771fe6b9SJerome Glisse # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff 1499771fe6b9SJerome Glisse # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 1500771fe6b9SJerome Glisse #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ 1501771fe6b9SJerome Glisse # define RADEON_P2PLL_REF_DIV_MASK 0x03ff 1502771fe6b9SJerome Glisse # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 1503771fe6b9SJerome Glisse # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 1504771fe6b9SJerome Glisse # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) 1505771fe6b9SJerome Glisse # define R300_PPLL_REF_DIV_ACC_SHIFT 18 1506771fe6b9SJerome Glisse #define RADEON_PALETTE_DATA 0x00b4 1507771fe6b9SJerome Glisse #define RADEON_PALETTE_30_DATA 0x00b8 1508771fe6b9SJerome Glisse #define RADEON_PALETTE_INDEX 0x00b0 1509771fe6b9SJerome Glisse #define RADEON_PCI_GART_PAGE 0x017c 1510771fe6b9SJerome Glisse #define RADEON_PIXCLKS_CNTL 0x002d 1511771fe6b9SJerome Glisse # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 1512771fe6b9SJerome Glisse # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 1513771fe6b9SJerome Glisse # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 1514771fe6b9SJerome Glisse # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 1515771fe6b9SJerome Glisse # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 1516771fe6b9SJerome Glisse # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) 1517771fe6b9SJerome Glisse # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) 1518771fe6b9SJerome Glisse # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) 1519771fe6b9SJerome Glisse # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) 1520771fe6b9SJerome Glisse # define R300_DVOCLK_ALWAYS_ONb (1 << 10) 1521771fe6b9SJerome Glisse # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) 1522771fe6b9SJerome Glisse # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) 1523771fe6b9SJerome Glisse # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) 1524771fe6b9SJerome Glisse # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) 1525771fe6b9SJerome Glisse # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 1526771fe6b9SJerome Glisse # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 1527771fe6b9SJerome Glisse # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) 1528771fe6b9SJerome Glisse # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) 1529771fe6b9SJerome Glisse # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) 1530771fe6b9SJerome Glisse # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) 1531771fe6b9SJerome Glisse # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) 1532771fe6b9SJerome Glisse #define RADEON_PLANE_3D_MASK_C 0x1d44 1533771fe6b9SJerome Glisse #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ 1534771fe6b9SJerome Glisse # define RADEON_PLL_MASK_READ_B (1 << 9) 1535771fe6b9SJerome Glisse #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ 1536771fe6b9SJerome Glisse #define RADEON_PMI_DATA 0x0f63 /* PCI */ 1537771fe6b9SJerome Glisse #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 1538771fe6b9SJerome Glisse #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ 1539771fe6b9SJerome Glisse #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ 1540771fe6b9SJerome Glisse #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ 1541771fe6b9SJerome Glisse #define RADEON_PPLL_CNTL 0x0002 /* PLL */ 1542771fe6b9SJerome Glisse # define RADEON_PPLL_RESET (1 << 0) 1543771fe6b9SJerome Glisse # define RADEON_PPLL_SLEEP (1 << 1) 1544771fe6b9SJerome Glisse # define RADEON_PPLL_PVG_MASK (7 << 11) 1545771fe6b9SJerome Glisse # define RADEON_PPLL_PVG_SHIFT 11 1546771fe6b9SJerome Glisse # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) 1547771fe6b9SJerome Glisse # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 1548771fe6b9SJerome Glisse # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 1549771fe6b9SJerome Glisse #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ 1550771fe6b9SJerome Glisse #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ 1551771fe6b9SJerome Glisse #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ 1552771fe6b9SJerome Glisse #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ 1553771fe6b9SJerome Glisse # define RADEON_PPLL_FB3_DIV_MASK 0x07ff 1554771fe6b9SJerome Glisse # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 1555771fe6b9SJerome Glisse #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ 1556771fe6b9SJerome Glisse # define RADEON_PPLL_REF_DIV_MASK 0x03ff 1557771fe6b9SJerome Glisse # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 1558771fe6b9SJerome Glisse # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 1559771fe6b9SJerome Glisse #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 1560771fe6b9SJerome Glisse 1561771fe6b9SJerome Glisse #define RADEON_RBBM_GUICNTL 0x172c 1562771fe6b9SJerome Glisse # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 1563771fe6b9SJerome Glisse # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 1564771fe6b9SJerome Glisse # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 1565771fe6b9SJerome Glisse # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 1566771fe6b9SJerome Glisse #define RADEON_RBBM_SOFT_RESET 0x00f0 1567771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_CP (1 << 0) 1568771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_HI (1 << 1) 1569771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_SE (1 << 2) 1570771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_RE (1 << 3) 1571771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_PP (1 << 4) 1572771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_E2 (1 << 5) 1573771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_RB (1 << 6) 1574771fe6b9SJerome Glisse # define RADEON_SOFT_RESET_HDP (1 << 7) 1575771fe6b9SJerome Glisse #define RADEON_RBBM_STATUS 0x0e40 1576771fe6b9SJerome Glisse # define RADEON_RBBM_FIFOCNT_MASK 0x007f 1577771fe6b9SJerome Glisse # define RADEON_RBBM_ACTIVE (1 << 31) 1578771fe6b9SJerome Glisse #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 1579771fe6b9SJerome Glisse # define RADEON_RB2D_DC_FLUSH (3 << 0) 1580771fe6b9SJerome Glisse # define RADEON_RB2D_DC_FREE (3 << 2) 1581771fe6b9SJerome Glisse # define RADEON_RB2D_DC_FLUSH_ALL 0xf 1582771fe6b9SJerome Glisse # define RADEON_RB2D_DC_BUSY (1 << 31) 1583771fe6b9SJerome Glisse #define RADEON_RB2D_DSTCACHE_MODE 0x3428 1584771fe6b9SJerome Glisse #define RADEON_DSTCACHE_CTLSTAT 0x1714 1585771fe6b9SJerome Glisse 1586771fe6b9SJerome Glisse #define RADEON_RB3D_ZCACHE_MODE 0x3250 1587771fe6b9SJerome Glisse #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 1588771fe6b9SJerome Glisse # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 1589771fe6b9SJerome Glisse #define RADEON_RB3D_DSTCACHE_MODE 0x3258 1590771fe6b9SJerome Glisse # define RADEON_RB3D_DC_CACHE_ENABLE (0) 1591771fe6b9SJerome Glisse # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) 1592771fe6b9SJerome Glisse # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) 1593771fe6b9SJerome Glisse # define RADEON_RB3D_DC_CACHE_DISABLE (3) 1594771fe6b9SJerome Glisse # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) 1595771fe6b9SJerome Glisse # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) 1596771fe6b9SJerome Glisse # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) 1597771fe6b9SJerome Glisse # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) 1598771fe6b9SJerome Glisse # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) 1599771fe6b9SJerome Glisse # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) 1600771fe6b9SJerome Glisse # define RADEON_RB3D_DC_FORCE_RMW (1 << 16) 1601771fe6b9SJerome Glisse # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) 1602771fe6b9SJerome Glisse # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) 1603771fe6b9SJerome Glisse 1604771fe6b9SJerome Glisse #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C 1605771fe6b9SJerome Glisse # define RADEON_RB3D_DC_FLUSH (3 << 0) 1606771fe6b9SJerome Glisse # define RADEON_RB3D_DC_FREE (3 << 2) 1607771fe6b9SJerome Glisse # define RADEON_RB3D_DC_FLUSH_ALL 0xf 1608771fe6b9SJerome Glisse # define RADEON_RB3D_DC_BUSY (1 << 31) 1609771fe6b9SJerome Glisse 1610771fe6b9SJerome Glisse #define RADEON_REG_BASE 0x0f18 /* PCI */ 1611771fe6b9SJerome Glisse #define RADEON_REGPROG_INF 0x0f09 /* PCI */ 1612771fe6b9SJerome Glisse #define RADEON_REVISION_ID 0x0f08 /* PCI */ 1613771fe6b9SJerome Glisse 1614771fe6b9SJerome Glisse #define RADEON_SC_BOTTOM 0x164c 1615771fe6b9SJerome Glisse #define RADEON_SC_BOTTOM_RIGHT 0x16f0 1616771fe6b9SJerome Glisse #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c 1617771fe6b9SJerome Glisse #define RADEON_SC_LEFT 0x1640 1618771fe6b9SJerome Glisse #define RADEON_SC_RIGHT 0x1644 1619771fe6b9SJerome Glisse #define RADEON_SC_TOP 0x1648 1620771fe6b9SJerome Glisse #define RADEON_SC_TOP_LEFT 0x16ec 1621771fe6b9SJerome Glisse #define RADEON_SC_TOP_LEFT_C 0x1c88 1622771fe6b9SJerome Glisse # define RADEON_SC_SIGN_MASK_LO 0x8000 1623771fe6b9SJerome Glisse # define RADEON_SC_SIGN_MASK_HI 0x80000000 1624771fe6b9SJerome Glisse #define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ 1625771fe6b9SJerome Glisse # define RADEON_M_SPLL_REF_DIV_SHIFT 0 1626771fe6b9SJerome Glisse # define RADEON_M_SPLL_REF_DIV_MASK 0xff 1627771fe6b9SJerome Glisse # define RADEON_MPLL_FB_DIV_SHIFT 8 1628771fe6b9SJerome Glisse # define RADEON_MPLL_FB_DIV_MASK 0xff 1629771fe6b9SJerome Glisse # define RADEON_SPLL_FB_DIV_SHIFT 16 1630771fe6b9SJerome Glisse # define RADEON_SPLL_FB_DIV_MASK 0xff 1631771fe6b9SJerome Glisse #define RADEON_SPLL_CNTL 0x000c /* PLL */ 1632771fe6b9SJerome Glisse # define RADEON_SPLL_SLEEP (1 << 0) 1633771fe6b9SJerome Glisse # define RADEON_SPLL_RESET (1 << 1) 1634771fe6b9SJerome Glisse # define RADEON_SPLL_PCP_MASK 0x7 1635771fe6b9SJerome Glisse # define RADEON_SPLL_PCP_SHIFT 8 1636771fe6b9SJerome Glisse # define RADEON_SPLL_PVG_MASK 0x7 1637771fe6b9SJerome Glisse # define RADEON_SPLL_PVG_SHIFT 11 1638771fe6b9SJerome Glisse # define RADEON_SPLL_PDC_MASK 0x3 1639771fe6b9SJerome Glisse # define RADEON_SPLL_PDC_SHIFT 14 1640771fe6b9SJerome Glisse #define RADEON_SCLK_CNTL 0x000d /* PLL */ 1641771fe6b9SJerome Glisse # define RADEON_SCLK_SRC_SEL_MASK 0x0007 1642771fe6b9SJerome Glisse # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 1643771fe6b9SJerome Glisse # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 1644771fe6b9SJerome Glisse # define RADEON_SCLK_FORCEON_MASK 0xffff8000 1645771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_DISP2 (1<<15) 1646771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_CP (1<<16) 1647771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_HDP (1<<17) 1648771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_DISP1 (1<<18) 1649771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_TOP (1<<19) 1650771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_E2 (1<<20) 1651771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_SE (1<<21) 1652771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_IDCT (1<<22) 1653771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_VIP (1<<23) 1654771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_RE (1<<24) 1655771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_PB (1<<25) 1656771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_TAM (1<<26) 1657771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_TDM (1<<27) 1658771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_RB (1<<28) 1659771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_TV_SCLK (1<<29) 1660771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_SUBPIC (1<<30) 1661771fe6b9SJerome Glisse # define RADEON_SCLK_FORCE_OV0 (1<<31) 1662771fe6b9SJerome Glisse # define R300_SCLK_FORCE_VAP (1<<21) 1663771fe6b9SJerome Glisse # define R300_SCLK_FORCE_SR (1<<25) 1664771fe6b9SJerome Glisse # define R300_SCLK_FORCE_PX (1<<26) 1665771fe6b9SJerome Glisse # define R300_SCLK_FORCE_TX (1<<27) 1666771fe6b9SJerome Glisse # define R300_SCLK_FORCE_US (1<<28) 1667771fe6b9SJerome Glisse # define R300_SCLK_FORCE_SU (1<<30) 1668771fe6b9SJerome Glisse #define R300_SCLK_CNTL2 0x1e /* PLL */ 1669771fe6b9SJerome Glisse # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) 1670771fe6b9SJerome Glisse # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) 1671771fe6b9SJerome Glisse # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) 1672771fe6b9SJerome Glisse # define R300_SCLK_FORCE_TCL (1<<13) 1673771fe6b9SJerome Glisse # define R300_SCLK_FORCE_CBA (1<<14) 1674771fe6b9SJerome Glisse # define R300_SCLK_FORCE_GA (1<<15) 1675771fe6b9SJerome Glisse #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ 1676771fe6b9SJerome Glisse # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 1677771fe6b9SJerome Glisse # define RADEON_SCLK_MORE_FORCEON 0x0700 1678771fe6b9SJerome Glisse #define RADEON_SDRAM_MODE_REG 0x0158 1679771fe6b9SJerome Glisse #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ 1680771fe6b9SJerome Glisse #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ 1681771fe6b9SJerome Glisse #define RADEON_SNAPSHOT_F_COUNT 0x0244 1682771fe6b9SJerome Glisse #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 1683771fe6b9SJerome Glisse #define RADEON_SNAPSHOT_VIF_COUNT 0x024c 1684771fe6b9SJerome Glisse #define RADEON_SRC_OFFSET 0x15ac 1685771fe6b9SJerome Glisse #define RADEON_SRC_PITCH 0x15b0 1686771fe6b9SJerome Glisse #define RADEON_SRC_PITCH_OFFSET 0x1428 1687771fe6b9SJerome Glisse #define RADEON_SRC_SC_BOTTOM 0x165c 1688771fe6b9SJerome Glisse #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 1689771fe6b9SJerome Glisse #define RADEON_SRC_SC_RIGHT 0x1654 1690771fe6b9SJerome Glisse #define RADEON_SRC_X 0x1414 1691771fe6b9SJerome Glisse #define RADEON_SRC_X_Y 0x1590 1692771fe6b9SJerome Glisse #define RADEON_SRC_Y 0x1418 1693771fe6b9SJerome Glisse #define RADEON_SRC_Y_X 0x1434 1694771fe6b9SJerome Glisse #define RADEON_STATUS 0x0f06 /* PCI */ 1695771fe6b9SJerome Glisse #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ 1696771fe6b9SJerome Glisse #define RADEON_SUB_CLASS 0x0f0a /* PCI */ 1697771fe6b9SJerome Glisse #define RADEON_SURFACE_CNTL 0x0b00 1698771fe6b9SJerome Glisse # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1699771fe6b9SJerome Glisse # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) 1700771fe6b9SJerome Glisse # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) 1701771fe6b9SJerome Glisse # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) 1702771fe6b9SJerome Glisse # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) 1703771fe6b9SJerome Glisse #define RADEON_SURFACE0_INFO 0x0b0c 1704771fe6b9SJerome Glisse # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) 1705771fe6b9SJerome Glisse # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) 1706771fe6b9SJerome Glisse # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) 1707771fe6b9SJerome Glisse # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) 1708771fe6b9SJerome Glisse # define R200_SURF_TILE_NONE (0 << 16) 1709771fe6b9SJerome Glisse # define R200_SURF_TILE_COLOR_MACRO (1 << 16) 1710771fe6b9SJerome Glisse # define R200_SURF_TILE_COLOR_MICRO (2 << 16) 1711771fe6b9SJerome Glisse # define R200_SURF_TILE_COLOR_BOTH (3 << 16) 1712771fe6b9SJerome Glisse # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) 1713771fe6b9SJerome Glisse # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) 1714771fe6b9SJerome Glisse # define R300_SURF_TILE_NONE (0 << 16) 1715771fe6b9SJerome Glisse # define R300_SURF_TILE_COLOR_MACRO (1 << 16) 1716771fe6b9SJerome Glisse # define R300_SURF_TILE_DEPTH_32BPP (2 << 16) 1717771fe6b9SJerome Glisse # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) 1718771fe6b9SJerome Glisse # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) 1719771fe6b9SJerome Glisse # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) 1720771fe6b9SJerome Glisse # define RADEON_SURF_AP1_SWP_32BPP (1 << 23) 1721771fe6b9SJerome Glisse #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1722771fe6b9SJerome Glisse #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1723771fe6b9SJerome Glisse #define RADEON_SURFACE1_INFO 0x0b1c 1724771fe6b9SJerome Glisse #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1725771fe6b9SJerome Glisse #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1726771fe6b9SJerome Glisse #define RADEON_SURFACE2_INFO 0x0b2c 1727771fe6b9SJerome Glisse #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1728771fe6b9SJerome Glisse #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1729771fe6b9SJerome Glisse #define RADEON_SURFACE3_INFO 0x0b3c 1730771fe6b9SJerome Glisse #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1731771fe6b9SJerome Glisse #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1732771fe6b9SJerome Glisse #define RADEON_SURFACE4_INFO 0x0b4c 1733771fe6b9SJerome Glisse #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1734771fe6b9SJerome Glisse #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1735771fe6b9SJerome Glisse #define RADEON_SURFACE5_INFO 0x0b5c 1736771fe6b9SJerome Glisse #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1737771fe6b9SJerome Glisse #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1738771fe6b9SJerome Glisse #define RADEON_SURFACE6_INFO 0x0b6c 1739771fe6b9SJerome Glisse #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1740771fe6b9SJerome Glisse #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1741771fe6b9SJerome Glisse #define RADEON_SURFACE7_INFO 0x0b7c 1742771fe6b9SJerome Glisse #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1743771fe6b9SJerome Glisse #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1744771fe6b9SJerome Glisse #define RADEON_SW_SEMAPHORE 0x013c 1745771fe6b9SJerome Glisse 1746771fe6b9SJerome Glisse #define RADEON_TEST_DEBUG_CNTL 0x0120 1747771fe6b9SJerome Glisse #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 1748771fe6b9SJerome Glisse 1749771fe6b9SJerome Glisse #define RADEON_TEST_DEBUG_MUX 0x0124 1750771fe6b9SJerome Glisse #define RADEON_TEST_DEBUG_OUT 0x012c 1751771fe6b9SJerome Glisse #define RADEON_TMDS_PLL_CNTL 0x02a8 1752771fe6b9SJerome Glisse #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 1753771fe6b9SJerome Glisse # define RADEON_TMDS_TRANSMITTER_PLLEN 1 1754771fe6b9SJerome Glisse # define RADEON_TMDS_TRANSMITTER_PLLRST 2 1755771fe6b9SJerome Glisse #define RADEON_TRAIL_BRES_DEC 0x1614 1756771fe6b9SJerome Glisse #define RADEON_TRAIL_BRES_ERR 0x160c 1757771fe6b9SJerome Glisse #define RADEON_TRAIL_BRES_INC 0x1610 1758771fe6b9SJerome Glisse #define RADEON_TRAIL_X 0x1618 1759771fe6b9SJerome Glisse #define RADEON_TRAIL_X_SUB 0x1620 1760771fe6b9SJerome Glisse 1761771fe6b9SJerome Glisse #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ 1762771fe6b9SJerome Glisse # define RADEON_VCLK_SRC_SEL_MASK 0x03 1763771fe6b9SJerome Glisse # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 1764771fe6b9SJerome Glisse # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 1765771fe6b9SJerome Glisse # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 1766771fe6b9SJerome Glisse # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 1767771fe6b9SJerome Glisse # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) 1768771fe6b9SJerome Glisse # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) 1769771fe6b9SJerome Glisse # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) 1770771fe6b9SJerome Glisse 1771771fe6b9SJerome Glisse #define RADEON_VENDOR_ID 0x0f00 /* PCI */ 1772771fe6b9SJerome Glisse #define RADEON_VGA_DDA_CONFIG 0x02e8 1773771fe6b9SJerome Glisse #define RADEON_VGA_DDA_ON_OFF 0x02ec 1774771fe6b9SJerome Glisse #define RADEON_VID_BUFFER_CONTROL 0x0900 1775771fe6b9SJerome Glisse #define RADEON_VIDEOMUX_CNTL 0x0190 1776771fe6b9SJerome Glisse 1777771fe6b9SJerome Glisse /* VIP bus */ 1778771fe6b9SJerome Glisse #define RADEON_VIPH_CH0_DATA 0x0c00 1779771fe6b9SJerome Glisse #define RADEON_VIPH_CH1_DATA 0x0c04 1780771fe6b9SJerome Glisse #define RADEON_VIPH_CH2_DATA 0x0c08 1781771fe6b9SJerome Glisse #define RADEON_VIPH_CH3_DATA 0x0c0c 1782771fe6b9SJerome Glisse #define RADEON_VIPH_CH0_ADDR 0x0c10 1783771fe6b9SJerome Glisse #define RADEON_VIPH_CH1_ADDR 0x0c14 1784771fe6b9SJerome Glisse #define RADEON_VIPH_CH2_ADDR 0x0c18 1785771fe6b9SJerome Glisse #define RADEON_VIPH_CH3_ADDR 0x0c1c 1786771fe6b9SJerome Glisse #define RADEON_VIPH_CH0_SBCNT 0x0c20 1787771fe6b9SJerome Glisse #define RADEON_VIPH_CH1_SBCNT 0x0c24 1788771fe6b9SJerome Glisse #define RADEON_VIPH_CH2_SBCNT 0x0c28 1789771fe6b9SJerome Glisse #define RADEON_VIPH_CH3_SBCNT 0x0c2c 1790771fe6b9SJerome Glisse #define RADEON_VIPH_CH0_ABCNT 0x0c30 1791771fe6b9SJerome Glisse #define RADEON_VIPH_CH1_ABCNT 0x0c34 1792771fe6b9SJerome Glisse #define RADEON_VIPH_CH2_ABCNT 0x0c38 1793771fe6b9SJerome Glisse #define RADEON_VIPH_CH3_ABCNT 0x0c3c 1794771fe6b9SJerome Glisse #define RADEON_VIPH_CONTROL 0x0c40 1795771fe6b9SJerome Glisse # define RADEON_VIP_BUSY 0 1796771fe6b9SJerome Glisse # define RADEON_VIP_IDLE 1 1797771fe6b9SJerome Glisse # define RADEON_VIP_RESET 2 1798771fe6b9SJerome Glisse # define RADEON_VIPH_EN (1 << 21) 1799771fe6b9SJerome Glisse #define RADEON_VIPH_DV_LAT 0x0c44 1800771fe6b9SJerome Glisse #define RADEON_VIPH_BM_CHUNK 0x0c48 1801771fe6b9SJerome Glisse #define RADEON_VIPH_DV_INT 0x0c4c 1802771fe6b9SJerome Glisse #define RADEON_VIPH_TIMEOUT_STAT 0x0c50 1803771fe6b9SJerome Glisse #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 1804771fe6b9SJerome Glisse #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 1805771fe6b9SJerome Glisse #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 1806771fe6b9SJerome Glisse 1807771fe6b9SJerome Glisse #define RADEON_VIPH_REG_DATA 0x0084 1808771fe6b9SJerome Glisse #define RADEON_VIPH_REG_ADDR 0x0080 1809771fe6b9SJerome Glisse 1810771fe6b9SJerome Glisse 1811771fe6b9SJerome Glisse #define RADEON_WAIT_UNTIL 0x1720 1812771fe6b9SJerome Glisse # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1813771fe6b9SJerome Glisse # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) 1814771fe6b9SJerome Glisse # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) 1815771fe6b9SJerome Glisse # define RADEON_WAIT_CRTC_VLINE (1 << 3) 1816771fe6b9SJerome Glisse # define RADEON_WAIT_DMA_VID_IDLE (1 << 8) 1817771fe6b9SJerome Glisse # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) 1818771fe6b9SJerome Glisse # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ 1819771fe6b9SJerome Glisse # define RADEON_WAIT_OV0_FLIP (1 << 11) 1820771fe6b9SJerome Glisse # define RADEON_WAIT_AGP_FLUSH (1 << 13) 1821771fe6b9SJerome Glisse # define RADEON_WAIT_2D_IDLE (1 << 14) 1822771fe6b9SJerome Glisse # define RADEON_WAIT_3D_IDLE (1 << 15) 1823771fe6b9SJerome Glisse # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1824771fe6b9SJerome Glisse # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1825771fe6b9SJerome Glisse # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1826771fe6b9SJerome Glisse # define RADEON_CMDFIFO_ENTRIES_SHIFT 10 1827771fe6b9SJerome Glisse # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f 1828771fe6b9SJerome Glisse # define RADEON_WAIT_VAP_IDLE (1 << 28) 1829771fe6b9SJerome Glisse # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) 1830771fe6b9SJerome Glisse # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) 1831771fe6b9SJerome Glisse # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) 1832771fe6b9SJerome Glisse 1833771fe6b9SJerome Glisse #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1834771fe6b9SJerome Glisse #define RADEON_XCLK_CNTL 0x000d /* PLL */ 1835771fe6b9SJerome Glisse #define RADEON_XDLL_CNTL 0x000c /* PLL */ 1836771fe6b9SJerome Glisse #define RADEON_XPLL_CNTL 0x000b /* PLL */ 1837771fe6b9SJerome Glisse 1838771fe6b9SJerome Glisse 1839771fe6b9SJerome Glisse 1840771fe6b9SJerome Glisse /* Registers for 3D/TCL */ 1841771fe6b9SJerome Glisse #define RADEON_PP_BORDER_COLOR_0 0x1d40 1842771fe6b9SJerome Glisse #define RADEON_PP_BORDER_COLOR_1 0x1d44 1843771fe6b9SJerome Glisse #define RADEON_PP_BORDER_COLOR_2 0x1d48 1844771fe6b9SJerome Glisse #define RADEON_PP_CNTL 0x1c38 1845771fe6b9SJerome Glisse # define RADEON_STIPPLE_ENABLE (1 << 0) 1846771fe6b9SJerome Glisse # define RADEON_SCISSOR_ENABLE (1 << 1) 1847771fe6b9SJerome Glisse # define RADEON_PATTERN_ENABLE (1 << 2) 1848771fe6b9SJerome Glisse # define RADEON_SHADOW_ENABLE (1 << 3) 1849771fe6b9SJerome Glisse # define RADEON_TEX_ENABLE_MASK (0xf << 4) 1850771fe6b9SJerome Glisse # define RADEON_TEX_0_ENABLE (1 << 4) 1851771fe6b9SJerome Glisse # define RADEON_TEX_1_ENABLE (1 << 5) 1852771fe6b9SJerome Glisse # define RADEON_TEX_2_ENABLE (1 << 6) 1853771fe6b9SJerome Glisse # define RADEON_TEX_3_ENABLE (1 << 7) 1854771fe6b9SJerome Glisse # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) 1855771fe6b9SJerome Glisse # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) 1856771fe6b9SJerome Glisse # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) 1857771fe6b9SJerome Glisse # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) 1858771fe6b9SJerome Glisse # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) 1859771fe6b9SJerome Glisse # define RADEON_PLANAR_YUV_ENABLE (1 << 20) 1860771fe6b9SJerome Glisse # define RADEON_SPECULAR_ENABLE (1 << 21) 1861771fe6b9SJerome Glisse # define RADEON_FOG_ENABLE (1 << 22) 1862771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_ENABLE (1 << 23) 1863771fe6b9SJerome Glisse # define RADEON_ANTI_ALIAS_NONE (0 << 24) 1864771fe6b9SJerome Glisse # define RADEON_ANTI_ALIAS_LINE (1 << 24) 1865771fe6b9SJerome Glisse # define RADEON_ANTI_ALIAS_POLY (2 << 24) 1866771fe6b9SJerome Glisse # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) 1867771fe6b9SJerome Glisse # define RADEON_BUMP_MAP_ENABLE (1 << 26) 1868771fe6b9SJerome Glisse # define RADEON_BUMPED_MAP_T0 (0 << 27) 1869771fe6b9SJerome Glisse # define RADEON_BUMPED_MAP_T1 (1 << 27) 1870771fe6b9SJerome Glisse # define RADEON_BUMPED_MAP_T2 (2 << 27) 1871771fe6b9SJerome Glisse # define RADEON_TEX_3D_ENABLE_0 (1 << 29) 1872771fe6b9SJerome Glisse # define RADEON_TEX_3D_ENABLE_1 (1 << 30) 1873771fe6b9SJerome Glisse # define RADEON_MC_ENABLE (1 << 31) 1874771fe6b9SJerome Glisse #define RADEON_PP_FOG_COLOR 0x1c18 1875771fe6b9SJerome Glisse # define RADEON_FOG_COLOR_MASK 0x00ffffff 1876771fe6b9SJerome Glisse # define RADEON_FOG_VERTEX (0 << 24) 1877771fe6b9SJerome Glisse # define RADEON_FOG_TABLE (1 << 24) 1878771fe6b9SJerome Glisse # define RADEON_FOG_USE_DEPTH (0 << 25) 1879771fe6b9SJerome Glisse # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) 1880771fe6b9SJerome Glisse # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) 1881771fe6b9SJerome Glisse #define RADEON_PP_LUM_MATRIX 0x1d00 1882771fe6b9SJerome Glisse #define RADEON_PP_MISC 0x1c14 1883771fe6b9SJerome Glisse # define RADEON_REF_ALPHA_MASK 0x000000ff 1884771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_FAIL (0 << 8) 1885771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_LESS (1 << 8) 1886771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) 1887771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_EQUAL (3 << 8) 1888771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) 1889771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_GREATER (5 << 8) 1890771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) 1891771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_PASS (7 << 8) 1892771fe6b9SJerome Glisse # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) 1893771fe6b9SJerome Glisse # define RADEON_CHROMA_FUNC_FAIL (0 << 16) 1894771fe6b9SJerome Glisse # define RADEON_CHROMA_FUNC_PASS (1 << 16) 1895771fe6b9SJerome Glisse # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) 1896771fe6b9SJerome Glisse # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) 1897771fe6b9SJerome Glisse # define RADEON_CHROMA_KEY_NEAREST (0 << 18) 1898771fe6b9SJerome Glisse # define RADEON_CHROMA_KEY_ZERO (1 << 18) 1899771fe6b9SJerome Glisse # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) 1900771fe6b9SJerome Glisse # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) 1901771fe6b9SJerome Glisse # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) 1902771fe6b9SJerome Glisse # define RADEON_SHADOW_PASS_1 (0 << 22) 1903771fe6b9SJerome Glisse # define RADEON_SHADOW_PASS_2 (1 << 22) 1904771fe6b9SJerome Glisse # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) 1905771fe6b9SJerome Glisse # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) 1906771fe6b9SJerome Glisse #define RADEON_PP_ROT_MATRIX_0 0x1d58 1907771fe6b9SJerome Glisse #define RADEON_PP_ROT_MATRIX_1 0x1d5c 1908771fe6b9SJerome Glisse #define RADEON_PP_TXFILTER_0 0x1c54 1909771fe6b9SJerome Glisse #define RADEON_PP_TXFILTER_1 0x1c6c 1910771fe6b9SJerome Glisse #define RADEON_PP_TXFILTER_2 0x1c84 1911771fe6b9SJerome Glisse # define RADEON_MAG_FILTER_NEAREST (0 << 0) 1912771fe6b9SJerome Glisse # define RADEON_MAG_FILTER_LINEAR (1 << 0) 1913771fe6b9SJerome Glisse # define RADEON_MAG_FILTER_MASK (1 << 0) 1914771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_NEAREST (0 << 1) 1915771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_LINEAR (1 << 1) 1916771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 1917771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 1918771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 1919771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 1920771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) 1921771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) 1922771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 1923771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 1924771fe6b9SJerome Glisse # define RADEON_MIN_FILTER_MASK (15 << 1) 1925771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) 1926771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) 1927771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) 1928771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) 1929771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) 1930771fe6b9SJerome Glisse # define RADEON_MAX_ANISO_MASK (7 << 5) 1931771fe6b9SJerome Glisse # define RADEON_LOD_BIAS_MASK (0xff << 8) 1932771fe6b9SJerome Glisse # define RADEON_LOD_BIAS_SHIFT 8 1933771fe6b9SJerome Glisse # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) 1934771fe6b9SJerome Glisse # define RADEON_MAX_MIP_LEVEL_SHIFT 16 1935771fe6b9SJerome Glisse # define RADEON_YUV_TO_RGB (1 << 20) 1936771fe6b9SJerome Glisse # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) 1937771fe6b9SJerome Glisse # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) 1938771fe6b9SJerome Glisse # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) 1939771fe6b9SJerome Glisse # define RADEON_WRAPEN_S (1 << 22) 1940771fe6b9SJerome Glisse # define RADEON_CLAMP_S_WRAP (0 << 23) 1941771fe6b9SJerome Glisse # define RADEON_CLAMP_S_MIRROR (1 << 23) 1942771fe6b9SJerome Glisse # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) 1943771fe6b9SJerome Glisse # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 1944771fe6b9SJerome Glisse # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) 1945771fe6b9SJerome Glisse # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 1946771fe6b9SJerome Glisse # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) 1947771fe6b9SJerome Glisse # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 1948771fe6b9SJerome Glisse # define RADEON_CLAMP_S_MASK (7 << 23) 1949771fe6b9SJerome Glisse # define RADEON_WRAPEN_T (1 << 26) 1950771fe6b9SJerome Glisse # define RADEON_CLAMP_T_WRAP (0 << 27) 1951771fe6b9SJerome Glisse # define RADEON_CLAMP_T_MIRROR (1 << 27) 1952771fe6b9SJerome Glisse # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) 1953771fe6b9SJerome Glisse # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 1954771fe6b9SJerome Glisse # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) 1955771fe6b9SJerome Glisse # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 1956771fe6b9SJerome Glisse # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) 1957771fe6b9SJerome Glisse # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 1958771fe6b9SJerome Glisse # define RADEON_CLAMP_T_MASK (7 << 27) 1959771fe6b9SJerome Glisse # define RADEON_BORDER_MODE_OGL (0 << 31) 1960771fe6b9SJerome Glisse # define RADEON_BORDER_MODE_D3D (1 << 31) 1961771fe6b9SJerome Glisse #define RADEON_PP_TXFORMAT_0 0x1c58 1962771fe6b9SJerome Glisse #define RADEON_PP_TXFORMAT_1 0x1c70 1963771fe6b9SJerome Glisse #define RADEON_PP_TXFORMAT_2 0x1c88 1964771fe6b9SJerome Glisse # define RADEON_TXFORMAT_I8 (0 << 0) 1965771fe6b9SJerome Glisse # define RADEON_TXFORMAT_AI88 (1 << 0) 1966771fe6b9SJerome Glisse # define RADEON_TXFORMAT_RGB332 (2 << 0) 1967771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ARGB1555 (3 << 0) 1968771fe6b9SJerome Glisse # define RADEON_TXFORMAT_RGB565 (4 << 0) 1969771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ARGB4444 (5 << 0) 1970771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ARGB8888 (6 << 0) 1971771fe6b9SJerome Glisse # define RADEON_TXFORMAT_RGBA8888 (7 << 0) 1972771fe6b9SJerome Glisse # define RADEON_TXFORMAT_Y8 (8 << 0) 1973771fe6b9SJerome Glisse # define RADEON_TXFORMAT_VYUY422 (10 << 0) 1974771fe6b9SJerome Glisse # define RADEON_TXFORMAT_YVYU422 (11 << 0) 1975771fe6b9SJerome Glisse # define RADEON_TXFORMAT_DXT1 (12 << 0) 1976771fe6b9SJerome Glisse # define RADEON_TXFORMAT_DXT23 (14 << 0) 1977771fe6b9SJerome Glisse # define RADEON_TXFORMAT_DXT45 (15 << 0) 1978551ebd83SDave Airlie # define RADEON_TXFORMAT_SHADOW16 (16 << 0) 1979551ebd83SDave Airlie # define RADEON_TXFORMAT_SHADOW32 (17 << 0) 1980551ebd83SDave Airlie # define RADEON_TXFORMAT_DUDV88 (18 << 0) 1981551ebd83SDave Airlie # define RADEON_TXFORMAT_LDUDV655 (19 << 0) 1982551ebd83SDave Airlie # define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) 1983771fe6b9SJerome Glisse # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1984771fe6b9SJerome Glisse # define RADEON_TXFORMAT_FORMAT_SHIFT 0 1985771fe6b9SJerome Glisse # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) 1986771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) 1987771fe6b9SJerome Glisse # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) 1988771fe6b9SJerome Glisse # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) 1989771fe6b9SJerome Glisse # define RADEON_TXFORMAT_WIDTH_SHIFT 8 1990771fe6b9SJerome Glisse # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) 1991771fe6b9SJerome Glisse # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 1992771fe6b9SJerome Glisse # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) 1993771fe6b9SJerome Glisse # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 1994771fe6b9SJerome Glisse # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 1995771fe6b9SJerome Glisse # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 1996771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 1997771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) 1998771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 1999771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 2000771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) 2001771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) 2002771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) 2003771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) 2004771fe6b9SJerome Glisse # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 2005771fe6b9SJerome Glisse # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 2006771fe6b9SJerome Glisse # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 2007771fe6b9SJerome Glisse # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) 2008771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_FACES_0 0x1d24 2009771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_FACES_1 0x1d28 2010771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_FACES_2 0x1d2c 2011771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_1_SHIFT 0 2012771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_1_SHIFT 4 2013771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) 2014771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) 2015771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_2_SHIFT 8 2016771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_2_SHIFT 12 2017771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) 2018771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) 2019771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_3_SHIFT 16 2020771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_3_SHIFT 20 2021771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) 2022771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) 2023771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_4_SHIFT 24 2024771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_4_SHIFT 28 2025771fe6b9SJerome Glisse # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) 2026771fe6b9SJerome Glisse # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) 2027771fe6b9SJerome Glisse 2028771fe6b9SJerome Glisse #define RADEON_PP_TXOFFSET_0 0x1c5c 2029771fe6b9SJerome Glisse #define RADEON_PP_TXOFFSET_1 0x1c74 2030771fe6b9SJerome Glisse #define RADEON_PP_TXOFFSET_2 0x1c8c 2031771fe6b9SJerome Glisse # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) 2032771fe6b9SJerome Glisse # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) 2033771fe6b9SJerome Glisse # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) 2034771fe6b9SJerome Glisse # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 2035771fe6b9SJerome Glisse # define RADEON_TXO_MACRO_LINEAR (0 << 2) 2036771fe6b9SJerome Glisse # define RADEON_TXO_MACRO_TILE (1 << 2) 2037771fe6b9SJerome Glisse # define RADEON_TXO_MICRO_LINEAR (0 << 3) 2038771fe6b9SJerome Glisse # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) 2039771fe6b9SJerome Glisse # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) 2040771fe6b9SJerome Glisse # define RADEON_TXO_OFFSET_MASK 0xffffffe0 2041771fe6b9SJerome Glisse # define RADEON_TXO_OFFSET_SHIFT 5 2042771fe6b9SJerome Glisse 2043771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 2044771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 2045771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 2046771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc 2047771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 2048771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 2049771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 2050771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 2051771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c 2052771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 2053771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 2054771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 2055771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c 2056771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 2057771fe6b9SJerome Glisse #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 2058771fe6b9SJerome Glisse 2059771fe6b9SJerome Glisse #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 2060771fe6b9SJerome Glisse #define RADEON_PP_TEX_SIZE_1 0x1d0c 2061771fe6b9SJerome Glisse #define RADEON_PP_TEX_SIZE_2 0x1d14 2062771fe6b9SJerome Glisse # define RADEON_TEX_USIZE_MASK (0x7ff << 0) 2063771fe6b9SJerome Glisse # define RADEON_TEX_USIZE_SHIFT 0 2064771fe6b9SJerome Glisse # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) 2065771fe6b9SJerome Glisse # define RADEON_TEX_VSIZE_SHIFT 16 2066771fe6b9SJerome Glisse # define RADEON_SIGNED_RGB_MASK (1 << 30) 2067771fe6b9SJerome Glisse # define RADEON_SIGNED_RGB_SHIFT 30 2068771fe6b9SJerome Glisse # define RADEON_SIGNED_ALPHA_MASK (1 << 31) 2069771fe6b9SJerome Glisse # define RADEON_SIGNED_ALPHA_SHIFT 31 2070771fe6b9SJerome Glisse #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ 2071771fe6b9SJerome Glisse #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ 2072771fe6b9SJerome Glisse #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ 2073771fe6b9SJerome Glisse /* note: bits 13-5: 32 byte aligned stride of texture map */ 2074771fe6b9SJerome Glisse 2075771fe6b9SJerome Glisse #define RADEON_PP_TXCBLEND_0 0x1c60 2076771fe6b9SJerome Glisse #define RADEON_PP_TXCBLEND_1 0x1c78 2077771fe6b9SJerome Glisse #define RADEON_PP_TXCBLEND_2 0x1c90 2078771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_SHIFT 0 2079771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) 2080771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_ZERO (0 << 0) 2081771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) 2082771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) 2083771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) 2084771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) 2085771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) 2086771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) 2087771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) 2088771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) 2089771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) 2090771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) 2091771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) 2092771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) 2093771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) 2094771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) 2095771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) 2096771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) 2097771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_SHIFT 5 2098771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) 2099771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_ZERO (0 << 5) 2100771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) 2101771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) 2102771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) 2103771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) 2104771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) 2105771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) 2106771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) 2107771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) 2108771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) 2109771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) 2110771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) 2111771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) 2112771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) 2113771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) 2114771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) 2115771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) 2116771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_SHIFT 10 2117771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) 2118771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_ZERO (0 << 10) 2119771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) 2120771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) 2121771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) 2122771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) 2123771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) 2124771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) 2125771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) 2126771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) 2127771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) 2128771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) 2129771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) 2130771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) 2131771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) 2132771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) 2133771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) 2134771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) 2135771fe6b9SJerome Glisse # define RADEON_COMP_ARG_A (1 << 15) 2136771fe6b9SJerome Glisse # define RADEON_COMP_ARG_A_SHIFT 15 2137771fe6b9SJerome Glisse # define RADEON_COMP_ARG_B (1 << 16) 2138771fe6b9SJerome Glisse # define RADEON_COMP_ARG_B_SHIFT 16 2139771fe6b9SJerome Glisse # define RADEON_COMP_ARG_C (1 << 17) 2140771fe6b9SJerome Glisse # define RADEON_COMP_ARG_C_SHIFT 17 2141771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_MASK (7 << 18) 2142771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_ADD (0 << 18) 2143771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) 2144771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) 2145771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_BLEND (3 << 18) 2146771fe6b9SJerome Glisse # define RADEON_BLEND_CTL_DOT3 (4 << 18) 2147771fe6b9SJerome Glisse # define RADEON_SCALE_SHIFT 21 2148771fe6b9SJerome Glisse # define RADEON_SCALE_MASK (3 << 21) 2149771fe6b9SJerome Glisse # define RADEON_SCALE_1X (0 << 21) 2150771fe6b9SJerome Glisse # define RADEON_SCALE_2X (1 << 21) 2151771fe6b9SJerome Glisse # define RADEON_SCALE_4X (2 << 21) 2152771fe6b9SJerome Glisse # define RADEON_CLAMP_TX (1 << 23) 2153771fe6b9SJerome Glisse # define RADEON_T0_EQ_TCUR (1 << 24) 2154771fe6b9SJerome Glisse # define RADEON_T1_EQ_TCUR (1 << 25) 2155771fe6b9SJerome Glisse # define RADEON_T2_EQ_TCUR (1 << 26) 2156771fe6b9SJerome Glisse # define RADEON_T3_EQ_TCUR (1 << 27) 2157771fe6b9SJerome Glisse # define RADEON_COLOR_ARG_MASK 0x1f 2158771fe6b9SJerome Glisse # define RADEON_COMP_ARG_SHIFT 15 2159771fe6b9SJerome Glisse #define RADEON_PP_TXABLEND_0 0x1c64 2160771fe6b9SJerome Glisse #define RADEON_PP_TXABLEND_1 0x1c7c 2161771fe6b9SJerome Glisse #define RADEON_PP_TXABLEND_2 0x1c94 2162771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_SHIFT 0 2163771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) 2164771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) 2165771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) 2166771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) 2167771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) 2168771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) 2169771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) 2170771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) 2171771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) 2172771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) 2173771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_SHIFT 4 2174771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) 2175771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) 2176771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) 2177771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) 2178771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) 2179771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) 2180771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) 2181771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) 2182771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) 2183771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) 2184771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_SHIFT 8 2185771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) 2186771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) 2187771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) 2188771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) 2189771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) 2190771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) 2191771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) 2192771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) 2193771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) 2194771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) 2195771fe6b9SJerome Glisse # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) 2196771fe6b9SJerome Glisse # define RADEON_ALPHA_ARG_MASK 0xf 2197771fe6b9SJerome Glisse 2198771fe6b9SJerome Glisse #define RADEON_PP_TFACTOR_0 0x1c68 2199771fe6b9SJerome Glisse #define RADEON_PP_TFACTOR_1 0x1c80 2200771fe6b9SJerome Glisse #define RADEON_PP_TFACTOR_2 0x1c98 2201771fe6b9SJerome Glisse 2202771fe6b9SJerome Glisse #define RADEON_RB3D_BLENDCNTL 0x1c20 2203771fe6b9SJerome Glisse # define RADEON_COMB_FCN_MASK (3 << 12) 2204771fe6b9SJerome Glisse # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) 2205771fe6b9SJerome Glisse # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) 2206771fe6b9SJerome Glisse # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) 2207771fe6b9SJerome Glisse # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) 2208771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) 2209771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ONE (33 << 16) 2210771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) 2211771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 2212771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) 2213771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 2214771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) 2215771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 2216771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) 2217771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 2218771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 2219771fe6b9SJerome Glisse # define RADEON_SRC_BLEND_MASK (63 << 16) 2220771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ZERO (32 << 24) 2221771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ONE (33 << 24) 2222771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) 2223771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 2224771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) 2225771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 2226771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) 2227771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 2228771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) 2229771fe6b9SJerome Glisse # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 2230771fe6b9SJerome Glisse # define RADEON_DST_BLEND_MASK (63 << 24) 2231771fe6b9SJerome Glisse #define RADEON_RB3D_CNTL 0x1c3c 2232771fe6b9SJerome Glisse # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 2233771fe6b9SJerome Glisse # define RADEON_PLANE_MASK_ENABLE (1 << 1) 2234771fe6b9SJerome Glisse # define RADEON_DITHER_ENABLE (1 << 2) 2235771fe6b9SJerome Glisse # define RADEON_ROUND_ENABLE (1 << 3) 2236771fe6b9SJerome Glisse # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 2237771fe6b9SJerome Glisse # define RADEON_DITHER_INIT (1 << 5) 2238771fe6b9SJerome Glisse # define RADEON_ROP_ENABLE (1 << 6) 2239771fe6b9SJerome Glisse # define RADEON_STENCIL_ENABLE (1 << 7) 2240771fe6b9SJerome Glisse # define RADEON_Z_ENABLE (1 << 8) 2241551ebd83SDave Airlie # define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9) 2242771fe6b9SJerome Glisse # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 2243771fe6b9SJerome Glisse 2244771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_ARGB1555 3 2245771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_RGB565 4 2246771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_ARGB8888 6 2247771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_RGB332 7 2248771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_Y8 8 2249771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_RGB8 9 2250771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_YUV422_VYUY 11 2251771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_YUV422_YVYU 12 2252771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_aYUV444 14 2253771fe6b9SJerome Glisse # define RADEON_COLOR_FORMAT_ARGB4444 15 2254771fe6b9SJerome Glisse 2255771fe6b9SJerome Glisse # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) 2256771fe6b9SJerome Glisse #define RADEON_RB3D_COLOROFFSET 0x1c40 2257771fe6b9SJerome Glisse # define RADEON_COLOROFFSET_MASK 0xfffffff0 2258771fe6b9SJerome Glisse #define RADEON_RB3D_COLORPITCH 0x1c48 2259771fe6b9SJerome Glisse # define RADEON_COLORPITCH_MASK 0x000001ff8 2260771fe6b9SJerome Glisse # define RADEON_COLOR_TILE_ENABLE (1 << 16) 2261771fe6b9SJerome Glisse # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) 2262771fe6b9SJerome Glisse # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) 2263771fe6b9SJerome Glisse # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) 2264771fe6b9SJerome Glisse # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) 2265771fe6b9SJerome Glisse #define RADEON_RB3D_DEPTHOFFSET 0x1c24 2266771fe6b9SJerome Glisse #define RADEON_RB3D_DEPTHPITCH 0x1c28 2267771fe6b9SJerome Glisse # define RADEON_DEPTHPITCH_MASK 0x00001ff8 2268771fe6b9SJerome Glisse # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) 2269771fe6b9SJerome Glisse # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) 2270771fe6b9SJerome Glisse # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 2271771fe6b9SJerome Glisse #define RADEON_RB3D_PLANEMASK 0x1d84 2272771fe6b9SJerome Glisse #define RADEON_RB3D_ROPCNTL 0x1d80 2273771fe6b9SJerome Glisse # define RADEON_ROP_MASK (15 << 8) 2274771fe6b9SJerome Glisse # define RADEON_ROP_CLEAR (0 << 8) 2275771fe6b9SJerome Glisse # define RADEON_ROP_NOR (1 << 8) 2276771fe6b9SJerome Glisse # define RADEON_ROP_AND_INVERTED (2 << 8) 2277771fe6b9SJerome Glisse # define RADEON_ROP_COPY_INVERTED (3 << 8) 2278771fe6b9SJerome Glisse # define RADEON_ROP_AND_REVERSE (4 << 8) 2279771fe6b9SJerome Glisse # define RADEON_ROP_INVERT (5 << 8) 2280771fe6b9SJerome Glisse # define RADEON_ROP_XOR (6 << 8) 2281771fe6b9SJerome Glisse # define RADEON_ROP_NAND (7 << 8) 2282771fe6b9SJerome Glisse # define RADEON_ROP_AND (8 << 8) 2283771fe6b9SJerome Glisse # define RADEON_ROP_EQUIV (9 << 8) 2284771fe6b9SJerome Glisse # define RADEON_ROP_NOOP (10 << 8) 2285771fe6b9SJerome Glisse # define RADEON_ROP_OR_INVERTED (11 << 8) 2286771fe6b9SJerome Glisse # define RADEON_ROP_COPY (12 << 8) 2287771fe6b9SJerome Glisse # define RADEON_ROP_OR_REVERSE (13 << 8) 2288771fe6b9SJerome Glisse # define RADEON_ROP_OR (14 << 8) 2289771fe6b9SJerome Glisse # define RADEON_ROP_SET (15 << 8) 2290771fe6b9SJerome Glisse #define RADEON_RB3D_STENCILREFMASK 0x1d7c 2291771fe6b9SJerome Glisse # define RADEON_STENCIL_REF_SHIFT 0 2292771fe6b9SJerome Glisse # define RADEON_STENCIL_REF_MASK (0xff << 0) 2293771fe6b9SJerome Glisse # define RADEON_STENCIL_MASK_SHIFT 16 2294771fe6b9SJerome Glisse # define RADEON_STENCIL_VALUE_MASK (0xff << 16) 2295771fe6b9SJerome Glisse # define RADEON_STENCIL_WRITEMASK_SHIFT 24 2296771fe6b9SJerome Glisse # define RADEON_STENCIL_WRITE_MASK (0xff << 24) 2297771fe6b9SJerome Glisse #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 2298771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) 2299771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 2300771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 2301771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 2302771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 2303771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 2304771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) 2305771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 2306771fe6b9SJerome Glisse # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 2307771fe6b9SJerome Glisse # define RADEON_Z_TEST_NEVER (0 << 4) 2308771fe6b9SJerome Glisse # define RADEON_Z_TEST_LESS (1 << 4) 2309771fe6b9SJerome Glisse # define RADEON_Z_TEST_LEQUAL (2 << 4) 2310771fe6b9SJerome Glisse # define RADEON_Z_TEST_EQUAL (3 << 4) 2311771fe6b9SJerome Glisse # define RADEON_Z_TEST_GEQUAL (4 << 4) 2312771fe6b9SJerome Glisse # define RADEON_Z_TEST_GREATER (5 << 4) 2313771fe6b9SJerome Glisse # define RADEON_Z_TEST_NEQUAL (6 << 4) 2314771fe6b9SJerome Glisse # define RADEON_Z_TEST_ALWAYS (7 << 4) 2315771fe6b9SJerome Glisse # define RADEON_Z_TEST_MASK (7 << 4) 2316771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_NEVER (0 << 12) 2317771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_LESS (1 << 12) 2318771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) 2319771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_EQUAL (3 << 12) 2320771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) 2321771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_GREATER (5 << 12) 2322771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) 2323771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 2324771fe6b9SJerome Glisse # define RADEON_STENCIL_TEST_MASK (0x7 << 12) 2325771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_KEEP (0 << 16) 2326771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_ZERO (1 << 16) 2327771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_REPLACE (2 << 16) 2328771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_INC (3 << 16) 2329771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_DEC (4 << 16) 2330771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_INVERT (5 << 16) 2331771fe6b9SJerome Glisse # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) 2332771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) 2333771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) 2334771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 2335771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_INC (3 << 20) 2336771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_DEC (4 << 20) 2337771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) 2338771fe6b9SJerome Glisse # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) 2339771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) 2340771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) 2341771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 2342771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_INC (3 << 24) 2343771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) 2344771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) 2345771fe6b9SJerome Glisse # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) 2346771fe6b9SJerome Glisse # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 2347771fe6b9SJerome Glisse # define RADEON_FORCE_Z_DIRTY (1 << 29) 2348771fe6b9SJerome Glisse # define RADEON_Z_WRITE_ENABLE (1 << 30) 2349771fe6b9SJerome Glisse #define RADEON_RE_LINE_PATTERN 0x1cd0 2350771fe6b9SJerome Glisse # define RADEON_LINE_PATTERN_MASK 0x0000ffff 2351771fe6b9SJerome Glisse # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 2352771fe6b9SJerome Glisse # define RADEON_LINE_PATTERN_START_SHIFT 24 2353771fe6b9SJerome Glisse # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 2354771fe6b9SJerome Glisse # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 2355771fe6b9SJerome Glisse # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) 2356771fe6b9SJerome Glisse #define RADEON_RE_LINE_STATE 0x1cd4 2357771fe6b9SJerome Glisse # define RADEON_LINE_CURRENT_PTR_SHIFT 0 2358771fe6b9SJerome Glisse # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 2359771fe6b9SJerome Glisse #define RADEON_RE_MISC 0x26c4 2360771fe6b9SJerome Glisse # define RADEON_STIPPLE_COORD_MASK 0x1f 2361771fe6b9SJerome Glisse # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 2362771fe6b9SJerome Glisse # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) 2363771fe6b9SJerome Glisse # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 2364771fe6b9SJerome Glisse # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) 2365771fe6b9SJerome Glisse # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) 2366771fe6b9SJerome Glisse # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) 2367771fe6b9SJerome Glisse #define RADEON_RE_SOLID_COLOR 0x1c1c 2368771fe6b9SJerome Glisse #define RADEON_RE_TOP_LEFT 0x26c0 2369771fe6b9SJerome Glisse # define RADEON_RE_LEFT_SHIFT 0 2370771fe6b9SJerome Glisse # define RADEON_RE_TOP_SHIFT 16 2371771fe6b9SJerome Glisse #define RADEON_RE_WIDTH_HEIGHT 0x1c44 2372771fe6b9SJerome Glisse # define RADEON_RE_WIDTH_SHIFT 0 2373771fe6b9SJerome Glisse # define RADEON_RE_HEIGHT_SHIFT 16 2374771fe6b9SJerome Glisse 237517782d99SDave Airlie #define RADEON_RB3D_ZPASS_DATA 0x3290 237617782d99SDave Airlie #define RADEON_RB3D_ZPASS_ADDR 0x3294 237717782d99SDave Airlie 2378771fe6b9SJerome Glisse #define RADEON_SE_CNTL 0x1c4c 2379771fe6b9SJerome Glisse # define RADEON_FFACE_CULL_CW (0 << 0) 2380771fe6b9SJerome Glisse # define RADEON_FFACE_CULL_CCW (1 << 0) 2381771fe6b9SJerome Glisse # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) 2382771fe6b9SJerome Glisse # define RADEON_BFACE_CULL (0 << 1) 2383771fe6b9SJerome Glisse # define RADEON_BFACE_SOLID (3 << 1) 2384771fe6b9SJerome Glisse # define RADEON_FFACE_CULL (0 << 3) 2385771fe6b9SJerome Glisse # define RADEON_FFACE_SOLID (3 << 3) 2386771fe6b9SJerome Glisse # define RADEON_FFACE_CULL_MASK (3 << 3) 2387771fe6b9SJerome Glisse # define RADEON_BADVTX_CULL_DISABLE (1 << 5) 2388771fe6b9SJerome Glisse # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) 2389771fe6b9SJerome Glisse # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) 2390771fe6b9SJerome Glisse # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) 2391771fe6b9SJerome Glisse # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 2392771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) 2393771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 2394771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 2395771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) 2396771fe6b9SJerome Glisse # define RADEON_ALPHA_SHADE_SOLID (0 << 10) 2397771fe6b9SJerome Glisse # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 2398771fe6b9SJerome Glisse # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 2399771fe6b9SJerome Glisse # define RADEON_ALPHA_SHADE_MASK (3 << 10) 2400771fe6b9SJerome Glisse # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) 2401771fe6b9SJerome Glisse # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 2402771fe6b9SJerome Glisse # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 2403771fe6b9SJerome Glisse # define RADEON_SPECULAR_SHADE_MASK (3 << 12) 2404771fe6b9SJerome Glisse # define RADEON_FOG_SHADE_SOLID (0 << 14) 2405771fe6b9SJerome Glisse # define RADEON_FOG_SHADE_FLAT (1 << 14) 2406771fe6b9SJerome Glisse # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 2407771fe6b9SJerome Glisse # define RADEON_FOG_SHADE_MASK (3 << 14) 2408771fe6b9SJerome Glisse # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) 2409771fe6b9SJerome Glisse # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) 2410771fe6b9SJerome Glisse # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) 2411771fe6b9SJerome Glisse # define RADEON_WIDELINE_ENABLE (1 << 20) 2412771fe6b9SJerome Glisse # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 2413771fe6b9SJerome Glisse # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 2414771fe6b9SJerome Glisse # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) 2415771fe6b9SJerome Glisse # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 2416771fe6b9SJerome Glisse # define RADEON_ROUND_MODE_TRUNC (0 << 28) 2417771fe6b9SJerome Glisse # define RADEON_ROUND_MODE_ROUND (1 << 28) 2418771fe6b9SJerome Glisse # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) 2419771fe6b9SJerome Glisse # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) 2420771fe6b9SJerome Glisse # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) 2421771fe6b9SJerome Glisse # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 2422771fe6b9SJerome Glisse # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) 2423771fe6b9SJerome Glisse # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) 2424771fe6b9SJerome Glisse #define R200_RE_CNTL 0x1c50 2425771fe6b9SJerome Glisse # define R200_STIPPLE_ENABLE 0x1 2426771fe6b9SJerome Glisse # define R200_SCISSOR_ENABLE 0x2 2427771fe6b9SJerome Glisse # define R200_PATTERN_ENABLE 0x4 2428771fe6b9SJerome Glisse # define R200_PERSPECTIVE_ENABLE 0x8 2429771fe6b9SJerome Glisse # define R200_POINT_SMOOTH 0x20 2430771fe6b9SJerome Glisse # define R200_VTX_STQ0_D3D 0x00010000 2431771fe6b9SJerome Glisse # define R200_VTX_STQ1_D3D 0x00040000 2432771fe6b9SJerome Glisse # define R200_VTX_STQ2_D3D 0x00100000 2433771fe6b9SJerome Glisse # define R200_VTX_STQ3_D3D 0x00400000 2434771fe6b9SJerome Glisse # define R200_VTX_STQ4_D3D 0x01000000 2435771fe6b9SJerome Glisse # define R200_VTX_STQ5_D3D 0x04000000 2436771fe6b9SJerome Glisse #define RADEON_SE_CNTL_STATUS 0x2140 2437771fe6b9SJerome Glisse # define RADEON_VC_NO_SWAP (0 << 0) 2438771fe6b9SJerome Glisse # define RADEON_VC_16BIT_SWAP (1 << 0) 2439771fe6b9SJerome Glisse # define RADEON_VC_32BIT_SWAP (2 << 0) 2440771fe6b9SJerome Glisse # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) 2441771fe6b9SJerome Glisse # define RADEON_TCL_BYPASS (1 << 8) 2442771fe6b9SJerome Glisse #define RADEON_SE_COORD_FMT 0x1c50 2443771fe6b9SJerome Glisse # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) 2444771fe6b9SJerome Glisse # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) 2445771fe6b9SJerome Glisse # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) 2446771fe6b9SJerome Glisse # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) 2447771fe6b9SJerome Glisse # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) 2448771fe6b9SJerome Glisse # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) 2449771fe6b9SJerome Glisse # define RADEON_VTX_W0_NORMALIZE (1 << 12) 2450771fe6b9SJerome Glisse # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) 2451771fe6b9SJerome Glisse # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) 2452771fe6b9SJerome Glisse # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) 2453771fe6b9SJerome Glisse # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) 2454771fe6b9SJerome Glisse # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) 2455771fe6b9SJerome Glisse # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) 2456771fe6b9SJerome Glisse # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) 2457771fe6b9SJerome Glisse #define RADEON_SE_LINE_WIDTH 0x1db8 2458771fe6b9SJerome Glisse #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c 2459771fe6b9SJerome Glisse # define RADEON_LIGHTING_ENABLE (1 << 0) 2460771fe6b9SJerome Glisse # define RADEON_LIGHT_IN_MODELSPACE (1 << 1) 2461771fe6b9SJerome Glisse # define RADEON_LOCAL_VIEWER (1 << 2) 2462771fe6b9SJerome Glisse # define RADEON_NORMALIZE_NORMALS (1 << 3) 2463771fe6b9SJerome Glisse # define RADEON_RESCALE_NORMALS (1 << 4) 2464771fe6b9SJerome Glisse # define RADEON_SPECULAR_LIGHTS (1 << 5) 2465771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) 2466771fe6b9SJerome Glisse # define RADEON_LIGHT_ALPHA (1 << 7) 2467771fe6b9SJerome Glisse # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) 2468771fe6b9SJerome Glisse # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) 2469771fe6b9SJerome Glisse # define RADEON_LM_SOURCE_STATE_PREMULT 0 2470771fe6b9SJerome Glisse # define RADEON_LM_SOURCE_STATE_MULT 1 2471771fe6b9SJerome Glisse # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 2472771fe6b9SJerome Glisse # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 2473771fe6b9SJerome Glisse # define RADEON_EMISSIVE_SOURCE_SHIFT 16 2474771fe6b9SJerome Glisse # define RADEON_AMBIENT_SOURCE_SHIFT 18 2475771fe6b9SJerome Glisse # define RADEON_DIFFUSE_SOURCE_SHIFT 20 2476771fe6b9SJerome Glisse # define RADEON_SPECULAR_SOURCE_SHIFT 22 2477771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 2478771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 2479771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 2480771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c 2481771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 2482771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 2483771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 2484771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c 2485771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 2486771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 2487771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 2488771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c 2489771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 2490771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 2491771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 2492771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c 2493771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c 2494771fe6b9SJerome Glisse # define RADEON_MODELVIEW_0_SHIFT 0 2495771fe6b9SJerome Glisse # define RADEON_MODELVIEW_1_SHIFT 4 2496771fe6b9SJerome Glisse # define RADEON_MODELVIEW_2_SHIFT 8 2497771fe6b9SJerome Glisse # define RADEON_MODELVIEW_3_SHIFT 12 2498771fe6b9SJerome Glisse # define RADEON_IT_MODELVIEW_0_SHIFT 16 2499771fe6b9SJerome Glisse # define RADEON_IT_MODELVIEW_1_SHIFT 20 2500771fe6b9SJerome Glisse # define RADEON_IT_MODELVIEW_2_SHIFT 24 2501771fe6b9SJerome Glisse # define RADEON_IT_MODELVIEW_3_SHIFT 28 2502771fe6b9SJerome Glisse #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 2503771fe6b9SJerome Glisse # define RADEON_MODELPROJECT_0_SHIFT 0 2504771fe6b9SJerome Glisse # define RADEON_MODELPROJECT_1_SHIFT 4 2505771fe6b9SJerome Glisse # define RADEON_MODELPROJECT_2_SHIFT 8 2506771fe6b9SJerome Glisse # define RADEON_MODELPROJECT_3_SHIFT 12 2507771fe6b9SJerome Glisse # define RADEON_TEXMAT_0_SHIFT 16 2508771fe6b9SJerome Glisse # define RADEON_TEXMAT_1_SHIFT 20 2509771fe6b9SJerome Glisse # define RADEON_TEXMAT_2_SHIFT 24 2510771fe6b9SJerome Glisse # define RADEON_TEXMAT_3_SHIFT 28 2511771fe6b9SJerome Glisse 2512771fe6b9SJerome Glisse 2513771fe6b9SJerome Glisse #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 2514771fe6b9SJerome Glisse # define RADEON_TCL_VTX_W0 (1 << 0) 2515771fe6b9SJerome Glisse # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) 2516771fe6b9SJerome Glisse # define RADEON_TCL_VTX_FP_ALPHA (1 << 2) 2517771fe6b9SJerome Glisse # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) 2518771fe6b9SJerome Glisse # define RADEON_TCL_VTX_FP_SPEC (1 << 4) 2519771fe6b9SJerome Glisse # define RADEON_TCL_VTX_FP_FOG (1 << 5) 2520771fe6b9SJerome Glisse # define RADEON_TCL_VTX_PK_SPEC (1 << 6) 2521771fe6b9SJerome Glisse # define RADEON_TCL_VTX_ST0 (1 << 7) 2522771fe6b9SJerome Glisse # define RADEON_TCL_VTX_ST1 (1 << 8) 2523771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Q1 (1 << 9) 2524771fe6b9SJerome Glisse # define RADEON_TCL_VTX_ST2 (1 << 10) 2525771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Q2 (1 << 11) 2526771fe6b9SJerome Glisse # define RADEON_TCL_VTX_ST3 (1 << 12) 2527771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Q3 (1 << 13) 2528771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Q0 (1 << 14) 2529771fe6b9SJerome Glisse # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 2530771fe6b9SJerome Glisse # define RADEON_TCL_VTX_NORM0 (1 << 18) 2531771fe6b9SJerome Glisse # define RADEON_TCL_VTX_XY1 (1 << 27) 2532771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Z1 (1 << 28) 2533771fe6b9SJerome Glisse # define RADEON_TCL_VTX_W1 (1 << 29) 2534771fe6b9SJerome Glisse # define RADEON_TCL_VTX_NORM1 (1 << 30) 2535771fe6b9SJerome Glisse # define RADEON_TCL_VTX_Z0 (1 << 31) 2536771fe6b9SJerome Glisse 2537771fe6b9SJerome Glisse #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 2538771fe6b9SJerome Glisse # define RADEON_TCL_COMPUTE_XYZW (1 << 0) 2539771fe6b9SJerome Glisse # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) 2540771fe6b9SJerome Glisse # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) 2541771fe6b9SJerome Glisse # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) 2542771fe6b9SJerome Glisse # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) 2543771fe6b9SJerome Glisse # define RADEON_TCL_TEX_INPUT_TEX_0 0 2544771fe6b9SJerome Glisse # define RADEON_TCL_TEX_INPUT_TEX_1 1 2545771fe6b9SJerome Glisse # define RADEON_TCL_TEX_INPUT_TEX_2 2 2546771fe6b9SJerome Glisse # define RADEON_TCL_TEX_INPUT_TEX_3 3 2547771fe6b9SJerome Glisse # define RADEON_TCL_TEX_COMPUTED_TEX_0 8 2548771fe6b9SJerome Glisse # define RADEON_TCL_TEX_COMPUTED_TEX_1 9 2549771fe6b9SJerome Glisse # define RADEON_TCL_TEX_COMPUTED_TEX_2 10 2550771fe6b9SJerome Glisse # define RADEON_TCL_TEX_COMPUTED_TEX_3 11 2551771fe6b9SJerome Glisse # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 2552771fe6b9SJerome Glisse # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 2553771fe6b9SJerome Glisse # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 2554771fe6b9SJerome Glisse # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 2555771fe6b9SJerome Glisse 2556771fe6b9SJerome Glisse #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 2557771fe6b9SJerome Glisse # define RADEON_LIGHT_0_ENABLE (1 << 0) 2558771fe6b9SJerome Glisse # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) 2559771fe6b9SJerome Glisse # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) 2560771fe6b9SJerome Glisse # define RADEON_LIGHT_0_IS_LOCAL (1 << 3) 2561771fe6b9SJerome Glisse # define RADEON_LIGHT_0_IS_SPOT (1 << 4) 2562771fe6b9SJerome Glisse # define RADEON_LIGHT_0_DUAL_CONE (1 << 5) 2563771fe6b9SJerome Glisse # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) 2564771fe6b9SJerome Glisse # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) 2565771fe6b9SJerome Glisse # define RADEON_LIGHT_0_SHIFT 0 2566771fe6b9SJerome Glisse # define RADEON_LIGHT_1_ENABLE (1 << 16) 2567771fe6b9SJerome Glisse # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) 2568771fe6b9SJerome Glisse # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) 2569771fe6b9SJerome Glisse # define RADEON_LIGHT_1_IS_LOCAL (1 << 19) 2570771fe6b9SJerome Glisse # define RADEON_LIGHT_1_IS_SPOT (1 << 20) 2571771fe6b9SJerome Glisse # define RADEON_LIGHT_1_DUAL_CONE (1 << 21) 2572771fe6b9SJerome Glisse # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) 2573771fe6b9SJerome Glisse # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) 2574771fe6b9SJerome Glisse # define RADEON_LIGHT_1_SHIFT 16 2575771fe6b9SJerome Glisse #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 2576771fe6b9SJerome Glisse # define RADEON_LIGHT_2_SHIFT 0 2577771fe6b9SJerome Glisse # define RADEON_LIGHT_3_SHIFT 16 2578771fe6b9SJerome Glisse #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 2579771fe6b9SJerome Glisse # define RADEON_LIGHT_4_SHIFT 0 2580771fe6b9SJerome Glisse # define RADEON_LIGHT_5_SHIFT 16 2581771fe6b9SJerome Glisse #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c 2582771fe6b9SJerome Glisse # define RADEON_LIGHT_6_SHIFT 0 2583771fe6b9SJerome Glisse # define RADEON_LIGHT_7_SHIFT 16 2584771fe6b9SJerome Glisse 2585771fe6b9SJerome Glisse #define RADEON_SE_TCL_SHININESS 0x2250 2586771fe6b9SJerome Glisse 2587771fe6b9SJerome Glisse #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 2588771fe6b9SJerome Glisse # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) 2589771fe6b9SJerome Glisse # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) 2590771fe6b9SJerome Glisse # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) 2591771fe6b9SJerome Glisse # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) 2592771fe6b9SJerome Glisse # define RADEON_TEXMAT_0_ENABLE (1 << 4) 2593771fe6b9SJerome Glisse # define RADEON_TEXMAT_1_ENABLE (1 << 5) 2594771fe6b9SJerome Glisse # define RADEON_TEXMAT_2_ENABLE (1 << 6) 2595771fe6b9SJerome Glisse # define RADEON_TEXMAT_3_ENABLE (1 << 7) 2596771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_MASK 0xf 2597771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 2598771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 2599771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 2600771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 2601771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_OBJ 4 2602771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_EYE 5 2603771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 2604771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 2605771fe6b9SJerome Glisse # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 2606771fe6b9SJerome Glisse # define RADEON_TEXGEN_0_INPUT_SHIFT 16 2607771fe6b9SJerome Glisse # define RADEON_TEXGEN_1_INPUT_SHIFT 20 2608771fe6b9SJerome Glisse # define RADEON_TEXGEN_2_INPUT_SHIFT 24 2609771fe6b9SJerome Glisse # define RADEON_TEXGEN_3_INPUT_SHIFT 28 2610771fe6b9SJerome Glisse 2611771fe6b9SJerome Glisse #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 2612771fe6b9SJerome Glisse # define RADEON_UCP_IN_CLIP_SPACE (1 << 0) 2613771fe6b9SJerome Glisse # define RADEON_UCP_IN_MODEL_SPACE (1 << 1) 2614771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_0 (1 << 2) 2615771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_1 (1 << 3) 2616771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_2 (1 << 4) 2617771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_3 (1 << 5) 2618771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_4 (1 << 6) 2619771fe6b9SJerome Glisse # define RADEON_UCP_ENABLE_5 (1 << 7) 2620771fe6b9SJerome Glisse # define RADEON_TCL_FOG_MASK (3 << 8) 2621771fe6b9SJerome Glisse # define RADEON_TCL_FOG_DISABLE (0 << 8) 2622771fe6b9SJerome Glisse # define RADEON_TCL_FOG_EXP (1 << 8) 2623771fe6b9SJerome Glisse # define RADEON_TCL_FOG_EXP2 (2 << 8) 2624771fe6b9SJerome Glisse # define RADEON_TCL_FOG_LINEAR (3 << 8) 2625771fe6b9SJerome Glisse # define RADEON_RNG_BASED_FOG (1 << 10) 2626771fe6b9SJerome Glisse # define RADEON_LIGHT_TWOSIDE (1 << 11) 2627771fe6b9SJerome Glisse # define RADEON_BLEND_OP_COUNT_MASK (7 << 12) 2628771fe6b9SJerome Glisse # define RADEON_BLEND_OP_COUNT_SHIFT 12 2629771fe6b9SJerome Glisse # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) 2630771fe6b9SJerome Glisse # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) 2631771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) 2632771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) 2633771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) 2634771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) 2635771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) 2636771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) 2637771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) 2638771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) 2639771fe6b9SJerome Glisse # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) 2640771fe6b9SJerome Glisse # define RADEON_CULL_FRONT_IS_CW (0 << 28) 2641771fe6b9SJerome Glisse # define RADEON_CULL_FRONT_IS_CCW (1 << 28) 2642771fe6b9SJerome Glisse # define RADEON_CULL_FRONT (1 << 29) 2643771fe6b9SJerome Glisse # define RADEON_CULL_BACK (1 << 30) 2644771fe6b9SJerome Glisse # define RADEON_FORCE_W_TO_ONE (1 << 31) 2645771fe6b9SJerome Glisse 2646771fe6b9SJerome Glisse #define RADEON_SE_VPORT_XSCALE 0x1d98 2647771fe6b9SJerome Glisse #define RADEON_SE_VPORT_XOFFSET 0x1d9c 2648771fe6b9SJerome Glisse #define RADEON_SE_VPORT_YSCALE 0x1da0 2649771fe6b9SJerome Glisse #define RADEON_SE_VPORT_YOFFSET 0x1da4 2650771fe6b9SJerome Glisse #define RADEON_SE_VPORT_ZSCALE 0x1da8 2651771fe6b9SJerome Glisse #define RADEON_SE_VPORT_ZOFFSET 0x1dac 2652771fe6b9SJerome Glisse #define RADEON_SE_ZBIAS_FACTOR 0x1db0 2653771fe6b9SJerome Glisse #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 2654771fe6b9SJerome Glisse 2655771fe6b9SJerome Glisse #define RADEON_SE_VTX_FMT 0x2080 2656771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_XY 0x00000000 2657771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_W0 0x00000001 2658771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 2659771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 2660771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 2661771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 2662771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_FPFOG 0x00000020 2663771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 2664771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_ST0 0x00000080 2665771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_ST1 0x00000100 2666771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Q1 0x00000200 2667771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_ST2 0x00000400 2668771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Q2 0x00000800 2669771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_ST3 0x00001000 2670771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Q3 0x00002000 2671771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Q0 0x00004000 2672771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 2673771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_N0 0x00040000 2674771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_XY1 0x08000000 2675771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Z1 0x10000000 2676771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_W1 0x20000000 2677771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_N1 0x40000000 2678771fe6b9SJerome Glisse # define RADEON_SE_VTX_FMT_Z 0x80000000 2679771fe6b9SJerome Glisse 2680771fe6b9SJerome Glisse #define RADEON_SE_VF_CNTL 0x2084 2681771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_POINT_LIST 1 2682771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_LINE_LIST 2 2683771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 2684771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 2685771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 2686771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 2687771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 2688771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 2689771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 2690771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 2691771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 2692771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 2693771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 2694771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 2695771fe6b9SJerome Glisse # define RADEON_VF_PRIM_TYPE_POLYGON 15 2696771fe6b9SJerome Glisse # define RADEON_VF_PRIM_WALK_STATE (0<<4) 2697771fe6b9SJerome Glisse # define RADEON_VF_PRIM_WALK_INDEX (1<<4) 2698771fe6b9SJerome Glisse # define RADEON_VF_PRIM_WALK_LIST (2<<4) 2699771fe6b9SJerome Glisse # define RADEON_VF_PRIM_WALK_DATA (3<<4) 2700771fe6b9SJerome Glisse # define RADEON_VF_COLOR_ORDER_RGBA (1<<6) 2701771fe6b9SJerome Glisse # define RADEON_VF_RADEON_MODE (1<<8) 2702771fe6b9SJerome Glisse # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) 2703771fe6b9SJerome Glisse # define RADEON_VF_PROG_STREAM_ENA (1<<10) 2704771fe6b9SJerome Glisse # define RADEON_VF_INDEX_SIZE_SHIFT 11 2705771fe6b9SJerome Glisse # define RADEON_VF_NUM_VERTICES_SHIFT 16 2706771fe6b9SJerome Glisse 2707771fe6b9SJerome Glisse #define RADEON_SE_PORT_DATA0 0x2000 2708771fe6b9SJerome Glisse 2709771fe6b9SJerome Glisse #define R200_SE_VAP_CNTL 0x2080 2710771fe6b9SJerome Glisse # define R200_VAP_TCL_ENABLE 0x00000001 2711771fe6b9SJerome Glisse # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 2712771fe6b9SJerome Glisse # define R200_VAP_FORCE_W_TO_ONE 0x00010000 2713771fe6b9SJerome Glisse # define R200_VAP_D3D_TEX_DEFAULT 0x00020000 2714771fe6b9SJerome Glisse # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 2715771fe6b9SJerome Glisse # define R200_VAP_VF_MAX_VTX_NUM (9 << 18) 2716771fe6b9SJerome Glisse # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 2717771fe6b9SJerome Glisse #define R200_VF_MAX_VTX_INDX 0x210c 2718771fe6b9SJerome Glisse #define R200_VF_MIN_VTX_INDX 0x2110 2719771fe6b9SJerome Glisse #define R200_SE_VTE_CNTL 0x20b0 2720771fe6b9SJerome Glisse # define R200_VPORT_X_SCALE_ENA 0x00000001 2721771fe6b9SJerome Glisse # define R200_VPORT_X_OFFSET_ENA 0x00000002 2722771fe6b9SJerome Glisse # define R200_VPORT_Y_SCALE_ENA 0x00000004 2723771fe6b9SJerome Glisse # define R200_VPORT_Y_OFFSET_ENA 0x00000008 2724771fe6b9SJerome Glisse # define R200_VPORT_Z_SCALE_ENA 0x00000010 2725771fe6b9SJerome Glisse # define R200_VPORT_Z_OFFSET_ENA 0x00000020 2726771fe6b9SJerome Glisse # define R200_VTX_XY_FMT 0x00000100 2727771fe6b9SJerome Glisse # define R200_VTX_Z_FMT 0x00000200 2728771fe6b9SJerome Glisse # define R200_VTX_W0_FMT 0x00000400 2729771fe6b9SJerome Glisse # define R200_VTX_W0_NORMALIZE 0x00000800 2730771fe6b9SJerome Glisse # define R200_VTX_ST_DENORMALIZED 0x00001000 2731771fe6b9SJerome Glisse #define R200_SE_VAP_CNTL_STATUS 0x2140 2732771fe6b9SJerome Glisse # define R200_VC_NO_SWAP (0 << 0) 2733771fe6b9SJerome Glisse # define R200_VC_16BIT_SWAP (1 << 0) 2734771fe6b9SJerome Glisse # define R200_VC_32BIT_SWAP (2 << 0) 2735771fe6b9SJerome Glisse #define R200_PP_TXFILTER_0 0x2c00 2736771fe6b9SJerome Glisse #define R200_PP_TXFILTER_1 0x2c20 2737771fe6b9SJerome Glisse #define R200_PP_TXFILTER_2 0x2c40 2738771fe6b9SJerome Glisse #define R200_PP_TXFILTER_3 0x2c60 2739771fe6b9SJerome Glisse #define R200_PP_TXFILTER_4 0x2c80 2740771fe6b9SJerome Glisse #define R200_PP_TXFILTER_5 0x2ca0 2741771fe6b9SJerome Glisse # define R200_MAG_FILTER_NEAREST (0 << 0) 2742771fe6b9SJerome Glisse # define R200_MAG_FILTER_LINEAR (1 << 0) 2743771fe6b9SJerome Glisse # define R200_MAG_FILTER_MASK (1 << 0) 2744771fe6b9SJerome Glisse # define R200_MIN_FILTER_NEAREST (0 << 1) 2745771fe6b9SJerome Glisse # define R200_MIN_FILTER_LINEAR (1 << 1) 2746771fe6b9SJerome Glisse # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 2747771fe6b9SJerome Glisse # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 2748771fe6b9SJerome Glisse # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 2749771fe6b9SJerome Glisse # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 2750771fe6b9SJerome Glisse # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) 2751771fe6b9SJerome Glisse # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) 2752771fe6b9SJerome Glisse # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 2753771fe6b9SJerome Glisse # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 2754771fe6b9SJerome Glisse # define R200_MIN_FILTER_MASK (15 << 1) 2755771fe6b9SJerome Glisse # define R200_MAX_ANISO_1_TO_1 (0 << 5) 2756771fe6b9SJerome Glisse # define R200_MAX_ANISO_2_TO_1 (1 << 5) 2757771fe6b9SJerome Glisse # define R200_MAX_ANISO_4_TO_1 (2 << 5) 2758771fe6b9SJerome Glisse # define R200_MAX_ANISO_8_TO_1 (3 << 5) 2759771fe6b9SJerome Glisse # define R200_MAX_ANISO_16_TO_1 (4 << 5) 2760771fe6b9SJerome Glisse # define R200_MAX_ANISO_MASK (7 << 5) 2761771fe6b9SJerome Glisse # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) 2762771fe6b9SJerome Glisse # define R200_MAX_MIP_LEVEL_SHIFT 16 2763771fe6b9SJerome Glisse # define R200_YUV_TO_RGB (1 << 20) 2764771fe6b9SJerome Glisse # define R200_YUV_TEMPERATURE_COOL (0 << 21) 2765771fe6b9SJerome Glisse # define R200_YUV_TEMPERATURE_HOT (1 << 21) 2766771fe6b9SJerome Glisse # define R200_YUV_TEMPERATURE_MASK (1 << 21) 2767771fe6b9SJerome Glisse # define R200_WRAPEN_S (1 << 22) 2768771fe6b9SJerome Glisse # define R200_CLAMP_S_WRAP (0 << 23) 2769771fe6b9SJerome Glisse # define R200_CLAMP_S_MIRROR (1 << 23) 2770771fe6b9SJerome Glisse # define R200_CLAMP_S_CLAMP_LAST (2 << 23) 2771771fe6b9SJerome Glisse # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 2772771fe6b9SJerome Glisse # define R200_CLAMP_S_CLAMP_BORDER (4 << 23) 2773771fe6b9SJerome Glisse # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 2774771fe6b9SJerome Glisse # define R200_CLAMP_S_CLAMP_GL (6 << 23) 2775771fe6b9SJerome Glisse # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 2776771fe6b9SJerome Glisse # define R200_CLAMP_S_MASK (7 << 23) 2777771fe6b9SJerome Glisse # define R200_WRAPEN_T (1 << 26) 2778771fe6b9SJerome Glisse # define R200_CLAMP_T_WRAP (0 << 27) 2779771fe6b9SJerome Glisse # define R200_CLAMP_T_MIRROR (1 << 27) 2780771fe6b9SJerome Glisse # define R200_CLAMP_T_CLAMP_LAST (2 << 27) 2781771fe6b9SJerome Glisse # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 2782771fe6b9SJerome Glisse # define R200_CLAMP_T_CLAMP_BORDER (4 << 27) 2783771fe6b9SJerome Glisse # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 2784771fe6b9SJerome Glisse # define R200_CLAMP_T_CLAMP_GL (6 << 27) 2785771fe6b9SJerome Glisse # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 2786771fe6b9SJerome Glisse # define R200_CLAMP_T_MASK (7 << 27) 2787771fe6b9SJerome Glisse # define R200_KILL_LT_ZERO (1 << 30) 2788771fe6b9SJerome Glisse # define R200_BORDER_MODE_OGL (0 << 31) 2789771fe6b9SJerome Glisse # define R200_BORDER_MODE_D3D (1 << 31) 2790771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_0 0x2c04 2791771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_1 0x2c24 2792771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_2 0x2c44 2793771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_3 0x2c64 2794771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_4 0x2c84 2795771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_5 0x2ca4 2796771fe6b9SJerome Glisse # define R200_TXFORMAT_I8 (0 << 0) 2797771fe6b9SJerome Glisse # define R200_TXFORMAT_AI88 (1 << 0) 2798771fe6b9SJerome Glisse # define R200_TXFORMAT_RGB332 (2 << 0) 2799771fe6b9SJerome Glisse # define R200_TXFORMAT_ARGB1555 (3 << 0) 2800771fe6b9SJerome Glisse # define R200_TXFORMAT_RGB565 (4 << 0) 2801771fe6b9SJerome Glisse # define R200_TXFORMAT_ARGB4444 (5 << 0) 2802771fe6b9SJerome Glisse # define R200_TXFORMAT_ARGB8888 (6 << 0) 2803771fe6b9SJerome Glisse # define R200_TXFORMAT_RGBA8888 (7 << 0) 2804771fe6b9SJerome Glisse # define R200_TXFORMAT_Y8 (8 << 0) 2805771fe6b9SJerome Glisse # define R200_TXFORMAT_AVYU4444 (9 << 0) 2806771fe6b9SJerome Glisse # define R200_TXFORMAT_VYUY422 (10 << 0) 2807771fe6b9SJerome Glisse # define R200_TXFORMAT_YVYU422 (11 << 0) 2808771fe6b9SJerome Glisse # define R200_TXFORMAT_DXT1 (12 << 0) 2809771fe6b9SJerome Glisse # define R200_TXFORMAT_DXT23 (14 << 0) 2810771fe6b9SJerome Glisse # define R200_TXFORMAT_DXT45 (15 << 0) 2811551ebd83SDave Airlie # define R200_TXFORMAT_DVDU88 (18 << 0) 2812551ebd83SDave Airlie # define R200_TXFORMAT_LDVDU655 (19 << 0) 2813551ebd83SDave Airlie # define R200_TXFORMAT_LDVDU8888 (20 << 0) 2814551ebd83SDave Airlie # define R200_TXFORMAT_GR1616 (21 << 0) 2815771fe6b9SJerome Glisse # define R200_TXFORMAT_ABGR8888 (22 << 0) 2816551ebd83SDave Airlie # define R200_TXFORMAT_BGR111110 (23 << 0) 2817771fe6b9SJerome Glisse # define R200_TXFORMAT_FORMAT_MASK (31 << 0) 2818771fe6b9SJerome Glisse # define R200_TXFORMAT_FORMAT_SHIFT 0 2819771fe6b9SJerome Glisse # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) 2820771fe6b9SJerome Glisse # define R200_TXFORMAT_NON_POWER2 (1 << 7) 2821771fe6b9SJerome Glisse # define R200_TXFORMAT_WIDTH_MASK (15 << 8) 2822771fe6b9SJerome Glisse # define R200_TXFORMAT_WIDTH_SHIFT 8 2823771fe6b9SJerome Glisse # define R200_TXFORMAT_HEIGHT_MASK (15 << 12) 2824771fe6b9SJerome Glisse # define R200_TXFORMAT_HEIGHT_SHIFT 12 2825771fe6b9SJerome Glisse # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ 2826771fe6b9SJerome Glisse # define R200_TXFORMAT_F5_WIDTH_SHIFT 16 2827771fe6b9SJerome Glisse # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 2828771fe6b9SJerome Glisse # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 2829771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 2830771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 2831771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 2832771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) 2833771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) 2834771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) 2835771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) 2836771fe6b9SJerome Glisse # define R200_TXFORMAT_ST_ROUTE_SHIFT 24 2837771fe6b9SJerome Glisse # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 2838771fe6b9SJerome Glisse # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 2839771fe6b9SJerome Glisse # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 2840771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_0 0x2c08 2841771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_1 0x2c28 2842771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_2 0x2c48 2843771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_3 0x2c68 2844771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_4 0x2c88 2845771fe6b9SJerome Glisse #define R200_PP_TXFORMAT_X_5 0x2ca8 2846771fe6b9SJerome Glisse 2847771fe6b9SJerome Glisse #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ 2848771fe6b9SJerome Glisse #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ 2849771fe6b9SJerome Glisse #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ 2850771fe6b9SJerome Glisse #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ 2851771fe6b9SJerome Glisse #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ 2852771fe6b9SJerome Glisse #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ 2853771fe6b9SJerome Glisse 2854771fe6b9SJerome Glisse #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ 2855771fe6b9SJerome Glisse #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ 2856771fe6b9SJerome Glisse #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ 2857771fe6b9SJerome Glisse #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ 2858771fe6b9SJerome Glisse #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ 2859771fe6b9SJerome Glisse #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ 2860771fe6b9SJerome Glisse 2861551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_0 0x2c18 2862551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_1 0x2c38 2863551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_2 0x2c58 2864551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_3 0x2c78 2865551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_4 0x2c98 2866551ebd83SDave Airlie #define R200_PP_CUBIC_FACES_5 0x2cb8 2867551ebd83SDave Airlie 2868771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_0 0x2d00 2869771fe6b9SJerome Glisse # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 2870771fe6b9SJerome Glisse # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) 2871771fe6b9SJerome Glisse # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) 2872771fe6b9SJerome Glisse # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 2873771fe6b9SJerome Glisse # define R200_TXO_MACRO_LINEAR (0 << 2) 2874771fe6b9SJerome Glisse # define R200_TXO_MACRO_TILE (1 << 2) 2875771fe6b9SJerome Glisse # define R200_TXO_MICRO_LINEAR (0 << 3) 2876771fe6b9SJerome Glisse # define R200_TXO_MICRO_TILE (1 << 3) 2877771fe6b9SJerome Glisse # define R200_TXO_OFFSET_MASK 0xffffffe0 2878771fe6b9SJerome Glisse # define R200_TXO_OFFSET_SHIFT 5 2879551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 2880551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 2881551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 2882551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 2883551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 2884551ebd83SDave Airlie 2885771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_1 0x2d18 2886551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 2887551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 2888551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 2889551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 2890551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 2891551ebd83SDave Airlie 2892771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_2 0x2d30 2893551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 2894551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 2895551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 2896551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 2897551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 2898551ebd83SDave Airlie 2899771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_3 0x2d48 2900551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 2901551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 2902551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 2903551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 2904551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 2905771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_4 0x2d60 2906551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 2907551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 2908551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 2909551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 2910551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 2911771fe6b9SJerome Glisse #define R200_PP_TXOFFSET_5 0x2d78 2912551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 2913551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 2914551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 2915551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 2916551ebd83SDave Airlie #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 2917771fe6b9SJerome Glisse 2918771fe6b9SJerome Glisse #define R200_PP_TFACTOR_0 0x2ee0 2919771fe6b9SJerome Glisse #define R200_PP_TFACTOR_1 0x2ee4 2920771fe6b9SJerome Glisse #define R200_PP_TFACTOR_2 0x2ee8 2921771fe6b9SJerome Glisse #define R200_PP_TFACTOR_3 0x2eec 2922771fe6b9SJerome Glisse #define R200_PP_TFACTOR_4 0x2ef0 2923771fe6b9SJerome Glisse #define R200_PP_TFACTOR_5 0x2ef4 2924771fe6b9SJerome Glisse 2925771fe6b9SJerome Glisse #define R200_PP_TXCBLEND_0 0x2f00 2926771fe6b9SJerome Glisse # define R200_TXC_ARG_A_ZERO (0) 2927771fe6b9SJerome Glisse # define R200_TXC_ARG_A_CURRENT_COLOR (2) 2928771fe6b9SJerome Glisse # define R200_TXC_ARG_A_CURRENT_ALPHA (3) 2929771fe6b9SJerome Glisse # define R200_TXC_ARG_A_DIFFUSE_COLOR (4) 2930771fe6b9SJerome Glisse # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) 2931771fe6b9SJerome Glisse # define R200_TXC_ARG_A_SPECULAR_COLOR (6) 2932771fe6b9SJerome Glisse # define R200_TXC_ARG_A_SPECULAR_ALPHA (7) 2933771fe6b9SJerome Glisse # define R200_TXC_ARG_A_TFACTOR_COLOR (8) 2934771fe6b9SJerome Glisse # define R200_TXC_ARG_A_TFACTOR_ALPHA (9) 2935771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R0_COLOR (10) 2936771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R0_ALPHA (11) 2937771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R1_COLOR (12) 2938771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R1_ALPHA (13) 2939771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R2_COLOR (14) 2940771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R2_ALPHA (15) 2941771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R3_COLOR (16) 2942771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R3_ALPHA (17) 2943771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R4_COLOR (18) 2944771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R4_ALPHA (19) 2945771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R5_COLOR (20) 2946771fe6b9SJerome Glisse # define R200_TXC_ARG_A_R5_ALPHA (21) 2947771fe6b9SJerome Glisse # define R200_TXC_ARG_A_TFACTOR1_COLOR (26) 2948771fe6b9SJerome Glisse # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) 2949771fe6b9SJerome Glisse # define R200_TXC_ARG_A_MASK (31 << 0) 2950771fe6b9SJerome Glisse # define R200_TXC_ARG_A_SHIFT 0 2951771fe6b9SJerome Glisse # define R200_TXC_ARG_B_ZERO (0 << 5) 2952771fe6b9SJerome Glisse # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) 2953771fe6b9SJerome Glisse # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) 2954771fe6b9SJerome Glisse # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) 2955771fe6b9SJerome Glisse # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) 2956771fe6b9SJerome Glisse # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) 2957771fe6b9SJerome Glisse # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) 2958771fe6b9SJerome Glisse # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) 2959771fe6b9SJerome Glisse # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) 2960771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R0_COLOR (10 << 5) 2961771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R0_ALPHA (11 << 5) 2962771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R1_COLOR (12 << 5) 2963771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R1_ALPHA (13 << 5) 2964771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R2_COLOR (14 << 5) 2965771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R2_ALPHA (15 << 5) 2966771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R3_COLOR (16 << 5) 2967771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R3_ALPHA (17 << 5) 2968771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R4_COLOR (18 << 5) 2969771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R4_ALPHA (19 << 5) 2970771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R5_COLOR (20 << 5) 2971771fe6b9SJerome Glisse # define R200_TXC_ARG_B_R5_ALPHA (21 << 5) 2972771fe6b9SJerome Glisse # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) 2973771fe6b9SJerome Glisse # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) 2974771fe6b9SJerome Glisse # define R200_TXC_ARG_B_MASK (31 << 5) 2975771fe6b9SJerome Glisse # define R200_TXC_ARG_B_SHIFT 5 2976771fe6b9SJerome Glisse # define R200_TXC_ARG_C_ZERO (0 << 10) 2977771fe6b9SJerome Glisse # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) 2978771fe6b9SJerome Glisse # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) 2979771fe6b9SJerome Glisse # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) 2980771fe6b9SJerome Glisse # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) 2981771fe6b9SJerome Glisse # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) 2982771fe6b9SJerome Glisse # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) 2983771fe6b9SJerome Glisse # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) 2984771fe6b9SJerome Glisse # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) 2985771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R0_COLOR (10 << 10) 2986771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R0_ALPHA (11 << 10) 2987771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R1_COLOR (12 << 10) 2988771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R1_ALPHA (13 << 10) 2989771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R2_COLOR (14 << 10) 2990771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R2_ALPHA (15 << 10) 2991771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R3_COLOR (16 << 10) 2992771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R3_ALPHA (17 << 10) 2993771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R4_COLOR (18 << 10) 2994771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R4_ALPHA (19 << 10) 2995771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R5_COLOR (20 << 10) 2996771fe6b9SJerome Glisse # define R200_TXC_ARG_C_R5_ALPHA (21 << 10) 2997771fe6b9SJerome Glisse # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) 2998771fe6b9SJerome Glisse # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) 2999771fe6b9SJerome Glisse # define R200_TXC_ARG_C_MASK (31 << 10) 3000771fe6b9SJerome Glisse # define R200_TXC_ARG_C_SHIFT 10 3001771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_A (1 << 16) 3002771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_A_SHIFT (16) 3003771fe6b9SJerome Glisse # define R200_TXC_BIAS_ARG_A (1 << 17) 3004771fe6b9SJerome Glisse # define R200_TXC_SCALE_ARG_A (1 << 18) 3005771fe6b9SJerome Glisse # define R200_TXC_NEG_ARG_A (1 << 19) 3006771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_B (1 << 20) 3007771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_B_SHIFT (20) 3008771fe6b9SJerome Glisse # define R200_TXC_BIAS_ARG_B (1 << 21) 3009771fe6b9SJerome Glisse # define R200_TXC_SCALE_ARG_B (1 << 22) 3010771fe6b9SJerome Glisse # define R200_TXC_NEG_ARG_B (1 << 23) 3011771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_C (1 << 24) 3012771fe6b9SJerome Glisse # define R200_TXC_COMP_ARG_C_SHIFT (24) 3013771fe6b9SJerome Glisse # define R200_TXC_BIAS_ARG_C (1 << 25) 3014771fe6b9SJerome Glisse # define R200_TXC_SCALE_ARG_C (1 << 26) 3015771fe6b9SJerome Glisse # define R200_TXC_NEG_ARG_C (1 << 27) 3016771fe6b9SJerome Glisse # define R200_TXC_OP_MADD (0 << 28) 3017771fe6b9SJerome Glisse # define R200_TXC_OP_CND0 (2 << 28) 3018771fe6b9SJerome Glisse # define R200_TXC_OP_LERP (3 << 28) 3019771fe6b9SJerome Glisse # define R200_TXC_OP_DOT3 (4 << 28) 3020771fe6b9SJerome Glisse # define R200_TXC_OP_DOT4 (5 << 28) 3021771fe6b9SJerome Glisse # define R200_TXC_OP_CONDITIONAL (6 << 28) 3022771fe6b9SJerome Glisse # define R200_TXC_OP_DOT2_ADD (7 << 28) 3023771fe6b9SJerome Glisse # define R200_TXC_OP_MASK (7 << 28) 3024771fe6b9SJerome Glisse #define R200_PP_TXCBLEND2_0 0x2f04 3025771fe6b9SJerome Glisse # define R200_TXC_TFACTOR_SEL_SHIFT 0 3026771fe6b9SJerome Glisse # define R200_TXC_TFACTOR_SEL_MASK 0x7 3027771fe6b9SJerome Glisse # define R200_TXC_TFACTOR1_SEL_SHIFT 4 3028771fe6b9SJerome Glisse # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) 3029771fe6b9SJerome Glisse # define R200_TXC_SCALE_SHIFT 8 3030771fe6b9SJerome Glisse # define R200_TXC_SCALE_MASK (7 << 8) 3031771fe6b9SJerome Glisse # define R200_TXC_SCALE_1X (0 << 8) 3032771fe6b9SJerome Glisse # define R200_TXC_SCALE_2X (1 << 8) 3033771fe6b9SJerome Glisse # define R200_TXC_SCALE_4X (2 << 8) 3034771fe6b9SJerome Glisse # define R200_TXC_SCALE_8X (3 << 8) 3035771fe6b9SJerome Glisse # define R200_TXC_SCALE_INV2 (5 << 8) 3036771fe6b9SJerome Glisse # define R200_TXC_SCALE_INV4 (6 << 8) 3037771fe6b9SJerome Glisse # define R200_TXC_SCALE_INV8 (7 << 8) 3038771fe6b9SJerome Glisse # define R200_TXC_CLAMP_SHIFT 12 3039771fe6b9SJerome Glisse # define R200_TXC_CLAMP_MASK (3 << 12) 3040771fe6b9SJerome Glisse # define R200_TXC_CLAMP_WRAP (0 << 12) 3041771fe6b9SJerome Glisse # define R200_TXC_CLAMP_0_1 (1 << 12) 3042771fe6b9SJerome Glisse # define R200_TXC_CLAMP_8_8 (2 << 12) 3043771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_MASK (7 << 16) 3044771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_NONE (0 << 16) 3045771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R0 (1 << 16) 3046771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R1 (2 << 16) 3047771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R2 (3 << 16) 3048771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R3 (4 << 16) 3049771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R4 (5 << 16) 3050771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_REG_R5 (6 << 16) 3051771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_MASK (7 << 20) 3052771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_RGB (0 << 20) 3053771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_RG (1 << 20) 3054771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_RB (2 << 20) 3055771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_R (3 << 20) 3056771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_GB (4 << 20) 3057771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_G (5 << 20) 3058771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_B (6 << 20) 3059771fe6b9SJerome Glisse # define R200_TXC_OUTPUT_MASK_NONE (7 << 20) 3060771fe6b9SJerome Glisse # define R200_TXC_REPL_NORMAL 0 3061771fe6b9SJerome Glisse # define R200_TXC_REPL_RED 1 3062771fe6b9SJerome Glisse # define R200_TXC_REPL_GREEN 2 3063771fe6b9SJerome Glisse # define R200_TXC_REPL_BLUE 3 3064771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_A_SHIFT 26 3065771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_A_MASK (3 << 26) 3066771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_B_SHIFT 28 3067771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_B_MASK (3 << 28) 3068771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_C_SHIFT 30 3069771fe6b9SJerome Glisse # define R200_TXC_REPL_ARG_C_MASK (3 << 30) 3070771fe6b9SJerome Glisse #define R200_PP_TXABLEND_0 0x2f08 3071771fe6b9SJerome Glisse # define R200_TXA_ARG_A_ZERO (0) 3072771fe6b9SJerome Glisse # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ 3073771fe6b9SJerome Glisse # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ 3074771fe6b9SJerome Glisse # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) 3075771fe6b9SJerome Glisse # define R200_TXA_ARG_A_DIFFUSE_BLUE (5) 3076771fe6b9SJerome Glisse # define R200_TXA_ARG_A_SPECULAR_ALPHA (6) 3077771fe6b9SJerome Glisse # define R200_TXA_ARG_A_SPECULAR_BLUE (7) 3078771fe6b9SJerome Glisse # define R200_TXA_ARG_A_TFACTOR_ALPHA (8) 3079771fe6b9SJerome Glisse # define R200_TXA_ARG_A_TFACTOR_BLUE (9) 3080771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R0_ALPHA (10) 3081771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R0_BLUE (11) 3082771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R1_ALPHA (12) 3083771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R1_BLUE (13) 3084771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R2_ALPHA (14) 3085771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R2_BLUE (15) 3086771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R3_ALPHA (16) 3087771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R3_BLUE (17) 3088771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R4_ALPHA (18) 3089771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R4_BLUE (19) 3090771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R5_ALPHA (20) 3091771fe6b9SJerome Glisse # define R200_TXA_ARG_A_R5_BLUE (21) 3092771fe6b9SJerome Glisse # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) 3093771fe6b9SJerome Glisse # define R200_TXA_ARG_A_TFACTOR1_BLUE (27) 3094771fe6b9SJerome Glisse # define R200_TXA_ARG_A_MASK (31 << 0) 3095771fe6b9SJerome Glisse # define R200_TXA_ARG_A_SHIFT 0 3096771fe6b9SJerome Glisse # define R200_TXA_ARG_B_ZERO (0 << 5) 3097771fe6b9SJerome Glisse # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ 3098771fe6b9SJerome Glisse # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ 3099771fe6b9SJerome Glisse # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) 3100771fe6b9SJerome Glisse # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) 3101771fe6b9SJerome Glisse # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) 3102771fe6b9SJerome Glisse # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) 3103771fe6b9SJerome Glisse # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) 3104771fe6b9SJerome Glisse # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) 3105771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R0_ALPHA (10 << 5) 3106771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R0_BLUE (11 << 5) 3107771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R1_ALPHA (12 << 5) 3108771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R1_BLUE (13 << 5) 3109771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R2_ALPHA (14 << 5) 3110771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R2_BLUE (15 << 5) 3111771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R3_ALPHA (16 << 5) 3112771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R3_BLUE (17 << 5) 3113771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R4_ALPHA (18 << 5) 3114771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R4_BLUE (19 << 5) 3115771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R5_ALPHA (20 << 5) 3116771fe6b9SJerome Glisse # define R200_TXA_ARG_B_R5_BLUE (21 << 5) 3117771fe6b9SJerome Glisse # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) 3118771fe6b9SJerome Glisse # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) 3119771fe6b9SJerome Glisse # define R200_TXA_ARG_B_MASK (31 << 5) 3120771fe6b9SJerome Glisse # define R200_TXA_ARG_B_SHIFT 5 3121771fe6b9SJerome Glisse # define R200_TXA_ARG_C_ZERO (0 << 10) 3122771fe6b9SJerome Glisse # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ 3123771fe6b9SJerome Glisse # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ 3124771fe6b9SJerome Glisse # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) 3125771fe6b9SJerome Glisse # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) 3126771fe6b9SJerome Glisse # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) 3127771fe6b9SJerome Glisse # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) 3128771fe6b9SJerome Glisse # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) 3129771fe6b9SJerome Glisse # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) 3130771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R0_ALPHA (10 << 10) 3131771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R0_BLUE (11 << 10) 3132771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R1_ALPHA (12 << 10) 3133771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R1_BLUE (13 << 10) 3134771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R2_ALPHA (14 << 10) 3135771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R2_BLUE (15 << 10) 3136771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R3_ALPHA (16 << 10) 3137771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R3_BLUE (17 << 10) 3138771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R4_ALPHA (18 << 10) 3139771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R4_BLUE (19 << 10) 3140771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R5_ALPHA (20 << 10) 3141771fe6b9SJerome Glisse # define R200_TXA_ARG_C_R5_BLUE (21 << 10) 3142771fe6b9SJerome Glisse # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) 3143771fe6b9SJerome Glisse # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) 3144771fe6b9SJerome Glisse # define R200_TXA_ARG_C_MASK (31 << 10) 3145771fe6b9SJerome Glisse # define R200_TXA_ARG_C_SHIFT 10 3146771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_A (1 << 16) 3147771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_A_SHIFT (16) 3148771fe6b9SJerome Glisse # define R200_TXA_BIAS_ARG_A (1 << 17) 3149771fe6b9SJerome Glisse # define R200_TXA_SCALE_ARG_A (1 << 18) 3150771fe6b9SJerome Glisse # define R200_TXA_NEG_ARG_A (1 << 19) 3151771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_B (1 << 20) 3152771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_B_SHIFT (20) 3153771fe6b9SJerome Glisse # define R200_TXA_BIAS_ARG_B (1 << 21) 3154771fe6b9SJerome Glisse # define R200_TXA_SCALE_ARG_B (1 << 22) 3155771fe6b9SJerome Glisse # define R200_TXA_NEG_ARG_B (1 << 23) 3156771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_C (1 << 24) 3157771fe6b9SJerome Glisse # define R200_TXA_COMP_ARG_C_SHIFT (24) 3158771fe6b9SJerome Glisse # define R200_TXA_BIAS_ARG_C (1 << 25) 3159771fe6b9SJerome Glisse # define R200_TXA_SCALE_ARG_C (1 << 26) 3160771fe6b9SJerome Glisse # define R200_TXA_NEG_ARG_C (1 << 27) 3161771fe6b9SJerome Glisse # define R200_TXA_OP_MADD (0 << 28) 3162771fe6b9SJerome Glisse # define R200_TXA_OP_CND0 (2 << 28) 3163771fe6b9SJerome Glisse # define R200_TXA_OP_LERP (3 << 28) 3164771fe6b9SJerome Glisse # define R200_TXA_OP_CONDITIONAL (6 << 28) 3165771fe6b9SJerome Glisse # define R200_TXA_OP_MASK (7 << 28) 3166771fe6b9SJerome Glisse #define R200_PP_TXABLEND2_0 0x2f0c 3167771fe6b9SJerome Glisse # define R200_TXA_TFACTOR_SEL_SHIFT 0 3168771fe6b9SJerome Glisse # define R200_TXA_TFACTOR_SEL_MASK 0x7 3169771fe6b9SJerome Glisse # define R200_TXA_TFACTOR1_SEL_SHIFT 4 3170771fe6b9SJerome Glisse # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) 3171771fe6b9SJerome Glisse # define R200_TXA_SCALE_SHIFT 8 3172771fe6b9SJerome Glisse # define R200_TXA_SCALE_MASK (7 << 8) 3173771fe6b9SJerome Glisse # define R200_TXA_SCALE_1X (0 << 8) 3174771fe6b9SJerome Glisse # define R200_TXA_SCALE_2X (1 << 8) 3175771fe6b9SJerome Glisse # define R200_TXA_SCALE_4X (2 << 8) 3176771fe6b9SJerome Glisse # define R200_TXA_SCALE_8X (3 << 8) 3177771fe6b9SJerome Glisse # define R200_TXA_SCALE_INV2 (5 << 8) 3178771fe6b9SJerome Glisse # define R200_TXA_SCALE_INV4 (6 << 8) 3179771fe6b9SJerome Glisse # define R200_TXA_SCALE_INV8 (7 << 8) 3180771fe6b9SJerome Glisse # define R200_TXA_CLAMP_SHIFT 12 3181771fe6b9SJerome Glisse # define R200_TXA_CLAMP_MASK (3 << 12) 3182771fe6b9SJerome Glisse # define R200_TXA_CLAMP_WRAP (0 << 12) 3183771fe6b9SJerome Glisse # define R200_TXA_CLAMP_0_1 (1 << 12) 3184771fe6b9SJerome Glisse # define R200_TXA_CLAMP_8_8 (2 << 12) 3185771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_MASK (7 << 16) 3186771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_NONE (0 << 16) 3187771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R0 (1 << 16) 3188771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R1 (2 << 16) 3189771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R2 (3 << 16) 3190771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R3 (4 << 16) 3191771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R4 (5 << 16) 3192771fe6b9SJerome Glisse # define R200_TXA_OUTPUT_REG_R5 (6 << 16) 3193771fe6b9SJerome Glisse # define R200_TXA_DOT_ALPHA (1 << 20) 3194771fe6b9SJerome Glisse # define R200_TXA_REPL_NORMAL 0 3195771fe6b9SJerome Glisse # define R200_TXA_REPL_RED 1 3196771fe6b9SJerome Glisse # define R200_TXA_REPL_GREEN 2 3197771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_A_SHIFT 26 3198771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_A_MASK (3 << 26) 3199771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_B_SHIFT 28 3200771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_B_MASK (3 << 28) 3201771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_C_SHIFT 30 3202771fe6b9SJerome Glisse # define R200_TXA_REPL_ARG_C_MASK (3 << 30) 3203771fe6b9SJerome Glisse 3204771fe6b9SJerome Glisse #define R200_SE_VTX_FMT_0 0x2088 3205771fe6b9SJerome Glisse # define R200_VTX_XY 0 /* always have xy */ 3206771fe6b9SJerome Glisse # define R200_VTX_Z0 (1<<0) 3207771fe6b9SJerome Glisse # define R200_VTX_W0 (1<<1) 3208771fe6b9SJerome Glisse # define R200_VTX_WEIGHT_COUNT_SHIFT (2) 3209771fe6b9SJerome Glisse # define R200_VTX_PV_MATRIX_SEL (1<<5) 3210771fe6b9SJerome Glisse # define R200_VTX_N0 (1<<6) 3211771fe6b9SJerome Glisse # define R200_VTX_POINT_SIZE (1<<7) 3212771fe6b9SJerome Glisse # define R200_VTX_DISCRETE_FOG (1<<8) 3213771fe6b9SJerome Glisse # define R200_VTX_SHININESS_0 (1<<9) 3214771fe6b9SJerome Glisse # define R200_VTX_SHININESS_1 (1<<10) 3215771fe6b9SJerome Glisse # define R200_VTX_COLOR_NOT_PRESENT 0 3216771fe6b9SJerome Glisse # define R200_VTX_PK_RGBA 1 3217771fe6b9SJerome Glisse # define R200_VTX_FP_RGB 2 3218771fe6b9SJerome Glisse # define R200_VTX_FP_RGBA 3 3219771fe6b9SJerome Glisse # define R200_VTX_COLOR_MASK 3 3220771fe6b9SJerome Glisse # define R200_VTX_COLOR_0_SHIFT 11 3221771fe6b9SJerome Glisse # define R200_VTX_COLOR_1_SHIFT 13 3222771fe6b9SJerome Glisse # define R200_VTX_COLOR_2_SHIFT 15 3223771fe6b9SJerome Glisse # define R200_VTX_COLOR_3_SHIFT 17 3224771fe6b9SJerome Glisse # define R200_VTX_COLOR_4_SHIFT 19 3225771fe6b9SJerome Glisse # define R200_VTX_COLOR_5_SHIFT 21 3226771fe6b9SJerome Glisse # define R200_VTX_COLOR_6_SHIFT 23 3227771fe6b9SJerome Glisse # define R200_VTX_COLOR_7_SHIFT 25 3228771fe6b9SJerome Glisse # define R200_VTX_XY1 (1<<28) 3229771fe6b9SJerome Glisse # define R200_VTX_Z1 (1<<29) 3230771fe6b9SJerome Glisse # define R200_VTX_W1 (1<<30) 3231771fe6b9SJerome Glisse # define R200_VTX_N1 (1<<31) 3232771fe6b9SJerome Glisse #define R200_SE_VTX_FMT_1 0x208c 3233771fe6b9SJerome Glisse # define R200_VTX_TEX0_COMP_CNT_SHIFT 0 3234771fe6b9SJerome Glisse # define R200_VTX_TEX1_COMP_CNT_SHIFT 3 3235771fe6b9SJerome Glisse # define R200_VTX_TEX2_COMP_CNT_SHIFT 6 3236771fe6b9SJerome Glisse # define R200_VTX_TEX3_COMP_CNT_SHIFT 9 3237771fe6b9SJerome Glisse # define R200_VTX_TEX4_COMP_CNT_SHIFT 12 3238771fe6b9SJerome Glisse # define R200_VTX_TEX5_COMP_CNT_SHIFT 15 3239771fe6b9SJerome Glisse 3240771fe6b9SJerome Glisse #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 3241771fe6b9SJerome Glisse #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 3242771fe6b9SJerome Glisse #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 3243771fe6b9SJerome Glisse # define R200_OUTPUT_XYZW (1<<0) 3244771fe6b9SJerome Glisse # define R200_OUTPUT_COLOR_0 (1<<8) 3245771fe6b9SJerome Glisse # define R200_OUTPUT_COLOR_1 (1<<9) 3246771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_0 (1<<16) 3247771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_1 (1<<17) 3248771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_2 (1<<18) 3249771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_3 (1<<19) 3250771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_4 (1<<20) 3251771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_5 (1<<21) 3252771fe6b9SJerome Glisse # define R200_OUTPUT_TEX_MASK (0x3f<<16) 3253771fe6b9SJerome Glisse # define R200_OUTPUT_DISCRETE_FOG (1<<24) 3254771fe6b9SJerome Glisse # define R200_OUTPUT_PT_SIZE (1<<25) 3255771fe6b9SJerome Glisse # define R200_FORCE_INORDER_PROC (1<<31) 3256771fe6b9SJerome Glisse #define R200_PP_CNTL_X 0x2cc4 3257771fe6b9SJerome Glisse #define R200_PP_TXMULTI_CTL_0 0x2c1c 3258551ebd83SDave Airlie #define R200_PP_TXMULTI_CTL_1 0x2c3c 3259551ebd83SDave Airlie #define R200_PP_TXMULTI_CTL_2 0x2c5c 3260551ebd83SDave Airlie #define R200_PP_TXMULTI_CTL_3 0x2c7c 3261551ebd83SDave Airlie #define R200_PP_TXMULTI_CTL_4 0x2c9c 3262551ebd83SDave Airlie #define R200_PP_TXMULTI_CTL_5 0x2cbc 3263771fe6b9SJerome Glisse #define R200_SE_VTX_STATE_CNTL 0x2180 3264771fe6b9SJerome Glisse # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) 3265771fe6b9SJerome Glisse 3266771fe6b9SJerome Glisse /* Registers for CP and Microcode Engine */ 3267771fe6b9SJerome Glisse #define RADEON_CP_ME_RAM_ADDR 0x07d4 3268771fe6b9SJerome Glisse #define RADEON_CP_ME_RAM_RADDR 0x07d8 3269771fe6b9SJerome Glisse #define RADEON_CP_ME_RAM_DATAH 0x07dc 3270771fe6b9SJerome Glisse #define RADEON_CP_ME_RAM_DATAL 0x07e0 3271771fe6b9SJerome Glisse 3272771fe6b9SJerome Glisse #define RADEON_CP_RB_BASE 0x0700 3273771fe6b9SJerome Glisse #define RADEON_CP_RB_CNTL 0x0704 3274771fe6b9SJerome Glisse # define RADEON_RB_BUFSZ_SHIFT 0 3275771fe6b9SJerome Glisse # define RADEON_RB_BUFSZ_MASK (0x3f << 0) 3276771fe6b9SJerome Glisse # define RADEON_RB_BLKSZ_SHIFT 8 3277771fe6b9SJerome Glisse # define RADEON_RB_BLKSZ_MASK (0x3f << 8) 32784e484e7dSMichel Dänzer # define RADEON_BUF_SWAP_32BIT (1 << 17) 3279771fe6b9SJerome Glisse # define RADEON_MAX_FETCH_SHIFT 18 3280771fe6b9SJerome Glisse # define RADEON_MAX_FETCH_MASK (0x3 << 18) 3281771fe6b9SJerome Glisse # define RADEON_RB_NO_UPDATE (1 << 27) 3282771fe6b9SJerome Glisse # define RADEON_RB_RPTR_WR_ENA (1 << 31) 3283771fe6b9SJerome Glisse #define RADEON_CP_RB_RPTR_ADDR 0x070c 3284771fe6b9SJerome Glisse #define RADEON_CP_RB_RPTR 0x0710 3285771fe6b9SJerome Glisse #define RADEON_CP_RB_WPTR 0x0714 3286771fe6b9SJerome Glisse #define RADEON_CP_RB_RPTR_WR 0x071c 3287771fe6b9SJerome Glisse 32883ce0a23dSJerome Glisse #define RADEON_SCRATCH_UMSK 0x0770 32893ce0a23dSJerome Glisse #define RADEON_SCRATCH_ADDR 0x0774 32903ce0a23dSJerome Glisse 32913ce0a23dSJerome Glisse #define R600_CP_RB_BASE 0xc100 32923ce0a23dSJerome Glisse #define R600_CP_RB_CNTL 0xc104 32933ce0a23dSJerome Glisse # define R600_RB_BUFSZ(x) ((x) << 0) 32943ce0a23dSJerome Glisse # define R600_RB_BLKSZ(x) ((x) << 8) 32953ce0a23dSJerome Glisse # define R600_RB_NO_UPDATE (1 << 27) 32963ce0a23dSJerome Glisse # define R600_RB_RPTR_WR_ENA (1 << 31) 32973ce0a23dSJerome Glisse #define R600_CP_RB_RPTR_WR 0xc108 32983ce0a23dSJerome Glisse #define R600_CP_RB_RPTR_ADDR 0xc10c 32993ce0a23dSJerome Glisse #define R600_CP_RB_RPTR_ADDR_HI 0xc110 33003ce0a23dSJerome Glisse #define R600_CP_RB_WPTR 0xc114 33013ce0a23dSJerome Glisse #define R600_CP_RB_WPTR_ADDR 0xc118 33023ce0a23dSJerome Glisse #define R600_CP_RB_WPTR_ADDR_HI 0xc11c 33033ce0a23dSJerome Glisse #define R600_CP_RB_RPTR 0x8700 33043ce0a23dSJerome Glisse #define R600_CP_RB_WPTR_DELAY 0x8704 33053ce0a23dSJerome Glisse 3306771fe6b9SJerome Glisse #define RADEON_CP_IB_BASE 0x0738 3307771fe6b9SJerome Glisse #define RADEON_CP_IB_BUFSZ 0x073c 3308771fe6b9SJerome Glisse 3309771fe6b9SJerome Glisse #define RADEON_CP_CSQ_CNTL 0x0740 3310771fe6b9SJerome Glisse # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 3311771fe6b9SJerome Glisse # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 3312771fe6b9SJerome Glisse # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 3313771fe6b9SJerome Glisse # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 3314771fe6b9SJerome Glisse # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 3315771fe6b9SJerome Glisse # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 3316771fe6b9SJerome Glisse # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 3317771fe6b9SJerome Glisse 3318771fe6b9SJerome Glisse #define R300_CP_RESYNC_ADDR 0x778 3319771fe6b9SJerome Glisse #define R300_CP_RESYNC_DATA 0x77c 3320771fe6b9SJerome Glisse 3321771fe6b9SJerome Glisse #define RADEON_CP_CSQ_STAT 0x07f8 3322771fe6b9SJerome Glisse # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) 3323771fe6b9SJerome Glisse # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) 3324771fe6b9SJerome Glisse # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) 3325771fe6b9SJerome Glisse # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) 3326771fe6b9SJerome Glisse #define RADEON_CP_CSQ2_STAT 0x07fc 3327771fe6b9SJerome Glisse #define RADEON_CP_CSQ_ADDR 0x07f0 3328771fe6b9SJerome Glisse #define RADEON_CP_CSQ_DATA 0x07f4 3329771fe6b9SJerome Glisse #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 3330771fe6b9SJerome Glisse #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 3331771fe6b9SJerome Glisse 3332771fe6b9SJerome Glisse #define RADEON_CP_RB_WPTR_DELAY 0x0718 3333771fe6b9SJerome Glisse # define RADEON_PRE_WRITE_TIMER_SHIFT 0 3334771fe6b9SJerome Glisse # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 3335771fe6b9SJerome Glisse #define RADEON_CP_CSQ_MODE 0x0744 3336771fe6b9SJerome Glisse # define RADEON_INDIRECT2_START_SHIFT 0 3337771fe6b9SJerome Glisse # define RADEON_INDIRECT2_START_MASK (0x7f << 0) 3338771fe6b9SJerome Glisse # define RADEON_INDIRECT1_START_SHIFT 8 3339771fe6b9SJerome Glisse # define RADEON_INDIRECT1_START_MASK (0x7f << 8) 3340771fe6b9SJerome Glisse 3341771fe6b9SJerome Glisse #define RADEON_AIC_CNTL 0x01d0 3342771fe6b9SJerome Glisse # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 3343771fe6b9SJerome Glisse # define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) 33443e5cb98dSAlex Deucher # define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */ 3345771fe6b9SJerome Glisse #define RADEON_AIC_LO_ADDR 0x01dc 3346771fe6b9SJerome Glisse #define RADEON_AIC_PT_BASE 0x01d8 3347771fe6b9SJerome Glisse #define RADEON_AIC_HI_ADDR 0x01e0 3348771fe6b9SJerome Glisse 3349771fe6b9SJerome Glisse 3350771fe6b9SJerome Glisse 3351771fe6b9SJerome Glisse /* Constants */ 3352771fe6b9SJerome Glisse /* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */ 3353771fe6b9SJerome Glisse /* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */ 3354771fe6b9SJerome Glisse 3355771fe6b9SJerome Glisse 3356771fe6b9SJerome Glisse 3357771fe6b9SJerome Glisse /* CP packet types */ 3358771fe6b9SJerome Glisse #define RADEON_CP_PACKET0 0x00000000 3359771fe6b9SJerome Glisse #define RADEON_CP_PACKET1 0x40000000 3360771fe6b9SJerome Glisse #define RADEON_CP_PACKET2 0x80000000 3361771fe6b9SJerome Glisse #define RADEON_CP_PACKET3 0xC0000000 3362771fe6b9SJerome Glisse # define RADEON_CP_PACKET_MASK 0xC0000000 3363771fe6b9SJerome Glisse # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 3364771fe6b9SJerome Glisse # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) 3365771fe6b9SJerome Glisse # define RADEON_CP_PACKET0_REG_MASK 0x000007ff 3366771fe6b9SJerome Glisse # define R300_CP_PACKET0_REG_MASK 0x00001fff 33672f67c6e0SAlex Deucher # define R600_CP_PACKET0_REG_MASK 0x0000ffff 3368771fe6b9SJerome Glisse # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 3369771fe6b9SJerome Glisse # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 3370771fe6b9SJerome Glisse 3371771fe6b9SJerome Glisse #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 3372771fe6b9SJerome Glisse 3373771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_NOP 0xC0001000 3374771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 3375771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 3376771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 3377771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 3378771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 3379771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 3380771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 3381771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 3382771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 3383771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 3384771fe6b9SJerome Glisse #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 3385771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 3386771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 3387771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 3388771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 3389771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 3390771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 3391771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 3392771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 3393771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 3394771fe6b9SJerome Glisse #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 3395771fe6b9SJerome Glisse 3396771fe6b9SJerome Glisse 3397771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_XY 0x00000000 3398771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_W0 0x00000001 3399771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 3400771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 3401771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 3402771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 3403771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 3404771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 3405771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_ST0 0x00000080 3406771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_ST1 0x00000100 3407771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Q1 0x00000200 3408771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_ST2 0x00000400 3409771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Q2 0x00000800 3410771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_ST3 0x00001000 3411771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Q3 0x00002000 3412771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Q0 0x00004000 3413771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 3414771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_N0 0x00040000 3415771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_XY1 0x08000000 3416771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Z1 0x10000000 3417771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_W1 0x20000000 3418771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_N1 0x40000000 3419771fe6b9SJerome Glisse #define RADEON_CP_VC_FRMT_Z 0x80000000 3420771fe6b9SJerome Glisse 3421771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 3422771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 3423771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 3424771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 3425771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 3426771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 3427771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 3428771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 3429771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 3430771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 3431771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a 3432771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 3433771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 3434771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 3435771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 3436771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 3437771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 3438771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 3439771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 3440771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 3441771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 3442771fe6b9SJerome Glisse #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 3443771fe6b9SJerome Glisse 3444771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_0_ADDR 0 3445771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_1_ADDR 4 3446771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_2_ADDR 8 3447771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_3_ADDR 12 3448771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_4_ADDR 16 3449771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_5_ADDR 20 3450771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_6_ADDR 24 3451771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_7_ADDR 28 3452771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_8_ADDR 32 3453771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_9_ADDR 36 3454771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_10_ADDR 40 3455771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_11_ADDR 44 3456771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_12_ADDR 48 3457771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_13_ADDR 52 3458771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_14_ADDR 56 3459771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_15_ADDR 60 3460771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_AMBIENT_ADDR 64 3461771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 3462771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_SPECULAR_ADDR 80 3463771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_DIRPOS_ADDR 88 3464771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 3465771fe6b9SJerome Glisse #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 3466771fe6b9SJerome Glisse #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 3467771fe6b9SJerome Glisse #define RADEON_VS_UCP_ADDR 116 3468771fe6b9SJerome Glisse #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 3469771fe6b9SJerome Glisse #define RADEON_VS_FOG_PARAM_ADDR 123 3470771fe6b9SJerome Glisse #define RADEON_VS_EYE_VECTOR_ADDR 124 3471771fe6b9SJerome Glisse 3472771fe6b9SJerome Glisse #define RADEON_SS_LIGHT_DCD_ADDR 0 3473771fe6b9SJerome Glisse #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 3474771fe6b9SJerome Glisse #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 3475771fe6b9SJerome Glisse #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 3476771fe6b9SJerome Glisse #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 3477771fe6b9SJerome Glisse #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 3478771fe6b9SJerome Glisse #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 3479771fe6b9SJerome Glisse #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 3480771fe6b9SJerome Glisse #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 3481771fe6b9SJerome Glisse #define RADEON_SS_SHININESS 60 3482771fe6b9SJerome Glisse 3483771fe6b9SJerome Glisse #define RADEON_TV_MASTER_CNTL 0x0800 3484771fe6b9SJerome Glisse # define RADEON_TV_ASYNC_RST (1 << 0) 3485771fe6b9SJerome Glisse # define RADEON_CRT_ASYNC_RST (1 << 1) 3486771fe6b9SJerome Glisse # define RADEON_RESTART_PHASE_FIX (1 << 3) 3487771fe6b9SJerome Glisse # define RADEON_TV_FIFO_ASYNC_RST (1 << 4) 3488771fe6b9SJerome Glisse # define RADEON_VIN_ASYNC_RST (1 << 5) 3489771fe6b9SJerome Glisse # define RADEON_AUD_ASYNC_RST (1 << 6) 3490771fe6b9SJerome Glisse # define RADEON_DVS_ASYNC_RST (1 << 7) 3491771fe6b9SJerome Glisse # define RADEON_CRT_FIFO_CE_EN (1 << 9) 3492771fe6b9SJerome Glisse # define RADEON_TV_FIFO_CE_EN (1 << 10) 3493771fe6b9SJerome Glisse # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) 3494771fe6b9SJerome Glisse # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) 3495771fe6b9SJerome Glisse # define RADEON_TV_ON (1 << 31) 3496771fe6b9SJerome Glisse #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 3497771fe6b9SJerome Glisse # define RADEON_Y_RED_EN (1 << 0) 3498771fe6b9SJerome Glisse # define RADEON_C_GRN_EN (1 << 1) 3499771fe6b9SJerome Glisse # define RADEON_CMP_BLU_EN (1 << 2) 3500771fe6b9SJerome Glisse # define RADEON_DAC_DITHER_EN (1 << 3) 3501771fe6b9SJerome Glisse # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) 3502771fe6b9SJerome Glisse # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) 3503771fe6b9SJerome Glisse # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) 3504771fe6b9SJerome Glisse # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 3505771fe6b9SJerome Glisse #define RADEON_TV_RGB_CNTL 0x0804 3506771fe6b9SJerome Glisse # define RADEON_SWITCH_TO_BLUE (1 << 4) 3507771fe6b9SJerome Glisse # define RADEON_RGB_DITHER_EN (1 << 5) 3508771fe6b9SJerome Glisse # define RADEON_RGB_SRC_SEL_MASK (3 << 8) 3509771fe6b9SJerome Glisse # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) 3510771fe6b9SJerome Glisse # define RADEON_RGB_SRC_SEL_RMX (1 << 8) 3511771fe6b9SJerome Glisse # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) 3512771fe6b9SJerome Glisse # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) 3513771fe6b9SJerome Glisse # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 3514771fe6b9SJerome Glisse # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 35154ce001abSDave Airlie # define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) 3516771fe6b9SJerome Glisse # define RADEON_TVOUT_SCALE_EN (1 << 26) 35174ce001abSDave Airlie # define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) 3518771fe6b9SJerome Glisse #define RADEON_TV_SYNC_CNTL 0x0808 3519771fe6b9SJerome Glisse # define RADEON_SYNC_OE (1 << 0) 3520771fe6b9SJerome Glisse # define RADEON_SYNC_OUT (1 << 1) 3521771fe6b9SJerome Glisse # define RADEON_SYNC_IN (1 << 2) 3522771fe6b9SJerome Glisse # define RADEON_SYNC_PUB (1 << 3) 3523771fe6b9SJerome Glisse # define RADEON_SYNC_PD (1 << 4) 3524771fe6b9SJerome Glisse # define RADEON_TV_SYNC_IO_DRIVE (1 << 5) 3525771fe6b9SJerome Glisse #define RADEON_TV_HTOTAL 0x080c 3526771fe6b9SJerome Glisse #define RADEON_TV_HDISP 0x0810 3527771fe6b9SJerome Glisse #define RADEON_TV_HSTART 0x0818 3528771fe6b9SJerome Glisse #define RADEON_TV_HCOUNT 0x081C 3529771fe6b9SJerome Glisse #define RADEON_TV_VTOTAL 0x0820 3530771fe6b9SJerome Glisse #define RADEON_TV_VDISP 0x0824 3531771fe6b9SJerome Glisse #define RADEON_TV_VCOUNT 0x0828 3532771fe6b9SJerome Glisse #define RADEON_TV_FTOTAL 0x082c 3533771fe6b9SJerome Glisse #define RADEON_TV_FCOUNT 0x0830 3534771fe6b9SJerome Glisse #define RADEON_TV_FRESTART 0x0834 3535771fe6b9SJerome Glisse #define RADEON_TV_HRESTART 0x0838 3536771fe6b9SJerome Glisse #define RADEON_TV_VRESTART 0x083c 3537771fe6b9SJerome Glisse #define RADEON_TV_HOST_READ_DATA 0x0840 3538771fe6b9SJerome Glisse #define RADEON_TV_HOST_WRITE_DATA 0x0844 3539771fe6b9SJerome Glisse #define RADEON_TV_HOST_RD_WT_CNTL 0x0848 3540771fe6b9SJerome Glisse # define RADEON_HOST_FIFO_RD (1 << 12) 3541771fe6b9SJerome Glisse # define RADEON_HOST_FIFO_RD_ACK (1 << 13) 3542771fe6b9SJerome Glisse # define RADEON_HOST_FIFO_WT (1 << 14) 3543771fe6b9SJerome Glisse # define RADEON_HOST_FIFO_WT_ACK (1 << 15) 3544771fe6b9SJerome Glisse #define RADEON_TV_VSCALER_CNTL1 0x084c 3545771fe6b9SJerome Glisse # define RADEON_UV_INC_MASK 0xffff 3546771fe6b9SJerome Glisse # define RADEON_UV_INC_SHIFT 0 3547771fe6b9SJerome Glisse # define RADEON_Y_W_EN (1 << 24) 3548771fe6b9SJerome Glisse # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ 3549771fe6b9SJerome Glisse # define RADEON_Y_DEL_W_SIG_SHIFT 26 3550771fe6b9SJerome Glisse #define RADEON_TV_TIMING_CNTL 0x0850 3551771fe6b9SJerome Glisse # define RADEON_H_INC_MASK 0xfff 3552771fe6b9SJerome Glisse # define RADEON_H_INC_SHIFT 0 3553771fe6b9SJerome Glisse # define RADEON_REQ_Y_FIRST (1 << 19) 3554771fe6b9SJerome Glisse # define RADEON_FORCE_BURST_ALWAYS (1 << 21) 3555771fe6b9SJerome Glisse # define RADEON_UV_POST_SCALE_BYPASS (1 << 23) 3556771fe6b9SJerome Glisse # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 3557771fe6b9SJerome Glisse #define RADEON_TV_VSCALER_CNTL2 0x0854 3558771fe6b9SJerome Glisse # define RADEON_DITHER_MODE (1 << 0) 3559771fe6b9SJerome Glisse # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) 3560771fe6b9SJerome Glisse # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) 3561771fe6b9SJerome Glisse # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) 3562771fe6b9SJerome Glisse #define RADEON_TV_Y_FALL_CNTL 0x0858 3563771fe6b9SJerome Glisse # define RADEON_Y_FALL_PING_PONG (1 << 16) 3564771fe6b9SJerome Glisse # define RADEON_Y_COEF_EN (1 << 17) 3565771fe6b9SJerome Glisse #define RADEON_TV_Y_RISE_CNTL 0x085c 3566771fe6b9SJerome Glisse # define RADEON_Y_RISE_PING_PONG (1 << 16) 3567771fe6b9SJerome Glisse #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 3568771fe6b9SJerome Glisse #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 3569771fe6b9SJerome Glisse # define RADEON_YUPSAMP_EN (1 << 0) 3570771fe6b9SJerome Glisse # define RADEON_UVUPSAMP_EN (1 << 2) 3571771fe6b9SJerome Glisse #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 3572771fe6b9SJerome Glisse # define RADEON_Y_GAIN_LIMIT_SHIFT 0 3573771fe6b9SJerome Glisse # define RADEON_UV_GAIN_LIMIT_SHIFT 16 3574771fe6b9SJerome Glisse #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c 3575771fe6b9SJerome Glisse # define RADEON_Y_GAIN_SHIFT 0 3576771fe6b9SJerome Glisse # define RADEON_UV_GAIN_SHIFT 16 3577771fe6b9SJerome Glisse #define RADEON_TV_MODULATOR_CNTL1 0x0870 3578771fe6b9SJerome Glisse # define RADEON_YFLT_EN (1 << 2) 3579771fe6b9SJerome Glisse # define RADEON_UVFLT_EN (1 << 3) 3580771fe6b9SJerome Glisse # define RADEON_ALT_PHASE_EN (1 << 6) 3581771fe6b9SJerome Glisse # define RADEON_SYNC_TIP_LEVEL (1 << 7) 3582771fe6b9SJerome Glisse # define RADEON_BLANK_LEVEL_SHIFT 8 3583771fe6b9SJerome Glisse # define RADEON_SET_UP_LEVEL_SHIFT 16 3584771fe6b9SJerome Glisse # define RADEON_SLEW_RATE_LIMIT (1 << 23) 3585771fe6b9SJerome Glisse # define RADEON_CY_FILT_BLEND_SHIFT 28 3586771fe6b9SJerome Glisse #define RADEON_TV_MODULATOR_CNTL2 0x0874 3587771fe6b9SJerome Glisse # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff 3588771fe6b9SJerome Glisse # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff 3589771fe6b9SJerome Glisse # define RADEON_TV_V_BURST_LEVEL_SHIFT 16 3590771fe6b9SJerome Glisse #define RADEON_TV_CRC_CNTL 0x0890 3591771fe6b9SJerome Glisse #define RADEON_TV_UV_ADR 0x08ac 3592771fe6b9SJerome Glisse # define RADEON_MAX_UV_ADR_MASK 0x000000ff 3593771fe6b9SJerome Glisse # define RADEON_MAX_UV_ADR_SHIFT 0 3594771fe6b9SJerome Glisse # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 3595771fe6b9SJerome Glisse # define RADEON_TABLE1_BOT_ADR_SHIFT 8 3596771fe6b9SJerome Glisse # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 3597771fe6b9SJerome Glisse # define RADEON_TABLE3_TOP_ADR_SHIFT 16 3598771fe6b9SJerome Glisse # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 3599771fe6b9SJerome Glisse # define RADEON_HCODE_TABLE_SEL_SHIFT 25 3600771fe6b9SJerome Glisse # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 3601771fe6b9SJerome Glisse # define RADEON_VCODE_TABLE_SEL_SHIFT 27 3602771fe6b9SJerome Glisse # define RADEON_TV_MAX_FIFO_ADDR 0x1a7 3603771fe6b9SJerome Glisse # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff 3604771fe6b9SJerome Glisse #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ 3605771fe6b9SJerome Glisse #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ 3606771fe6b9SJerome Glisse # define RADEON_TV_M0LO_MASK 0xff 3607771fe6b9SJerome Glisse # define RADEON_TV_M0HI_MASK 0x7 3608771fe6b9SJerome Glisse # define RADEON_TV_M0HI_SHIFT 18 3609771fe6b9SJerome Glisse # define RADEON_TV_N0LO_MASK 0x1ff 3610771fe6b9SJerome Glisse # define RADEON_TV_N0LO_SHIFT 8 3611771fe6b9SJerome Glisse # define RADEON_TV_N0HI_MASK 0x3 3612771fe6b9SJerome Glisse # define RADEON_TV_N0HI_SHIFT 21 3613771fe6b9SJerome Glisse # define RADEON_TV_P_MASK 0xf 3614771fe6b9SJerome Glisse # define RADEON_TV_P_SHIFT 24 3615771fe6b9SJerome Glisse # define RADEON_TV_SLIP_EN (1 << 23) 3616771fe6b9SJerome Glisse # define RADEON_TV_DTO_EN (1 << 28) 3617771fe6b9SJerome Glisse #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ 3618771fe6b9SJerome Glisse # define RADEON_TVPLL_RESET (1 << 1) 3619771fe6b9SJerome Glisse # define RADEON_TVPLL_SLEEP (1 << 3) 3620771fe6b9SJerome Glisse # define RADEON_TVPLL_REFCLK_SEL (1 << 4) 3621771fe6b9SJerome Glisse # define RADEON_TVPCP_SHIFT 8 3622771fe6b9SJerome Glisse # define RADEON_TVPCP_MASK (7 << 8) 3623771fe6b9SJerome Glisse # define RADEON_TVPVG_SHIFT 11 3624771fe6b9SJerome Glisse # define RADEON_TVPVG_MASK (7 << 11) 3625771fe6b9SJerome Glisse # define RADEON_TVPDC_SHIFT 14 3626771fe6b9SJerome Glisse # define RADEON_TVPDC_MASK (3 << 14) 3627771fe6b9SJerome Glisse # define RADEON_TVPLL_TEST_DIS (1 << 31) 3628771fe6b9SJerome Glisse # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) 3629771fe6b9SJerome Glisse 3630771fe6b9SJerome Glisse #define RS400_DISP2_REQ_CNTL1 0xe30 3631771fe6b9SJerome Glisse # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 3632771fe6b9SJerome Glisse # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff 3633771fe6b9SJerome Glisse # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 3634771fe6b9SJerome Glisse # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff 3635771fe6b9SJerome Glisse # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 3636771fe6b9SJerome Glisse # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff 3637771fe6b9SJerome Glisse #define RS400_DISP2_REQ_CNTL2 0xe34 3638771fe6b9SJerome Glisse # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 3639771fe6b9SJerome Glisse # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff 3640771fe6b9SJerome Glisse # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 3641771fe6b9SJerome Glisse # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff 3642771fe6b9SJerome Glisse #define RS400_DMIF_MEM_CNTL1 0xe38 3643771fe6b9SJerome Glisse # define RS400_DISP2_START_ADR_SHIFT 0 3644771fe6b9SJerome Glisse # define RS400_DISP2_START_ADR_MASK 0x3ff 3645771fe6b9SJerome Glisse # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 3646771fe6b9SJerome Glisse # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff 3647771fe6b9SJerome Glisse # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 3648771fe6b9SJerome Glisse # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff 3649771fe6b9SJerome Glisse #define RS400_DISP1_REQ_CNTL1 0xe3c 3650771fe6b9SJerome Glisse # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 3651771fe6b9SJerome Glisse # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff 3652771fe6b9SJerome Glisse # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 3653771fe6b9SJerome Glisse # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff 3654771fe6b9SJerome Glisse # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 3655771fe6b9SJerome Glisse # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff 3656771fe6b9SJerome Glisse 3657771fe6b9SJerome Glisse #define RADEON_PCIE_INDEX 0x0030 3658771fe6b9SJerome Glisse #define RADEON_PCIE_DATA 0x0034 3659771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_CNTL 0x10 3660771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_EN (1 << 0) 3661771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 3662771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 3663771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 3664771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 3665771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 3666771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 3667771fe6b9SJerome Glisse # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 3668771fe6b9SJerome Glisse #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 3669771fe6b9SJerome Glisse #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 3670771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_BASE 0x13 3671771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_START_LO 0x14 3672771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_START_HI 0x15 3673771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_END_LO 0x16 3674771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_END_HI 0x17 3675771fe6b9SJerome Glisse #define RADEON_PCIE_TX_GART_ERROR 0x18 3676771fe6b9SJerome Glisse 3677771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG0 0x15e0 3678771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG1 0x15e4 3679771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG2 0x15e8 3680771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG3 0x15ec 3681771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG4 0x15f0 3682771fe6b9SJerome Glisse #define RADEON_SCRATCH_REG5 0x15f4 3683771fe6b9SJerome Glisse 3684f779b3e5SAlex Deucher #define RV530_GB_PIPE_SELECT2 0x4124 3685f779b3e5SAlex Deucher 3686771fe6b9SJerome Glisse #endif 3687