xref: /openbmc/linux/drivers/gpu/drm/radeon/radeon_pm.c (revision b34e08d5)
1 /*
2  * Permission is hereby granted, free of charge, to any person obtaining a
3  * copy of this software and associated documentation files (the "Software"),
4  * to deal in the Software without restriction, including without limitation
5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6  * and/or sell copies of the Software, and to permit persons to whom the
7  * Software is furnished to do so, subject to the following conditions:
8  *
9  * The above copyright notice and this permission notice shall be included in
10  * all copies or substantial portions of the Software.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18  * OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * Authors: Rafał Miłecki <zajec5@gmail.com>
21  *          Alex Deucher <alexdeucher@gmail.com>
22  */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
30 
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34 
35 static const char *radeon_pm_state_type_name[5] = {
36 	"",
37 	"Powersave",
38 	"Battery",
39 	"Balanced",
40 	"Performance",
41 };
42 
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
49 
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 			     enum radeon_pm_state_type ps_type,
52 			     int instance)
53 {
54 	int i;
55 	int found_instance = -1;
56 
57 	for (i = 0; i < rdev->pm.num_power_states; i++) {
58 		if (rdev->pm.power_state[i].type == ps_type) {
59 			found_instance++;
60 			if (found_instance == instance)
61 				return i;
62 		}
63 	}
64 	/* return default if no match */
65 	return rdev->pm.default_power_state_index;
66 }
67 
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69 {
70 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 		mutex_lock(&rdev->pm.mutex);
72 		if (power_supply_is_system_supplied() > 0)
73 			rdev->pm.dpm.ac_power = true;
74 		else
75 			rdev->pm.dpm.ac_power = false;
76 		if (rdev->asic->dpm.enable_bapm)
77 			radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 		mutex_unlock(&rdev->pm.mutex);
79         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 		if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 			mutex_lock(&rdev->pm.mutex);
82 			radeon_pm_update_profile(rdev);
83 			radeon_pm_set_clocks(rdev);
84 			mutex_unlock(&rdev->pm.mutex);
85 		}
86 	}
87 }
88 
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
90 {
91 	switch (rdev->pm.profile) {
92 	case PM_PROFILE_DEFAULT:
93 		rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
94 		break;
95 	case PM_PROFILE_AUTO:
96 		if (power_supply_is_system_supplied() > 0) {
97 			if (rdev->pm.active_crtc_count > 1)
98 				rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
99 			else
100 				rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
101 		} else {
102 			if (rdev->pm.active_crtc_count > 1)
103 				rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
104 			else
105 				rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
106 		}
107 		break;
108 	case PM_PROFILE_LOW:
109 		if (rdev->pm.active_crtc_count > 1)
110 			rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
111 		else
112 			rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
113 		break;
114 	case PM_PROFILE_MID:
115 		if (rdev->pm.active_crtc_count > 1)
116 			rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
117 		else
118 			rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
119 		break;
120 	case PM_PROFILE_HIGH:
121 		if (rdev->pm.active_crtc_count > 1)
122 			rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
123 		else
124 			rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
125 		break;
126 	}
127 
128 	if (rdev->pm.active_crtc_count == 0) {
129 		rdev->pm.requested_power_state_index =
130 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 		rdev->pm.requested_clock_mode_index =
132 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
133 	} else {
134 		rdev->pm.requested_power_state_index =
135 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 		rdev->pm.requested_clock_mode_index =
137 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
138 	}
139 }
140 
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
142 {
143 	struct radeon_bo *bo, *n;
144 
145 	if (list_empty(&rdev->gem.objects))
146 		return;
147 
148 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 			ttm_bo_unmap_virtual(&bo->tbo);
151 	}
152 }
153 
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
155 {
156 	if (rdev->pm.active_crtcs) {
157 		rdev->pm.vblank_sync = false;
158 		wait_event_timeout(
159 			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
161 	}
162 }
163 
164 static void radeon_set_power_state(struct radeon_device *rdev)
165 {
166 	u32 sclk, mclk;
167 	bool misc_after = false;
168 
169 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
171 		return;
172 
173 	if (radeon_gui_idle(rdev)) {
174 		sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 			clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 		if (sclk > rdev->pm.default_sclk)
177 			sclk = rdev->pm.default_sclk;
178 
179 		/* starting with BTC, there is one state that is used for both
180 		 * MH and SH.  Difference is that we always use the high clock index for
181 		 * mclk and vddci.
182 		 */
183 		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 		    (rdev->family >= CHIP_BARTS) &&
185 		    rdev->pm.active_crtc_count &&
186 		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
190 		else
191 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 				clock_info[rdev->pm.requested_clock_mode_index].mclk;
193 
194 		if (mclk > rdev->pm.default_mclk)
195 			mclk = rdev->pm.default_mclk;
196 
197 		/* upvolt before raising clocks, downvolt after lowering clocks */
198 		if (sclk < rdev->pm.current_sclk)
199 			misc_after = true;
200 
201 		radeon_sync_with_vblank(rdev);
202 
203 		if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 			if (!radeon_pm_in_vbl(rdev))
205 				return;
206 		}
207 
208 		radeon_pm_prepare(rdev);
209 
210 		if (!misc_after)
211 			/* voltage, pcie lanes, etc.*/
212 			radeon_pm_misc(rdev);
213 
214 		/* set engine clock */
215 		if (sclk != rdev->pm.current_sclk) {
216 			radeon_pm_debug_check_in_vbl(rdev, false);
217 			radeon_set_engine_clock(rdev, sclk);
218 			radeon_pm_debug_check_in_vbl(rdev, true);
219 			rdev->pm.current_sclk = sclk;
220 			DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
221 		}
222 
223 		/* set memory clock */
224 		if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 			radeon_pm_debug_check_in_vbl(rdev, false);
226 			radeon_set_memory_clock(rdev, mclk);
227 			radeon_pm_debug_check_in_vbl(rdev, true);
228 			rdev->pm.current_mclk = mclk;
229 			DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
230 		}
231 
232 		if (misc_after)
233 			/* voltage, pcie lanes, etc.*/
234 			radeon_pm_misc(rdev);
235 
236 		radeon_pm_finish(rdev);
237 
238 		rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 		rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 	} else
241 		DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
242 }
243 
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
245 {
246 	int i, r;
247 
248 	/* no need to take locks, etc. if nothing's going to change */
249 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 		return;
252 
253 	mutex_lock(&rdev->ddev->struct_mutex);
254 	down_write(&rdev->pm.mclk_lock);
255 	mutex_lock(&rdev->ring_lock);
256 
257 	/* wait for the rings to drain */
258 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 		struct radeon_ring *ring = &rdev->ring[i];
260 		if (!ring->ready) {
261 			continue;
262 		}
263 		r = radeon_fence_wait_empty(rdev, i);
264 		if (r) {
265 			/* needs a GPU reset dont reset here */
266 			mutex_unlock(&rdev->ring_lock);
267 			up_write(&rdev->pm.mclk_lock);
268 			mutex_unlock(&rdev->ddev->struct_mutex);
269 			return;
270 		}
271 	}
272 
273 	radeon_unmap_vram_bos(rdev);
274 
275 	if (rdev->irq.installed) {
276 		for (i = 0; i < rdev->num_crtc; i++) {
277 			if (rdev->pm.active_crtcs & (1 << i)) {
278 				rdev->pm.req_vblank |= (1 << i);
279 				drm_vblank_get(rdev->ddev, i);
280 			}
281 		}
282 	}
283 
284 	radeon_set_power_state(rdev);
285 
286 	if (rdev->irq.installed) {
287 		for (i = 0; i < rdev->num_crtc; i++) {
288 			if (rdev->pm.req_vblank & (1 << i)) {
289 				rdev->pm.req_vblank &= ~(1 << i);
290 				drm_vblank_put(rdev->ddev, i);
291 			}
292 		}
293 	}
294 
295 	/* update display watermarks based on new power state */
296 	radeon_update_bandwidth_info(rdev);
297 	if (rdev->pm.active_crtc_count)
298 		radeon_bandwidth_update(rdev);
299 
300 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
301 
302 	mutex_unlock(&rdev->ring_lock);
303 	up_write(&rdev->pm.mclk_lock);
304 	mutex_unlock(&rdev->ddev->struct_mutex);
305 }
306 
307 static void radeon_pm_print_states(struct radeon_device *rdev)
308 {
309 	int i, j;
310 	struct radeon_power_state *power_state;
311 	struct radeon_pm_clock_info *clock_info;
312 
313 	DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 	for (i = 0; i < rdev->pm.num_power_states; i++) {
315 		power_state = &rdev->pm.power_state[i];
316 		DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 			radeon_pm_state_type_name[power_state->type]);
318 		if (i == rdev->pm.default_power_state_index)
319 			DRM_DEBUG_DRIVER("\tDefault");
320 		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 			DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 		if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 			DRM_DEBUG_DRIVER("\tSingle display only\n");
324 		DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 		for (j = 0; j < power_state->num_clock_modes; j++) {
326 			clock_info = &(power_state->clock_info[j]);
327 			if (rdev->flags & RADEON_IS_IGP)
328 				DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 						 j,
330 						 clock_info->sclk * 10);
331 			else
332 				DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 						 j,
334 						 clock_info->sclk * 10,
335 						 clock_info->mclk * 10,
336 						 clock_info->voltage.voltage);
337 		}
338 	}
339 }
340 
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 				     struct device_attribute *attr,
343 				     char *buf)
344 {
345 	struct drm_device *ddev = dev_get_drvdata(dev);
346 	struct radeon_device *rdev = ddev->dev_private;
347 	int cp = rdev->pm.profile;
348 
349 	return snprintf(buf, PAGE_SIZE, "%s\n",
350 			(cp == PM_PROFILE_AUTO) ? "auto" :
351 			(cp == PM_PROFILE_LOW) ? "low" :
352 			(cp == PM_PROFILE_MID) ? "mid" :
353 			(cp == PM_PROFILE_HIGH) ? "high" : "default");
354 }
355 
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 				     struct device_attribute *attr,
358 				     const char *buf,
359 				     size_t count)
360 {
361 	struct drm_device *ddev = dev_get_drvdata(dev);
362 	struct radeon_device *rdev = ddev->dev_private;
363 
364 	mutex_lock(&rdev->pm.mutex);
365 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 		if (strncmp("default", buf, strlen("default")) == 0)
367 			rdev->pm.profile = PM_PROFILE_DEFAULT;
368 		else if (strncmp("auto", buf, strlen("auto")) == 0)
369 			rdev->pm.profile = PM_PROFILE_AUTO;
370 		else if (strncmp("low", buf, strlen("low")) == 0)
371 			rdev->pm.profile = PM_PROFILE_LOW;
372 		else if (strncmp("mid", buf, strlen("mid")) == 0)
373 			rdev->pm.profile = PM_PROFILE_MID;
374 		else if (strncmp("high", buf, strlen("high")) == 0)
375 			rdev->pm.profile = PM_PROFILE_HIGH;
376 		else {
377 			count = -EINVAL;
378 			goto fail;
379 		}
380 		radeon_pm_update_profile(rdev);
381 		radeon_pm_set_clocks(rdev);
382 	} else
383 		count = -EINVAL;
384 
385 fail:
386 	mutex_unlock(&rdev->pm.mutex);
387 
388 	return count;
389 }
390 
391 static ssize_t radeon_get_pm_method(struct device *dev,
392 				    struct device_attribute *attr,
393 				    char *buf)
394 {
395 	struct drm_device *ddev = dev_get_drvdata(dev);
396 	struct radeon_device *rdev = ddev->dev_private;
397 	int pm = rdev->pm.pm_method;
398 
399 	return snprintf(buf, PAGE_SIZE, "%s\n",
400 			(pm == PM_METHOD_DYNPM) ? "dynpm" :
401 			(pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
402 }
403 
404 static ssize_t radeon_set_pm_method(struct device *dev,
405 				    struct device_attribute *attr,
406 				    const char *buf,
407 				    size_t count)
408 {
409 	struct drm_device *ddev = dev_get_drvdata(dev);
410 	struct radeon_device *rdev = ddev->dev_private;
411 
412 	/* we don't support the legacy modes with dpm */
413 	if (rdev->pm.pm_method == PM_METHOD_DPM) {
414 		count = -EINVAL;
415 		goto fail;
416 	}
417 
418 	if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
419 		mutex_lock(&rdev->pm.mutex);
420 		rdev->pm.pm_method = PM_METHOD_DYNPM;
421 		rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
422 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
423 		mutex_unlock(&rdev->pm.mutex);
424 	} else if (strncmp("profile", buf, strlen("profile")) == 0) {
425 		mutex_lock(&rdev->pm.mutex);
426 		/* disable dynpm */
427 		rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
428 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
429 		rdev->pm.pm_method = PM_METHOD_PROFILE;
430 		mutex_unlock(&rdev->pm.mutex);
431 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
432 	} else {
433 		count = -EINVAL;
434 		goto fail;
435 	}
436 	radeon_pm_compute_clocks(rdev);
437 fail:
438 	return count;
439 }
440 
441 static ssize_t radeon_get_dpm_state(struct device *dev,
442 				    struct device_attribute *attr,
443 				    char *buf)
444 {
445 	struct drm_device *ddev = dev_get_drvdata(dev);
446 	struct radeon_device *rdev = ddev->dev_private;
447 	enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
448 
449 	return snprintf(buf, PAGE_SIZE, "%s\n",
450 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
451 			(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
452 }
453 
454 static ssize_t radeon_set_dpm_state(struct device *dev,
455 				    struct device_attribute *attr,
456 				    const char *buf,
457 				    size_t count)
458 {
459 	struct drm_device *ddev = dev_get_drvdata(dev);
460 	struct radeon_device *rdev = ddev->dev_private;
461 
462 	mutex_lock(&rdev->pm.mutex);
463 	if (strncmp("battery", buf, strlen("battery")) == 0)
464 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
465 	else if (strncmp("balanced", buf, strlen("balanced")) == 0)
466 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
467 	else if (strncmp("performance", buf, strlen("performance")) == 0)
468 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
469 	else {
470 		mutex_unlock(&rdev->pm.mutex);
471 		count = -EINVAL;
472 		goto fail;
473 	}
474 	mutex_unlock(&rdev->pm.mutex);
475 	radeon_pm_compute_clocks(rdev);
476 fail:
477 	return count;
478 }
479 
480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
481 						       struct device_attribute *attr,
482 						       char *buf)
483 {
484 	struct drm_device *ddev = dev_get_drvdata(dev);
485 	struct radeon_device *rdev = ddev->dev_private;
486 	enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
487 
488 	return snprintf(buf, PAGE_SIZE, "%s\n",
489 			(level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
490 			(level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
491 }
492 
493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
494 						       struct device_attribute *attr,
495 						       const char *buf,
496 						       size_t count)
497 {
498 	struct drm_device *ddev = dev_get_drvdata(dev);
499 	struct radeon_device *rdev = ddev->dev_private;
500 	enum radeon_dpm_forced_level level;
501 	int ret = 0;
502 
503 	mutex_lock(&rdev->pm.mutex);
504 	if (strncmp("low", buf, strlen("low")) == 0) {
505 		level = RADEON_DPM_FORCED_LEVEL_LOW;
506 	} else if (strncmp("high", buf, strlen("high")) == 0) {
507 		level = RADEON_DPM_FORCED_LEVEL_HIGH;
508 	} else if (strncmp("auto", buf, strlen("auto")) == 0) {
509 		level = RADEON_DPM_FORCED_LEVEL_AUTO;
510 	} else {
511 		count = -EINVAL;
512 		goto fail;
513 	}
514 	if (rdev->asic->dpm.force_performance_level) {
515 		if (rdev->pm.dpm.thermal_active) {
516 			count = -EINVAL;
517 			goto fail;
518 		}
519 		ret = radeon_dpm_force_performance_level(rdev, level);
520 		if (ret)
521 			count = -EINVAL;
522 	}
523 fail:
524 	mutex_unlock(&rdev->pm.mutex);
525 
526 	return count;
527 }
528 
529 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
530 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
531 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
532 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
533 		   radeon_get_dpm_forced_performance_level,
534 		   radeon_set_dpm_forced_performance_level);
535 
536 static ssize_t radeon_hwmon_show_temp(struct device *dev,
537 				      struct device_attribute *attr,
538 				      char *buf)
539 {
540 	struct radeon_device *rdev = dev_get_drvdata(dev);
541 	int temp;
542 
543 	if (rdev->asic->pm.get_temperature)
544 		temp = radeon_get_temperature(rdev);
545 	else
546 		temp = 0;
547 
548 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
549 }
550 
551 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
552 					     struct device_attribute *attr,
553 					     char *buf)
554 {
555 	struct radeon_device *rdev = dev_get_drvdata(dev);
556 	int hyst = to_sensor_dev_attr(attr)->index;
557 	int temp;
558 
559 	if (hyst)
560 		temp = rdev->pm.dpm.thermal.min_temp;
561 	else
562 		temp = rdev->pm.dpm.thermal.max_temp;
563 
564 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
565 }
566 
567 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
568 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
569 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
570 
571 static struct attribute *hwmon_attributes[] = {
572 	&sensor_dev_attr_temp1_input.dev_attr.attr,
573 	&sensor_dev_attr_temp1_crit.dev_attr.attr,
574 	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
575 	NULL
576 };
577 
578 static umode_t hwmon_attributes_visible(struct kobject *kobj,
579 					struct attribute *attr, int index)
580 {
581 	struct device *dev = container_of(kobj, struct device, kobj);
582 	struct radeon_device *rdev = dev_get_drvdata(dev);
583 
584 	/* Skip limit attributes if DPM is not enabled */
585 	if (rdev->pm.pm_method != PM_METHOD_DPM &&
586 	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
587 	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
588 		return 0;
589 
590 	return attr->mode;
591 }
592 
593 static const struct attribute_group hwmon_attrgroup = {
594 	.attrs = hwmon_attributes,
595 	.is_visible = hwmon_attributes_visible,
596 };
597 
598 static const struct attribute_group *hwmon_groups[] = {
599 	&hwmon_attrgroup,
600 	NULL
601 };
602 
603 static int radeon_hwmon_init(struct radeon_device *rdev)
604 {
605 	int err = 0;
606 	struct device *hwmon_dev;
607 
608 	switch (rdev->pm.int_thermal_type) {
609 	case THERMAL_TYPE_RV6XX:
610 	case THERMAL_TYPE_RV770:
611 	case THERMAL_TYPE_EVERGREEN:
612 	case THERMAL_TYPE_NI:
613 	case THERMAL_TYPE_SUMO:
614 	case THERMAL_TYPE_SI:
615 	case THERMAL_TYPE_CI:
616 	case THERMAL_TYPE_KV:
617 		if (rdev->asic->pm.get_temperature == NULL)
618 			return err;
619 		hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
620 							      "radeon", rdev,
621 							      hwmon_groups);
622 		if (IS_ERR(hwmon_dev)) {
623 			err = PTR_ERR(hwmon_dev);
624 			dev_err(rdev->dev,
625 				"Unable to register hwmon device: %d\n", err);
626 		}
627 		break;
628 	default:
629 		break;
630 	}
631 
632 	return err;
633 }
634 
635 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
636 {
637 	struct radeon_device *rdev =
638 		container_of(work, struct radeon_device,
639 			     pm.dpm.thermal.work);
640 	/* switch to the thermal state */
641 	enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
642 
643 	if (!rdev->pm.dpm_enabled)
644 		return;
645 
646 	if (rdev->asic->pm.get_temperature) {
647 		int temp = radeon_get_temperature(rdev);
648 
649 		if (temp < rdev->pm.dpm.thermal.min_temp)
650 			/* switch back the user state */
651 			dpm_state = rdev->pm.dpm.user_state;
652 	} else {
653 		if (rdev->pm.dpm.thermal.high_to_low)
654 			/* switch back the user state */
655 			dpm_state = rdev->pm.dpm.user_state;
656 	}
657 	mutex_lock(&rdev->pm.mutex);
658 	if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
659 		rdev->pm.dpm.thermal_active = true;
660 	else
661 		rdev->pm.dpm.thermal_active = false;
662 	rdev->pm.dpm.state = dpm_state;
663 	mutex_unlock(&rdev->pm.mutex);
664 
665 	radeon_pm_compute_clocks(rdev);
666 }
667 
668 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
669 						     enum radeon_pm_state_type dpm_state)
670 {
671 	int i;
672 	struct radeon_ps *ps;
673 	u32 ui_class;
674 	bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
675 		true : false;
676 
677 	/* check if the vblank period is too short to adjust the mclk */
678 	if (single_display && rdev->asic->dpm.vblank_too_short) {
679 		if (radeon_dpm_vblank_too_short(rdev))
680 			single_display = false;
681 	}
682 
683 	/* certain older asics have a separare 3D performance state,
684 	 * so try that first if the user selected performance
685 	 */
686 	if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
687 		dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
688 	/* balanced states don't exist at the moment */
689 	if (dpm_state == POWER_STATE_TYPE_BALANCED)
690 		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
691 
692 restart_search:
693 	/* Pick the best power state based on current conditions */
694 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
695 		ps = &rdev->pm.dpm.ps[i];
696 		ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
697 		switch (dpm_state) {
698 		/* user states */
699 		case POWER_STATE_TYPE_BATTERY:
700 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
701 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
702 					if (single_display)
703 						return ps;
704 				} else
705 					return ps;
706 			}
707 			break;
708 		case POWER_STATE_TYPE_BALANCED:
709 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
710 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
711 					if (single_display)
712 						return ps;
713 				} else
714 					return ps;
715 			}
716 			break;
717 		case POWER_STATE_TYPE_PERFORMANCE:
718 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
719 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
720 					if (single_display)
721 						return ps;
722 				} else
723 					return ps;
724 			}
725 			break;
726 		/* internal states */
727 		case POWER_STATE_TYPE_INTERNAL_UVD:
728 			if (rdev->pm.dpm.uvd_ps)
729 				return rdev->pm.dpm.uvd_ps;
730 			else
731 				break;
732 		case POWER_STATE_TYPE_INTERNAL_UVD_SD:
733 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
734 				return ps;
735 			break;
736 		case POWER_STATE_TYPE_INTERNAL_UVD_HD:
737 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
738 				return ps;
739 			break;
740 		case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
741 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
742 				return ps;
743 			break;
744 		case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
745 			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
746 				return ps;
747 			break;
748 		case POWER_STATE_TYPE_INTERNAL_BOOT:
749 			return rdev->pm.dpm.boot_ps;
750 		case POWER_STATE_TYPE_INTERNAL_THERMAL:
751 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
752 				return ps;
753 			break;
754 		case POWER_STATE_TYPE_INTERNAL_ACPI:
755 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
756 				return ps;
757 			break;
758 		case POWER_STATE_TYPE_INTERNAL_ULV:
759 			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
760 				return ps;
761 			break;
762 		case POWER_STATE_TYPE_INTERNAL_3DPERF:
763 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
764 				return ps;
765 			break;
766 		default:
767 			break;
768 		}
769 	}
770 	/* use a fallback state if we didn't match */
771 	switch (dpm_state) {
772 	case POWER_STATE_TYPE_INTERNAL_UVD_SD:
773 		dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
774 		goto restart_search;
775 	case POWER_STATE_TYPE_INTERNAL_UVD_HD:
776 	case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
777 	case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
778 		if (rdev->pm.dpm.uvd_ps) {
779 			return rdev->pm.dpm.uvd_ps;
780 		} else {
781 			dpm_state = POWER_STATE_TYPE_PERFORMANCE;
782 			goto restart_search;
783 		}
784 	case POWER_STATE_TYPE_INTERNAL_THERMAL:
785 		dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
786 		goto restart_search;
787 	case POWER_STATE_TYPE_INTERNAL_ACPI:
788 		dpm_state = POWER_STATE_TYPE_BATTERY;
789 		goto restart_search;
790 	case POWER_STATE_TYPE_BATTERY:
791 	case POWER_STATE_TYPE_BALANCED:
792 	case POWER_STATE_TYPE_INTERNAL_3DPERF:
793 		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
794 		goto restart_search;
795 	default:
796 		break;
797 	}
798 
799 	return NULL;
800 }
801 
802 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
803 {
804 	int i;
805 	struct radeon_ps *ps;
806 	enum radeon_pm_state_type dpm_state;
807 	int ret;
808 
809 	/* if dpm init failed */
810 	if (!rdev->pm.dpm_enabled)
811 		return;
812 
813 	if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
814 		/* add other state override checks here */
815 		if ((!rdev->pm.dpm.thermal_active) &&
816 		    (!rdev->pm.dpm.uvd_active))
817 			rdev->pm.dpm.state = rdev->pm.dpm.user_state;
818 	}
819 	dpm_state = rdev->pm.dpm.state;
820 
821 	ps = radeon_dpm_pick_power_state(rdev, dpm_state);
822 	if (ps)
823 		rdev->pm.dpm.requested_ps = ps;
824 	else
825 		return;
826 
827 	/* no need to reprogram if nothing changed unless we are on BTC+ */
828 	if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
829 		/* vce just modifies an existing state so force a change */
830 		if (ps->vce_active != rdev->pm.dpm.vce_active)
831 			goto force;
832 		if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
833 			/* for pre-BTC and APUs if the num crtcs changed but state is the same,
834 			 * all we need to do is update the display configuration.
835 			 */
836 			if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
837 				/* update display watermarks based on new power state */
838 				radeon_bandwidth_update(rdev);
839 				/* update displays */
840 				radeon_dpm_display_configuration_changed(rdev);
841 				rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
842 				rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
843 			}
844 			return;
845 		} else {
846 			/* for BTC+ if the num crtcs hasn't changed and state is the same,
847 			 * nothing to do, if the num crtcs is > 1 and state is the same,
848 			 * update display configuration.
849 			 */
850 			if (rdev->pm.dpm.new_active_crtcs ==
851 			    rdev->pm.dpm.current_active_crtcs) {
852 				return;
853 			} else {
854 				if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
855 				    (rdev->pm.dpm.new_active_crtc_count > 1)) {
856 					/* update display watermarks based on new power state */
857 					radeon_bandwidth_update(rdev);
858 					/* update displays */
859 					radeon_dpm_display_configuration_changed(rdev);
860 					rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
861 					rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
862 					return;
863 				}
864 			}
865 		}
866 	}
867 
868 force:
869 	if (radeon_dpm == 1) {
870 		printk("switching from power state:\n");
871 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
872 		printk("switching to power state:\n");
873 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
874 	}
875 
876 	mutex_lock(&rdev->ddev->struct_mutex);
877 	down_write(&rdev->pm.mclk_lock);
878 	mutex_lock(&rdev->ring_lock);
879 
880 	/* update whether vce is active */
881 	ps->vce_active = rdev->pm.dpm.vce_active;
882 
883 	ret = radeon_dpm_pre_set_power_state(rdev);
884 	if (ret)
885 		goto done;
886 
887 	/* update display watermarks based on new power state */
888 	radeon_bandwidth_update(rdev);
889 	/* update displays */
890 	radeon_dpm_display_configuration_changed(rdev);
891 
892 	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
893 	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
894 
895 	/* wait for the rings to drain */
896 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
897 		struct radeon_ring *ring = &rdev->ring[i];
898 		if (ring->ready)
899 			radeon_fence_wait_empty(rdev, i);
900 	}
901 
902 	/* program the new power state */
903 	radeon_dpm_set_power_state(rdev);
904 
905 	/* update current power state */
906 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
907 
908 	radeon_dpm_post_set_power_state(rdev);
909 
910 	if (rdev->asic->dpm.force_performance_level) {
911 		if (rdev->pm.dpm.thermal_active) {
912 			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
913 			/* force low perf level for thermal */
914 			radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
915 			/* save the user's level */
916 			rdev->pm.dpm.forced_level = level;
917 		} else {
918 			/* otherwise, user selected level */
919 			radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
920 		}
921 	}
922 
923 done:
924 	mutex_unlock(&rdev->ring_lock);
925 	up_write(&rdev->pm.mclk_lock);
926 	mutex_unlock(&rdev->ddev->struct_mutex);
927 }
928 
929 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
930 {
931 	enum radeon_pm_state_type dpm_state;
932 
933 	if (rdev->asic->dpm.powergate_uvd) {
934 		mutex_lock(&rdev->pm.mutex);
935 		/* don't powergate anything if we
936 		   have active but pause streams */
937 		enable |= rdev->pm.dpm.sd > 0;
938 		enable |= rdev->pm.dpm.hd > 0;
939 		/* enable/disable UVD */
940 		radeon_dpm_powergate_uvd(rdev, !enable);
941 		mutex_unlock(&rdev->pm.mutex);
942 	} else {
943 		if (enable) {
944 			mutex_lock(&rdev->pm.mutex);
945 			rdev->pm.dpm.uvd_active = true;
946 			if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
947 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
948 			else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
949 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
950 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
951 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
952 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
953 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
954 			else
955 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
956 			rdev->pm.dpm.state = dpm_state;
957 			mutex_unlock(&rdev->pm.mutex);
958 		} else {
959 			mutex_lock(&rdev->pm.mutex);
960 			rdev->pm.dpm.uvd_active = false;
961 			mutex_unlock(&rdev->pm.mutex);
962 		}
963 
964 		radeon_pm_compute_clocks(rdev);
965 	}
966 }
967 
968 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
969 {
970 	if (enable) {
971 		mutex_lock(&rdev->pm.mutex);
972 		rdev->pm.dpm.vce_active = true;
973 		/* XXX select vce level based on ring/task */
974 		rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
975 		mutex_unlock(&rdev->pm.mutex);
976 	} else {
977 		mutex_lock(&rdev->pm.mutex);
978 		rdev->pm.dpm.vce_active = false;
979 		mutex_unlock(&rdev->pm.mutex);
980 	}
981 
982 	radeon_pm_compute_clocks(rdev);
983 }
984 
985 static void radeon_pm_suspend_old(struct radeon_device *rdev)
986 {
987 	mutex_lock(&rdev->pm.mutex);
988 	if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
989 		if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
990 			rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
991 	}
992 	mutex_unlock(&rdev->pm.mutex);
993 
994 	cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
995 }
996 
997 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
998 {
999 	mutex_lock(&rdev->pm.mutex);
1000 	/* disable dpm */
1001 	radeon_dpm_disable(rdev);
1002 	/* reset the power state */
1003 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1004 	rdev->pm.dpm_enabled = false;
1005 	mutex_unlock(&rdev->pm.mutex);
1006 }
1007 
1008 void radeon_pm_suspend(struct radeon_device *rdev)
1009 {
1010 	if (rdev->pm.pm_method == PM_METHOD_DPM)
1011 		radeon_pm_suspend_dpm(rdev);
1012 	else
1013 		radeon_pm_suspend_old(rdev);
1014 }
1015 
1016 static void radeon_pm_resume_old(struct radeon_device *rdev)
1017 {
1018 	/* set up the default clocks if the MC ucode is loaded */
1019 	if ((rdev->family >= CHIP_BARTS) &&
1020 	    (rdev->family <= CHIP_CAYMAN) &&
1021 	    rdev->mc_fw) {
1022 		if (rdev->pm.default_vddc)
1023 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1024 						SET_VOLTAGE_TYPE_ASIC_VDDC);
1025 		if (rdev->pm.default_vddci)
1026 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1027 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
1028 		if (rdev->pm.default_sclk)
1029 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1030 		if (rdev->pm.default_mclk)
1031 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1032 	}
1033 	/* asic init will reset the default power state */
1034 	mutex_lock(&rdev->pm.mutex);
1035 	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1036 	rdev->pm.current_clock_mode_index = 0;
1037 	rdev->pm.current_sclk = rdev->pm.default_sclk;
1038 	rdev->pm.current_mclk = rdev->pm.default_mclk;
1039 	if (rdev->pm.power_state) {
1040 		rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1041 		rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1042 	}
1043 	if (rdev->pm.pm_method == PM_METHOD_DYNPM
1044 	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1045 		rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1046 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1047 				      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1048 	}
1049 	mutex_unlock(&rdev->pm.mutex);
1050 	radeon_pm_compute_clocks(rdev);
1051 }
1052 
1053 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1054 {
1055 	int ret;
1056 
1057 	/* asic init will reset to the boot state */
1058 	mutex_lock(&rdev->pm.mutex);
1059 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1060 	radeon_dpm_setup_asic(rdev);
1061 	ret = radeon_dpm_enable(rdev);
1062 	mutex_unlock(&rdev->pm.mutex);
1063 	if (ret)
1064 		goto dpm_resume_fail;
1065 	rdev->pm.dpm_enabled = true;
1066 	radeon_pm_compute_clocks(rdev);
1067 	return;
1068 
1069 dpm_resume_fail:
1070 	DRM_ERROR("radeon: dpm resume failed\n");
1071 	if ((rdev->family >= CHIP_BARTS) &&
1072 	    (rdev->family <= CHIP_CAYMAN) &&
1073 	    rdev->mc_fw) {
1074 		if (rdev->pm.default_vddc)
1075 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1076 						SET_VOLTAGE_TYPE_ASIC_VDDC);
1077 		if (rdev->pm.default_vddci)
1078 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1079 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
1080 		if (rdev->pm.default_sclk)
1081 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1082 		if (rdev->pm.default_mclk)
1083 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1084 	}
1085 }
1086 
1087 void radeon_pm_resume(struct radeon_device *rdev)
1088 {
1089 	if (rdev->pm.pm_method == PM_METHOD_DPM)
1090 		radeon_pm_resume_dpm(rdev);
1091 	else
1092 		radeon_pm_resume_old(rdev);
1093 }
1094 
1095 static int radeon_pm_init_old(struct radeon_device *rdev)
1096 {
1097 	int ret;
1098 
1099 	rdev->pm.profile = PM_PROFILE_DEFAULT;
1100 	rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1101 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1102 	rdev->pm.dynpm_can_upclock = true;
1103 	rdev->pm.dynpm_can_downclock = true;
1104 	rdev->pm.default_sclk = rdev->clock.default_sclk;
1105 	rdev->pm.default_mclk = rdev->clock.default_mclk;
1106 	rdev->pm.current_sclk = rdev->clock.default_sclk;
1107 	rdev->pm.current_mclk = rdev->clock.default_mclk;
1108 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1109 
1110 	if (rdev->bios) {
1111 		if (rdev->is_atom_bios)
1112 			radeon_atombios_get_power_modes(rdev);
1113 		else
1114 			radeon_combios_get_power_modes(rdev);
1115 		radeon_pm_print_states(rdev);
1116 		radeon_pm_init_profile(rdev);
1117 		/* set up the default clocks if the MC ucode is loaded */
1118 		if ((rdev->family >= CHIP_BARTS) &&
1119 		    (rdev->family <= CHIP_CAYMAN) &&
1120 		    rdev->mc_fw) {
1121 			if (rdev->pm.default_vddc)
1122 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1123 							SET_VOLTAGE_TYPE_ASIC_VDDC);
1124 			if (rdev->pm.default_vddci)
1125 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1126 							SET_VOLTAGE_TYPE_ASIC_VDDCI);
1127 			if (rdev->pm.default_sclk)
1128 				radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1129 			if (rdev->pm.default_mclk)
1130 				radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1131 		}
1132 	}
1133 
1134 	/* set up the internal thermal sensor if applicable */
1135 	ret = radeon_hwmon_init(rdev);
1136 	if (ret)
1137 		return ret;
1138 
1139 	INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1140 
1141 	if (rdev->pm.num_power_states > 1) {
1142 		/* where's the best place to put these? */
1143 		ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1144 		if (ret)
1145 			DRM_ERROR("failed to create device file for power profile\n");
1146 		ret = device_create_file(rdev->dev, &dev_attr_power_method);
1147 		if (ret)
1148 			DRM_ERROR("failed to create device file for power method\n");
1149 
1150 		if (radeon_debugfs_pm_init(rdev)) {
1151 			DRM_ERROR("Failed to register debugfs file for PM!\n");
1152 		}
1153 
1154 		DRM_INFO("radeon: power management initialized\n");
1155 	}
1156 
1157 	return 0;
1158 }
1159 
1160 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1161 {
1162 	int i;
1163 
1164 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1165 		printk("== power state %d ==\n", i);
1166 		radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1167 	}
1168 }
1169 
1170 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1171 {
1172 	int ret;
1173 
1174 	/* default to balanced state */
1175 	rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1176 	rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1177 	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1178 	rdev->pm.default_sclk = rdev->clock.default_sclk;
1179 	rdev->pm.default_mclk = rdev->clock.default_mclk;
1180 	rdev->pm.current_sclk = rdev->clock.default_sclk;
1181 	rdev->pm.current_mclk = rdev->clock.default_mclk;
1182 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1183 
1184 	if (rdev->bios && rdev->is_atom_bios)
1185 		radeon_atombios_get_power_modes(rdev);
1186 	else
1187 		return -EINVAL;
1188 
1189 	/* set up the internal thermal sensor if applicable */
1190 	ret = radeon_hwmon_init(rdev);
1191 	if (ret)
1192 		return ret;
1193 
1194 	INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1195 	mutex_lock(&rdev->pm.mutex);
1196 	radeon_dpm_init(rdev);
1197 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1198 	if (radeon_dpm == 1)
1199 		radeon_dpm_print_power_states(rdev);
1200 	radeon_dpm_setup_asic(rdev);
1201 	ret = radeon_dpm_enable(rdev);
1202 	mutex_unlock(&rdev->pm.mutex);
1203 	if (ret)
1204 		goto dpm_failed;
1205 	rdev->pm.dpm_enabled = true;
1206 
1207 	ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1208 	if (ret)
1209 		DRM_ERROR("failed to create device file for dpm state\n");
1210 	ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1211 	if (ret)
1212 		DRM_ERROR("failed to create device file for dpm state\n");
1213 	/* XXX: these are noops for dpm but are here for backwards compat */
1214 	ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1215 	if (ret)
1216 		DRM_ERROR("failed to create device file for power profile\n");
1217 	ret = device_create_file(rdev->dev, &dev_attr_power_method);
1218 	if (ret)
1219 		DRM_ERROR("failed to create device file for power method\n");
1220 
1221 	if (radeon_debugfs_pm_init(rdev)) {
1222 		DRM_ERROR("Failed to register debugfs file for dpm!\n");
1223 	}
1224 
1225 	DRM_INFO("radeon: dpm initialized\n");
1226 
1227 	return 0;
1228 
1229 dpm_failed:
1230 	rdev->pm.dpm_enabled = false;
1231 	if ((rdev->family >= CHIP_BARTS) &&
1232 	    (rdev->family <= CHIP_CAYMAN) &&
1233 	    rdev->mc_fw) {
1234 		if (rdev->pm.default_vddc)
1235 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1236 						SET_VOLTAGE_TYPE_ASIC_VDDC);
1237 		if (rdev->pm.default_vddci)
1238 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1239 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
1240 		if (rdev->pm.default_sclk)
1241 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1242 		if (rdev->pm.default_mclk)
1243 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1244 	}
1245 	DRM_ERROR("radeon: dpm initialization failed\n");
1246 	return ret;
1247 }
1248 
1249 int radeon_pm_init(struct radeon_device *rdev)
1250 {
1251 	/* enable dpm on rv6xx+ */
1252 	switch (rdev->family) {
1253 	case CHIP_RV610:
1254 	case CHIP_RV630:
1255 	case CHIP_RV620:
1256 	case CHIP_RV635:
1257 	case CHIP_RV670:
1258 	case CHIP_RS780:
1259 	case CHIP_RS880:
1260 	case CHIP_BARTS:
1261 	case CHIP_TURKS:
1262 	case CHIP_CAICOS:
1263 	case CHIP_CAYMAN:
1264 		/* DPM requires the RLC, RV770+ dGPU requires SMC */
1265 		if (!rdev->rlc_fw)
1266 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1267 		else if ((rdev->family >= CHIP_RV770) &&
1268 			 (!(rdev->flags & RADEON_IS_IGP)) &&
1269 			 (!rdev->smc_fw))
1270 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1271 		else if (radeon_dpm == 1)
1272 			rdev->pm.pm_method = PM_METHOD_DPM;
1273 		else
1274 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1275 		break;
1276 	case CHIP_RV770:
1277 	case CHIP_RV730:
1278 	case CHIP_RV710:
1279 	case CHIP_RV740:
1280 	case CHIP_CEDAR:
1281 	case CHIP_REDWOOD:
1282 	case CHIP_JUNIPER:
1283 	case CHIP_CYPRESS:
1284 	case CHIP_HEMLOCK:
1285 	case CHIP_PALM:
1286 	case CHIP_SUMO:
1287 	case CHIP_SUMO2:
1288 	case CHIP_ARUBA:
1289 	case CHIP_TAHITI:
1290 	case CHIP_PITCAIRN:
1291 	case CHIP_VERDE:
1292 	case CHIP_OLAND:
1293 	case CHIP_HAINAN:
1294 	case CHIP_BONAIRE:
1295 	case CHIP_KABINI:
1296 	case CHIP_KAVERI:
1297 	case CHIP_HAWAII:
1298 		/* DPM requires the RLC, RV770+ dGPU requires SMC */
1299 		if (!rdev->rlc_fw)
1300 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1301 		else if ((rdev->family >= CHIP_RV770) &&
1302 			 (!(rdev->flags & RADEON_IS_IGP)) &&
1303 			 (!rdev->smc_fw))
1304 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1305 		else if (radeon_dpm == 0)
1306 			rdev->pm.pm_method = PM_METHOD_PROFILE;
1307 		else
1308 			rdev->pm.pm_method = PM_METHOD_DPM;
1309 		break;
1310 	default:
1311 		/* default to profile method */
1312 		rdev->pm.pm_method = PM_METHOD_PROFILE;
1313 		break;
1314 	}
1315 
1316 	if (rdev->pm.pm_method == PM_METHOD_DPM)
1317 		return radeon_pm_init_dpm(rdev);
1318 	else
1319 		return radeon_pm_init_old(rdev);
1320 }
1321 
1322 int radeon_pm_late_init(struct radeon_device *rdev)
1323 {
1324 	int ret = 0;
1325 
1326 	if (rdev->pm.pm_method == PM_METHOD_DPM) {
1327 		mutex_lock(&rdev->pm.mutex);
1328 		ret = radeon_dpm_late_enable(rdev);
1329 		mutex_unlock(&rdev->pm.mutex);
1330 	}
1331 	return ret;
1332 }
1333 
1334 static void radeon_pm_fini_old(struct radeon_device *rdev)
1335 {
1336 	if (rdev->pm.num_power_states > 1) {
1337 		mutex_lock(&rdev->pm.mutex);
1338 		if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1339 			rdev->pm.profile = PM_PROFILE_DEFAULT;
1340 			radeon_pm_update_profile(rdev);
1341 			radeon_pm_set_clocks(rdev);
1342 		} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1343 			/* reset default clocks */
1344 			rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1345 			rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1346 			radeon_pm_set_clocks(rdev);
1347 		}
1348 		mutex_unlock(&rdev->pm.mutex);
1349 
1350 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1351 
1352 		device_remove_file(rdev->dev, &dev_attr_power_profile);
1353 		device_remove_file(rdev->dev, &dev_attr_power_method);
1354 	}
1355 
1356 	if (rdev->pm.power_state)
1357 		kfree(rdev->pm.power_state);
1358 }
1359 
1360 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1361 {
1362 	if (rdev->pm.num_power_states > 1) {
1363 		mutex_lock(&rdev->pm.mutex);
1364 		radeon_dpm_disable(rdev);
1365 		mutex_unlock(&rdev->pm.mutex);
1366 
1367 		device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1368 		device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1369 		/* XXX backwards compat */
1370 		device_remove_file(rdev->dev, &dev_attr_power_profile);
1371 		device_remove_file(rdev->dev, &dev_attr_power_method);
1372 	}
1373 	radeon_dpm_fini(rdev);
1374 
1375 	if (rdev->pm.power_state)
1376 		kfree(rdev->pm.power_state);
1377 }
1378 
1379 void radeon_pm_fini(struct radeon_device *rdev)
1380 {
1381 	if (rdev->pm.pm_method == PM_METHOD_DPM)
1382 		radeon_pm_fini_dpm(rdev);
1383 	else
1384 		radeon_pm_fini_old(rdev);
1385 }
1386 
1387 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1388 {
1389 	struct drm_device *ddev = rdev->ddev;
1390 	struct drm_crtc *crtc;
1391 	struct radeon_crtc *radeon_crtc;
1392 
1393 	if (rdev->pm.num_power_states < 2)
1394 		return;
1395 
1396 	mutex_lock(&rdev->pm.mutex);
1397 
1398 	rdev->pm.active_crtcs = 0;
1399 	rdev->pm.active_crtc_count = 0;
1400 	list_for_each_entry(crtc,
1401 		&ddev->mode_config.crtc_list, head) {
1402 		radeon_crtc = to_radeon_crtc(crtc);
1403 		if (radeon_crtc->enabled) {
1404 			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1405 			rdev->pm.active_crtc_count++;
1406 		}
1407 	}
1408 
1409 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1410 		radeon_pm_update_profile(rdev);
1411 		radeon_pm_set_clocks(rdev);
1412 	} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1413 		if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1414 			if (rdev->pm.active_crtc_count > 1) {
1415 				if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1416 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1417 
1418 					rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1419 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1420 					radeon_pm_get_dynpm_state(rdev);
1421 					radeon_pm_set_clocks(rdev);
1422 
1423 					DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1424 				}
1425 			} else if (rdev->pm.active_crtc_count == 1) {
1426 				/* TODO: Increase clocks if needed for current mode */
1427 
1428 				if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1429 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1430 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1431 					radeon_pm_get_dynpm_state(rdev);
1432 					radeon_pm_set_clocks(rdev);
1433 
1434 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1435 							      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1436 				} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1437 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1438 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1439 							      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1440 					DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1441 				}
1442 			} else { /* count == 0 */
1443 				if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1444 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1445 
1446 					rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1447 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1448 					radeon_pm_get_dynpm_state(rdev);
1449 					radeon_pm_set_clocks(rdev);
1450 				}
1451 			}
1452 		}
1453 	}
1454 
1455 	mutex_unlock(&rdev->pm.mutex);
1456 }
1457 
1458 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1459 {
1460 	struct drm_device *ddev = rdev->ddev;
1461 	struct drm_crtc *crtc;
1462 	struct radeon_crtc *radeon_crtc;
1463 
1464 	if (!rdev->pm.dpm_enabled)
1465 		return;
1466 
1467 	mutex_lock(&rdev->pm.mutex);
1468 
1469 	/* update active crtc counts */
1470 	rdev->pm.dpm.new_active_crtcs = 0;
1471 	rdev->pm.dpm.new_active_crtc_count = 0;
1472 	list_for_each_entry(crtc,
1473 		&ddev->mode_config.crtc_list, head) {
1474 		radeon_crtc = to_radeon_crtc(crtc);
1475 		if (crtc->enabled) {
1476 			rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1477 			rdev->pm.dpm.new_active_crtc_count++;
1478 		}
1479 	}
1480 
1481 	/* update battery/ac status */
1482 	if (power_supply_is_system_supplied() > 0)
1483 		rdev->pm.dpm.ac_power = true;
1484 	else
1485 		rdev->pm.dpm.ac_power = false;
1486 
1487 	radeon_dpm_change_power_state_locked(rdev);
1488 
1489 	mutex_unlock(&rdev->pm.mutex);
1490 
1491 }
1492 
1493 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1494 {
1495 	if (rdev->pm.pm_method == PM_METHOD_DPM)
1496 		radeon_pm_compute_clocks_dpm(rdev);
1497 	else
1498 		radeon_pm_compute_clocks_old(rdev);
1499 }
1500 
1501 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1502 {
1503 	int  crtc, vpos, hpos, vbl_status;
1504 	bool in_vbl = true;
1505 
1506 	/* Iterate over all active crtc's. All crtc's must be in vblank,
1507 	 * otherwise return in_vbl == false.
1508 	 */
1509 	for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1510 		if (rdev->pm.active_crtcs & (1 << crtc)) {
1511 			vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1512 			if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1513 			    !(vbl_status & DRM_SCANOUTPOS_INVBL))
1514 				in_vbl = false;
1515 		}
1516 	}
1517 
1518 	return in_vbl;
1519 }
1520 
1521 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1522 {
1523 	u32 stat_crtc = 0;
1524 	bool in_vbl = radeon_pm_in_vbl(rdev);
1525 
1526 	if (in_vbl == false)
1527 		DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1528 			 finish ? "exit" : "entry");
1529 	return in_vbl;
1530 }
1531 
1532 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1533 {
1534 	struct radeon_device *rdev;
1535 	int resched;
1536 	rdev = container_of(work, struct radeon_device,
1537 				pm.dynpm_idle_work.work);
1538 
1539 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1540 	mutex_lock(&rdev->pm.mutex);
1541 	if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1542 		int not_processed = 0;
1543 		int i;
1544 
1545 		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1546 			struct radeon_ring *ring = &rdev->ring[i];
1547 
1548 			if (ring->ready) {
1549 				not_processed += radeon_fence_count_emitted(rdev, i);
1550 				if (not_processed >= 3)
1551 					break;
1552 			}
1553 		}
1554 
1555 		if (not_processed >= 3) { /* should upclock */
1556 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1557 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1558 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1559 				   rdev->pm.dynpm_can_upclock) {
1560 				rdev->pm.dynpm_planned_action =
1561 					DYNPM_ACTION_UPCLOCK;
1562 				rdev->pm.dynpm_action_timeout = jiffies +
1563 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1564 			}
1565 		} else if (not_processed == 0) { /* should downclock */
1566 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1567 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1568 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1569 				   rdev->pm.dynpm_can_downclock) {
1570 				rdev->pm.dynpm_planned_action =
1571 					DYNPM_ACTION_DOWNCLOCK;
1572 				rdev->pm.dynpm_action_timeout = jiffies +
1573 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1574 			}
1575 		}
1576 
1577 		/* Note, radeon_pm_set_clocks is called with static_switch set
1578 		 * to false since we want to wait for vbl to avoid flicker.
1579 		 */
1580 		if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1581 		    jiffies > rdev->pm.dynpm_action_timeout) {
1582 			radeon_pm_get_dynpm_state(rdev);
1583 			radeon_pm_set_clocks(rdev);
1584 		}
1585 
1586 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1587 				      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1588 	}
1589 	mutex_unlock(&rdev->pm.mutex);
1590 	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1591 }
1592 
1593 /*
1594  * Debugfs info
1595  */
1596 #if defined(CONFIG_DEBUG_FS)
1597 
1598 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1599 {
1600 	struct drm_info_node *node = (struct drm_info_node *) m->private;
1601 	struct drm_device *dev = node->minor->dev;
1602 	struct radeon_device *rdev = dev->dev_private;
1603 
1604 	if (rdev->pm.dpm_enabled) {
1605 		mutex_lock(&rdev->pm.mutex);
1606 		if (rdev->asic->dpm.debugfs_print_current_performance_level)
1607 			radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1608 		else
1609 			seq_printf(m, "Debugfs support not implemented for this asic\n");
1610 		mutex_unlock(&rdev->pm.mutex);
1611 	} else {
1612 		seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1613 		/* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1614 		if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1615 			seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1616 		else
1617 			seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1618 		seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1619 		if (rdev->asic->pm.get_memory_clock)
1620 			seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1621 		if (rdev->pm.current_vddc)
1622 			seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1623 		if (rdev->asic->pm.get_pcie_lanes)
1624 			seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1625 	}
1626 
1627 	return 0;
1628 }
1629 
1630 static struct drm_info_list radeon_pm_info_list[] = {
1631 	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1632 };
1633 #endif
1634 
1635 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1636 {
1637 #if defined(CONFIG_DEBUG_FS)
1638 	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1639 #else
1640 	return 0;
1641 #endif
1642 }
1643