1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include "drmP.h" 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #ifdef CONFIG_ACPI 28 #include <linux/acpi.h> 29 #endif 30 #include <linux/power_supply.h> 31 #include <linux/hwmon.h> 32 #include <linux/hwmon-sysfs.h> 33 34 #define RADEON_IDLE_LOOP_MS 100 35 #define RADEON_RECLOCK_DELAY_MS 200 36 #define RADEON_WAIT_VBLANK_TIMEOUT 200 37 #define RADEON_WAIT_IDLE_TIMEOUT 200 38 39 static const char *radeon_pm_state_type_name[5] = { 40 "Default", 41 "Powersave", 42 "Battery", 43 "Balanced", 44 "Performance", 45 }; 46 47 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 48 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 49 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 51 static void radeon_pm_update_profile(struct radeon_device *rdev); 52 static void radeon_pm_set_clocks(struct radeon_device *rdev); 53 54 #define ACPI_AC_CLASS "ac_adapter" 55 56 #ifdef CONFIG_ACPI 57 static int radeon_acpi_event(struct notifier_block *nb, 58 unsigned long val, 59 void *data) 60 { 61 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb); 62 struct acpi_bus_event *entry = (struct acpi_bus_event *)data; 63 64 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { 65 if (power_supply_is_system_supplied() > 0) 66 DRM_DEBUG_DRIVER("pm: AC\n"); 67 else 68 DRM_DEBUG_DRIVER("pm: DC\n"); 69 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 71 if (rdev->pm.profile == PM_PROFILE_AUTO) { 72 mutex_lock(&rdev->pm.mutex); 73 radeon_pm_update_profile(rdev); 74 radeon_pm_set_clocks(rdev); 75 mutex_unlock(&rdev->pm.mutex); 76 } 77 } 78 } 79 80 return NOTIFY_OK; 81 } 82 #endif 83 84 static void radeon_pm_update_profile(struct radeon_device *rdev) 85 { 86 switch (rdev->pm.profile) { 87 case PM_PROFILE_DEFAULT: 88 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 89 break; 90 case PM_PROFILE_AUTO: 91 if (power_supply_is_system_supplied() > 0) { 92 if (rdev->pm.active_crtc_count > 1) 93 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 94 else 95 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 96 } else { 97 if (rdev->pm.active_crtc_count > 1) 98 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 99 else 100 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 101 } 102 break; 103 case PM_PROFILE_LOW: 104 if (rdev->pm.active_crtc_count > 1) 105 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 106 else 107 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 108 break; 109 case PM_PROFILE_MID: 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 break; 115 case PM_PROFILE_HIGH: 116 if (rdev->pm.active_crtc_count > 1) 117 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 118 else 119 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 120 break; 121 } 122 123 if (rdev->pm.active_crtc_count == 0) { 124 rdev->pm.requested_power_state_index = 125 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 126 rdev->pm.requested_clock_mode_index = 127 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 128 } else { 129 rdev->pm.requested_power_state_index = 130 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 131 rdev->pm.requested_clock_mode_index = 132 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 133 } 134 } 135 136 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 137 { 138 struct radeon_bo *bo, *n; 139 140 if (list_empty(&rdev->gem.objects)) 141 return; 142 143 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 144 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 145 ttm_bo_unmap_virtual(&bo->tbo); 146 } 147 } 148 149 static void radeon_sync_with_vblank(struct radeon_device *rdev) 150 { 151 if (rdev->pm.active_crtcs) { 152 rdev->pm.vblank_sync = false; 153 wait_event_timeout( 154 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 155 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 156 } 157 } 158 159 static void radeon_set_power_state(struct radeon_device *rdev) 160 { 161 u32 sclk, mclk; 162 bool misc_after = false; 163 164 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 165 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 166 return; 167 168 if (radeon_gui_idle(rdev)) { 169 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 170 clock_info[rdev->pm.requested_clock_mode_index].sclk; 171 if (sclk > rdev->pm.default_sclk) 172 sclk = rdev->pm.default_sclk; 173 174 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 175 clock_info[rdev->pm.requested_clock_mode_index].mclk; 176 if (mclk > rdev->pm.default_mclk) 177 mclk = rdev->pm.default_mclk; 178 179 /* upvolt before raising clocks, downvolt after lowering clocks */ 180 if (sclk < rdev->pm.current_sclk) 181 misc_after = true; 182 183 radeon_sync_with_vblank(rdev); 184 185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 186 if (!radeon_pm_in_vbl(rdev)) 187 return; 188 } 189 190 radeon_pm_prepare(rdev); 191 192 if (!misc_after) 193 /* voltage, pcie lanes, etc.*/ 194 radeon_pm_misc(rdev); 195 196 /* set engine clock */ 197 if (sclk != rdev->pm.current_sclk) { 198 radeon_pm_debug_check_in_vbl(rdev, false); 199 radeon_set_engine_clock(rdev, sclk); 200 radeon_pm_debug_check_in_vbl(rdev, true); 201 rdev->pm.current_sclk = sclk; 202 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 203 } 204 205 /* set memory clock */ 206 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) { 207 radeon_pm_debug_check_in_vbl(rdev, false); 208 radeon_set_memory_clock(rdev, mclk); 209 radeon_pm_debug_check_in_vbl(rdev, true); 210 rdev->pm.current_mclk = mclk; 211 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 212 } 213 214 if (misc_after) 215 /* voltage, pcie lanes, etc.*/ 216 radeon_pm_misc(rdev); 217 218 radeon_pm_finish(rdev); 219 220 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 221 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 222 } else 223 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 224 } 225 226 static void radeon_pm_set_clocks(struct radeon_device *rdev) 227 { 228 int i; 229 230 /* no need to take locks, etc. if nothing's going to change */ 231 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 232 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 233 return; 234 235 mutex_lock(&rdev->ddev->struct_mutex); 236 mutex_lock(&rdev->vram_mutex); 237 mutex_lock(&rdev->cp.mutex); 238 239 /* gui idle int has issues on older chips it seems */ 240 if (rdev->family >= CHIP_R600) { 241 if (rdev->irq.installed) { 242 /* wait for GPU idle */ 243 rdev->pm.gui_idle = false; 244 rdev->irq.gui_idle = true; 245 radeon_irq_set(rdev); 246 wait_event_interruptible_timeout( 247 rdev->irq.idle_queue, rdev->pm.gui_idle, 248 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT)); 249 rdev->irq.gui_idle = false; 250 radeon_irq_set(rdev); 251 } 252 } else { 253 if (rdev->cp.ready) { 254 struct radeon_fence *fence; 255 radeon_ring_alloc(rdev, 64); 256 radeon_fence_create(rdev, &fence); 257 radeon_fence_emit(rdev, fence); 258 radeon_ring_commit(rdev); 259 radeon_fence_wait(fence, false); 260 radeon_fence_unref(&fence); 261 } 262 } 263 radeon_unmap_vram_bos(rdev); 264 265 if (rdev->irq.installed) { 266 for (i = 0; i < rdev->num_crtc; i++) { 267 if (rdev->pm.active_crtcs & (1 << i)) { 268 rdev->pm.req_vblank |= (1 << i); 269 drm_vblank_get(rdev->ddev, i); 270 } 271 } 272 } 273 274 radeon_set_power_state(rdev); 275 276 if (rdev->irq.installed) { 277 for (i = 0; i < rdev->num_crtc; i++) { 278 if (rdev->pm.req_vblank & (1 << i)) { 279 rdev->pm.req_vblank &= ~(1 << i); 280 drm_vblank_put(rdev->ddev, i); 281 } 282 } 283 } 284 285 /* update display watermarks based on new power state */ 286 radeon_update_bandwidth_info(rdev); 287 if (rdev->pm.active_crtc_count) 288 radeon_bandwidth_update(rdev); 289 290 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 291 292 mutex_unlock(&rdev->cp.mutex); 293 mutex_unlock(&rdev->vram_mutex); 294 mutex_unlock(&rdev->ddev->struct_mutex); 295 } 296 297 static void radeon_pm_print_states(struct radeon_device *rdev) 298 { 299 int i, j; 300 struct radeon_power_state *power_state; 301 struct radeon_pm_clock_info *clock_info; 302 303 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 304 for (i = 0; i < rdev->pm.num_power_states; i++) { 305 power_state = &rdev->pm.power_state[i]; 306 DRM_DEBUG_DRIVER("State %d: %s\n", i, 307 radeon_pm_state_type_name[power_state->type]); 308 if (i == rdev->pm.default_power_state_index) 309 DRM_DEBUG_DRIVER("\tDefault"); 310 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 311 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 312 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 313 DRM_DEBUG_DRIVER("\tSingle display only\n"); 314 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 315 for (j = 0; j < power_state->num_clock_modes; j++) { 316 clock_info = &(power_state->clock_info[j]); 317 if (rdev->flags & RADEON_IS_IGP) 318 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n", 319 j, 320 clock_info->sclk * 10, 321 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); 322 else 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n", 324 j, 325 clock_info->sclk * 10, 326 clock_info->mclk * 10, 327 clock_info->voltage.voltage, 328 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); 329 } 330 } 331 } 332 333 static ssize_t radeon_get_pm_profile(struct device *dev, 334 struct device_attribute *attr, 335 char *buf) 336 { 337 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 338 struct radeon_device *rdev = ddev->dev_private; 339 int cp = rdev->pm.profile; 340 341 return snprintf(buf, PAGE_SIZE, "%s\n", 342 (cp == PM_PROFILE_AUTO) ? "auto" : 343 (cp == PM_PROFILE_LOW) ? "low" : 344 (cp == PM_PROFILE_MID) ? "mid" : 345 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 346 } 347 348 static ssize_t radeon_set_pm_profile(struct device *dev, 349 struct device_attribute *attr, 350 const char *buf, 351 size_t count) 352 { 353 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 354 struct radeon_device *rdev = ddev->dev_private; 355 356 mutex_lock(&rdev->pm.mutex); 357 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 358 if (strncmp("default", buf, strlen("default")) == 0) 359 rdev->pm.profile = PM_PROFILE_DEFAULT; 360 else if (strncmp("auto", buf, strlen("auto")) == 0) 361 rdev->pm.profile = PM_PROFILE_AUTO; 362 else if (strncmp("low", buf, strlen("low")) == 0) 363 rdev->pm.profile = PM_PROFILE_LOW; 364 else if (strncmp("mid", buf, strlen("mid")) == 0) 365 rdev->pm.profile = PM_PROFILE_MID; 366 else if (strncmp("high", buf, strlen("high")) == 0) 367 rdev->pm.profile = PM_PROFILE_HIGH; 368 else { 369 count = -EINVAL; 370 goto fail; 371 } 372 radeon_pm_update_profile(rdev); 373 radeon_pm_set_clocks(rdev); 374 } else 375 count = -EINVAL; 376 377 fail: 378 mutex_unlock(&rdev->pm.mutex); 379 380 return count; 381 } 382 383 static ssize_t radeon_get_pm_method(struct device *dev, 384 struct device_attribute *attr, 385 char *buf) 386 { 387 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 388 struct radeon_device *rdev = ddev->dev_private; 389 int pm = rdev->pm.pm_method; 390 391 return snprintf(buf, PAGE_SIZE, "%s\n", 392 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); 393 } 394 395 static ssize_t radeon_set_pm_method(struct device *dev, 396 struct device_attribute *attr, 397 const char *buf, 398 size_t count) 399 { 400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 401 struct radeon_device *rdev = ddev->dev_private; 402 403 404 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 405 mutex_lock(&rdev->pm.mutex); 406 rdev->pm.pm_method = PM_METHOD_DYNPM; 407 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 408 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 409 mutex_unlock(&rdev->pm.mutex); 410 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 411 mutex_lock(&rdev->pm.mutex); 412 /* disable dynpm */ 413 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 414 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 415 rdev->pm.pm_method = PM_METHOD_PROFILE; 416 mutex_unlock(&rdev->pm.mutex); 417 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 418 } else { 419 count = -EINVAL; 420 goto fail; 421 } 422 radeon_pm_compute_clocks(rdev); 423 fail: 424 return count; 425 } 426 427 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 428 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 429 430 static ssize_t radeon_hwmon_show_temp(struct device *dev, 431 struct device_attribute *attr, 432 char *buf) 433 { 434 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 435 struct radeon_device *rdev = ddev->dev_private; 436 int temp; 437 438 switch (rdev->pm.int_thermal_type) { 439 case THERMAL_TYPE_RV6XX: 440 temp = rv6xx_get_temp(rdev); 441 break; 442 case THERMAL_TYPE_RV770: 443 temp = rv770_get_temp(rdev); 444 break; 445 case THERMAL_TYPE_EVERGREEN: 446 case THERMAL_TYPE_NI: 447 temp = evergreen_get_temp(rdev); 448 break; 449 case THERMAL_TYPE_SUMO: 450 temp = sumo_get_temp(rdev); 451 break; 452 default: 453 temp = 0; 454 break; 455 } 456 457 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 458 } 459 460 static ssize_t radeon_hwmon_show_name(struct device *dev, 461 struct device_attribute *attr, 462 char *buf) 463 { 464 return sprintf(buf, "radeon\n"); 465 } 466 467 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 468 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0); 469 470 static struct attribute *hwmon_attributes[] = { 471 &sensor_dev_attr_temp1_input.dev_attr.attr, 472 &sensor_dev_attr_name.dev_attr.attr, 473 NULL 474 }; 475 476 static const struct attribute_group hwmon_attrgroup = { 477 .attrs = hwmon_attributes, 478 }; 479 480 static int radeon_hwmon_init(struct radeon_device *rdev) 481 { 482 int err = 0; 483 484 rdev->pm.int_hwmon_dev = NULL; 485 486 switch (rdev->pm.int_thermal_type) { 487 case THERMAL_TYPE_RV6XX: 488 case THERMAL_TYPE_RV770: 489 case THERMAL_TYPE_EVERGREEN: 490 case THERMAL_TYPE_NI: 491 case THERMAL_TYPE_SUMO: 492 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 493 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 494 err = PTR_ERR(rdev->pm.int_hwmon_dev); 495 dev_err(rdev->dev, 496 "Unable to register hwmon device: %d\n", err); 497 break; 498 } 499 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); 500 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, 501 &hwmon_attrgroup); 502 if (err) { 503 dev_err(rdev->dev, 504 "Unable to create hwmon sysfs file: %d\n", err); 505 hwmon_device_unregister(rdev->dev); 506 } 507 break; 508 default: 509 break; 510 } 511 512 return err; 513 } 514 515 static void radeon_hwmon_fini(struct radeon_device *rdev) 516 { 517 if (rdev->pm.int_hwmon_dev) { 518 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup); 519 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 520 } 521 } 522 523 void radeon_pm_suspend(struct radeon_device *rdev) 524 { 525 mutex_lock(&rdev->pm.mutex); 526 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 527 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 528 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 529 } 530 mutex_unlock(&rdev->pm.mutex); 531 532 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 533 } 534 535 void radeon_pm_resume(struct radeon_device *rdev) 536 { 537 /* set up the default clocks if the MC ucode is loaded */ 538 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { 539 if (rdev->pm.default_vddc) 540 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 541 SET_VOLTAGE_TYPE_ASIC_VDDC); 542 if (rdev->pm.default_vddci) 543 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 544 SET_VOLTAGE_TYPE_ASIC_VDDCI); 545 if (rdev->pm.default_sclk) 546 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 547 if (rdev->pm.default_mclk) 548 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 549 } 550 /* asic init will reset the default power state */ 551 mutex_lock(&rdev->pm.mutex); 552 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 553 rdev->pm.current_clock_mode_index = 0; 554 rdev->pm.current_sclk = rdev->pm.default_sclk; 555 rdev->pm.current_mclk = rdev->pm.default_mclk; 556 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 557 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 558 if (rdev->pm.pm_method == PM_METHOD_DYNPM 559 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 560 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 561 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 562 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 563 } 564 mutex_unlock(&rdev->pm.mutex); 565 radeon_pm_compute_clocks(rdev); 566 } 567 568 int radeon_pm_init(struct radeon_device *rdev) 569 { 570 int ret; 571 572 /* default to profile method */ 573 rdev->pm.pm_method = PM_METHOD_PROFILE; 574 rdev->pm.profile = PM_PROFILE_DEFAULT; 575 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 576 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 577 rdev->pm.dynpm_can_upclock = true; 578 rdev->pm.dynpm_can_downclock = true; 579 rdev->pm.default_sclk = rdev->clock.default_sclk; 580 rdev->pm.default_mclk = rdev->clock.default_mclk; 581 rdev->pm.current_sclk = rdev->clock.default_sclk; 582 rdev->pm.current_mclk = rdev->clock.default_mclk; 583 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 584 585 if (rdev->bios) { 586 if (rdev->is_atom_bios) 587 radeon_atombios_get_power_modes(rdev); 588 else 589 radeon_combios_get_power_modes(rdev); 590 radeon_pm_print_states(rdev); 591 radeon_pm_init_profile(rdev); 592 /* set up the default clocks if the MC ucode is loaded */ 593 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { 594 if (rdev->pm.default_vddc) 595 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 596 SET_VOLTAGE_TYPE_ASIC_VDDC); 597 if (rdev->pm.default_vddci) 598 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 599 SET_VOLTAGE_TYPE_ASIC_VDDCI); 600 if (rdev->pm.default_sclk) 601 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 602 if (rdev->pm.default_mclk) 603 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 604 } 605 } 606 607 /* set up the internal thermal sensor if applicable */ 608 ret = radeon_hwmon_init(rdev); 609 if (ret) 610 return ret; 611 612 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 613 614 if (rdev->pm.num_power_states > 1) { 615 /* where's the best place to put these? */ 616 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 617 if (ret) 618 DRM_ERROR("failed to create device file for power profile\n"); 619 ret = device_create_file(rdev->dev, &dev_attr_power_method); 620 if (ret) 621 DRM_ERROR("failed to create device file for power method\n"); 622 623 #ifdef CONFIG_ACPI 624 rdev->acpi_nb.notifier_call = radeon_acpi_event; 625 register_acpi_notifier(&rdev->acpi_nb); 626 #endif 627 if (radeon_debugfs_pm_init(rdev)) { 628 DRM_ERROR("Failed to register debugfs file for PM!\n"); 629 } 630 631 DRM_INFO("radeon: power management initialized\n"); 632 } 633 634 return 0; 635 } 636 637 void radeon_pm_fini(struct radeon_device *rdev) 638 { 639 if (rdev->pm.num_power_states > 1) { 640 mutex_lock(&rdev->pm.mutex); 641 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 642 rdev->pm.profile = PM_PROFILE_DEFAULT; 643 radeon_pm_update_profile(rdev); 644 radeon_pm_set_clocks(rdev); 645 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 646 /* reset default clocks */ 647 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 648 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 649 radeon_pm_set_clocks(rdev); 650 } 651 mutex_unlock(&rdev->pm.mutex); 652 653 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 654 655 device_remove_file(rdev->dev, &dev_attr_power_profile); 656 device_remove_file(rdev->dev, &dev_attr_power_method); 657 #ifdef CONFIG_ACPI 658 unregister_acpi_notifier(&rdev->acpi_nb); 659 #endif 660 } 661 662 if (rdev->pm.power_state) 663 kfree(rdev->pm.power_state); 664 665 radeon_hwmon_fini(rdev); 666 } 667 668 void radeon_pm_compute_clocks(struct radeon_device *rdev) 669 { 670 struct drm_device *ddev = rdev->ddev; 671 struct drm_crtc *crtc; 672 struct radeon_crtc *radeon_crtc; 673 674 if (rdev->pm.num_power_states < 2) 675 return; 676 677 mutex_lock(&rdev->pm.mutex); 678 679 rdev->pm.active_crtcs = 0; 680 rdev->pm.active_crtc_count = 0; 681 list_for_each_entry(crtc, 682 &ddev->mode_config.crtc_list, head) { 683 radeon_crtc = to_radeon_crtc(crtc); 684 if (radeon_crtc->enabled) { 685 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 686 rdev->pm.active_crtc_count++; 687 } 688 } 689 690 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 691 radeon_pm_update_profile(rdev); 692 radeon_pm_set_clocks(rdev); 693 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 694 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 695 if (rdev->pm.active_crtc_count > 1) { 696 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 697 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 698 699 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 700 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 701 radeon_pm_get_dynpm_state(rdev); 702 radeon_pm_set_clocks(rdev); 703 704 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 705 } 706 } else if (rdev->pm.active_crtc_count == 1) { 707 /* TODO: Increase clocks if needed for current mode */ 708 709 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 710 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 711 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 712 radeon_pm_get_dynpm_state(rdev); 713 radeon_pm_set_clocks(rdev); 714 715 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 716 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 717 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 718 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 719 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 720 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 721 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 722 } 723 } else { /* count == 0 */ 724 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 725 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 726 727 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 728 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 729 radeon_pm_get_dynpm_state(rdev); 730 radeon_pm_set_clocks(rdev); 731 } 732 } 733 } 734 } 735 736 mutex_unlock(&rdev->pm.mutex); 737 } 738 739 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 740 { 741 int crtc, vpos, hpos, vbl_status; 742 bool in_vbl = true; 743 744 /* Iterate over all active crtc's. All crtc's must be in vblank, 745 * otherwise return in_vbl == false. 746 */ 747 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 748 if (rdev->pm.active_crtcs & (1 << crtc)) { 749 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos); 750 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 751 !(vbl_status & DRM_SCANOUTPOS_INVBL)) 752 in_vbl = false; 753 } 754 } 755 756 return in_vbl; 757 } 758 759 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 760 { 761 u32 stat_crtc = 0; 762 bool in_vbl = radeon_pm_in_vbl(rdev); 763 764 if (in_vbl == false) 765 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 766 finish ? "exit" : "entry"); 767 return in_vbl; 768 } 769 770 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 771 { 772 struct radeon_device *rdev; 773 int resched; 774 rdev = container_of(work, struct radeon_device, 775 pm.dynpm_idle_work.work); 776 777 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 778 mutex_lock(&rdev->pm.mutex); 779 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 780 unsigned long irq_flags; 781 int not_processed = 0; 782 783 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 784 if (!list_empty(&rdev->fence_drv.emited)) { 785 struct list_head *ptr; 786 list_for_each(ptr, &rdev->fence_drv.emited) { 787 /* count up to 3, that's enought info */ 788 if (++not_processed >= 3) 789 break; 790 } 791 } 792 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 793 794 if (not_processed >= 3) { /* should upclock */ 795 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 796 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 797 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 798 rdev->pm.dynpm_can_upclock) { 799 rdev->pm.dynpm_planned_action = 800 DYNPM_ACTION_UPCLOCK; 801 rdev->pm.dynpm_action_timeout = jiffies + 802 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 803 } 804 } else if (not_processed == 0) { /* should downclock */ 805 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 806 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 807 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 808 rdev->pm.dynpm_can_downclock) { 809 rdev->pm.dynpm_planned_action = 810 DYNPM_ACTION_DOWNCLOCK; 811 rdev->pm.dynpm_action_timeout = jiffies + 812 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 813 } 814 } 815 816 /* Note, radeon_pm_set_clocks is called with static_switch set 817 * to false since we want to wait for vbl to avoid flicker. 818 */ 819 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 820 jiffies > rdev->pm.dynpm_action_timeout) { 821 radeon_pm_get_dynpm_state(rdev); 822 radeon_pm_set_clocks(rdev); 823 } 824 825 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 826 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 827 } 828 mutex_unlock(&rdev->pm.mutex); 829 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 830 } 831 832 /* 833 * Debugfs info 834 */ 835 #if defined(CONFIG_DEBUG_FS) 836 837 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 838 { 839 struct drm_info_node *node = (struct drm_info_node *) m->private; 840 struct drm_device *dev = node->minor->dev; 841 struct radeon_device *rdev = dev->dev_private; 842 843 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 844 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 845 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 846 if (rdev->asic->get_memory_clock) 847 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 848 if (rdev->pm.current_vddc) 849 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 850 if (rdev->asic->get_pcie_lanes) 851 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 852 853 return 0; 854 } 855 856 static struct drm_info_list radeon_pm_info_list[] = { 857 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 858 }; 859 #endif 860 861 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 862 { 863 #if defined(CONFIG_DEBUG_FS) 864 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 865 #else 866 return 0; 867 #endif 868 } 869