1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include <linux/power_supply.h> 28 #include <linux/hwmon.h> 29 #include <linux/hwmon-sysfs.h> 30 31 #define RADEON_IDLE_LOOP_MS 100 32 #define RADEON_RECLOCK_DELAY_MS 200 33 #define RADEON_WAIT_VBLANK_TIMEOUT 200 34 35 static const char *radeon_pm_state_type_name[5] = { 36 "", 37 "Powersave", 38 "Battery", 39 "Balanced", 40 "Performance", 41 }; 42 43 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 44 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 45 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 47 static void radeon_pm_update_profile(struct radeon_device *rdev); 48 static void radeon_pm_set_clocks(struct radeon_device *rdev); 49 50 int radeon_pm_get_type_index(struct radeon_device *rdev, 51 enum radeon_pm_state_type ps_type, 52 int instance) 53 { 54 int i; 55 int found_instance = -1; 56 57 for (i = 0; i < rdev->pm.num_power_states; i++) { 58 if (rdev->pm.power_state[i].type == ps_type) { 59 found_instance++; 60 if (found_instance == instance) 61 return i; 62 } 63 } 64 /* return default if no match */ 65 return rdev->pm.default_power_state_index; 66 } 67 68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 69 { 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 71 if (rdev->pm.profile == PM_PROFILE_AUTO) { 72 mutex_lock(&rdev->pm.mutex); 73 radeon_pm_update_profile(rdev); 74 radeon_pm_set_clocks(rdev); 75 mutex_unlock(&rdev->pm.mutex); 76 } 77 } 78 } 79 80 static void radeon_pm_update_profile(struct radeon_device *rdev) 81 { 82 switch (rdev->pm.profile) { 83 case PM_PROFILE_DEFAULT: 84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 85 break; 86 case PM_PROFILE_AUTO: 87 if (power_supply_is_system_supplied() > 0) { 88 if (rdev->pm.active_crtc_count > 1) 89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 90 else 91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 92 } else { 93 if (rdev->pm.active_crtc_count > 1) 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 95 else 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 97 } 98 break; 99 case PM_PROFILE_LOW: 100 if (rdev->pm.active_crtc_count > 1) 101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 102 else 103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 104 break; 105 case PM_PROFILE_MID: 106 if (rdev->pm.active_crtc_count > 1) 107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 108 else 109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 110 break; 111 case PM_PROFILE_HIGH: 112 if (rdev->pm.active_crtc_count > 1) 113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 114 else 115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 116 break; 117 } 118 119 if (rdev->pm.active_crtc_count == 0) { 120 rdev->pm.requested_power_state_index = 121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 122 rdev->pm.requested_clock_mode_index = 123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 124 } else { 125 rdev->pm.requested_power_state_index = 126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 127 rdev->pm.requested_clock_mode_index = 128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 129 } 130 } 131 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 133 { 134 struct radeon_bo *bo, *n; 135 136 if (list_empty(&rdev->gem.objects)) 137 return; 138 139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 141 ttm_bo_unmap_virtual(&bo->tbo); 142 } 143 } 144 145 static void radeon_sync_with_vblank(struct radeon_device *rdev) 146 { 147 if (rdev->pm.active_crtcs) { 148 rdev->pm.vblank_sync = false; 149 wait_event_timeout( 150 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 152 } 153 } 154 155 static void radeon_set_power_state(struct radeon_device *rdev) 156 { 157 u32 sclk, mclk; 158 bool misc_after = false; 159 160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 162 return; 163 164 if (radeon_gui_idle(rdev)) { 165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 166 clock_info[rdev->pm.requested_clock_mode_index].sclk; 167 if (sclk > rdev->pm.default_sclk) 168 sclk = rdev->pm.default_sclk; 169 170 /* starting with BTC, there is one state that is used for both 171 * MH and SH. Difference is that we always use the high clock index for 172 * mclk and vddci. 173 */ 174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 175 (rdev->family >= CHIP_BARTS) && 176 rdev->pm.active_crtc_count && 177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 181 else 182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 clock_info[rdev->pm.requested_clock_mode_index].mclk; 184 185 if (mclk > rdev->pm.default_mclk) 186 mclk = rdev->pm.default_mclk; 187 188 /* upvolt before raising clocks, downvolt after lowering clocks */ 189 if (sclk < rdev->pm.current_sclk) 190 misc_after = true; 191 192 radeon_sync_with_vblank(rdev); 193 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 195 if (!radeon_pm_in_vbl(rdev)) 196 return; 197 } 198 199 radeon_pm_prepare(rdev); 200 201 if (!misc_after) 202 /* voltage, pcie lanes, etc.*/ 203 radeon_pm_misc(rdev); 204 205 /* set engine clock */ 206 if (sclk != rdev->pm.current_sclk) { 207 radeon_pm_debug_check_in_vbl(rdev, false); 208 radeon_set_engine_clock(rdev, sclk); 209 radeon_pm_debug_check_in_vbl(rdev, true); 210 rdev->pm.current_sclk = sclk; 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 212 } 213 214 /* set memory clock */ 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 216 radeon_pm_debug_check_in_vbl(rdev, false); 217 radeon_set_memory_clock(rdev, mclk); 218 radeon_pm_debug_check_in_vbl(rdev, true); 219 rdev->pm.current_mclk = mclk; 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 221 } 222 223 if (misc_after) 224 /* voltage, pcie lanes, etc.*/ 225 radeon_pm_misc(rdev); 226 227 radeon_pm_finish(rdev); 228 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 231 } else 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 233 } 234 235 static void radeon_pm_set_clocks(struct radeon_device *rdev) 236 { 237 int i, r; 238 239 /* no need to take locks, etc. if nothing's going to change */ 240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 242 return; 243 244 mutex_lock(&rdev->ddev->struct_mutex); 245 down_write(&rdev->pm.mclk_lock); 246 mutex_lock(&rdev->ring_lock); 247 248 /* wait for the rings to drain */ 249 for (i = 0; i < RADEON_NUM_RINGS; i++) { 250 struct radeon_ring *ring = &rdev->ring[i]; 251 if (!ring->ready) { 252 continue; 253 } 254 r = radeon_fence_wait_empty_locked(rdev, i); 255 if (r) { 256 /* needs a GPU reset dont reset here */ 257 mutex_unlock(&rdev->ring_lock); 258 up_write(&rdev->pm.mclk_lock); 259 mutex_unlock(&rdev->ddev->struct_mutex); 260 return; 261 } 262 } 263 264 radeon_unmap_vram_bos(rdev); 265 266 if (rdev->irq.installed) { 267 for (i = 0; i < rdev->num_crtc; i++) { 268 if (rdev->pm.active_crtcs & (1 << i)) { 269 rdev->pm.req_vblank |= (1 << i); 270 drm_vblank_get(rdev->ddev, i); 271 } 272 } 273 } 274 275 radeon_set_power_state(rdev); 276 277 if (rdev->irq.installed) { 278 for (i = 0; i < rdev->num_crtc; i++) { 279 if (rdev->pm.req_vblank & (1 << i)) { 280 rdev->pm.req_vblank &= ~(1 << i); 281 drm_vblank_put(rdev->ddev, i); 282 } 283 } 284 } 285 286 /* update display watermarks based on new power state */ 287 radeon_update_bandwidth_info(rdev); 288 if (rdev->pm.active_crtc_count) 289 radeon_bandwidth_update(rdev); 290 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 292 293 mutex_unlock(&rdev->ring_lock); 294 up_write(&rdev->pm.mclk_lock); 295 mutex_unlock(&rdev->ddev->struct_mutex); 296 } 297 298 static void radeon_pm_print_states(struct radeon_device *rdev) 299 { 300 int i, j; 301 struct radeon_power_state *power_state; 302 struct radeon_pm_clock_info *clock_info; 303 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 305 for (i = 0; i < rdev->pm.num_power_states; i++) { 306 power_state = &rdev->pm.power_state[i]; 307 DRM_DEBUG_DRIVER("State %d: %s\n", i, 308 radeon_pm_state_type_name[power_state->type]); 309 if (i == rdev->pm.default_power_state_index) 310 DRM_DEBUG_DRIVER("\tDefault"); 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 314 DRM_DEBUG_DRIVER("\tSingle display only\n"); 315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 316 for (j = 0; j < power_state->num_clock_modes; j++) { 317 clock_info = &(power_state->clock_info[j]); 318 if (rdev->flags & RADEON_IS_IGP) 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 320 j, 321 clock_info->sclk * 10); 322 else 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 324 j, 325 clock_info->sclk * 10, 326 clock_info->mclk * 10, 327 clock_info->voltage.voltage); 328 } 329 } 330 } 331 332 static ssize_t radeon_get_pm_profile(struct device *dev, 333 struct device_attribute *attr, 334 char *buf) 335 { 336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 337 struct radeon_device *rdev = ddev->dev_private; 338 int cp = rdev->pm.profile; 339 340 return snprintf(buf, PAGE_SIZE, "%s\n", 341 (cp == PM_PROFILE_AUTO) ? "auto" : 342 (cp == PM_PROFILE_LOW) ? "low" : 343 (cp == PM_PROFILE_MID) ? "mid" : 344 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 345 } 346 347 static ssize_t radeon_set_pm_profile(struct device *dev, 348 struct device_attribute *attr, 349 const char *buf, 350 size_t count) 351 { 352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 353 struct radeon_device *rdev = ddev->dev_private; 354 355 mutex_lock(&rdev->pm.mutex); 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 357 if (strncmp("default", buf, strlen("default")) == 0) 358 rdev->pm.profile = PM_PROFILE_DEFAULT; 359 else if (strncmp("auto", buf, strlen("auto")) == 0) 360 rdev->pm.profile = PM_PROFILE_AUTO; 361 else if (strncmp("low", buf, strlen("low")) == 0) 362 rdev->pm.profile = PM_PROFILE_LOW; 363 else if (strncmp("mid", buf, strlen("mid")) == 0) 364 rdev->pm.profile = PM_PROFILE_MID; 365 else if (strncmp("high", buf, strlen("high")) == 0) 366 rdev->pm.profile = PM_PROFILE_HIGH; 367 else { 368 count = -EINVAL; 369 goto fail; 370 } 371 radeon_pm_update_profile(rdev); 372 radeon_pm_set_clocks(rdev); 373 } else 374 count = -EINVAL; 375 376 fail: 377 mutex_unlock(&rdev->pm.mutex); 378 379 return count; 380 } 381 382 static ssize_t radeon_get_pm_method(struct device *dev, 383 struct device_attribute *attr, 384 char *buf) 385 { 386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 387 struct radeon_device *rdev = ddev->dev_private; 388 int pm = rdev->pm.pm_method; 389 390 return snprintf(buf, PAGE_SIZE, "%s\n", 391 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); 392 } 393 394 static ssize_t radeon_set_pm_method(struct device *dev, 395 struct device_attribute *attr, 396 const char *buf, 397 size_t count) 398 { 399 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 400 struct radeon_device *rdev = ddev->dev_private; 401 402 403 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 404 mutex_lock(&rdev->pm.mutex); 405 rdev->pm.pm_method = PM_METHOD_DYNPM; 406 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 407 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 408 mutex_unlock(&rdev->pm.mutex); 409 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 410 mutex_lock(&rdev->pm.mutex); 411 /* disable dynpm */ 412 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 414 rdev->pm.pm_method = PM_METHOD_PROFILE; 415 mutex_unlock(&rdev->pm.mutex); 416 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 417 } else { 418 count = -EINVAL; 419 goto fail; 420 } 421 radeon_pm_compute_clocks(rdev); 422 fail: 423 return count; 424 } 425 426 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 427 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 428 429 static ssize_t radeon_hwmon_show_temp(struct device *dev, 430 struct device_attribute *attr, 431 char *buf) 432 { 433 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 434 struct radeon_device *rdev = ddev->dev_private; 435 int temp; 436 437 switch (rdev->pm.int_thermal_type) { 438 case THERMAL_TYPE_RV6XX: 439 temp = rv6xx_get_temp(rdev); 440 break; 441 case THERMAL_TYPE_RV770: 442 temp = rv770_get_temp(rdev); 443 break; 444 case THERMAL_TYPE_EVERGREEN: 445 case THERMAL_TYPE_NI: 446 temp = evergreen_get_temp(rdev); 447 break; 448 case THERMAL_TYPE_SUMO: 449 temp = sumo_get_temp(rdev); 450 break; 451 case THERMAL_TYPE_SI: 452 temp = si_get_temp(rdev); 453 break; 454 default: 455 temp = 0; 456 break; 457 } 458 459 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 460 } 461 462 static ssize_t radeon_hwmon_show_name(struct device *dev, 463 struct device_attribute *attr, 464 char *buf) 465 { 466 return sprintf(buf, "radeon\n"); 467 } 468 469 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 470 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0); 471 472 static struct attribute *hwmon_attributes[] = { 473 &sensor_dev_attr_temp1_input.dev_attr.attr, 474 &sensor_dev_attr_name.dev_attr.attr, 475 NULL 476 }; 477 478 static const struct attribute_group hwmon_attrgroup = { 479 .attrs = hwmon_attributes, 480 }; 481 482 static int radeon_hwmon_init(struct radeon_device *rdev) 483 { 484 int err = 0; 485 486 rdev->pm.int_hwmon_dev = NULL; 487 488 switch (rdev->pm.int_thermal_type) { 489 case THERMAL_TYPE_RV6XX: 490 case THERMAL_TYPE_RV770: 491 case THERMAL_TYPE_EVERGREEN: 492 case THERMAL_TYPE_NI: 493 case THERMAL_TYPE_SUMO: 494 case THERMAL_TYPE_SI: 495 /* No support for TN yet */ 496 if (rdev->family == CHIP_ARUBA) 497 return err; 498 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 499 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 500 err = PTR_ERR(rdev->pm.int_hwmon_dev); 501 dev_err(rdev->dev, 502 "Unable to register hwmon device: %d\n", err); 503 break; 504 } 505 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); 506 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, 507 &hwmon_attrgroup); 508 if (err) { 509 dev_err(rdev->dev, 510 "Unable to create hwmon sysfs file: %d\n", err); 511 hwmon_device_unregister(rdev->dev); 512 } 513 break; 514 default: 515 break; 516 } 517 518 return err; 519 } 520 521 static void radeon_hwmon_fini(struct radeon_device *rdev) 522 { 523 if (rdev->pm.int_hwmon_dev) { 524 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup); 525 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 526 } 527 } 528 529 void radeon_pm_suspend(struct radeon_device *rdev) 530 { 531 mutex_lock(&rdev->pm.mutex); 532 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 533 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 534 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 535 } 536 mutex_unlock(&rdev->pm.mutex); 537 538 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 539 } 540 541 void radeon_pm_resume(struct radeon_device *rdev) 542 { 543 /* set up the default clocks if the MC ucode is loaded */ 544 if ((rdev->family >= CHIP_BARTS) && 545 (rdev->family <= CHIP_CAYMAN) && 546 rdev->mc_fw) { 547 if (rdev->pm.default_vddc) 548 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 549 SET_VOLTAGE_TYPE_ASIC_VDDC); 550 if (rdev->pm.default_vddci) 551 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 552 SET_VOLTAGE_TYPE_ASIC_VDDCI); 553 if (rdev->pm.default_sclk) 554 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 555 if (rdev->pm.default_mclk) 556 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 557 } 558 /* asic init will reset the default power state */ 559 mutex_lock(&rdev->pm.mutex); 560 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 561 rdev->pm.current_clock_mode_index = 0; 562 rdev->pm.current_sclk = rdev->pm.default_sclk; 563 rdev->pm.current_mclk = rdev->pm.default_mclk; 564 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 565 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 566 if (rdev->pm.pm_method == PM_METHOD_DYNPM 567 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 568 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 569 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 570 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 571 } 572 mutex_unlock(&rdev->pm.mutex); 573 radeon_pm_compute_clocks(rdev); 574 } 575 576 int radeon_pm_init(struct radeon_device *rdev) 577 { 578 int ret; 579 580 /* default to profile method */ 581 rdev->pm.pm_method = PM_METHOD_PROFILE; 582 rdev->pm.profile = PM_PROFILE_DEFAULT; 583 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 584 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 585 rdev->pm.dynpm_can_upclock = true; 586 rdev->pm.dynpm_can_downclock = true; 587 rdev->pm.default_sclk = rdev->clock.default_sclk; 588 rdev->pm.default_mclk = rdev->clock.default_mclk; 589 rdev->pm.current_sclk = rdev->clock.default_sclk; 590 rdev->pm.current_mclk = rdev->clock.default_mclk; 591 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 592 593 if (rdev->bios) { 594 if (rdev->is_atom_bios) 595 radeon_atombios_get_power_modes(rdev); 596 else 597 radeon_combios_get_power_modes(rdev); 598 radeon_pm_print_states(rdev); 599 radeon_pm_init_profile(rdev); 600 /* set up the default clocks if the MC ucode is loaded */ 601 if ((rdev->family >= CHIP_BARTS) && 602 (rdev->family <= CHIP_CAYMAN) && 603 rdev->mc_fw) { 604 if (rdev->pm.default_vddc) 605 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 606 SET_VOLTAGE_TYPE_ASIC_VDDC); 607 if (rdev->pm.default_vddci) 608 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 609 SET_VOLTAGE_TYPE_ASIC_VDDCI); 610 if (rdev->pm.default_sclk) 611 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 612 if (rdev->pm.default_mclk) 613 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 614 } 615 } 616 617 /* set up the internal thermal sensor if applicable */ 618 ret = radeon_hwmon_init(rdev); 619 if (ret) 620 return ret; 621 622 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 623 624 if (rdev->pm.num_power_states > 1) { 625 /* where's the best place to put these? */ 626 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 627 if (ret) 628 DRM_ERROR("failed to create device file for power profile\n"); 629 ret = device_create_file(rdev->dev, &dev_attr_power_method); 630 if (ret) 631 DRM_ERROR("failed to create device file for power method\n"); 632 633 if (radeon_debugfs_pm_init(rdev)) { 634 DRM_ERROR("Failed to register debugfs file for PM!\n"); 635 } 636 637 DRM_INFO("radeon: power management initialized\n"); 638 } 639 640 return 0; 641 } 642 643 void radeon_pm_fini(struct radeon_device *rdev) 644 { 645 if (rdev->pm.num_power_states > 1) { 646 mutex_lock(&rdev->pm.mutex); 647 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 648 rdev->pm.profile = PM_PROFILE_DEFAULT; 649 radeon_pm_update_profile(rdev); 650 radeon_pm_set_clocks(rdev); 651 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 652 /* reset default clocks */ 653 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 654 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 655 radeon_pm_set_clocks(rdev); 656 } 657 mutex_unlock(&rdev->pm.mutex); 658 659 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 660 661 device_remove_file(rdev->dev, &dev_attr_power_profile); 662 device_remove_file(rdev->dev, &dev_attr_power_method); 663 } 664 665 if (rdev->pm.power_state) 666 kfree(rdev->pm.power_state); 667 668 radeon_hwmon_fini(rdev); 669 } 670 671 void radeon_pm_compute_clocks(struct radeon_device *rdev) 672 { 673 struct drm_device *ddev = rdev->ddev; 674 struct drm_crtc *crtc; 675 struct radeon_crtc *radeon_crtc; 676 677 if (rdev->pm.num_power_states < 2) 678 return; 679 680 mutex_lock(&rdev->pm.mutex); 681 682 rdev->pm.active_crtcs = 0; 683 rdev->pm.active_crtc_count = 0; 684 list_for_each_entry(crtc, 685 &ddev->mode_config.crtc_list, head) { 686 radeon_crtc = to_radeon_crtc(crtc); 687 if (radeon_crtc->enabled) { 688 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 689 rdev->pm.active_crtc_count++; 690 } 691 } 692 693 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 694 radeon_pm_update_profile(rdev); 695 radeon_pm_set_clocks(rdev); 696 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 697 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 698 if (rdev->pm.active_crtc_count > 1) { 699 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 700 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 701 702 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 703 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 704 radeon_pm_get_dynpm_state(rdev); 705 radeon_pm_set_clocks(rdev); 706 707 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 708 } 709 } else if (rdev->pm.active_crtc_count == 1) { 710 /* TODO: Increase clocks if needed for current mode */ 711 712 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 713 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 714 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 715 radeon_pm_get_dynpm_state(rdev); 716 radeon_pm_set_clocks(rdev); 717 718 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 719 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 720 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 721 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 722 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 723 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 724 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 725 } 726 } else { /* count == 0 */ 727 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 728 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 729 730 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 731 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 732 radeon_pm_get_dynpm_state(rdev); 733 radeon_pm_set_clocks(rdev); 734 } 735 } 736 } 737 } 738 739 mutex_unlock(&rdev->pm.mutex); 740 } 741 742 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 743 { 744 int crtc, vpos, hpos, vbl_status; 745 bool in_vbl = true; 746 747 /* Iterate over all active crtc's. All crtc's must be in vblank, 748 * otherwise return in_vbl == false. 749 */ 750 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 751 if (rdev->pm.active_crtcs & (1 << crtc)) { 752 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos); 753 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 754 !(vbl_status & DRM_SCANOUTPOS_INVBL)) 755 in_vbl = false; 756 } 757 } 758 759 return in_vbl; 760 } 761 762 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 763 { 764 u32 stat_crtc = 0; 765 bool in_vbl = radeon_pm_in_vbl(rdev); 766 767 if (in_vbl == false) 768 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 769 finish ? "exit" : "entry"); 770 return in_vbl; 771 } 772 773 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 774 { 775 struct radeon_device *rdev; 776 int resched; 777 rdev = container_of(work, struct radeon_device, 778 pm.dynpm_idle_work.work); 779 780 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 781 mutex_lock(&rdev->pm.mutex); 782 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 783 int not_processed = 0; 784 int i; 785 786 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 787 struct radeon_ring *ring = &rdev->ring[i]; 788 789 if (ring->ready) { 790 not_processed += radeon_fence_count_emitted(rdev, i); 791 if (not_processed >= 3) 792 break; 793 } 794 } 795 796 if (not_processed >= 3) { /* should upclock */ 797 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 798 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 799 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 800 rdev->pm.dynpm_can_upclock) { 801 rdev->pm.dynpm_planned_action = 802 DYNPM_ACTION_UPCLOCK; 803 rdev->pm.dynpm_action_timeout = jiffies + 804 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 805 } 806 } else if (not_processed == 0) { /* should downclock */ 807 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 808 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 809 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 810 rdev->pm.dynpm_can_downclock) { 811 rdev->pm.dynpm_planned_action = 812 DYNPM_ACTION_DOWNCLOCK; 813 rdev->pm.dynpm_action_timeout = jiffies + 814 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 815 } 816 } 817 818 /* Note, radeon_pm_set_clocks is called with static_switch set 819 * to false since we want to wait for vbl to avoid flicker. 820 */ 821 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 822 jiffies > rdev->pm.dynpm_action_timeout) { 823 radeon_pm_get_dynpm_state(rdev); 824 radeon_pm_set_clocks(rdev); 825 } 826 827 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 828 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 829 } 830 mutex_unlock(&rdev->pm.mutex); 831 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 832 } 833 834 /* 835 * Debugfs info 836 */ 837 #if defined(CONFIG_DEBUG_FS) 838 839 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 840 { 841 struct drm_info_node *node = (struct drm_info_node *) m->private; 842 struct drm_device *dev = node->minor->dev; 843 struct radeon_device *rdev = dev->dev_private; 844 845 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 846 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 847 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 848 if (rdev->asic->pm.get_memory_clock) 849 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 850 if (rdev->pm.current_vddc) 851 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 852 if (rdev->asic->pm.get_pcie_lanes) 853 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 854 855 return 0; 856 } 857 858 static struct drm_info_list radeon_pm_info_list[] = { 859 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 860 }; 861 #endif 862 863 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 864 { 865 #if defined(CONFIG_DEBUG_FS) 866 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 867 #else 868 return 0; 869 #endif 870 } 871