1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 #include <linux/hwmon-sysfs.h> 31 32 #define RADEON_IDLE_LOOP_MS 100 33 #define RADEON_RECLOCK_DELAY_MS 200 34 #define RADEON_WAIT_VBLANK_TIMEOUT 200 35 36 static const char *radeon_pm_state_type_name[5] = { 37 "", 38 "Powersave", 39 "Battery", 40 "Balanced", 41 "Performance", 42 }; 43 44 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 45 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 46 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 48 static void radeon_pm_update_profile(struct radeon_device *rdev); 49 static void radeon_pm_set_clocks(struct radeon_device *rdev); 50 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev); 51 52 int radeon_pm_get_type_index(struct radeon_device *rdev, 53 enum radeon_pm_state_type ps_type, 54 int instance) 55 { 56 int i; 57 int found_instance = -1; 58 59 for (i = 0; i < rdev->pm.num_power_states; i++) { 60 if (rdev->pm.power_state[i].type == ps_type) { 61 found_instance++; 62 if (found_instance == instance) 63 return i; 64 } 65 } 66 /* return default if no match */ 67 return rdev->pm.default_power_state_index; 68 } 69 70 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 71 { 72 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 73 mutex_lock(&rdev->pm.mutex); 74 if (power_supply_is_system_supplied() > 0) 75 rdev->pm.dpm.ac_power = true; 76 else 77 rdev->pm.dpm.ac_power = false; 78 if (rdev->family == CHIP_ARUBA) { 79 if (rdev->asic->dpm.enable_bapm) 80 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 81 } 82 mutex_unlock(&rdev->pm.mutex); 83 /* allow new DPM state to be picked */ 84 radeon_pm_compute_clocks_dpm(rdev); 85 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 86 if (rdev->pm.profile == PM_PROFILE_AUTO) { 87 mutex_lock(&rdev->pm.mutex); 88 radeon_pm_update_profile(rdev); 89 radeon_pm_set_clocks(rdev); 90 mutex_unlock(&rdev->pm.mutex); 91 } 92 } 93 } 94 95 static void radeon_pm_update_profile(struct radeon_device *rdev) 96 { 97 switch (rdev->pm.profile) { 98 case PM_PROFILE_DEFAULT: 99 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 100 break; 101 case PM_PROFILE_AUTO: 102 if (power_supply_is_system_supplied() > 0) { 103 if (rdev->pm.active_crtc_count > 1) 104 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 105 else 106 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 107 } else { 108 if (rdev->pm.active_crtc_count > 1) 109 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 110 else 111 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 112 } 113 break; 114 case PM_PROFILE_LOW: 115 if (rdev->pm.active_crtc_count > 1) 116 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 117 else 118 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 119 break; 120 case PM_PROFILE_MID: 121 if (rdev->pm.active_crtc_count > 1) 122 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 123 else 124 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 125 break; 126 case PM_PROFILE_HIGH: 127 if (rdev->pm.active_crtc_count > 1) 128 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 129 else 130 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 131 break; 132 } 133 134 if (rdev->pm.active_crtc_count == 0) { 135 rdev->pm.requested_power_state_index = 136 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 137 rdev->pm.requested_clock_mode_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 139 } else { 140 rdev->pm.requested_power_state_index = 141 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 142 rdev->pm.requested_clock_mode_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 144 } 145 } 146 147 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 148 { 149 struct radeon_bo *bo, *n; 150 151 if (list_empty(&rdev->gem.objects)) 152 return; 153 154 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 155 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 156 ttm_bo_unmap_virtual(&bo->tbo); 157 } 158 } 159 160 static void radeon_sync_with_vblank(struct radeon_device *rdev) 161 { 162 if (rdev->pm.active_crtcs) { 163 rdev->pm.vblank_sync = false; 164 wait_event_timeout( 165 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 166 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 167 } 168 } 169 170 static void radeon_set_power_state(struct radeon_device *rdev) 171 { 172 u32 sclk, mclk; 173 bool misc_after = false; 174 175 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 176 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 177 return; 178 179 if (radeon_gui_idle(rdev)) { 180 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 181 clock_info[rdev->pm.requested_clock_mode_index].sclk; 182 if (sclk > rdev->pm.default_sclk) 183 sclk = rdev->pm.default_sclk; 184 185 /* starting with BTC, there is one state that is used for both 186 * MH and SH. Difference is that we always use the high clock index for 187 * mclk and vddci. 188 */ 189 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 190 (rdev->family >= CHIP_BARTS) && 191 rdev->pm.active_crtc_count && 192 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 193 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 195 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 196 else 197 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 198 clock_info[rdev->pm.requested_clock_mode_index].mclk; 199 200 if (mclk > rdev->pm.default_mclk) 201 mclk = rdev->pm.default_mclk; 202 203 /* upvolt before raising clocks, downvolt after lowering clocks */ 204 if (sclk < rdev->pm.current_sclk) 205 misc_after = true; 206 207 radeon_sync_with_vblank(rdev); 208 209 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 210 if (!radeon_pm_in_vbl(rdev)) 211 return; 212 } 213 214 radeon_pm_prepare(rdev); 215 216 if (!misc_after) 217 /* voltage, pcie lanes, etc.*/ 218 radeon_pm_misc(rdev); 219 220 /* set engine clock */ 221 if (sclk != rdev->pm.current_sclk) { 222 radeon_pm_debug_check_in_vbl(rdev, false); 223 radeon_set_engine_clock(rdev, sclk); 224 radeon_pm_debug_check_in_vbl(rdev, true); 225 rdev->pm.current_sclk = sclk; 226 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 227 } 228 229 /* set memory clock */ 230 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 231 radeon_pm_debug_check_in_vbl(rdev, false); 232 radeon_set_memory_clock(rdev, mclk); 233 radeon_pm_debug_check_in_vbl(rdev, true); 234 rdev->pm.current_mclk = mclk; 235 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 236 } 237 238 if (misc_after) 239 /* voltage, pcie lanes, etc.*/ 240 radeon_pm_misc(rdev); 241 242 radeon_pm_finish(rdev); 243 244 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 245 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 246 } else 247 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 248 } 249 250 static void radeon_pm_set_clocks(struct radeon_device *rdev) 251 { 252 struct drm_crtc *crtc; 253 int i, r; 254 255 /* no need to take locks, etc. if nothing's going to change */ 256 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 257 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 258 return; 259 260 down_write(&rdev->pm.mclk_lock); 261 mutex_lock(&rdev->ring_lock); 262 263 /* wait for the rings to drain */ 264 for (i = 0; i < RADEON_NUM_RINGS; i++) { 265 struct radeon_ring *ring = &rdev->ring[i]; 266 if (!ring->ready) { 267 continue; 268 } 269 r = radeon_fence_wait_empty(rdev, i); 270 if (r) { 271 /* needs a GPU reset dont reset here */ 272 mutex_unlock(&rdev->ring_lock); 273 up_write(&rdev->pm.mclk_lock); 274 return; 275 } 276 } 277 278 radeon_unmap_vram_bos(rdev); 279 280 if (rdev->irq.installed) { 281 i = 0; 282 drm_for_each_crtc(crtc, rdev->ddev) { 283 if (rdev->pm.active_crtcs & (1 << i)) { 284 /* This can fail if a modeset is in progress */ 285 if (drm_crtc_vblank_get(crtc) == 0) 286 rdev->pm.req_vblank |= (1 << i); 287 else 288 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 289 i); 290 } 291 i++; 292 } 293 } 294 295 radeon_set_power_state(rdev); 296 297 if (rdev->irq.installed) { 298 i = 0; 299 drm_for_each_crtc(crtc, rdev->ddev) { 300 if (rdev->pm.req_vblank & (1 << i)) { 301 rdev->pm.req_vblank &= ~(1 << i); 302 drm_crtc_vblank_put(crtc); 303 } 304 i++; 305 } 306 } 307 308 /* update display watermarks based on new power state */ 309 radeon_update_bandwidth_info(rdev); 310 if (rdev->pm.active_crtc_count) 311 radeon_bandwidth_update(rdev); 312 313 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 314 315 mutex_unlock(&rdev->ring_lock); 316 up_write(&rdev->pm.mclk_lock); 317 } 318 319 static void radeon_pm_print_states(struct radeon_device *rdev) 320 { 321 int i, j; 322 struct radeon_power_state *power_state; 323 struct radeon_pm_clock_info *clock_info; 324 325 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 326 for (i = 0; i < rdev->pm.num_power_states; i++) { 327 power_state = &rdev->pm.power_state[i]; 328 DRM_DEBUG_DRIVER("State %d: %s\n", i, 329 radeon_pm_state_type_name[power_state->type]); 330 if (i == rdev->pm.default_power_state_index) 331 DRM_DEBUG_DRIVER("\tDefault"); 332 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 333 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 334 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 335 DRM_DEBUG_DRIVER("\tSingle display only\n"); 336 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 337 for (j = 0; j < power_state->num_clock_modes; j++) { 338 clock_info = &(power_state->clock_info[j]); 339 if (rdev->flags & RADEON_IS_IGP) 340 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 341 j, 342 clock_info->sclk * 10); 343 else 344 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 345 j, 346 clock_info->sclk * 10, 347 clock_info->mclk * 10, 348 clock_info->voltage.voltage); 349 } 350 } 351 } 352 353 static ssize_t radeon_get_pm_profile(struct device *dev, 354 struct device_attribute *attr, 355 char *buf) 356 { 357 struct drm_device *ddev = dev_get_drvdata(dev); 358 struct radeon_device *rdev = ddev->dev_private; 359 int cp = rdev->pm.profile; 360 361 return snprintf(buf, PAGE_SIZE, "%s\n", 362 (cp == PM_PROFILE_AUTO) ? "auto" : 363 (cp == PM_PROFILE_LOW) ? "low" : 364 (cp == PM_PROFILE_MID) ? "mid" : 365 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 366 } 367 368 static ssize_t radeon_set_pm_profile(struct device *dev, 369 struct device_attribute *attr, 370 const char *buf, 371 size_t count) 372 { 373 struct drm_device *ddev = dev_get_drvdata(dev); 374 struct radeon_device *rdev = ddev->dev_private; 375 376 /* Can't set profile when the card is off */ 377 if ((rdev->flags & RADEON_IS_PX) && 378 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 379 return -EINVAL; 380 381 mutex_lock(&rdev->pm.mutex); 382 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 383 if (strncmp("default", buf, strlen("default")) == 0) 384 rdev->pm.profile = PM_PROFILE_DEFAULT; 385 else if (strncmp("auto", buf, strlen("auto")) == 0) 386 rdev->pm.profile = PM_PROFILE_AUTO; 387 else if (strncmp("low", buf, strlen("low")) == 0) 388 rdev->pm.profile = PM_PROFILE_LOW; 389 else if (strncmp("mid", buf, strlen("mid")) == 0) 390 rdev->pm.profile = PM_PROFILE_MID; 391 else if (strncmp("high", buf, strlen("high")) == 0) 392 rdev->pm.profile = PM_PROFILE_HIGH; 393 else { 394 count = -EINVAL; 395 goto fail; 396 } 397 radeon_pm_update_profile(rdev); 398 radeon_pm_set_clocks(rdev); 399 } else 400 count = -EINVAL; 401 402 fail: 403 mutex_unlock(&rdev->pm.mutex); 404 405 return count; 406 } 407 408 static ssize_t radeon_get_pm_method(struct device *dev, 409 struct device_attribute *attr, 410 char *buf) 411 { 412 struct drm_device *ddev = dev_get_drvdata(dev); 413 struct radeon_device *rdev = ddev->dev_private; 414 int pm = rdev->pm.pm_method; 415 416 return snprintf(buf, PAGE_SIZE, "%s\n", 417 (pm == PM_METHOD_DYNPM) ? "dynpm" : 418 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 419 } 420 421 static ssize_t radeon_set_pm_method(struct device *dev, 422 struct device_attribute *attr, 423 const char *buf, 424 size_t count) 425 { 426 struct drm_device *ddev = dev_get_drvdata(dev); 427 struct radeon_device *rdev = ddev->dev_private; 428 429 /* Can't set method when the card is off */ 430 if ((rdev->flags & RADEON_IS_PX) && 431 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 432 count = -EINVAL; 433 goto fail; 434 } 435 436 /* we don't support the legacy modes with dpm */ 437 if (rdev->pm.pm_method == PM_METHOD_DPM) { 438 count = -EINVAL; 439 goto fail; 440 } 441 442 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 443 mutex_lock(&rdev->pm.mutex); 444 rdev->pm.pm_method = PM_METHOD_DYNPM; 445 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 446 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 447 mutex_unlock(&rdev->pm.mutex); 448 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 449 mutex_lock(&rdev->pm.mutex); 450 /* disable dynpm */ 451 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 453 rdev->pm.pm_method = PM_METHOD_PROFILE; 454 mutex_unlock(&rdev->pm.mutex); 455 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 456 } else { 457 count = -EINVAL; 458 goto fail; 459 } 460 radeon_pm_compute_clocks(rdev); 461 fail: 462 return count; 463 } 464 465 static ssize_t radeon_get_dpm_state(struct device *dev, 466 struct device_attribute *attr, 467 char *buf) 468 { 469 struct drm_device *ddev = dev_get_drvdata(dev); 470 struct radeon_device *rdev = ddev->dev_private; 471 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 472 473 return snprintf(buf, PAGE_SIZE, "%s\n", 474 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 475 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 476 } 477 478 static ssize_t radeon_set_dpm_state(struct device *dev, 479 struct device_attribute *attr, 480 const char *buf, 481 size_t count) 482 { 483 struct drm_device *ddev = dev_get_drvdata(dev); 484 struct radeon_device *rdev = ddev->dev_private; 485 486 mutex_lock(&rdev->pm.mutex); 487 if (strncmp("battery", buf, strlen("battery")) == 0) 488 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 489 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 491 else if (strncmp("performance", buf, strlen("performance")) == 0) 492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 493 else { 494 mutex_unlock(&rdev->pm.mutex); 495 count = -EINVAL; 496 goto fail; 497 } 498 mutex_unlock(&rdev->pm.mutex); 499 500 /* Can't set dpm state when the card is off */ 501 if (!(rdev->flags & RADEON_IS_PX) || 502 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 503 radeon_pm_compute_clocks(rdev); 504 505 fail: 506 return count; 507 } 508 509 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 510 struct device_attribute *attr, 511 char *buf) 512 { 513 struct drm_device *ddev = dev_get_drvdata(dev); 514 struct radeon_device *rdev = ddev->dev_private; 515 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 516 517 if ((rdev->flags & RADEON_IS_PX) && 518 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 519 return snprintf(buf, PAGE_SIZE, "off\n"); 520 521 return snprintf(buf, PAGE_SIZE, "%s\n", 522 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 523 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 524 } 525 526 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 527 struct device_attribute *attr, 528 const char *buf, 529 size_t count) 530 { 531 struct drm_device *ddev = dev_get_drvdata(dev); 532 struct radeon_device *rdev = ddev->dev_private; 533 enum radeon_dpm_forced_level level; 534 int ret = 0; 535 536 /* Can't force performance level when the card is off */ 537 if ((rdev->flags & RADEON_IS_PX) && 538 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 539 return -EINVAL; 540 541 mutex_lock(&rdev->pm.mutex); 542 if (strncmp("low", buf, strlen("low")) == 0) { 543 level = RADEON_DPM_FORCED_LEVEL_LOW; 544 } else if (strncmp("high", buf, strlen("high")) == 0) { 545 level = RADEON_DPM_FORCED_LEVEL_HIGH; 546 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 547 level = RADEON_DPM_FORCED_LEVEL_AUTO; 548 } else { 549 count = -EINVAL; 550 goto fail; 551 } 552 if (rdev->asic->dpm.force_performance_level) { 553 if (rdev->pm.dpm.thermal_active) { 554 count = -EINVAL; 555 goto fail; 556 } 557 ret = radeon_dpm_force_performance_level(rdev, level); 558 if (ret) 559 count = -EINVAL; 560 } 561 fail: 562 mutex_unlock(&rdev->pm.mutex); 563 564 return count; 565 } 566 567 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 568 struct device_attribute *attr, 569 char *buf) 570 { 571 struct radeon_device *rdev = dev_get_drvdata(dev); 572 u32 pwm_mode = 0; 573 574 if (rdev->asic->dpm.fan_ctrl_get_mode) 575 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 576 577 /* never 0 (full-speed), fuse or smc-controlled always */ 578 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 579 } 580 581 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 582 struct device_attribute *attr, 583 const char *buf, 584 size_t count) 585 { 586 struct radeon_device *rdev = dev_get_drvdata(dev); 587 int err; 588 int value; 589 590 if(!rdev->asic->dpm.fan_ctrl_set_mode) 591 return -EINVAL; 592 593 err = kstrtoint(buf, 10, &value); 594 if (err) 595 return err; 596 597 switch (value) { 598 case 1: /* manual, percent-based */ 599 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 600 break; 601 default: /* disable */ 602 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 603 break; 604 } 605 606 return count; 607 } 608 609 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 610 struct device_attribute *attr, 611 char *buf) 612 { 613 return sprintf(buf, "%i\n", 0); 614 } 615 616 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 617 struct device_attribute *attr, 618 char *buf) 619 { 620 return sprintf(buf, "%i\n", 255); 621 } 622 623 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 624 struct device_attribute *attr, 625 const char *buf, size_t count) 626 { 627 struct radeon_device *rdev = dev_get_drvdata(dev); 628 int err; 629 u32 value; 630 631 err = kstrtou32(buf, 10, &value); 632 if (err) 633 return err; 634 635 value = (value * 100) / 255; 636 637 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 638 if (err) 639 return err; 640 641 return count; 642 } 643 644 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 645 struct device_attribute *attr, 646 char *buf) 647 { 648 struct radeon_device *rdev = dev_get_drvdata(dev); 649 int err; 650 u32 speed; 651 652 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 653 if (err) 654 return err; 655 656 speed = (speed * 255) / 100; 657 658 return sprintf(buf, "%i\n", speed); 659 } 660 661 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 662 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 663 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 664 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 665 radeon_get_dpm_forced_performance_level, 666 radeon_set_dpm_forced_performance_level); 667 668 static ssize_t radeon_hwmon_show_temp(struct device *dev, 669 struct device_attribute *attr, 670 char *buf) 671 { 672 struct radeon_device *rdev = dev_get_drvdata(dev); 673 struct drm_device *ddev = rdev->ddev; 674 int temp; 675 676 /* Can't get temperature when the card is off */ 677 if ((rdev->flags & RADEON_IS_PX) && 678 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 679 return -EINVAL; 680 681 if (rdev->asic->pm.get_temperature) 682 temp = radeon_get_temperature(rdev); 683 else 684 temp = 0; 685 686 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 687 } 688 689 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 690 struct device_attribute *attr, 691 char *buf) 692 { 693 struct radeon_device *rdev = dev_get_drvdata(dev); 694 int hyst = to_sensor_dev_attr(attr)->index; 695 int temp; 696 697 if (hyst) 698 temp = rdev->pm.dpm.thermal.min_temp; 699 else 700 temp = rdev->pm.dpm.thermal.max_temp; 701 702 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 703 } 704 705 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 706 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 707 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 708 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 709 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 710 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 711 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 712 713 714 static struct attribute *hwmon_attributes[] = { 715 &sensor_dev_attr_temp1_input.dev_attr.attr, 716 &sensor_dev_attr_temp1_crit.dev_attr.attr, 717 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 718 &sensor_dev_attr_pwm1.dev_attr.attr, 719 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 720 &sensor_dev_attr_pwm1_min.dev_attr.attr, 721 &sensor_dev_attr_pwm1_max.dev_attr.attr, 722 NULL 723 }; 724 725 static umode_t hwmon_attributes_visible(struct kobject *kobj, 726 struct attribute *attr, int index) 727 { 728 struct device *dev = kobj_to_dev(kobj); 729 struct radeon_device *rdev = dev_get_drvdata(dev); 730 umode_t effective_mode = attr->mode; 731 732 /* Skip attributes if DPM is not enabled */ 733 if (rdev->pm.pm_method != PM_METHOD_DPM && 734 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 735 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 736 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 737 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 738 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 739 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 740 return 0; 741 742 /* Skip fan attributes if fan is not present */ 743 if (rdev->pm.no_fan && 744 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 745 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 746 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 747 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 748 return 0; 749 750 /* mask fan attributes if we have no bindings for this asic to expose */ 751 if ((!rdev->asic->dpm.get_fan_speed_percent && 752 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 753 (!rdev->asic->dpm.fan_ctrl_get_mode && 754 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 755 effective_mode &= ~S_IRUGO; 756 757 if ((!rdev->asic->dpm.set_fan_speed_percent && 758 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 759 (!rdev->asic->dpm.fan_ctrl_set_mode && 760 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 761 effective_mode &= ~S_IWUSR; 762 763 /* hide max/min values if we can't both query and manage the fan */ 764 if ((!rdev->asic->dpm.set_fan_speed_percent && 765 !rdev->asic->dpm.get_fan_speed_percent) && 766 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 767 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 768 return 0; 769 770 return effective_mode; 771 } 772 773 static const struct attribute_group hwmon_attrgroup = { 774 .attrs = hwmon_attributes, 775 .is_visible = hwmon_attributes_visible, 776 }; 777 778 static const struct attribute_group *hwmon_groups[] = { 779 &hwmon_attrgroup, 780 NULL 781 }; 782 783 static int radeon_hwmon_init(struct radeon_device *rdev) 784 { 785 int err = 0; 786 787 switch (rdev->pm.int_thermal_type) { 788 case THERMAL_TYPE_RV6XX: 789 case THERMAL_TYPE_RV770: 790 case THERMAL_TYPE_EVERGREEN: 791 case THERMAL_TYPE_NI: 792 case THERMAL_TYPE_SUMO: 793 case THERMAL_TYPE_SI: 794 case THERMAL_TYPE_CI: 795 case THERMAL_TYPE_KV: 796 if (rdev->asic->pm.get_temperature == NULL) 797 return err; 798 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 799 "radeon", rdev, 800 hwmon_groups); 801 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 802 err = PTR_ERR(rdev->pm.int_hwmon_dev); 803 dev_err(rdev->dev, 804 "Unable to register hwmon device: %d\n", err); 805 } 806 break; 807 default: 808 break; 809 } 810 811 return err; 812 } 813 814 static void radeon_hwmon_fini(struct radeon_device *rdev) 815 { 816 if (rdev->pm.int_hwmon_dev) 817 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 818 } 819 820 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 821 { 822 struct radeon_device *rdev = 823 container_of(work, struct radeon_device, 824 pm.dpm.thermal.work); 825 /* switch to the thermal state */ 826 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 827 828 if (!rdev->pm.dpm_enabled) 829 return; 830 831 if (rdev->asic->pm.get_temperature) { 832 int temp = radeon_get_temperature(rdev); 833 834 if (temp < rdev->pm.dpm.thermal.min_temp) 835 /* switch back the user state */ 836 dpm_state = rdev->pm.dpm.user_state; 837 } else { 838 if (rdev->pm.dpm.thermal.high_to_low) 839 /* switch back the user state */ 840 dpm_state = rdev->pm.dpm.user_state; 841 } 842 mutex_lock(&rdev->pm.mutex); 843 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 844 rdev->pm.dpm.thermal_active = true; 845 else 846 rdev->pm.dpm.thermal_active = false; 847 rdev->pm.dpm.state = dpm_state; 848 mutex_unlock(&rdev->pm.mutex); 849 850 radeon_pm_compute_clocks(rdev); 851 } 852 853 static bool radeon_dpm_single_display(struct radeon_device *rdev) 854 { 855 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 856 true : false; 857 858 /* check if the vblank period is too short to adjust the mclk */ 859 if (single_display && rdev->asic->dpm.vblank_too_short) { 860 if (radeon_dpm_vblank_too_short(rdev)) 861 single_display = false; 862 } 863 864 /* 120hz tends to be problematic even if they are under the 865 * vblank limit. 866 */ 867 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 868 single_display = false; 869 870 return single_display; 871 } 872 873 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 874 enum radeon_pm_state_type dpm_state) 875 { 876 int i; 877 struct radeon_ps *ps; 878 u32 ui_class; 879 bool single_display = radeon_dpm_single_display(rdev); 880 881 /* certain older asics have a separare 3D performance state, 882 * so try that first if the user selected performance 883 */ 884 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 885 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 886 /* balanced states don't exist at the moment */ 887 if (dpm_state == POWER_STATE_TYPE_BALANCED) 888 dpm_state = rdev->pm.dpm.ac_power ? 889 POWER_STATE_TYPE_PERFORMANCE : POWER_STATE_TYPE_BATTERY; 890 891 restart_search: 892 /* Pick the best power state based on current conditions */ 893 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 894 ps = &rdev->pm.dpm.ps[i]; 895 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 896 switch (dpm_state) { 897 /* user states */ 898 case POWER_STATE_TYPE_BATTERY: 899 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 900 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 901 if (single_display) 902 return ps; 903 } else 904 return ps; 905 } 906 break; 907 case POWER_STATE_TYPE_BALANCED: 908 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 909 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 910 if (single_display) 911 return ps; 912 } else 913 return ps; 914 } 915 break; 916 case POWER_STATE_TYPE_PERFORMANCE: 917 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 918 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 919 if (single_display) 920 return ps; 921 } else 922 return ps; 923 } 924 break; 925 /* internal states */ 926 case POWER_STATE_TYPE_INTERNAL_UVD: 927 if (rdev->pm.dpm.uvd_ps) 928 return rdev->pm.dpm.uvd_ps; 929 else 930 break; 931 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 932 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 933 return ps; 934 break; 935 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 936 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 937 return ps; 938 break; 939 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 940 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 941 return ps; 942 break; 943 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 944 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 945 return ps; 946 break; 947 case POWER_STATE_TYPE_INTERNAL_BOOT: 948 return rdev->pm.dpm.boot_ps; 949 case POWER_STATE_TYPE_INTERNAL_THERMAL: 950 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 951 return ps; 952 break; 953 case POWER_STATE_TYPE_INTERNAL_ACPI: 954 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 955 return ps; 956 break; 957 case POWER_STATE_TYPE_INTERNAL_ULV: 958 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 959 return ps; 960 break; 961 case POWER_STATE_TYPE_INTERNAL_3DPERF: 962 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 963 return ps; 964 break; 965 default: 966 break; 967 } 968 } 969 /* use a fallback state if we didn't match */ 970 switch (dpm_state) { 971 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 972 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 973 goto restart_search; 974 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 975 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 976 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 977 if (rdev->pm.dpm.uvd_ps) { 978 return rdev->pm.dpm.uvd_ps; 979 } else { 980 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 981 goto restart_search; 982 } 983 case POWER_STATE_TYPE_INTERNAL_THERMAL: 984 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 985 goto restart_search; 986 case POWER_STATE_TYPE_INTERNAL_ACPI: 987 dpm_state = POWER_STATE_TYPE_BATTERY; 988 goto restart_search; 989 case POWER_STATE_TYPE_BATTERY: 990 case POWER_STATE_TYPE_BALANCED: 991 case POWER_STATE_TYPE_INTERNAL_3DPERF: 992 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 993 goto restart_search; 994 default: 995 break; 996 } 997 998 return NULL; 999 } 1000 1001 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1002 { 1003 int i; 1004 struct radeon_ps *ps; 1005 enum radeon_pm_state_type dpm_state; 1006 int ret; 1007 bool single_display = radeon_dpm_single_display(rdev); 1008 1009 /* if dpm init failed */ 1010 if (!rdev->pm.dpm_enabled) 1011 return; 1012 1013 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1014 /* add other state override checks here */ 1015 if ((!rdev->pm.dpm.thermal_active) && 1016 (!rdev->pm.dpm.uvd_active)) 1017 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1018 } 1019 dpm_state = rdev->pm.dpm.state; 1020 1021 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1022 if (ps) 1023 rdev->pm.dpm.requested_ps = ps; 1024 else 1025 return; 1026 1027 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1028 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1029 /* vce just modifies an existing state so force a change */ 1030 if (ps->vce_active != rdev->pm.dpm.vce_active) 1031 goto force; 1032 /* user has made a display change (such as timing) */ 1033 if (rdev->pm.dpm.single_display != single_display) 1034 goto force; 1035 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1036 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1037 * all we need to do is update the display configuration. 1038 */ 1039 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1040 /* update display watermarks based on new power state */ 1041 radeon_bandwidth_update(rdev); 1042 /* update displays */ 1043 radeon_dpm_display_configuration_changed(rdev); 1044 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1045 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1046 } 1047 return; 1048 } else { 1049 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1050 * nothing to do, if the num crtcs is > 1 and state is the same, 1051 * update display configuration. 1052 */ 1053 if (rdev->pm.dpm.new_active_crtcs == 1054 rdev->pm.dpm.current_active_crtcs) { 1055 return; 1056 } else { 1057 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1058 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1059 /* update display watermarks based on new power state */ 1060 radeon_bandwidth_update(rdev); 1061 /* update displays */ 1062 radeon_dpm_display_configuration_changed(rdev); 1063 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1064 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1065 return; 1066 } 1067 } 1068 } 1069 } 1070 1071 force: 1072 if (radeon_dpm == 1) { 1073 printk("switching from power state:\n"); 1074 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1075 printk("switching to power state:\n"); 1076 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1077 } 1078 1079 down_write(&rdev->pm.mclk_lock); 1080 mutex_lock(&rdev->ring_lock); 1081 1082 /* update whether vce is active */ 1083 ps->vce_active = rdev->pm.dpm.vce_active; 1084 1085 ret = radeon_dpm_pre_set_power_state(rdev); 1086 if (ret) 1087 goto done; 1088 1089 /* update display watermarks based on new power state */ 1090 radeon_bandwidth_update(rdev); 1091 /* update displays */ 1092 radeon_dpm_display_configuration_changed(rdev); 1093 1094 /* wait for the rings to drain */ 1095 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1096 struct radeon_ring *ring = &rdev->ring[i]; 1097 if (ring->ready) 1098 radeon_fence_wait_empty(rdev, i); 1099 } 1100 1101 /* program the new power state */ 1102 radeon_dpm_set_power_state(rdev); 1103 1104 /* update current power state */ 1105 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1106 1107 radeon_dpm_post_set_power_state(rdev); 1108 1109 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1110 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1111 rdev->pm.dpm.single_display = single_display; 1112 1113 if (rdev->asic->dpm.force_performance_level) { 1114 if (rdev->pm.dpm.thermal_active) { 1115 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1116 /* force low perf level for thermal */ 1117 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1118 /* save the user's level */ 1119 rdev->pm.dpm.forced_level = level; 1120 } else { 1121 /* otherwise, user selected level */ 1122 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1123 } 1124 } 1125 1126 done: 1127 mutex_unlock(&rdev->ring_lock); 1128 up_write(&rdev->pm.mclk_lock); 1129 } 1130 1131 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1132 { 1133 enum radeon_pm_state_type dpm_state; 1134 1135 if (rdev->asic->dpm.powergate_uvd) { 1136 mutex_lock(&rdev->pm.mutex); 1137 /* don't powergate anything if we 1138 have active but pause streams */ 1139 enable |= rdev->pm.dpm.sd > 0; 1140 enable |= rdev->pm.dpm.hd > 0; 1141 /* enable/disable UVD */ 1142 radeon_dpm_powergate_uvd(rdev, !enable); 1143 mutex_unlock(&rdev->pm.mutex); 1144 } else { 1145 if (enable) { 1146 mutex_lock(&rdev->pm.mutex); 1147 rdev->pm.dpm.uvd_active = true; 1148 /* disable this for now */ 1149 #if 0 1150 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1151 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1152 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1153 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1154 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1155 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1156 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1157 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1158 else 1159 #endif 1160 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1161 rdev->pm.dpm.state = dpm_state; 1162 mutex_unlock(&rdev->pm.mutex); 1163 } else { 1164 mutex_lock(&rdev->pm.mutex); 1165 rdev->pm.dpm.uvd_active = false; 1166 mutex_unlock(&rdev->pm.mutex); 1167 } 1168 1169 radeon_pm_compute_clocks(rdev); 1170 } 1171 } 1172 1173 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1174 { 1175 if (enable) { 1176 mutex_lock(&rdev->pm.mutex); 1177 rdev->pm.dpm.vce_active = true; 1178 /* XXX select vce level based on ring/task */ 1179 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1180 mutex_unlock(&rdev->pm.mutex); 1181 } else { 1182 mutex_lock(&rdev->pm.mutex); 1183 rdev->pm.dpm.vce_active = false; 1184 mutex_unlock(&rdev->pm.mutex); 1185 } 1186 1187 radeon_pm_compute_clocks(rdev); 1188 } 1189 1190 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1191 { 1192 mutex_lock(&rdev->pm.mutex); 1193 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1194 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1195 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1196 } 1197 mutex_unlock(&rdev->pm.mutex); 1198 1199 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1200 } 1201 1202 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1203 { 1204 mutex_lock(&rdev->pm.mutex); 1205 /* disable dpm */ 1206 radeon_dpm_disable(rdev); 1207 /* reset the power state */ 1208 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1209 rdev->pm.dpm_enabled = false; 1210 mutex_unlock(&rdev->pm.mutex); 1211 } 1212 1213 void radeon_pm_suspend(struct radeon_device *rdev) 1214 { 1215 if (rdev->pm.pm_method == PM_METHOD_DPM) 1216 radeon_pm_suspend_dpm(rdev); 1217 else 1218 radeon_pm_suspend_old(rdev); 1219 } 1220 1221 static void radeon_pm_resume_old(struct radeon_device *rdev) 1222 { 1223 /* set up the default clocks if the MC ucode is loaded */ 1224 if ((rdev->family >= CHIP_BARTS) && 1225 (rdev->family <= CHIP_CAYMAN) && 1226 rdev->mc_fw) { 1227 if (rdev->pm.default_vddc) 1228 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1229 SET_VOLTAGE_TYPE_ASIC_VDDC); 1230 if (rdev->pm.default_vddci) 1231 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1232 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1233 if (rdev->pm.default_sclk) 1234 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1235 if (rdev->pm.default_mclk) 1236 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1237 } 1238 /* asic init will reset the default power state */ 1239 mutex_lock(&rdev->pm.mutex); 1240 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1241 rdev->pm.current_clock_mode_index = 0; 1242 rdev->pm.current_sclk = rdev->pm.default_sclk; 1243 rdev->pm.current_mclk = rdev->pm.default_mclk; 1244 if (rdev->pm.power_state) { 1245 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1246 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1247 } 1248 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1249 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1250 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1251 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1252 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1253 } 1254 mutex_unlock(&rdev->pm.mutex); 1255 radeon_pm_compute_clocks(rdev); 1256 } 1257 1258 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1259 { 1260 int ret; 1261 1262 /* asic init will reset to the boot state */ 1263 mutex_lock(&rdev->pm.mutex); 1264 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1265 radeon_dpm_setup_asic(rdev); 1266 ret = radeon_dpm_enable(rdev); 1267 mutex_unlock(&rdev->pm.mutex); 1268 if (ret) 1269 goto dpm_resume_fail; 1270 rdev->pm.dpm_enabled = true; 1271 return; 1272 1273 dpm_resume_fail: 1274 DRM_ERROR("radeon: dpm resume failed\n"); 1275 if ((rdev->family >= CHIP_BARTS) && 1276 (rdev->family <= CHIP_CAYMAN) && 1277 rdev->mc_fw) { 1278 if (rdev->pm.default_vddc) 1279 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1280 SET_VOLTAGE_TYPE_ASIC_VDDC); 1281 if (rdev->pm.default_vddci) 1282 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1283 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1284 if (rdev->pm.default_sclk) 1285 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1286 if (rdev->pm.default_mclk) 1287 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1288 } 1289 } 1290 1291 void radeon_pm_resume(struct radeon_device *rdev) 1292 { 1293 if (rdev->pm.pm_method == PM_METHOD_DPM) 1294 radeon_pm_resume_dpm(rdev); 1295 else 1296 radeon_pm_resume_old(rdev); 1297 } 1298 1299 static int radeon_pm_init_old(struct radeon_device *rdev) 1300 { 1301 int ret; 1302 1303 rdev->pm.profile = PM_PROFILE_DEFAULT; 1304 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1305 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1306 rdev->pm.dynpm_can_upclock = true; 1307 rdev->pm.dynpm_can_downclock = true; 1308 rdev->pm.default_sclk = rdev->clock.default_sclk; 1309 rdev->pm.default_mclk = rdev->clock.default_mclk; 1310 rdev->pm.current_sclk = rdev->clock.default_sclk; 1311 rdev->pm.current_mclk = rdev->clock.default_mclk; 1312 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1313 1314 if (rdev->bios) { 1315 if (rdev->is_atom_bios) 1316 radeon_atombios_get_power_modes(rdev); 1317 else 1318 radeon_combios_get_power_modes(rdev); 1319 radeon_pm_print_states(rdev); 1320 radeon_pm_init_profile(rdev); 1321 /* set up the default clocks if the MC ucode is loaded */ 1322 if ((rdev->family >= CHIP_BARTS) && 1323 (rdev->family <= CHIP_CAYMAN) && 1324 rdev->mc_fw) { 1325 if (rdev->pm.default_vddc) 1326 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1327 SET_VOLTAGE_TYPE_ASIC_VDDC); 1328 if (rdev->pm.default_vddci) 1329 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1330 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1331 if (rdev->pm.default_sclk) 1332 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1333 if (rdev->pm.default_mclk) 1334 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1335 } 1336 } 1337 1338 /* set up the internal thermal sensor if applicable */ 1339 ret = radeon_hwmon_init(rdev); 1340 if (ret) 1341 return ret; 1342 1343 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1344 1345 if (rdev->pm.num_power_states > 1) { 1346 if (radeon_debugfs_pm_init(rdev)) { 1347 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1348 } 1349 1350 DRM_INFO("radeon: power management initialized\n"); 1351 } 1352 1353 return 0; 1354 } 1355 1356 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1357 { 1358 int i; 1359 1360 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1361 printk("== power state %d ==\n", i); 1362 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1363 } 1364 } 1365 1366 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1367 { 1368 int ret; 1369 1370 /* default to balanced state */ 1371 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1372 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1373 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1374 rdev->pm.default_sclk = rdev->clock.default_sclk; 1375 rdev->pm.default_mclk = rdev->clock.default_mclk; 1376 rdev->pm.current_sclk = rdev->clock.default_sclk; 1377 rdev->pm.current_mclk = rdev->clock.default_mclk; 1378 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1379 1380 if (rdev->bios && rdev->is_atom_bios) 1381 radeon_atombios_get_power_modes(rdev); 1382 else 1383 return -EINVAL; 1384 1385 /* set up the internal thermal sensor if applicable */ 1386 ret = radeon_hwmon_init(rdev); 1387 if (ret) 1388 return ret; 1389 1390 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1391 mutex_lock(&rdev->pm.mutex); 1392 radeon_dpm_init(rdev); 1393 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1394 if (radeon_dpm == 1) 1395 radeon_dpm_print_power_states(rdev); 1396 radeon_dpm_setup_asic(rdev); 1397 ret = radeon_dpm_enable(rdev); 1398 mutex_unlock(&rdev->pm.mutex); 1399 if (ret) 1400 goto dpm_failed; 1401 rdev->pm.dpm_enabled = true; 1402 1403 if (radeon_debugfs_pm_init(rdev)) { 1404 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1405 } 1406 1407 DRM_INFO("radeon: dpm initialized\n"); 1408 1409 return 0; 1410 1411 dpm_failed: 1412 rdev->pm.dpm_enabled = false; 1413 if ((rdev->family >= CHIP_BARTS) && 1414 (rdev->family <= CHIP_CAYMAN) && 1415 rdev->mc_fw) { 1416 if (rdev->pm.default_vddc) 1417 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1418 SET_VOLTAGE_TYPE_ASIC_VDDC); 1419 if (rdev->pm.default_vddci) 1420 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1421 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1422 if (rdev->pm.default_sclk) 1423 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1424 if (rdev->pm.default_mclk) 1425 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1426 } 1427 DRM_ERROR("radeon: dpm initialization failed\n"); 1428 return ret; 1429 } 1430 1431 struct radeon_dpm_quirk { 1432 u32 chip_vendor; 1433 u32 chip_device; 1434 u32 subsys_vendor; 1435 u32 subsys_device; 1436 }; 1437 1438 /* cards with dpm stability problems */ 1439 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1440 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1441 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1442 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1443 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1444 { 0, 0, 0, 0 }, 1445 }; 1446 1447 int radeon_pm_init(struct radeon_device *rdev) 1448 { 1449 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1450 bool disable_dpm = false; 1451 1452 /* Apply dpm quirks */ 1453 while (p && p->chip_device != 0) { 1454 if (rdev->pdev->vendor == p->chip_vendor && 1455 rdev->pdev->device == p->chip_device && 1456 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1457 rdev->pdev->subsystem_device == p->subsys_device) { 1458 disable_dpm = true; 1459 break; 1460 } 1461 ++p; 1462 } 1463 1464 /* enable dpm on rv6xx+ */ 1465 switch (rdev->family) { 1466 case CHIP_RV610: 1467 case CHIP_RV630: 1468 case CHIP_RV620: 1469 case CHIP_RV635: 1470 case CHIP_RV670: 1471 case CHIP_RS780: 1472 case CHIP_RS880: 1473 case CHIP_RV770: 1474 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1475 if (!rdev->rlc_fw) 1476 rdev->pm.pm_method = PM_METHOD_PROFILE; 1477 else if ((rdev->family >= CHIP_RV770) && 1478 (!(rdev->flags & RADEON_IS_IGP)) && 1479 (!rdev->smc_fw)) 1480 rdev->pm.pm_method = PM_METHOD_PROFILE; 1481 else if (radeon_dpm == 1) 1482 rdev->pm.pm_method = PM_METHOD_DPM; 1483 else 1484 rdev->pm.pm_method = PM_METHOD_PROFILE; 1485 break; 1486 case CHIP_RV730: 1487 case CHIP_RV710: 1488 case CHIP_RV740: 1489 case CHIP_CEDAR: 1490 case CHIP_REDWOOD: 1491 case CHIP_JUNIPER: 1492 case CHIP_CYPRESS: 1493 case CHIP_HEMLOCK: 1494 case CHIP_PALM: 1495 case CHIP_SUMO: 1496 case CHIP_SUMO2: 1497 case CHIP_BARTS: 1498 case CHIP_TURKS: 1499 case CHIP_CAICOS: 1500 case CHIP_CAYMAN: 1501 case CHIP_ARUBA: 1502 case CHIP_TAHITI: 1503 case CHIP_PITCAIRN: 1504 case CHIP_VERDE: 1505 case CHIP_OLAND: 1506 case CHIP_HAINAN: 1507 case CHIP_BONAIRE: 1508 case CHIP_KABINI: 1509 case CHIP_KAVERI: 1510 case CHIP_HAWAII: 1511 case CHIP_MULLINS: 1512 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1513 if (!rdev->rlc_fw) 1514 rdev->pm.pm_method = PM_METHOD_PROFILE; 1515 else if ((rdev->family >= CHIP_RV770) && 1516 (!(rdev->flags & RADEON_IS_IGP)) && 1517 (!rdev->smc_fw)) 1518 rdev->pm.pm_method = PM_METHOD_PROFILE; 1519 else if (disable_dpm && (radeon_dpm == -1)) 1520 rdev->pm.pm_method = PM_METHOD_PROFILE; 1521 else if (radeon_dpm == 0) 1522 rdev->pm.pm_method = PM_METHOD_PROFILE; 1523 else 1524 rdev->pm.pm_method = PM_METHOD_DPM; 1525 break; 1526 default: 1527 /* default to profile method */ 1528 rdev->pm.pm_method = PM_METHOD_PROFILE; 1529 break; 1530 } 1531 1532 if (rdev->pm.pm_method == PM_METHOD_DPM) 1533 return radeon_pm_init_dpm(rdev); 1534 else 1535 return radeon_pm_init_old(rdev); 1536 } 1537 1538 int radeon_pm_late_init(struct radeon_device *rdev) 1539 { 1540 int ret = 0; 1541 1542 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1543 if (rdev->pm.dpm_enabled) { 1544 if (!rdev->pm.sysfs_initialized) { 1545 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1546 if (ret) 1547 DRM_ERROR("failed to create device file for dpm state\n"); 1548 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1549 if (ret) 1550 DRM_ERROR("failed to create device file for dpm state\n"); 1551 /* XXX: these are noops for dpm but are here for backwards compat */ 1552 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1553 if (ret) 1554 DRM_ERROR("failed to create device file for power profile\n"); 1555 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1556 if (ret) 1557 DRM_ERROR("failed to create device file for power method\n"); 1558 rdev->pm.sysfs_initialized = true; 1559 } 1560 1561 mutex_lock(&rdev->pm.mutex); 1562 ret = radeon_dpm_late_enable(rdev); 1563 mutex_unlock(&rdev->pm.mutex); 1564 if (ret) { 1565 rdev->pm.dpm_enabled = false; 1566 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1567 } else { 1568 /* set the dpm state for PX since there won't be 1569 * a modeset to call this. 1570 */ 1571 radeon_pm_compute_clocks(rdev); 1572 } 1573 } 1574 } else { 1575 if ((rdev->pm.num_power_states > 1) && 1576 (!rdev->pm.sysfs_initialized)) { 1577 /* where's the best place to put these? */ 1578 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1579 if (ret) 1580 DRM_ERROR("failed to create device file for power profile\n"); 1581 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1582 if (ret) 1583 DRM_ERROR("failed to create device file for power method\n"); 1584 if (!ret) 1585 rdev->pm.sysfs_initialized = true; 1586 } 1587 } 1588 return ret; 1589 } 1590 1591 static void radeon_pm_fini_old(struct radeon_device *rdev) 1592 { 1593 if (rdev->pm.num_power_states > 1) { 1594 mutex_lock(&rdev->pm.mutex); 1595 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1596 rdev->pm.profile = PM_PROFILE_DEFAULT; 1597 radeon_pm_update_profile(rdev); 1598 radeon_pm_set_clocks(rdev); 1599 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1600 /* reset default clocks */ 1601 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1602 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1603 radeon_pm_set_clocks(rdev); 1604 } 1605 mutex_unlock(&rdev->pm.mutex); 1606 1607 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1608 1609 device_remove_file(rdev->dev, &dev_attr_power_profile); 1610 device_remove_file(rdev->dev, &dev_attr_power_method); 1611 } 1612 1613 radeon_hwmon_fini(rdev); 1614 kfree(rdev->pm.power_state); 1615 } 1616 1617 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1618 { 1619 if (rdev->pm.num_power_states > 1) { 1620 mutex_lock(&rdev->pm.mutex); 1621 radeon_dpm_disable(rdev); 1622 mutex_unlock(&rdev->pm.mutex); 1623 1624 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1625 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1626 /* XXX backwards compat */ 1627 device_remove_file(rdev->dev, &dev_attr_power_profile); 1628 device_remove_file(rdev->dev, &dev_attr_power_method); 1629 } 1630 radeon_dpm_fini(rdev); 1631 1632 radeon_hwmon_fini(rdev); 1633 kfree(rdev->pm.power_state); 1634 } 1635 1636 void radeon_pm_fini(struct radeon_device *rdev) 1637 { 1638 if (rdev->pm.pm_method == PM_METHOD_DPM) 1639 radeon_pm_fini_dpm(rdev); 1640 else 1641 radeon_pm_fini_old(rdev); 1642 } 1643 1644 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1645 { 1646 struct drm_device *ddev = rdev->ddev; 1647 struct drm_crtc *crtc; 1648 struct radeon_crtc *radeon_crtc; 1649 1650 if (rdev->pm.num_power_states < 2) 1651 return; 1652 1653 mutex_lock(&rdev->pm.mutex); 1654 1655 rdev->pm.active_crtcs = 0; 1656 rdev->pm.active_crtc_count = 0; 1657 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1658 list_for_each_entry(crtc, 1659 &ddev->mode_config.crtc_list, head) { 1660 radeon_crtc = to_radeon_crtc(crtc); 1661 if (radeon_crtc->enabled) { 1662 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1663 rdev->pm.active_crtc_count++; 1664 } 1665 } 1666 } 1667 1668 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1669 radeon_pm_update_profile(rdev); 1670 radeon_pm_set_clocks(rdev); 1671 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1672 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1673 if (rdev->pm.active_crtc_count > 1) { 1674 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1675 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1676 1677 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1678 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1679 radeon_pm_get_dynpm_state(rdev); 1680 radeon_pm_set_clocks(rdev); 1681 1682 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1683 } 1684 } else if (rdev->pm.active_crtc_count == 1) { 1685 /* TODO: Increase clocks if needed for current mode */ 1686 1687 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1688 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1689 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1690 radeon_pm_get_dynpm_state(rdev); 1691 radeon_pm_set_clocks(rdev); 1692 1693 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1694 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1695 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1696 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1697 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1698 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1699 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1700 } 1701 } else { /* count == 0 */ 1702 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1703 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1704 1705 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1706 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1707 radeon_pm_get_dynpm_state(rdev); 1708 radeon_pm_set_clocks(rdev); 1709 } 1710 } 1711 } 1712 } 1713 1714 mutex_unlock(&rdev->pm.mutex); 1715 } 1716 1717 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1718 { 1719 struct drm_device *ddev = rdev->ddev; 1720 struct drm_crtc *crtc; 1721 struct radeon_crtc *radeon_crtc; 1722 1723 if (!rdev->pm.dpm_enabled) 1724 return; 1725 1726 mutex_lock(&rdev->pm.mutex); 1727 1728 /* update active crtc counts */ 1729 rdev->pm.dpm.new_active_crtcs = 0; 1730 rdev->pm.dpm.new_active_crtc_count = 0; 1731 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1732 list_for_each_entry(crtc, 1733 &ddev->mode_config.crtc_list, head) { 1734 radeon_crtc = to_radeon_crtc(crtc); 1735 if (crtc->enabled) { 1736 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1737 rdev->pm.dpm.new_active_crtc_count++; 1738 } 1739 } 1740 } 1741 1742 /* update battery/ac status */ 1743 if (power_supply_is_system_supplied() > 0) 1744 rdev->pm.dpm.ac_power = true; 1745 else 1746 rdev->pm.dpm.ac_power = false; 1747 1748 radeon_dpm_change_power_state_locked(rdev); 1749 1750 mutex_unlock(&rdev->pm.mutex); 1751 1752 } 1753 1754 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1755 { 1756 if (rdev->pm.pm_method == PM_METHOD_DPM) 1757 radeon_pm_compute_clocks_dpm(rdev); 1758 else 1759 radeon_pm_compute_clocks_old(rdev); 1760 } 1761 1762 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1763 { 1764 int crtc, vpos, hpos, vbl_status; 1765 bool in_vbl = true; 1766 1767 /* Iterate over all active crtc's. All crtc's must be in vblank, 1768 * otherwise return in_vbl == false. 1769 */ 1770 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1771 if (rdev->pm.active_crtcs & (1 << crtc)) { 1772 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1773 crtc, 1774 USE_REAL_VBLANKSTART, 1775 &vpos, &hpos, NULL, NULL, 1776 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1777 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1778 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1779 in_vbl = false; 1780 } 1781 } 1782 1783 return in_vbl; 1784 } 1785 1786 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1787 { 1788 u32 stat_crtc = 0; 1789 bool in_vbl = radeon_pm_in_vbl(rdev); 1790 1791 if (in_vbl == false) 1792 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1793 finish ? "exit" : "entry"); 1794 return in_vbl; 1795 } 1796 1797 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1798 { 1799 struct radeon_device *rdev; 1800 int resched; 1801 rdev = container_of(work, struct radeon_device, 1802 pm.dynpm_idle_work.work); 1803 1804 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1805 mutex_lock(&rdev->pm.mutex); 1806 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1807 int not_processed = 0; 1808 int i; 1809 1810 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1811 struct radeon_ring *ring = &rdev->ring[i]; 1812 1813 if (ring->ready) { 1814 not_processed += radeon_fence_count_emitted(rdev, i); 1815 if (not_processed >= 3) 1816 break; 1817 } 1818 } 1819 1820 if (not_processed >= 3) { /* should upclock */ 1821 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1822 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1823 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1824 rdev->pm.dynpm_can_upclock) { 1825 rdev->pm.dynpm_planned_action = 1826 DYNPM_ACTION_UPCLOCK; 1827 rdev->pm.dynpm_action_timeout = jiffies + 1828 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1829 } 1830 } else if (not_processed == 0) { /* should downclock */ 1831 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1832 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1833 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1834 rdev->pm.dynpm_can_downclock) { 1835 rdev->pm.dynpm_planned_action = 1836 DYNPM_ACTION_DOWNCLOCK; 1837 rdev->pm.dynpm_action_timeout = jiffies + 1838 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1839 } 1840 } 1841 1842 /* Note, radeon_pm_set_clocks is called with static_switch set 1843 * to false since we want to wait for vbl to avoid flicker. 1844 */ 1845 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1846 jiffies > rdev->pm.dynpm_action_timeout) { 1847 radeon_pm_get_dynpm_state(rdev); 1848 radeon_pm_set_clocks(rdev); 1849 } 1850 1851 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1852 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1853 } 1854 mutex_unlock(&rdev->pm.mutex); 1855 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1856 } 1857 1858 /* 1859 * Debugfs info 1860 */ 1861 #if defined(CONFIG_DEBUG_FS) 1862 1863 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1864 { 1865 struct drm_info_node *node = (struct drm_info_node *) m->private; 1866 struct drm_device *dev = node->minor->dev; 1867 struct radeon_device *rdev = dev->dev_private; 1868 struct drm_device *ddev = rdev->ddev; 1869 1870 if ((rdev->flags & RADEON_IS_PX) && 1871 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1872 seq_printf(m, "PX asic powered off\n"); 1873 } else if (rdev->pm.dpm_enabled) { 1874 mutex_lock(&rdev->pm.mutex); 1875 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1876 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1877 else 1878 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1879 mutex_unlock(&rdev->pm.mutex); 1880 } else { 1881 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1882 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1883 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1884 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1885 else 1886 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1887 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1888 if (rdev->asic->pm.get_memory_clock) 1889 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1890 if (rdev->pm.current_vddc) 1891 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1892 if (rdev->asic->pm.get_pcie_lanes) 1893 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1894 } 1895 1896 return 0; 1897 } 1898 1899 static struct drm_info_list radeon_pm_info_list[] = { 1900 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1901 }; 1902 #endif 1903 1904 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1905 { 1906 #if defined(CONFIG_DEBUG_FS) 1907 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1908 #else 1909 return 0; 1910 #endif 1911 } 1912