1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 24 #include <linux/hwmon-sysfs.h> 25 #include <linux/hwmon.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 29 #include <drm/drm_vblank.h> 30 31 #include "atom.h" 32 #include "avivod.h" 33 #include "r600_dpm.h" 34 #include "radeon.h" 35 #include "radeon_pm.h" 36 37 #define RADEON_IDLE_LOOP_MS 100 38 #define RADEON_RECLOCK_DELAY_MS 200 39 #define RADEON_WAIT_VBLANK_TIMEOUT 200 40 41 static const char *radeon_pm_state_type_name[5] = { 42 "", 43 "Powersave", 44 "Battery", 45 "Balanced", 46 "Performance", 47 }; 48 49 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 50 static void radeon_debugfs_pm_init(struct radeon_device *rdev); 51 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 53 static void radeon_pm_update_profile(struct radeon_device *rdev); 54 static void radeon_pm_set_clocks(struct radeon_device *rdev); 55 56 int radeon_pm_get_type_index(struct radeon_device *rdev, 57 enum radeon_pm_state_type ps_type, 58 int instance) 59 { 60 int i; 61 int found_instance = -1; 62 63 for (i = 0; i < rdev->pm.num_power_states; i++) { 64 if (rdev->pm.power_state[i].type == ps_type) { 65 found_instance++; 66 if (found_instance == instance) 67 return i; 68 } 69 } 70 /* return default if no match */ 71 return rdev->pm.default_power_state_index; 72 } 73 74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 75 { 76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 77 mutex_lock(&rdev->pm.mutex); 78 if (power_supply_is_system_supplied() > 0) 79 rdev->pm.dpm.ac_power = true; 80 else 81 rdev->pm.dpm.ac_power = false; 82 if (rdev->family == CHIP_ARUBA) { 83 if (rdev->asic->dpm.enable_bapm) 84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 85 } 86 mutex_unlock(&rdev->pm.mutex); 87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 88 if (rdev->pm.profile == PM_PROFILE_AUTO) { 89 mutex_lock(&rdev->pm.mutex); 90 radeon_pm_update_profile(rdev); 91 radeon_pm_set_clocks(rdev); 92 mutex_unlock(&rdev->pm.mutex); 93 } 94 } 95 } 96 97 static void radeon_pm_update_profile(struct radeon_device *rdev) 98 { 99 switch (rdev->pm.profile) { 100 case PM_PROFILE_DEFAULT: 101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 102 break; 103 case PM_PROFILE_AUTO: 104 if (power_supply_is_system_supplied() > 0) { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 109 } else { 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 } 115 break; 116 case PM_PROFILE_LOW: 117 if (rdev->pm.active_crtc_count > 1) 118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 119 else 120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 121 break; 122 case PM_PROFILE_MID: 123 if (rdev->pm.active_crtc_count > 1) 124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 125 else 126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 127 break; 128 case PM_PROFILE_HIGH: 129 if (rdev->pm.active_crtc_count > 1) 130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 131 else 132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 133 break; 134 } 135 136 if (rdev->pm.active_crtc_count == 0) { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 141 } else { 142 rdev->pm.requested_power_state_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 144 rdev->pm.requested_clock_mode_index = 145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 146 } 147 } 148 149 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 150 { 151 struct radeon_bo *bo, *n; 152 153 if (list_empty(&rdev->gem.objects)) 154 return; 155 156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 157 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 158 ttm_bo_unmap_virtual(&bo->tbo); 159 } 160 } 161 162 static void radeon_sync_with_vblank(struct radeon_device *rdev) 163 { 164 if (rdev->pm.active_crtcs) { 165 rdev->pm.vblank_sync = false; 166 wait_event_timeout( 167 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 168 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 169 } 170 } 171 172 static void radeon_set_power_state(struct radeon_device *rdev) 173 { 174 u32 sclk, mclk; 175 bool misc_after = false; 176 177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 179 return; 180 181 if (radeon_gui_idle(rdev)) { 182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 clock_info[rdev->pm.requested_clock_mode_index].sclk; 184 if (sclk > rdev->pm.default_sclk) 185 sclk = rdev->pm.default_sclk; 186 187 /* starting with BTC, there is one state that is used for both 188 * MH and SH. Difference is that we always use the high clock index for 189 * mclk and vddci. 190 */ 191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 192 (rdev->family >= CHIP_BARTS) && 193 rdev->pm.active_crtc_count && 194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 198 else 199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 200 clock_info[rdev->pm.requested_clock_mode_index].mclk; 201 202 if (mclk > rdev->pm.default_mclk) 203 mclk = rdev->pm.default_mclk; 204 205 /* upvolt before raising clocks, downvolt after lowering clocks */ 206 if (sclk < rdev->pm.current_sclk) 207 misc_after = true; 208 209 radeon_sync_with_vblank(rdev); 210 211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 212 if (!radeon_pm_in_vbl(rdev)) 213 return; 214 } 215 216 radeon_pm_prepare(rdev); 217 218 if (!misc_after) 219 /* voltage, pcie lanes, etc.*/ 220 radeon_pm_misc(rdev); 221 222 /* set engine clock */ 223 if (sclk != rdev->pm.current_sclk) { 224 radeon_pm_debug_check_in_vbl(rdev, false); 225 radeon_set_engine_clock(rdev, sclk); 226 radeon_pm_debug_check_in_vbl(rdev, true); 227 rdev->pm.current_sclk = sclk; 228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 229 } 230 231 /* set memory clock */ 232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 233 radeon_pm_debug_check_in_vbl(rdev, false); 234 radeon_set_memory_clock(rdev, mclk); 235 radeon_pm_debug_check_in_vbl(rdev, true); 236 rdev->pm.current_mclk = mclk; 237 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 238 } 239 240 if (misc_after) 241 /* voltage, pcie lanes, etc.*/ 242 radeon_pm_misc(rdev); 243 244 radeon_pm_finish(rdev); 245 246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 248 } else 249 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 250 } 251 252 static void radeon_pm_set_clocks(struct radeon_device *rdev) 253 { 254 struct drm_crtc *crtc; 255 int i, r; 256 257 /* no need to take locks, etc. if nothing's going to change */ 258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 260 return; 261 262 down_write(&rdev->pm.mclk_lock); 263 mutex_lock(&rdev->ring_lock); 264 265 /* wait for the rings to drain */ 266 for (i = 0; i < RADEON_NUM_RINGS; i++) { 267 struct radeon_ring *ring = &rdev->ring[i]; 268 if (!ring->ready) { 269 continue; 270 } 271 r = radeon_fence_wait_empty(rdev, i); 272 if (r) { 273 /* needs a GPU reset dont reset here */ 274 mutex_unlock(&rdev->ring_lock); 275 up_write(&rdev->pm.mclk_lock); 276 return; 277 } 278 } 279 280 radeon_unmap_vram_bos(rdev); 281 282 if (rdev->irq.installed) { 283 i = 0; 284 drm_for_each_crtc(crtc, rdev->ddev) { 285 if (rdev->pm.active_crtcs & (1 << i)) { 286 /* This can fail if a modeset is in progress */ 287 if (drm_crtc_vblank_get(crtc) == 0) 288 rdev->pm.req_vblank |= (1 << i); 289 else 290 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 291 i); 292 } 293 i++; 294 } 295 } 296 297 radeon_set_power_state(rdev); 298 299 if (rdev->irq.installed) { 300 i = 0; 301 drm_for_each_crtc(crtc, rdev->ddev) { 302 if (rdev->pm.req_vblank & (1 << i)) { 303 rdev->pm.req_vblank &= ~(1 << i); 304 drm_crtc_vblank_put(crtc); 305 } 306 i++; 307 } 308 } 309 310 /* update display watermarks based on new power state */ 311 radeon_update_bandwidth_info(rdev); 312 if (rdev->pm.active_crtc_count) 313 radeon_bandwidth_update(rdev); 314 315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 316 317 mutex_unlock(&rdev->ring_lock); 318 up_write(&rdev->pm.mclk_lock); 319 } 320 321 static void radeon_pm_print_states(struct radeon_device *rdev) 322 { 323 int i, j; 324 struct radeon_power_state *power_state; 325 struct radeon_pm_clock_info *clock_info; 326 327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 328 for (i = 0; i < rdev->pm.num_power_states; i++) { 329 power_state = &rdev->pm.power_state[i]; 330 DRM_DEBUG_DRIVER("State %d: %s\n", i, 331 radeon_pm_state_type_name[power_state->type]); 332 if (i == rdev->pm.default_power_state_index) 333 DRM_DEBUG_DRIVER("\tDefault"); 334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 336 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 337 DRM_DEBUG_DRIVER("\tSingle display only\n"); 338 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 339 for (j = 0; j < power_state->num_clock_modes; j++) { 340 clock_info = &(power_state->clock_info[j]); 341 if (rdev->flags & RADEON_IS_IGP) 342 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 343 j, 344 clock_info->sclk * 10); 345 else 346 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 347 j, 348 clock_info->sclk * 10, 349 clock_info->mclk * 10, 350 clock_info->voltage.voltage); 351 } 352 } 353 } 354 355 static ssize_t radeon_get_pm_profile(struct device *dev, 356 struct device_attribute *attr, 357 char *buf) 358 { 359 struct drm_device *ddev = dev_get_drvdata(dev); 360 struct radeon_device *rdev = ddev->dev_private; 361 int cp = rdev->pm.profile; 362 363 return snprintf(buf, PAGE_SIZE, "%s\n", 364 (cp == PM_PROFILE_AUTO) ? "auto" : 365 (cp == PM_PROFILE_LOW) ? "low" : 366 (cp == PM_PROFILE_MID) ? "mid" : 367 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 368 } 369 370 static ssize_t radeon_set_pm_profile(struct device *dev, 371 struct device_attribute *attr, 372 const char *buf, 373 size_t count) 374 { 375 struct drm_device *ddev = dev_get_drvdata(dev); 376 struct radeon_device *rdev = ddev->dev_private; 377 378 /* Can't set profile when the card is off */ 379 if ((rdev->flags & RADEON_IS_PX) && 380 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 381 return -EINVAL; 382 383 mutex_lock(&rdev->pm.mutex); 384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 385 if (strncmp("default", buf, strlen("default")) == 0) 386 rdev->pm.profile = PM_PROFILE_DEFAULT; 387 else if (strncmp("auto", buf, strlen("auto")) == 0) 388 rdev->pm.profile = PM_PROFILE_AUTO; 389 else if (strncmp("low", buf, strlen("low")) == 0) 390 rdev->pm.profile = PM_PROFILE_LOW; 391 else if (strncmp("mid", buf, strlen("mid")) == 0) 392 rdev->pm.profile = PM_PROFILE_MID; 393 else if (strncmp("high", buf, strlen("high")) == 0) 394 rdev->pm.profile = PM_PROFILE_HIGH; 395 else { 396 count = -EINVAL; 397 goto fail; 398 } 399 radeon_pm_update_profile(rdev); 400 radeon_pm_set_clocks(rdev); 401 } else 402 count = -EINVAL; 403 404 fail: 405 mutex_unlock(&rdev->pm.mutex); 406 407 return count; 408 } 409 410 static ssize_t radeon_get_pm_method(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413 { 414 struct drm_device *ddev = dev_get_drvdata(dev); 415 struct radeon_device *rdev = ddev->dev_private; 416 int pm = rdev->pm.pm_method; 417 418 return snprintf(buf, PAGE_SIZE, "%s\n", 419 (pm == PM_METHOD_DYNPM) ? "dynpm" : 420 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 421 } 422 423 static ssize_t radeon_set_pm_method(struct device *dev, 424 struct device_attribute *attr, 425 const char *buf, 426 size_t count) 427 { 428 struct drm_device *ddev = dev_get_drvdata(dev); 429 struct radeon_device *rdev = ddev->dev_private; 430 431 /* Can't set method when the card is off */ 432 if ((rdev->flags & RADEON_IS_PX) && 433 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 434 count = -EINVAL; 435 goto fail; 436 } 437 438 /* we don't support the legacy modes with dpm */ 439 if (rdev->pm.pm_method == PM_METHOD_DPM) { 440 count = -EINVAL; 441 goto fail; 442 } 443 444 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 445 mutex_lock(&rdev->pm.mutex); 446 rdev->pm.pm_method = PM_METHOD_DYNPM; 447 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 448 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 449 mutex_unlock(&rdev->pm.mutex); 450 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 451 mutex_lock(&rdev->pm.mutex); 452 /* disable dynpm */ 453 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 454 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 455 rdev->pm.pm_method = PM_METHOD_PROFILE; 456 mutex_unlock(&rdev->pm.mutex); 457 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 458 } else { 459 count = -EINVAL; 460 goto fail; 461 } 462 radeon_pm_compute_clocks(rdev); 463 fail: 464 return count; 465 } 466 467 static ssize_t radeon_get_dpm_state(struct device *dev, 468 struct device_attribute *attr, 469 char *buf) 470 { 471 struct drm_device *ddev = dev_get_drvdata(dev); 472 struct radeon_device *rdev = ddev->dev_private; 473 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 474 475 return snprintf(buf, PAGE_SIZE, "%s\n", 476 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 477 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 478 } 479 480 static ssize_t radeon_set_dpm_state(struct device *dev, 481 struct device_attribute *attr, 482 const char *buf, 483 size_t count) 484 { 485 struct drm_device *ddev = dev_get_drvdata(dev); 486 struct radeon_device *rdev = ddev->dev_private; 487 488 mutex_lock(&rdev->pm.mutex); 489 if (strncmp("battery", buf, strlen("battery")) == 0) 490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 491 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 493 else if (strncmp("performance", buf, strlen("performance")) == 0) 494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 495 else { 496 mutex_unlock(&rdev->pm.mutex); 497 count = -EINVAL; 498 goto fail; 499 } 500 mutex_unlock(&rdev->pm.mutex); 501 502 /* Can't set dpm state when the card is off */ 503 if (!(rdev->flags & RADEON_IS_PX) || 504 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 505 radeon_pm_compute_clocks(rdev); 506 507 fail: 508 return count; 509 } 510 511 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 512 struct device_attribute *attr, 513 char *buf) 514 { 515 struct drm_device *ddev = dev_get_drvdata(dev); 516 struct radeon_device *rdev = ddev->dev_private; 517 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 518 519 if ((rdev->flags & RADEON_IS_PX) && 520 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 521 return snprintf(buf, PAGE_SIZE, "off\n"); 522 523 return snprintf(buf, PAGE_SIZE, "%s\n", 524 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 525 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 526 } 527 528 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 529 struct device_attribute *attr, 530 const char *buf, 531 size_t count) 532 { 533 struct drm_device *ddev = dev_get_drvdata(dev); 534 struct radeon_device *rdev = ddev->dev_private; 535 enum radeon_dpm_forced_level level; 536 int ret = 0; 537 538 /* Can't force performance level when the card is off */ 539 if ((rdev->flags & RADEON_IS_PX) && 540 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 541 return -EINVAL; 542 543 mutex_lock(&rdev->pm.mutex); 544 if (strncmp("low", buf, strlen("low")) == 0) { 545 level = RADEON_DPM_FORCED_LEVEL_LOW; 546 } else if (strncmp("high", buf, strlen("high")) == 0) { 547 level = RADEON_DPM_FORCED_LEVEL_HIGH; 548 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 549 level = RADEON_DPM_FORCED_LEVEL_AUTO; 550 } else { 551 count = -EINVAL; 552 goto fail; 553 } 554 if (rdev->asic->dpm.force_performance_level) { 555 if (rdev->pm.dpm.thermal_active) { 556 count = -EINVAL; 557 goto fail; 558 } 559 ret = radeon_dpm_force_performance_level(rdev, level); 560 if (ret) 561 count = -EINVAL; 562 } 563 fail: 564 mutex_unlock(&rdev->pm.mutex); 565 566 return count; 567 } 568 569 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 570 struct device_attribute *attr, 571 char *buf) 572 { 573 struct radeon_device *rdev = dev_get_drvdata(dev); 574 u32 pwm_mode = 0; 575 576 if (rdev->asic->dpm.fan_ctrl_get_mode) 577 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 578 579 /* never 0 (full-speed), fuse or smc-controlled always */ 580 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 581 } 582 583 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 584 struct device_attribute *attr, 585 const char *buf, 586 size_t count) 587 { 588 struct radeon_device *rdev = dev_get_drvdata(dev); 589 int err; 590 int value; 591 592 if(!rdev->asic->dpm.fan_ctrl_set_mode) 593 return -EINVAL; 594 595 err = kstrtoint(buf, 10, &value); 596 if (err) 597 return err; 598 599 switch (value) { 600 case 1: /* manual, percent-based */ 601 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 602 break; 603 default: /* disable */ 604 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 605 break; 606 } 607 608 return count; 609 } 610 611 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 612 struct device_attribute *attr, 613 char *buf) 614 { 615 return sprintf(buf, "%i\n", 0); 616 } 617 618 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 619 struct device_attribute *attr, 620 char *buf) 621 { 622 return sprintf(buf, "%i\n", 255); 623 } 624 625 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 626 struct device_attribute *attr, 627 const char *buf, size_t count) 628 { 629 struct radeon_device *rdev = dev_get_drvdata(dev); 630 int err; 631 u32 value; 632 633 err = kstrtou32(buf, 10, &value); 634 if (err) 635 return err; 636 637 value = (value * 100) / 255; 638 639 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 640 if (err) 641 return err; 642 643 return count; 644 } 645 646 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 647 struct device_attribute *attr, 648 char *buf) 649 { 650 struct radeon_device *rdev = dev_get_drvdata(dev); 651 int err; 652 u32 speed; 653 654 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 655 if (err) 656 return err; 657 658 speed = (speed * 255) / 100; 659 660 return sprintf(buf, "%i\n", speed); 661 } 662 663 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 664 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 665 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 666 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 667 radeon_get_dpm_forced_performance_level, 668 radeon_set_dpm_forced_performance_level); 669 670 static ssize_t radeon_hwmon_show_temp(struct device *dev, 671 struct device_attribute *attr, 672 char *buf) 673 { 674 struct radeon_device *rdev = dev_get_drvdata(dev); 675 struct drm_device *ddev = rdev->ddev; 676 int temp; 677 678 /* Can't get temperature when the card is off */ 679 if ((rdev->flags & RADEON_IS_PX) && 680 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 681 return -EINVAL; 682 683 if (rdev->asic->pm.get_temperature) 684 temp = radeon_get_temperature(rdev); 685 else 686 temp = 0; 687 688 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 689 } 690 691 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 692 struct device_attribute *attr, 693 char *buf) 694 { 695 struct radeon_device *rdev = dev_get_drvdata(dev); 696 int hyst = to_sensor_dev_attr(attr)->index; 697 int temp; 698 699 if (hyst) 700 temp = rdev->pm.dpm.thermal.min_temp; 701 else 702 temp = rdev->pm.dpm.thermal.max_temp; 703 704 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 705 } 706 707 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 708 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 709 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 710 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 711 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 712 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 713 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 714 715 static ssize_t radeon_hwmon_show_sclk(struct device *dev, 716 struct device_attribute *attr, char *buf) 717 { 718 struct radeon_device *rdev = dev_get_drvdata(dev); 719 struct drm_device *ddev = rdev->ddev; 720 u32 sclk = 0; 721 722 /* Can't get clock frequency when the card is off */ 723 if ((rdev->flags & RADEON_IS_PX) && 724 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 725 return -EINVAL; 726 727 if (rdev->asic->dpm.get_current_sclk) 728 sclk = radeon_dpm_get_current_sclk(rdev); 729 730 /* Value returned by dpm is in 10 KHz units, need to convert it into Hz 731 for hwmon */ 732 sclk *= 10000; 733 734 return snprintf(buf, PAGE_SIZE, "%u\n", sclk); 735 } 736 737 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL, 738 0); 739 740 static ssize_t radeon_hwmon_show_vddc(struct device *dev, 741 struct device_attribute *attr, char *buf) 742 { 743 struct radeon_device *rdev = dev_get_drvdata(dev); 744 struct drm_device *ddev = rdev->ddev; 745 u16 vddc = 0; 746 747 /* Can't get vddc when the card is off */ 748 if ((rdev->flags & RADEON_IS_PX) && 749 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 750 return -EINVAL; 751 752 if (rdev->asic->dpm.get_current_vddc) 753 vddc = rdev->asic->dpm.get_current_vddc(rdev); 754 755 return snprintf(buf, PAGE_SIZE, "%u\n", vddc); 756 } 757 758 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL, 759 0); 760 761 static struct attribute *hwmon_attributes[] = { 762 &sensor_dev_attr_temp1_input.dev_attr.attr, 763 &sensor_dev_attr_temp1_crit.dev_attr.attr, 764 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 765 &sensor_dev_attr_pwm1.dev_attr.attr, 766 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 767 &sensor_dev_attr_pwm1_min.dev_attr.attr, 768 &sensor_dev_attr_pwm1_max.dev_attr.attr, 769 &sensor_dev_attr_freq1_input.dev_attr.attr, 770 &sensor_dev_attr_in0_input.dev_attr.attr, 771 NULL 772 }; 773 774 static umode_t hwmon_attributes_visible(struct kobject *kobj, 775 struct attribute *attr, int index) 776 { 777 struct device *dev = kobj_to_dev(kobj); 778 struct radeon_device *rdev = dev_get_drvdata(dev); 779 umode_t effective_mode = attr->mode; 780 781 /* Skip attributes if DPM is not enabled */ 782 if (rdev->pm.pm_method != PM_METHOD_DPM && 783 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 784 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 785 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 786 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 787 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 788 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 789 attr == &sensor_dev_attr_freq1_input.dev_attr.attr || 790 attr == &sensor_dev_attr_in0_input.dev_attr.attr)) 791 return 0; 792 793 /* Skip vddc attribute if get_current_vddc is not implemented */ 794 if(attr == &sensor_dev_attr_in0_input.dev_attr.attr && 795 !rdev->asic->dpm.get_current_vddc) 796 return 0; 797 798 /* Skip fan attributes if fan is not present */ 799 if (rdev->pm.no_fan && 800 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 801 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 802 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 803 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 804 return 0; 805 806 /* mask fan attributes if we have no bindings for this asic to expose */ 807 if ((!rdev->asic->dpm.get_fan_speed_percent && 808 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 809 (!rdev->asic->dpm.fan_ctrl_get_mode && 810 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 811 effective_mode &= ~S_IRUGO; 812 813 if ((!rdev->asic->dpm.set_fan_speed_percent && 814 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 815 (!rdev->asic->dpm.fan_ctrl_set_mode && 816 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 817 effective_mode &= ~S_IWUSR; 818 819 /* hide max/min values if we can't both query and manage the fan */ 820 if ((!rdev->asic->dpm.set_fan_speed_percent && 821 !rdev->asic->dpm.get_fan_speed_percent) && 822 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 823 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 824 return 0; 825 826 return effective_mode; 827 } 828 829 static const struct attribute_group hwmon_attrgroup = { 830 .attrs = hwmon_attributes, 831 .is_visible = hwmon_attributes_visible, 832 }; 833 834 static const struct attribute_group *hwmon_groups[] = { 835 &hwmon_attrgroup, 836 NULL 837 }; 838 839 static int radeon_hwmon_init(struct radeon_device *rdev) 840 { 841 int err = 0; 842 843 switch (rdev->pm.int_thermal_type) { 844 case THERMAL_TYPE_RV6XX: 845 case THERMAL_TYPE_RV770: 846 case THERMAL_TYPE_EVERGREEN: 847 case THERMAL_TYPE_NI: 848 case THERMAL_TYPE_SUMO: 849 case THERMAL_TYPE_SI: 850 case THERMAL_TYPE_CI: 851 case THERMAL_TYPE_KV: 852 if (rdev->asic->pm.get_temperature == NULL) 853 return err; 854 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 855 "radeon", rdev, 856 hwmon_groups); 857 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 858 err = PTR_ERR(rdev->pm.int_hwmon_dev); 859 dev_err(rdev->dev, 860 "Unable to register hwmon device: %d\n", err); 861 } 862 break; 863 default: 864 break; 865 } 866 867 return err; 868 } 869 870 static void radeon_hwmon_fini(struct radeon_device *rdev) 871 { 872 if (rdev->pm.int_hwmon_dev) 873 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 874 } 875 876 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 877 { 878 struct radeon_device *rdev = 879 container_of(work, struct radeon_device, 880 pm.dpm.thermal.work); 881 /* switch to the thermal state */ 882 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 883 884 if (!rdev->pm.dpm_enabled) 885 return; 886 887 if (rdev->asic->pm.get_temperature) { 888 int temp = radeon_get_temperature(rdev); 889 890 if (temp < rdev->pm.dpm.thermal.min_temp) 891 /* switch back the user state */ 892 dpm_state = rdev->pm.dpm.user_state; 893 } else { 894 if (rdev->pm.dpm.thermal.high_to_low) 895 /* switch back the user state */ 896 dpm_state = rdev->pm.dpm.user_state; 897 } 898 mutex_lock(&rdev->pm.mutex); 899 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 900 rdev->pm.dpm.thermal_active = true; 901 else 902 rdev->pm.dpm.thermal_active = false; 903 rdev->pm.dpm.state = dpm_state; 904 mutex_unlock(&rdev->pm.mutex); 905 906 radeon_pm_compute_clocks(rdev); 907 } 908 909 static bool radeon_dpm_single_display(struct radeon_device *rdev) 910 { 911 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 912 true : false; 913 914 /* check if the vblank period is too short to adjust the mclk */ 915 if (single_display && rdev->asic->dpm.vblank_too_short) { 916 if (radeon_dpm_vblank_too_short(rdev)) 917 single_display = false; 918 } 919 920 /* 120hz tends to be problematic even if they are under the 921 * vblank limit. 922 */ 923 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 924 single_display = false; 925 926 return single_display; 927 } 928 929 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 930 enum radeon_pm_state_type dpm_state) 931 { 932 int i; 933 struct radeon_ps *ps; 934 u32 ui_class; 935 bool single_display = radeon_dpm_single_display(rdev); 936 937 /* certain older asics have a separare 3D performance state, 938 * so try that first if the user selected performance 939 */ 940 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 941 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 942 /* balanced states don't exist at the moment */ 943 if (dpm_state == POWER_STATE_TYPE_BALANCED) 944 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 945 946 restart_search: 947 /* Pick the best power state based on current conditions */ 948 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 949 ps = &rdev->pm.dpm.ps[i]; 950 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 951 switch (dpm_state) { 952 /* user states */ 953 case POWER_STATE_TYPE_BATTERY: 954 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 955 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 956 if (single_display) 957 return ps; 958 } else 959 return ps; 960 } 961 break; 962 case POWER_STATE_TYPE_BALANCED: 963 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 964 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 965 if (single_display) 966 return ps; 967 } else 968 return ps; 969 } 970 break; 971 case POWER_STATE_TYPE_PERFORMANCE: 972 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 973 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 974 if (single_display) 975 return ps; 976 } else 977 return ps; 978 } 979 break; 980 /* internal states */ 981 case POWER_STATE_TYPE_INTERNAL_UVD: 982 if (rdev->pm.dpm.uvd_ps) 983 return rdev->pm.dpm.uvd_ps; 984 else 985 break; 986 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 987 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 988 return ps; 989 break; 990 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 991 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 992 return ps; 993 break; 994 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 995 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 996 return ps; 997 break; 998 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 999 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 1000 return ps; 1001 break; 1002 case POWER_STATE_TYPE_INTERNAL_BOOT: 1003 return rdev->pm.dpm.boot_ps; 1004 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1005 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1006 return ps; 1007 break; 1008 case POWER_STATE_TYPE_INTERNAL_ACPI: 1009 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 1010 return ps; 1011 break; 1012 case POWER_STATE_TYPE_INTERNAL_ULV: 1013 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 1014 return ps; 1015 break; 1016 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1017 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 1018 return ps; 1019 break; 1020 default: 1021 break; 1022 } 1023 } 1024 /* use a fallback state if we didn't match */ 1025 switch (dpm_state) { 1026 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1027 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1028 goto restart_search; 1029 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1030 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1031 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1032 if (rdev->pm.dpm.uvd_ps) { 1033 return rdev->pm.dpm.uvd_ps; 1034 } else { 1035 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1036 goto restart_search; 1037 } 1038 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1039 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1040 goto restart_search; 1041 case POWER_STATE_TYPE_INTERNAL_ACPI: 1042 dpm_state = POWER_STATE_TYPE_BATTERY; 1043 goto restart_search; 1044 case POWER_STATE_TYPE_BATTERY: 1045 case POWER_STATE_TYPE_BALANCED: 1046 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1047 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1048 goto restart_search; 1049 default: 1050 break; 1051 } 1052 1053 return NULL; 1054 } 1055 1056 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1057 { 1058 int i; 1059 struct radeon_ps *ps; 1060 enum radeon_pm_state_type dpm_state; 1061 int ret; 1062 bool single_display = radeon_dpm_single_display(rdev); 1063 1064 /* if dpm init failed */ 1065 if (!rdev->pm.dpm_enabled) 1066 return; 1067 1068 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1069 /* add other state override checks here */ 1070 if ((!rdev->pm.dpm.thermal_active) && 1071 (!rdev->pm.dpm.uvd_active)) 1072 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1073 } 1074 dpm_state = rdev->pm.dpm.state; 1075 1076 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1077 if (ps) 1078 rdev->pm.dpm.requested_ps = ps; 1079 else 1080 return; 1081 1082 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1083 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1084 /* vce just modifies an existing state so force a change */ 1085 if (ps->vce_active != rdev->pm.dpm.vce_active) 1086 goto force; 1087 /* user has made a display change (such as timing) */ 1088 if (rdev->pm.dpm.single_display != single_display) 1089 goto force; 1090 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1091 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1092 * all we need to do is update the display configuration. 1093 */ 1094 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1095 /* update display watermarks based on new power state */ 1096 radeon_bandwidth_update(rdev); 1097 /* update displays */ 1098 radeon_dpm_display_configuration_changed(rdev); 1099 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1100 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1101 } 1102 return; 1103 } else { 1104 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1105 * nothing to do, if the num crtcs is > 1 and state is the same, 1106 * update display configuration. 1107 */ 1108 if (rdev->pm.dpm.new_active_crtcs == 1109 rdev->pm.dpm.current_active_crtcs) { 1110 return; 1111 } else { 1112 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1113 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1114 /* update display watermarks based on new power state */ 1115 radeon_bandwidth_update(rdev); 1116 /* update displays */ 1117 radeon_dpm_display_configuration_changed(rdev); 1118 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1119 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1120 return; 1121 } 1122 } 1123 } 1124 } 1125 1126 force: 1127 if (radeon_dpm == 1) { 1128 printk("switching from power state:\n"); 1129 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1130 printk("switching to power state:\n"); 1131 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1132 } 1133 1134 down_write(&rdev->pm.mclk_lock); 1135 mutex_lock(&rdev->ring_lock); 1136 1137 /* update whether vce is active */ 1138 ps->vce_active = rdev->pm.dpm.vce_active; 1139 1140 ret = radeon_dpm_pre_set_power_state(rdev); 1141 if (ret) 1142 goto done; 1143 1144 /* update display watermarks based on new power state */ 1145 radeon_bandwidth_update(rdev); 1146 /* update displays */ 1147 radeon_dpm_display_configuration_changed(rdev); 1148 1149 /* wait for the rings to drain */ 1150 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1151 struct radeon_ring *ring = &rdev->ring[i]; 1152 if (ring->ready) 1153 radeon_fence_wait_empty(rdev, i); 1154 } 1155 1156 /* program the new power state */ 1157 radeon_dpm_set_power_state(rdev); 1158 1159 /* update current power state */ 1160 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1161 1162 radeon_dpm_post_set_power_state(rdev); 1163 1164 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1165 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1166 rdev->pm.dpm.single_display = single_display; 1167 1168 if (rdev->asic->dpm.force_performance_level) { 1169 if (rdev->pm.dpm.thermal_active) { 1170 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1171 /* force low perf level for thermal */ 1172 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1173 /* save the user's level */ 1174 rdev->pm.dpm.forced_level = level; 1175 } else { 1176 /* otherwise, user selected level */ 1177 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1178 } 1179 } 1180 1181 done: 1182 mutex_unlock(&rdev->ring_lock); 1183 up_write(&rdev->pm.mclk_lock); 1184 } 1185 1186 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1187 { 1188 enum radeon_pm_state_type dpm_state; 1189 1190 if (rdev->asic->dpm.powergate_uvd) { 1191 mutex_lock(&rdev->pm.mutex); 1192 /* don't powergate anything if we 1193 have active but pause streams */ 1194 enable |= rdev->pm.dpm.sd > 0; 1195 enable |= rdev->pm.dpm.hd > 0; 1196 /* enable/disable UVD */ 1197 radeon_dpm_powergate_uvd(rdev, !enable); 1198 mutex_unlock(&rdev->pm.mutex); 1199 } else { 1200 if (enable) { 1201 mutex_lock(&rdev->pm.mutex); 1202 rdev->pm.dpm.uvd_active = true; 1203 /* disable this for now */ 1204 #if 0 1205 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1206 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1207 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1208 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1209 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1210 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1211 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1212 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1213 else 1214 #endif 1215 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1216 rdev->pm.dpm.state = dpm_state; 1217 mutex_unlock(&rdev->pm.mutex); 1218 } else { 1219 mutex_lock(&rdev->pm.mutex); 1220 rdev->pm.dpm.uvd_active = false; 1221 mutex_unlock(&rdev->pm.mutex); 1222 } 1223 1224 radeon_pm_compute_clocks(rdev); 1225 } 1226 } 1227 1228 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1229 { 1230 if (enable) { 1231 mutex_lock(&rdev->pm.mutex); 1232 rdev->pm.dpm.vce_active = true; 1233 /* XXX select vce level based on ring/task */ 1234 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1235 mutex_unlock(&rdev->pm.mutex); 1236 } else { 1237 mutex_lock(&rdev->pm.mutex); 1238 rdev->pm.dpm.vce_active = false; 1239 mutex_unlock(&rdev->pm.mutex); 1240 } 1241 1242 radeon_pm_compute_clocks(rdev); 1243 } 1244 1245 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1246 { 1247 mutex_lock(&rdev->pm.mutex); 1248 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1249 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1250 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1251 } 1252 mutex_unlock(&rdev->pm.mutex); 1253 1254 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1255 } 1256 1257 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1258 { 1259 mutex_lock(&rdev->pm.mutex); 1260 /* disable dpm */ 1261 radeon_dpm_disable(rdev); 1262 /* reset the power state */ 1263 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1264 rdev->pm.dpm_enabled = false; 1265 mutex_unlock(&rdev->pm.mutex); 1266 } 1267 1268 void radeon_pm_suspend(struct radeon_device *rdev) 1269 { 1270 if (rdev->pm.pm_method == PM_METHOD_DPM) 1271 radeon_pm_suspend_dpm(rdev); 1272 else 1273 radeon_pm_suspend_old(rdev); 1274 } 1275 1276 static void radeon_pm_resume_old(struct radeon_device *rdev) 1277 { 1278 /* set up the default clocks if the MC ucode is loaded */ 1279 if ((rdev->family >= CHIP_BARTS) && 1280 (rdev->family <= CHIP_CAYMAN) && 1281 rdev->mc_fw) { 1282 if (rdev->pm.default_vddc) 1283 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1284 SET_VOLTAGE_TYPE_ASIC_VDDC); 1285 if (rdev->pm.default_vddci) 1286 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1287 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1288 if (rdev->pm.default_sclk) 1289 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1290 if (rdev->pm.default_mclk) 1291 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1292 } 1293 /* asic init will reset the default power state */ 1294 mutex_lock(&rdev->pm.mutex); 1295 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1296 rdev->pm.current_clock_mode_index = 0; 1297 rdev->pm.current_sclk = rdev->pm.default_sclk; 1298 rdev->pm.current_mclk = rdev->pm.default_mclk; 1299 if (rdev->pm.power_state) { 1300 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1301 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1302 } 1303 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1304 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1305 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1306 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1307 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1308 } 1309 mutex_unlock(&rdev->pm.mutex); 1310 radeon_pm_compute_clocks(rdev); 1311 } 1312 1313 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1314 { 1315 int ret; 1316 1317 /* asic init will reset to the boot state */ 1318 mutex_lock(&rdev->pm.mutex); 1319 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1320 radeon_dpm_setup_asic(rdev); 1321 ret = radeon_dpm_enable(rdev); 1322 mutex_unlock(&rdev->pm.mutex); 1323 if (ret) 1324 goto dpm_resume_fail; 1325 rdev->pm.dpm_enabled = true; 1326 return; 1327 1328 dpm_resume_fail: 1329 DRM_ERROR("radeon: dpm resume failed\n"); 1330 if ((rdev->family >= CHIP_BARTS) && 1331 (rdev->family <= CHIP_CAYMAN) && 1332 rdev->mc_fw) { 1333 if (rdev->pm.default_vddc) 1334 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1335 SET_VOLTAGE_TYPE_ASIC_VDDC); 1336 if (rdev->pm.default_vddci) 1337 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1338 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1339 if (rdev->pm.default_sclk) 1340 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1341 if (rdev->pm.default_mclk) 1342 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1343 } 1344 } 1345 1346 void radeon_pm_resume(struct radeon_device *rdev) 1347 { 1348 if (rdev->pm.pm_method == PM_METHOD_DPM) 1349 radeon_pm_resume_dpm(rdev); 1350 else 1351 radeon_pm_resume_old(rdev); 1352 } 1353 1354 static int radeon_pm_init_old(struct radeon_device *rdev) 1355 { 1356 int ret; 1357 1358 rdev->pm.profile = PM_PROFILE_DEFAULT; 1359 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1360 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1361 rdev->pm.dynpm_can_upclock = true; 1362 rdev->pm.dynpm_can_downclock = true; 1363 rdev->pm.default_sclk = rdev->clock.default_sclk; 1364 rdev->pm.default_mclk = rdev->clock.default_mclk; 1365 rdev->pm.current_sclk = rdev->clock.default_sclk; 1366 rdev->pm.current_mclk = rdev->clock.default_mclk; 1367 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1368 1369 if (rdev->bios) { 1370 if (rdev->is_atom_bios) 1371 radeon_atombios_get_power_modes(rdev); 1372 else 1373 radeon_combios_get_power_modes(rdev); 1374 radeon_pm_print_states(rdev); 1375 radeon_pm_init_profile(rdev); 1376 /* set up the default clocks if the MC ucode is loaded */ 1377 if ((rdev->family >= CHIP_BARTS) && 1378 (rdev->family <= CHIP_CAYMAN) && 1379 rdev->mc_fw) { 1380 if (rdev->pm.default_vddc) 1381 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1382 SET_VOLTAGE_TYPE_ASIC_VDDC); 1383 if (rdev->pm.default_vddci) 1384 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1385 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1386 if (rdev->pm.default_sclk) 1387 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1388 if (rdev->pm.default_mclk) 1389 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1390 } 1391 } 1392 1393 /* set up the internal thermal sensor if applicable */ 1394 ret = radeon_hwmon_init(rdev); 1395 if (ret) 1396 return ret; 1397 1398 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1399 1400 if (rdev->pm.num_power_states > 1) { 1401 radeon_debugfs_pm_init(rdev); 1402 DRM_INFO("radeon: power management initialized\n"); 1403 } 1404 1405 return 0; 1406 } 1407 1408 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1409 { 1410 int i; 1411 1412 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1413 printk("== power state %d ==\n", i); 1414 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1415 } 1416 } 1417 1418 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1419 { 1420 int ret; 1421 1422 /* default to balanced state */ 1423 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1424 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1425 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1426 rdev->pm.default_sclk = rdev->clock.default_sclk; 1427 rdev->pm.default_mclk = rdev->clock.default_mclk; 1428 rdev->pm.current_sclk = rdev->clock.default_sclk; 1429 rdev->pm.current_mclk = rdev->clock.default_mclk; 1430 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1431 1432 if (rdev->bios && rdev->is_atom_bios) 1433 radeon_atombios_get_power_modes(rdev); 1434 else 1435 return -EINVAL; 1436 1437 /* set up the internal thermal sensor if applicable */ 1438 ret = radeon_hwmon_init(rdev); 1439 if (ret) 1440 return ret; 1441 1442 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1443 mutex_lock(&rdev->pm.mutex); 1444 radeon_dpm_init(rdev); 1445 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1446 if (radeon_dpm == 1) 1447 radeon_dpm_print_power_states(rdev); 1448 radeon_dpm_setup_asic(rdev); 1449 ret = radeon_dpm_enable(rdev); 1450 mutex_unlock(&rdev->pm.mutex); 1451 if (ret) 1452 goto dpm_failed; 1453 rdev->pm.dpm_enabled = true; 1454 1455 radeon_debugfs_pm_init(rdev); 1456 1457 DRM_INFO("radeon: dpm initialized\n"); 1458 1459 return 0; 1460 1461 dpm_failed: 1462 rdev->pm.dpm_enabled = false; 1463 if ((rdev->family >= CHIP_BARTS) && 1464 (rdev->family <= CHIP_CAYMAN) && 1465 rdev->mc_fw) { 1466 if (rdev->pm.default_vddc) 1467 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1468 SET_VOLTAGE_TYPE_ASIC_VDDC); 1469 if (rdev->pm.default_vddci) 1470 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1471 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1472 if (rdev->pm.default_sclk) 1473 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1474 if (rdev->pm.default_mclk) 1475 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1476 } 1477 DRM_ERROR("radeon: dpm initialization failed\n"); 1478 return ret; 1479 } 1480 1481 struct radeon_dpm_quirk { 1482 u32 chip_vendor; 1483 u32 chip_device; 1484 u32 subsys_vendor; 1485 u32 subsys_device; 1486 }; 1487 1488 /* cards with dpm stability problems */ 1489 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1490 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1491 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1492 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1493 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1494 { 0, 0, 0, 0 }, 1495 }; 1496 1497 int radeon_pm_init(struct radeon_device *rdev) 1498 { 1499 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1500 bool disable_dpm = false; 1501 1502 /* Apply dpm quirks */ 1503 while (p && p->chip_device != 0) { 1504 if (rdev->pdev->vendor == p->chip_vendor && 1505 rdev->pdev->device == p->chip_device && 1506 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1507 rdev->pdev->subsystem_device == p->subsys_device) { 1508 disable_dpm = true; 1509 break; 1510 } 1511 ++p; 1512 } 1513 1514 /* enable dpm on rv6xx+ */ 1515 switch (rdev->family) { 1516 case CHIP_RV610: 1517 case CHIP_RV630: 1518 case CHIP_RV620: 1519 case CHIP_RV635: 1520 case CHIP_RV670: 1521 case CHIP_RS780: 1522 case CHIP_RS880: 1523 case CHIP_RV770: 1524 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1525 if (!rdev->rlc_fw) 1526 rdev->pm.pm_method = PM_METHOD_PROFILE; 1527 else if ((rdev->family >= CHIP_RV770) && 1528 (!(rdev->flags & RADEON_IS_IGP)) && 1529 (!rdev->smc_fw)) 1530 rdev->pm.pm_method = PM_METHOD_PROFILE; 1531 else if (radeon_dpm == 1) 1532 rdev->pm.pm_method = PM_METHOD_DPM; 1533 else 1534 rdev->pm.pm_method = PM_METHOD_PROFILE; 1535 break; 1536 case CHIP_RV730: 1537 case CHIP_RV710: 1538 case CHIP_RV740: 1539 case CHIP_CEDAR: 1540 case CHIP_REDWOOD: 1541 case CHIP_JUNIPER: 1542 case CHIP_CYPRESS: 1543 case CHIP_HEMLOCK: 1544 case CHIP_PALM: 1545 case CHIP_SUMO: 1546 case CHIP_SUMO2: 1547 case CHIP_BARTS: 1548 case CHIP_TURKS: 1549 case CHIP_CAICOS: 1550 case CHIP_CAYMAN: 1551 case CHIP_ARUBA: 1552 case CHIP_TAHITI: 1553 case CHIP_PITCAIRN: 1554 case CHIP_VERDE: 1555 case CHIP_OLAND: 1556 case CHIP_HAINAN: 1557 case CHIP_BONAIRE: 1558 case CHIP_KABINI: 1559 case CHIP_KAVERI: 1560 case CHIP_HAWAII: 1561 case CHIP_MULLINS: 1562 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1563 if (!rdev->rlc_fw) 1564 rdev->pm.pm_method = PM_METHOD_PROFILE; 1565 else if ((rdev->family >= CHIP_RV770) && 1566 (!(rdev->flags & RADEON_IS_IGP)) && 1567 (!rdev->smc_fw)) 1568 rdev->pm.pm_method = PM_METHOD_PROFILE; 1569 else if (disable_dpm && (radeon_dpm == -1)) 1570 rdev->pm.pm_method = PM_METHOD_PROFILE; 1571 else if (radeon_dpm == 0) 1572 rdev->pm.pm_method = PM_METHOD_PROFILE; 1573 else 1574 rdev->pm.pm_method = PM_METHOD_DPM; 1575 break; 1576 default: 1577 /* default to profile method */ 1578 rdev->pm.pm_method = PM_METHOD_PROFILE; 1579 break; 1580 } 1581 1582 if (rdev->pm.pm_method == PM_METHOD_DPM) 1583 return radeon_pm_init_dpm(rdev); 1584 else 1585 return radeon_pm_init_old(rdev); 1586 } 1587 1588 int radeon_pm_late_init(struct radeon_device *rdev) 1589 { 1590 int ret = 0; 1591 1592 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1593 if (rdev->pm.dpm_enabled) { 1594 if (!rdev->pm.sysfs_initialized) { 1595 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1596 if (ret) 1597 DRM_ERROR("failed to create device file for dpm state\n"); 1598 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1599 if (ret) 1600 DRM_ERROR("failed to create device file for dpm state\n"); 1601 /* XXX: these are noops for dpm but are here for backwards compat */ 1602 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1603 if (ret) 1604 DRM_ERROR("failed to create device file for power profile\n"); 1605 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1606 if (ret) 1607 DRM_ERROR("failed to create device file for power method\n"); 1608 rdev->pm.sysfs_initialized = true; 1609 } 1610 1611 mutex_lock(&rdev->pm.mutex); 1612 ret = radeon_dpm_late_enable(rdev); 1613 mutex_unlock(&rdev->pm.mutex); 1614 if (ret) { 1615 rdev->pm.dpm_enabled = false; 1616 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1617 } else { 1618 /* set the dpm state for PX since there won't be 1619 * a modeset to call this. 1620 */ 1621 radeon_pm_compute_clocks(rdev); 1622 } 1623 } 1624 } else { 1625 if ((rdev->pm.num_power_states > 1) && 1626 (!rdev->pm.sysfs_initialized)) { 1627 /* where's the best place to put these? */ 1628 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1629 if (ret) 1630 DRM_ERROR("failed to create device file for power profile\n"); 1631 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1632 if (ret) 1633 DRM_ERROR("failed to create device file for power method\n"); 1634 if (!ret) 1635 rdev->pm.sysfs_initialized = true; 1636 } 1637 } 1638 return ret; 1639 } 1640 1641 static void radeon_pm_fini_old(struct radeon_device *rdev) 1642 { 1643 if (rdev->pm.num_power_states > 1) { 1644 mutex_lock(&rdev->pm.mutex); 1645 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1646 rdev->pm.profile = PM_PROFILE_DEFAULT; 1647 radeon_pm_update_profile(rdev); 1648 radeon_pm_set_clocks(rdev); 1649 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1650 /* reset default clocks */ 1651 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1652 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1653 radeon_pm_set_clocks(rdev); 1654 } 1655 mutex_unlock(&rdev->pm.mutex); 1656 1657 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1658 1659 device_remove_file(rdev->dev, &dev_attr_power_profile); 1660 device_remove_file(rdev->dev, &dev_attr_power_method); 1661 } 1662 1663 radeon_hwmon_fini(rdev); 1664 kfree(rdev->pm.power_state); 1665 } 1666 1667 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1668 { 1669 if (rdev->pm.num_power_states > 1) { 1670 mutex_lock(&rdev->pm.mutex); 1671 radeon_dpm_disable(rdev); 1672 mutex_unlock(&rdev->pm.mutex); 1673 1674 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1675 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1676 /* XXX backwards compat */ 1677 device_remove_file(rdev->dev, &dev_attr_power_profile); 1678 device_remove_file(rdev->dev, &dev_attr_power_method); 1679 } 1680 radeon_dpm_fini(rdev); 1681 1682 radeon_hwmon_fini(rdev); 1683 kfree(rdev->pm.power_state); 1684 } 1685 1686 void radeon_pm_fini(struct radeon_device *rdev) 1687 { 1688 if (rdev->pm.pm_method == PM_METHOD_DPM) 1689 radeon_pm_fini_dpm(rdev); 1690 else 1691 radeon_pm_fini_old(rdev); 1692 } 1693 1694 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1695 { 1696 struct drm_device *ddev = rdev->ddev; 1697 struct drm_crtc *crtc; 1698 struct radeon_crtc *radeon_crtc; 1699 1700 if (rdev->pm.num_power_states < 2) 1701 return; 1702 1703 mutex_lock(&rdev->pm.mutex); 1704 1705 rdev->pm.active_crtcs = 0; 1706 rdev->pm.active_crtc_count = 0; 1707 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1708 list_for_each_entry(crtc, 1709 &ddev->mode_config.crtc_list, head) { 1710 radeon_crtc = to_radeon_crtc(crtc); 1711 if (radeon_crtc->enabled) { 1712 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1713 rdev->pm.active_crtc_count++; 1714 } 1715 } 1716 } 1717 1718 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1719 radeon_pm_update_profile(rdev); 1720 radeon_pm_set_clocks(rdev); 1721 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1722 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1723 if (rdev->pm.active_crtc_count > 1) { 1724 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1725 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1726 1727 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1728 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1729 radeon_pm_get_dynpm_state(rdev); 1730 radeon_pm_set_clocks(rdev); 1731 1732 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1733 } 1734 } else if (rdev->pm.active_crtc_count == 1) { 1735 /* TODO: Increase clocks if needed for current mode */ 1736 1737 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1738 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1739 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1740 radeon_pm_get_dynpm_state(rdev); 1741 radeon_pm_set_clocks(rdev); 1742 1743 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1744 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1745 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1746 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1747 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1748 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1749 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1750 } 1751 } else { /* count == 0 */ 1752 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1753 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1754 1755 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1756 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1757 radeon_pm_get_dynpm_state(rdev); 1758 radeon_pm_set_clocks(rdev); 1759 } 1760 } 1761 } 1762 } 1763 1764 mutex_unlock(&rdev->pm.mutex); 1765 } 1766 1767 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1768 { 1769 struct drm_device *ddev = rdev->ddev; 1770 struct drm_crtc *crtc; 1771 struct radeon_crtc *radeon_crtc; 1772 1773 if (!rdev->pm.dpm_enabled) 1774 return; 1775 1776 mutex_lock(&rdev->pm.mutex); 1777 1778 /* update active crtc counts */ 1779 rdev->pm.dpm.new_active_crtcs = 0; 1780 rdev->pm.dpm.new_active_crtc_count = 0; 1781 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1782 list_for_each_entry(crtc, 1783 &ddev->mode_config.crtc_list, head) { 1784 radeon_crtc = to_radeon_crtc(crtc); 1785 if (crtc->enabled) { 1786 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1787 rdev->pm.dpm.new_active_crtc_count++; 1788 } 1789 } 1790 } 1791 1792 /* update battery/ac status */ 1793 if (power_supply_is_system_supplied() > 0) 1794 rdev->pm.dpm.ac_power = true; 1795 else 1796 rdev->pm.dpm.ac_power = false; 1797 1798 radeon_dpm_change_power_state_locked(rdev); 1799 1800 mutex_unlock(&rdev->pm.mutex); 1801 1802 } 1803 1804 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1805 { 1806 if (rdev->pm.pm_method == PM_METHOD_DPM) 1807 radeon_pm_compute_clocks_dpm(rdev); 1808 else 1809 radeon_pm_compute_clocks_old(rdev); 1810 } 1811 1812 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1813 { 1814 int crtc, vpos, hpos, vbl_status; 1815 bool in_vbl = true; 1816 1817 /* Iterate over all active crtc's. All crtc's must be in vblank, 1818 * otherwise return in_vbl == false. 1819 */ 1820 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1821 if (rdev->pm.active_crtcs & (1 << crtc)) { 1822 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1823 crtc, 1824 USE_REAL_VBLANKSTART, 1825 &vpos, &hpos, NULL, NULL, 1826 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1827 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1828 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1829 in_vbl = false; 1830 } 1831 } 1832 1833 return in_vbl; 1834 } 1835 1836 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1837 { 1838 u32 stat_crtc = 0; 1839 bool in_vbl = radeon_pm_in_vbl(rdev); 1840 1841 if (!in_vbl) 1842 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1843 finish ? "exit" : "entry"); 1844 return in_vbl; 1845 } 1846 1847 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1848 { 1849 struct radeon_device *rdev; 1850 int resched; 1851 rdev = container_of(work, struct radeon_device, 1852 pm.dynpm_idle_work.work); 1853 1854 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1855 mutex_lock(&rdev->pm.mutex); 1856 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1857 int not_processed = 0; 1858 int i; 1859 1860 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1861 struct radeon_ring *ring = &rdev->ring[i]; 1862 1863 if (ring->ready) { 1864 not_processed += radeon_fence_count_emitted(rdev, i); 1865 if (not_processed >= 3) 1866 break; 1867 } 1868 } 1869 1870 if (not_processed >= 3) { /* should upclock */ 1871 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1872 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1873 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1874 rdev->pm.dynpm_can_upclock) { 1875 rdev->pm.dynpm_planned_action = 1876 DYNPM_ACTION_UPCLOCK; 1877 rdev->pm.dynpm_action_timeout = jiffies + 1878 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1879 } 1880 } else if (not_processed == 0) { /* should downclock */ 1881 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1882 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1883 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1884 rdev->pm.dynpm_can_downclock) { 1885 rdev->pm.dynpm_planned_action = 1886 DYNPM_ACTION_DOWNCLOCK; 1887 rdev->pm.dynpm_action_timeout = jiffies + 1888 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1889 } 1890 } 1891 1892 /* Note, radeon_pm_set_clocks is called with static_switch set 1893 * to false since we want to wait for vbl to avoid flicker. 1894 */ 1895 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1896 jiffies > rdev->pm.dynpm_action_timeout) { 1897 radeon_pm_get_dynpm_state(rdev); 1898 radeon_pm_set_clocks(rdev); 1899 } 1900 1901 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1902 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1903 } 1904 mutex_unlock(&rdev->pm.mutex); 1905 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1906 } 1907 1908 /* 1909 * Debugfs info 1910 */ 1911 #if defined(CONFIG_DEBUG_FS) 1912 1913 static int radeon_debugfs_pm_info_show(struct seq_file *m, void *unused) 1914 { 1915 struct radeon_device *rdev = (struct radeon_device *)m->private; 1916 struct drm_device *ddev = rdev->ddev; 1917 1918 if ((rdev->flags & RADEON_IS_PX) && 1919 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1920 seq_printf(m, "PX asic powered off\n"); 1921 } else if (rdev->pm.dpm_enabled) { 1922 mutex_lock(&rdev->pm.mutex); 1923 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1924 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1925 else 1926 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1927 mutex_unlock(&rdev->pm.mutex); 1928 } else { 1929 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1930 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1931 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1932 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1933 else 1934 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1935 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1936 if (rdev->asic->pm.get_memory_clock) 1937 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1938 if (rdev->pm.current_vddc) 1939 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1940 if (rdev->asic->pm.get_pcie_lanes) 1941 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1942 } 1943 1944 return 0; 1945 } 1946 1947 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_pm_info); 1948 #endif 1949 1950 static void radeon_debugfs_pm_init(struct radeon_device *rdev) 1951 { 1952 #if defined(CONFIG_DEBUG_FS) 1953 struct dentry *root = rdev->ddev->primary->debugfs_root; 1954 1955 debugfs_create_file("radeon_pm_info", 0444, root, rdev, 1956 &radeon_debugfs_pm_info_fops); 1957 1958 #endif 1959 } 1960