1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 #include <linux/hwmon-sysfs.h> 31 32 #define RADEON_IDLE_LOOP_MS 100 33 #define RADEON_RECLOCK_DELAY_MS 200 34 #define RADEON_WAIT_VBLANK_TIMEOUT 200 35 36 static const char *radeon_pm_state_type_name[5] = { 37 "", 38 "Powersave", 39 "Battery", 40 "Balanced", 41 "Performance", 42 }; 43 44 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 45 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 46 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 48 static void radeon_pm_update_profile(struct radeon_device *rdev); 49 static void radeon_pm_set_clocks(struct radeon_device *rdev); 50 51 int radeon_pm_get_type_index(struct radeon_device *rdev, 52 enum radeon_pm_state_type ps_type, 53 int instance) 54 { 55 int i; 56 int found_instance = -1; 57 58 for (i = 0; i < rdev->pm.num_power_states; i++) { 59 if (rdev->pm.power_state[i].type == ps_type) { 60 found_instance++; 61 if (found_instance == instance) 62 return i; 63 } 64 } 65 /* return default if no match */ 66 return rdev->pm.default_power_state_index; 67 } 68 69 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 70 { 71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 72 mutex_lock(&rdev->pm.mutex); 73 if (power_supply_is_system_supplied() > 0) 74 rdev->pm.dpm.ac_power = true; 75 else 76 rdev->pm.dpm.ac_power = false; 77 if (rdev->family == CHIP_ARUBA) { 78 if (rdev->asic->dpm.enable_bapm) 79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 80 } 81 mutex_unlock(&rdev->pm.mutex); 82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 83 if (rdev->pm.profile == PM_PROFILE_AUTO) { 84 mutex_lock(&rdev->pm.mutex); 85 radeon_pm_update_profile(rdev); 86 radeon_pm_set_clocks(rdev); 87 mutex_unlock(&rdev->pm.mutex); 88 } 89 } 90 } 91 92 static void radeon_pm_update_profile(struct radeon_device *rdev) 93 { 94 switch (rdev->pm.profile) { 95 case PM_PROFILE_DEFAULT: 96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 97 break; 98 case PM_PROFILE_AUTO: 99 if (power_supply_is_system_supplied() > 0) { 100 if (rdev->pm.active_crtc_count > 1) 101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 102 else 103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 104 } else { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 109 } 110 break; 111 case PM_PROFILE_LOW: 112 if (rdev->pm.active_crtc_count > 1) 113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 114 else 115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 116 break; 117 case PM_PROFILE_MID: 118 if (rdev->pm.active_crtc_count > 1) 119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 120 else 121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 122 break; 123 case PM_PROFILE_HIGH: 124 if (rdev->pm.active_crtc_count > 1) 125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 126 else 127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 128 break; 129 } 130 131 if (rdev->pm.active_crtc_count == 0) { 132 rdev->pm.requested_power_state_index = 133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 134 rdev->pm.requested_clock_mode_index = 135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 136 } else { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 141 } 142 } 143 144 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 145 { 146 struct radeon_bo *bo, *n; 147 148 if (list_empty(&rdev->gem.objects)) 149 return; 150 151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 153 ttm_bo_unmap_virtual(&bo->tbo); 154 } 155 } 156 157 static void radeon_sync_with_vblank(struct radeon_device *rdev) 158 { 159 if (rdev->pm.active_crtcs) { 160 rdev->pm.vblank_sync = false; 161 wait_event_timeout( 162 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 164 } 165 } 166 167 static void radeon_set_power_state(struct radeon_device *rdev) 168 { 169 u32 sclk, mclk; 170 bool misc_after = false; 171 172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 174 return; 175 176 if (radeon_gui_idle(rdev)) { 177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 178 clock_info[rdev->pm.requested_clock_mode_index].sclk; 179 if (sclk > rdev->pm.default_sclk) 180 sclk = rdev->pm.default_sclk; 181 182 /* starting with BTC, there is one state that is used for both 183 * MH and SH. Difference is that we always use the high clock index for 184 * mclk and vddci. 185 */ 186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 187 (rdev->family >= CHIP_BARTS) && 188 rdev->pm.active_crtc_count && 189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 193 else 194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 195 clock_info[rdev->pm.requested_clock_mode_index].mclk; 196 197 if (mclk > rdev->pm.default_mclk) 198 mclk = rdev->pm.default_mclk; 199 200 /* upvolt before raising clocks, downvolt after lowering clocks */ 201 if (sclk < rdev->pm.current_sclk) 202 misc_after = true; 203 204 radeon_sync_with_vblank(rdev); 205 206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 207 if (!radeon_pm_in_vbl(rdev)) 208 return; 209 } 210 211 radeon_pm_prepare(rdev); 212 213 if (!misc_after) 214 /* voltage, pcie lanes, etc.*/ 215 radeon_pm_misc(rdev); 216 217 /* set engine clock */ 218 if (sclk != rdev->pm.current_sclk) { 219 radeon_pm_debug_check_in_vbl(rdev, false); 220 radeon_set_engine_clock(rdev, sclk); 221 radeon_pm_debug_check_in_vbl(rdev, true); 222 rdev->pm.current_sclk = sclk; 223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 224 } 225 226 /* set memory clock */ 227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 228 radeon_pm_debug_check_in_vbl(rdev, false); 229 radeon_set_memory_clock(rdev, mclk); 230 radeon_pm_debug_check_in_vbl(rdev, true); 231 rdev->pm.current_mclk = mclk; 232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 233 } 234 235 if (misc_after) 236 /* voltage, pcie lanes, etc.*/ 237 radeon_pm_misc(rdev); 238 239 radeon_pm_finish(rdev); 240 241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 243 } else 244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 245 } 246 247 static void radeon_pm_set_clocks(struct radeon_device *rdev) 248 { 249 int i, r; 250 251 /* no need to take locks, etc. if nothing's going to change */ 252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 254 return; 255 256 down_write(&rdev->pm.mclk_lock); 257 mutex_lock(&rdev->ring_lock); 258 259 /* wait for the rings to drain */ 260 for (i = 0; i < RADEON_NUM_RINGS; i++) { 261 struct radeon_ring *ring = &rdev->ring[i]; 262 if (!ring->ready) { 263 continue; 264 } 265 r = radeon_fence_wait_empty(rdev, i); 266 if (r) { 267 /* needs a GPU reset dont reset here */ 268 mutex_unlock(&rdev->ring_lock); 269 up_write(&rdev->pm.mclk_lock); 270 return; 271 } 272 } 273 274 radeon_unmap_vram_bos(rdev); 275 276 if (rdev->irq.installed) { 277 for (i = 0; i < rdev->num_crtc; i++) { 278 if (rdev->pm.active_crtcs & (1 << i)) { 279 /* This can fail if a modeset is in progress */ 280 if (drm_vblank_get(rdev->ddev, i) == 0) 281 rdev->pm.req_vblank |= (1 << i); 282 else 283 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 284 i); 285 } 286 } 287 } 288 289 radeon_set_power_state(rdev); 290 291 if (rdev->irq.installed) { 292 for (i = 0; i < rdev->num_crtc; i++) { 293 if (rdev->pm.req_vblank & (1 << i)) { 294 rdev->pm.req_vblank &= ~(1 << i); 295 drm_vblank_put(rdev->ddev, i); 296 } 297 } 298 } 299 300 /* update display watermarks based on new power state */ 301 radeon_update_bandwidth_info(rdev); 302 if (rdev->pm.active_crtc_count) 303 radeon_bandwidth_update(rdev); 304 305 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 306 307 mutex_unlock(&rdev->ring_lock); 308 up_write(&rdev->pm.mclk_lock); 309 } 310 311 static void radeon_pm_print_states(struct radeon_device *rdev) 312 { 313 int i, j; 314 struct radeon_power_state *power_state; 315 struct radeon_pm_clock_info *clock_info; 316 317 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 318 for (i = 0; i < rdev->pm.num_power_states; i++) { 319 power_state = &rdev->pm.power_state[i]; 320 DRM_DEBUG_DRIVER("State %d: %s\n", i, 321 radeon_pm_state_type_name[power_state->type]); 322 if (i == rdev->pm.default_power_state_index) 323 DRM_DEBUG_DRIVER("\tDefault"); 324 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 325 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 326 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 327 DRM_DEBUG_DRIVER("\tSingle display only\n"); 328 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 329 for (j = 0; j < power_state->num_clock_modes; j++) { 330 clock_info = &(power_state->clock_info[j]); 331 if (rdev->flags & RADEON_IS_IGP) 332 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 333 j, 334 clock_info->sclk * 10); 335 else 336 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 337 j, 338 clock_info->sclk * 10, 339 clock_info->mclk * 10, 340 clock_info->voltage.voltage); 341 } 342 } 343 } 344 345 static ssize_t radeon_get_pm_profile(struct device *dev, 346 struct device_attribute *attr, 347 char *buf) 348 { 349 struct drm_device *ddev = dev_get_drvdata(dev); 350 struct radeon_device *rdev = ddev->dev_private; 351 int cp = rdev->pm.profile; 352 353 return snprintf(buf, PAGE_SIZE, "%s\n", 354 (cp == PM_PROFILE_AUTO) ? "auto" : 355 (cp == PM_PROFILE_LOW) ? "low" : 356 (cp == PM_PROFILE_MID) ? "mid" : 357 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 358 } 359 360 static ssize_t radeon_set_pm_profile(struct device *dev, 361 struct device_attribute *attr, 362 const char *buf, 363 size_t count) 364 { 365 struct drm_device *ddev = dev_get_drvdata(dev); 366 struct radeon_device *rdev = ddev->dev_private; 367 368 /* Can't set profile when the card is off */ 369 if ((rdev->flags & RADEON_IS_PX) && 370 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 371 return -EINVAL; 372 373 mutex_lock(&rdev->pm.mutex); 374 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 375 if (strncmp("default", buf, strlen("default")) == 0) 376 rdev->pm.profile = PM_PROFILE_DEFAULT; 377 else if (strncmp("auto", buf, strlen("auto")) == 0) 378 rdev->pm.profile = PM_PROFILE_AUTO; 379 else if (strncmp("low", buf, strlen("low")) == 0) 380 rdev->pm.profile = PM_PROFILE_LOW; 381 else if (strncmp("mid", buf, strlen("mid")) == 0) 382 rdev->pm.profile = PM_PROFILE_MID; 383 else if (strncmp("high", buf, strlen("high")) == 0) 384 rdev->pm.profile = PM_PROFILE_HIGH; 385 else { 386 count = -EINVAL; 387 goto fail; 388 } 389 radeon_pm_update_profile(rdev); 390 radeon_pm_set_clocks(rdev); 391 } else 392 count = -EINVAL; 393 394 fail: 395 mutex_unlock(&rdev->pm.mutex); 396 397 return count; 398 } 399 400 static ssize_t radeon_get_pm_method(struct device *dev, 401 struct device_attribute *attr, 402 char *buf) 403 { 404 struct drm_device *ddev = dev_get_drvdata(dev); 405 struct radeon_device *rdev = ddev->dev_private; 406 int pm = rdev->pm.pm_method; 407 408 return snprintf(buf, PAGE_SIZE, "%s\n", 409 (pm == PM_METHOD_DYNPM) ? "dynpm" : 410 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 411 } 412 413 static ssize_t radeon_set_pm_method(struct device *dev, 414 struct device_attribute *attr, 415 const char *buf, 416 size_t count) 417 { 418 struct drm_device *ddev = dev_get_drvdata(dev); 419 struct radeon_device *rdev = ddev->dev_private; 420 421 /* Can't set method when the card is off */ 422 if ((rdev->flags & RADEON_IS_PX) && 423 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 424 count = -EINVAL; 425 goto fail; 426 } 427 428 /* we don't support the legacy modes with dpm */ 429 if (rdev->pm.pm_method == PM_METHOD_DPM) { 430 count = -EINVAL; 431 goto fail; 432 } 433 434 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 435 mutex_lock(&rdev->pm.mutex); 436 rdev->pm.pm_method = PM_METHOD_DYNPM; 437 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 438 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 439 mutex_unlock(&rdev->pm.mutex); 440 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 441 mutex_lock(&rdev->pm.mutex); 442 /* disable dynpm */ 443 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 444 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 445 rdev->pm.pm_method = PM_METHOD_PROFILE; 446 mutex_unlock(&rdev->pm.mutex); 447 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 448 } else { 449 count = -EINVAL; 450 goto fail; 451 } 452 radeon_pm_compute_clocks(rdev); 453 fail: 454 return count; 455 } 456 457 static ssize_t radeon_get_dpm_state(struct device *dev, 458 struct device_attribute *attr, 459 char *buf) 460 { 461 struct drm_device *ddev = dev_get_drvdata(dev); 462 struct radeon_device *rdev = ddev->dev_private; 463 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 464 465 return snprintf(buf, PAGE_SIZE, "%s\n", 466 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 467 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 468 } 469 470 static ssize_t radeon_set_dpm_state(struct device *dev, 471 struct device_attribute *attr, 472 const char *buf, 473 size_t count) 474 { 475 struct drm_device *ddev = dev_get_drvdata(dev); 476 struct radeon_device *rdev = ddev->dev_private; 477 478 mutex_lock(&rdev->pm.mutex); 479 if (strncmp("battery", buf, strlen("battery")) == 0) 480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 481 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 482 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 483 else if (strncmp("performance", buf, strlen("performance")) == 0) 484 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 485 else { 486 mutex_unlock(&rdev->pm.mutex); 487 count = -EINVAL; 488 goto fail; 489 } 490 mutex_unlock(&rdev->pm.mutex); 491 492 /* Can't set dpm state when the card is off */ 493 if (!(rdev->flags & RADEON_IS_PX) || 494 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 495 radeon_pm_compute_clocks(rdev); 496 497 fail: 498 return count; 499 } 500 501 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 502 struct device_attribute *attr, 503 char *buf) 504 { 505 struct drm_device *ddev = dev_get_drvdata(dev); 506 struct radeon_device *rdev = ddev->dev_private; 507 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 508 509 if ((rdev->flags & RADEON_IS_PX) && 510 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 511 return snprintf(buf, PAGE_SIZE, "off\n"); 512 513 return snprintf(buf, PAGE_SIZE, "%s\n", 514 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 515 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 516 } 517 518 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 519 struct device_attribute *attr, 520 const char *buf, 521 size_t count) 522 { 523 struct drm_device *ddev = dev_get_drvdata(dev); 524 struct radeon_device *rdev = ddev->dev_private; 525 enum radeon_dpm_forced_level level; 526 int ret = 0; 527 528 /* Can't force performance level when the card is off */ 529 if ((rdev->flags & RADEON_IS_PX) && 530 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 531 return -EINVAL; 532 533 mutex_lock(&rdev->pm.mutex); 534 if (strncmp("low", buf, strlen("low")) == 0) { 535 level = RADEON_DPM_FORCED_LEVEL_LOW; 536 } else if (strncmp("high", buf, strlen("high")) == 0) { 537 level = RADEON_DPM_FORCED_LEVEL_HIGH; 538 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 539 level = RADEON_DPM_FORCED_LEVEL_AUTO; 540 } else { 541 count = -EINVAL; 542 goto fail; 543 } 544 if (rdev->asic->dpm.force_performance_level) { 545 if (rdev->pm.dpm.thermal_active) { 546 count = -EINVAL; 547 goto fail; 548 } 549 ret = radeon_dpm_force_performance_level(rdev, level); 550 if (ret) 551 count = -EINVAL; 552 } 553 fail: 554 mutex_unlock(&rdev->pm.mutex); 555 556 return count; 557 } 558 559 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 560 struct device_attribute *attr, 561 char *buf) 562 { 563 struct radeon_device *rdev = dev_get_drvdata(dev); 564 u32 pwm_mode = 0; 565 566 if (rdev->asic->dpm.fan_ctrl_get_mode) 567 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 568 569 /* never 0 (full-speed), fuse or smc-controlled always */ 570 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 571 } 572 573 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 574 struct device_attribute *attr, 575 const char *buf, 576 size_t count) 577 { 578 struct radeon_device *rdev = dev_get_drvdata(dev); 579 int err; 580 int value; 581 582 if(!rdev->asic->dpm.fan_ctrl_set_mode) 583 return -EINVAL; 584 585 err = kstrtoint(buf, 10, &value); 586 if (err) 587 return err; 588 589 switch (value) { 590 case 1: /* manual, percent-based */ 591 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 592 break; 593 default: /* disable */ 594 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 595 break; 596 } 597 598 return count; 599 } 600 601 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 602 struct device_attribute *attr, 603 char *buf) 604 { 605 return sprintf(buf, "%i\n", 0); 606 } 607 608 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 609 struct device_attribute *attr, 610 char *buf) 611 { 612 return sprintf(buf, "%i\n", 255); 613 } 614 615 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 616 struct device_attribute *attr, 617 const char *buf, size_t count) 618 { 619 struct radeon_device *rdev = dev_get_drvdata(dev); 620 int err; 621 u32 value; 622 623 err = kstrtou32(buf, 10, &value); 624 if (err) 625 return err; 626 627 value = (value * 100) / 255; 628 629 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 630 if (err) 631 return err; 632 633 return count; 634 } 635 636 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 637 struct device_attribute *attr, 638 char *buf) 639 { 640 struct radeon_device *rdev = dev_get_drvdata(dev); 641 int err; 642 u32 speed; 643 644 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 645 if (err) 646 return err; 647 648 speed = (speed * 255) / 100; 649 650 return sprintf(buf, "%i\n", speed); 651 } 652 653 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 654 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 655 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 656 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 657 radeon_get_dpm_forced_performance_level, 658 radeon_set_dpm_forced_performance_level); 659 660 static ssize_t radeon_hwmon_show_temp(struct device *dev, 661 struct device_attribute *attr, 662 char *buf) 663 { 664 struct radeon_device *rdev = dev_get_drvdata(dev); 665 struct drm_device *ddev = rdev->ddev; 666 int temp; 667 668 /* Can't get temperature when the card is off */ 669 if ((rdev->flags & RADEON_IS_PX) && 670 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 671 return -EINVAL; 672 673 if (rdev->asic->pm.get_temperature) 674 temp = radeon_get_temperature(rdev); 675 else 676 temp = 0; 677 678 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 679 } 680 681 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 682 struct device_attribute *attr, 683 char *buf) 684 { 685 struct radeon_device *rdev = dev_get_drvdata(dev); 686 int hyst = to_sensor_dev_attr(attr)->index; 687 int temp; 688 689 if (hyst) 690 temp = rdev->pm.dpm.thermal.min_temp; 691 else 692 temp = rdev->pm.dpm.thermal.max_temp; 693 694 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 695 } 696 697 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 698 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 699 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 700 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 701 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 702 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 703 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 704 705 706 static struct attribute *hwmon_attributes[] = { 707 &sensor_dev_attr_temp1_input.dev_attr.attr, 708 &sensor_dev_attr_temp1_crit.dev_attr.attr, 709 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 710 &sensor_dev_attr_pwm1.dev_attr.attr, 711 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 712 &sensor_dev_attr_pwm1_min.dev_attr.attr, 713 &sensor_dev_attr_pwm1_max.dev_attr.attr, 714 NULL 715 }; 716 717 static umode_t hwmon_attributes_visible(struct kobject *kobj, 718 struct attribute *attr, int index) 719 { 720 struct device *dev = kobj_to_dev(kobj); 721 struct radeon_device *rdev = dev_get_drvdata(dev); 722 umode_t effective_mode = attr->mode; 723 724 /* Skip attributes if DPM is not enabled */ 725 if (rdev->pm.pm_method != PM_METHOD_DPM && 726 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 727 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 728 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 729 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 730 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 731 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 732 return 0; 733 734 /* Skip fan attributes if fan is not present */ 735 if (rdev->pm.no_fan && 736 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 737 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 738 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 739 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 740 return 0; 741 742 /* mask fan attributes if we have no bindings for this asic to expose */ 743 if ((!rdev->asic->dpm.get_fan_speed_percent && 744 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 745 (!rdev->asic->dpm.fan_ctrl_get_mode && 746 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 747 effective_mode &= ~S_IRUGO; 748 749 if ((!rdev->asic->dpm.set_fan_speed_percent && 750 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 751 (!rdev->asic->dpm.fan_ctrl_set_mode && 752 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 753 effective_mode &= ~S_IWUSR; 754 755 /* hide max/min values if we can't both query and manage the fan */ 756 if ((!rdev->asic->dpm.set_fan_speed_percent && 757 !rdev->asic->dpm.get_fan_speed_percent) && 758 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 759 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 760 return 0; 761 762 return effective_mode; 763 } 764 765 static const struct attribute_group hwmon_attrgroup = { 766 .attrs = hwmon_attributes, 767 .is_visible = hwmon_attributes_visible, 768 }; 769 770 static const struct attribute_group *hwmon_groups[] = { 771 &hwmon_attrgroup, 772 NULL 773 }; 774 775 static int radeon_hwmon_init(struct radeon_device *rdev) 776 { 777 int err = 0; 778 779 switch (rdev->pm.int_thermal_type) { 780 case THERMAL_TYPE_RV6XX: 781 case THERMAL_TYPE_RV770: 782 case THERMAL_TYPE_EVERGREEN: 783 case THERMAL_TYPE_NI: 784 case THERMAL_TYPE_SUMO: 785 case THERMAL_TYPE_SI: 786 case THERMAL_TYPE_CI: 787 case THERMAL_TYPE_KV: 788 if (rdev->asic->pm.get_temperature == NULL) 789 return err; 790 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 791 "radeon", rdev, 792 hwmon_groups); 793 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 794 err = PTR_ERR(rdev->pm.int_hwmon_dev); 795 dev_err(rdev->dev, 796 "Unable to register hwmon device: %d\n", err); 797 } 798 break; 799 default: 800 break; 801 } 802 803 return err; 804 } 805 806 static void radeon_hwmon_fini(struct radeon_device *rdev) 807 { 808 if (rdev->pm.int_hwmon_dev) 809 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 810 } 811 812 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 813 { 814 struct radeon_device *rdev = 815 container_of(work, struct radeon_device, 816 pm.dpm.thermal.work); 817 /* switch to the thermal state */ 818 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 819 820 if (!rdev->pm.dpm_enabled) 821 return; 822 823 if (rdev->asic->pm.get_temperature) { 824 int temp = radeon_get_temperature(rdev); 825 826 if (temp < rdev->pm.dpm.thermal.min_temp) 827 /* switch back the user state */ 828 dpm_state = rdev->pm.dpm.user_state; 829 } else { 830 if (rdev->pm.dpm.thermal.high_to_low) 831 /* switch back the user state */ 832 dpm_state = rdev->pm.dpm.user_state; 833 } 834 mutex_lock(&rdev->pm.mutex); 835 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 836 rdev->pm.dpm.thermal_active = true; 837 else 838 rdev->pm.dpm.thermal_active = false; 839 rdev->pm.dpm.state = dpm_state; 840 mutex_unlock(&rdev->pm.mutex); 841 842 radeon_pm_compute_clocks(rdev); 843 } 844 845 static bool radeon_dpm_single_display(struct radeon_device *rdev) 846 { 847 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 848 true : false; 849 850 /* check if the vblank period is too short to adjust the mclk */ 851 if (single_display && rdev->asic->dpm.vblank_too_short) { 852 if (radeon_dpm_vblank_too_short(rdev)) 853 single_display = false; 854 } 855 856 /* 120hz tends to be problematic even if they are under the 857 * vblank limit. 858 */ 859 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 860 single_display = false; 861 862 return single_display; 863 } 864 865 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 866 enum radeon_pm_state_type dpm_state) 867 { 868 int i; 869 struct radeon_ps *ps; 870 u32 ui_class; 871 bool single_display = radeon_dpm_single_display(rdev); 872 873 /* certain older asics have a separare 3D performance state, 874 * so try that first if the user selected performance 875 */ 876 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 877 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 878 /* balanced states don't exist at the moment */ 879 if (dpm_state == POWER_STATE_TYPE_BALANCED) 880 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 881 882 restart_search: 883 /* Pick the best power state based on current conditions */ 884 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 885 ps = &rdev->pm.dpm.ps[i]; 886 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 887 switch (dpm_state) { 888 /* user states */ 889 case POWER_STATE_TYPE_BATTERY: 890 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 891 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 892 if (single_display) 893 return ps; 894 } else 895 return ps; 896 } 897 break; 898 case POWER_STATE_TYPE_BALANCED: 899 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 900 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 901 if (single_display) 902 return ps; 903 } else 904 return ps; 905 } 906 break; 907 case POWER_STATE_TYPE_PERFORMANCE: 908 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 909 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 910 if (single_display) 911 return ps; 912 } else 913 return ps; 914 } 915 break; 916 /* internal states */ 917 case POWER_STATE_TYPE_INTERNAL_UVD: 918 if (rdev->pm.dpm.uvd_ps) 919 return rdev->pm.dpm.uvd_ps; 920 else 921 break; 922 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 923 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 924 return ps; 925 break; 926 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 927 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 928 return ps; 929 break; 930 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 931 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 932 return ps; 933 break; 934 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 935 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 936 return ps; 937 break; 938 case POWER_STATE_TYPE_INTERNAL_BOOT: 939 return rdev->pm.dpm.boot_ps; 940 case POWER_STATE_TYPE_INTERNAL_THERMAL: 941 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 942 return ps; 943 break; 944 case POWER_STATE_TYPE_INTERNAL_ACPI: 945 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 946 return ps; 947 break; 948 case POWER_STATE_TYPE_INTERNAL_ULV: 949 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 950 return ps; 951 break; 952 case POWER_STATE_TYPE_INTERNAL_3DPERF: 953 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 954 return ps; 955 break; 956 default: 957 break; 958 } 959 } 960 /* use a fallback state if we didn't match */ 961 switch (dpm_state) { 962 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 963 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 964 goto restart_search; 965 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 966 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 967 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 968 if (rdev->pm.dpm.uvd_ps) { 969 return rdev->pm.dpm.uvd_ps; 970 } else { 971 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 972 goto restart_search; 973 } 974 case POWER_STATE_TYPE_INTERNAL_THERMAL: 975 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 976 goto restart_search; 977 case POWER_STATE_TYPE_INTERNAL_ACPI: 978 dpm_state = POWER_STATE_TYPE_BATTERY; 979 goto restart_search; 980 case POWER_STATE_TYPE_BATTERY: 981 case POWER_STATE_TYPE_BALANCED: 982 case POWER_STATE_TYPE_INTERNAL_3DPERF: 983 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 984 goto restart_search; 985 default: 986 break; 987 } 988 989 return NULL; 990 } 991 992 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 993 { 994 int i; 995 struct radeon_ps *ps; 996 enum radeon_pm_state_type dpm_state; 997 int ret; 998 bool single_display = radeon_dpm_single_display(rdev); 999 1000 /* if dpm init failed */ 1001 if (!rdev->pm.dpm_enabled) 1002 return; 1003 1004 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1005 /* add other state override checks here */ 1006 if ((!rdev->pm.dpm.thermal_active) && 1007 (!rdev->pm.dpm.uvd_active)) 1008 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1009 } 1010 dpm_state = rdev->pm.dpm.state; 1011 1012 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1013 if (ps) 1014 rdev->pm.dpm.requested_ps = ps; 1015 else 1016 return; 1017 1018 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1019 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1020 /* vce just modifies an existing state so force a change */ 1021 if (ps->vce_active != rdev->pm.dpm.vce_active) 1022 goto force; 1023 /* user has made a display change (such as timing) */ 1024 if (rdev->pm.dpm.single_display != single_display) 1025 goto force; 1026 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1027 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1028 * all we need to do is update the display configuration. 1029 */ 1030 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1031 /* update display watermarks based on new power state */ 1032 radeon_bandwidth_update(rdev); 1033 /* update displays */ 1034 radeon_dpm_display_configuration_changed(rdev); 1035 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1036 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1037 } 1038 return; 1039 } else { 1040 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1041 * nothing to do, if the num crtcs is > 1 and state is the same, 1042 * update display configuration. 1043 */ 1044 if (rdev->pm.dpm.new_active_crtcs == 1045 rdev->pm.dpm.current_active_crtcs) { 1046 return; 1047 } else { 1048 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1049 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1050 /* update display watermarks based on new power state */ 1051 radeon_bandwidth_update(rdev); 1052 /* update displays */ 1053 radeon_dpm_display_configuration_changed(rdev); 1054 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1055 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1056 return; 1057 } 1058 } 1059 } 1060 } 1061 1062 force: 1063 if (radeon_dpm == 1) { 1064 printk("switching from power state:\n"); 1065 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1066 printk("switching to power state:\n"); 1067 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1068 } 1069 1070 down_write(&rdev->pm.mclk_lock); 1071 mutex_lock(&rdev->ring_lock); 1072 1073 /* update whether vce is active */ 1074 ps->vce_active = rdev->pm.dpm.vce_active; 1075 1076 ret = radeon_dpm_pre_set_power_state(rdev); 1077 if (ret) 1078 goto done; 1079 1080 /* update display watermarks based on new power state */ 1081 radeon_bandwidth_update(rdev); 1082 /* update displays */ 1083 radeon_dpm_display_configuration_changed(rdev); 1084 1085 /* wait for the rings to drain */ 1086 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1087 struct radeon_ring *ring = &rdev->ring[i]; 1088 if (ring->ready) 1089 radeon_fence_wait_empty(rdev, i); 1090 } 1091 1092 /* program the new power state */ 1093 radeon_dpm_set_power_state(rdev); 1094 1095 /* update current power state */ 1096 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1097 1098 radeon_dpm_post_set_power_state(rdev); 1099 1100 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1101 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1102 rdev->pm.dpm.single_display = single_display; 1103 1104 if (rdev->asic->dpm.force_performance_level) { 1105 if (rdev->pm.dpm.thermal_active) { 1106 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1107 /* force low perf level for thermal */ 1108 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1109 /* save the user's level */ 1110 rdev->pm.dpm.forced_level = level; 1111 } else { 1112 /* otherwise, user selected level */ 1113 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1114 } 1115 } 1116 1117 done: 1118 mutex_unlock(&rdev->ring_lock); 1119 up_write(&rdev->pm.mclk_lock); 1120 } 1121 1122 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1123 { 1124 enum radeon_pm_state_type dpm_state; 1125 1126 if (rdev->asic->dpm.powergate_uvd) { 1127 mutex_lock(&rdev->pm.mutex); 1128 /* don't powergate anything if we 1129 have active but pause streams */ 1130 enable |= rdev->pm.dpm.sd > 0; 1131 enable |= rdev->pm.dpm.hd > 0; 1132 /* enable/disable UVD */ 1133 radeon_dpm_powergate_uvd(rdev, !enable); 1134 mutex_unlock(&rdev->pm.mutex); 1135 } else { 1136 if (enable) { 1137 mutex_lock(&rdev->pm.mutex); 1138 rdev->pm.dpm.uvd_active = true; 1139 /* disable this for now */ 1140 #if 0 1141 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1142 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1143 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1144 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1145 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1146 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1147 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1148 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1149 else 1150 #endif 1151 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1152 rdev->pm.dpm.state = dpm_state; 1153 mutex_unlock(&rdev->pm.mutex); 1154 } else { 1155 mutex_lock(&rdev->pm.mutex); 1156 rdev->pm.dpm.uvd_active = false; 1157 mutex_unlock(&rdev->pm.mutex); 1158 } 1159 1160 radeon_pm_compute_clocks(rdev); 1161 } 1162 } 1163 1164 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1165 { 1166 if (enable) { 1167 mutex_lock(&rdev->pm.mutex); 1168 rdev->pm.dpm.vce_active = true; 1169 /* XXX select vce level based on ring/task */ 1170 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1171 mutex_unlock(&rdev->pm.mutex); 1172 } else { 1173 mutex_lock(&rdev->pm.mutex); 1174 rdev->pm.dpm.vce_active = false; 1175 mutex_unlock(&rdev->pm.mutex); 1176 } 1177 1178 radeon_pm_compute_clocks(rdev); 1179 } 1180 1181 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1182 { 1183 mutex_lock(&rdev->pm.mutex); 1184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1185 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1186 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1187 } 1188 mutex_unlock(&rdev->pm.mutex); 1189 1190 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1191 } 1192 1193 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1194 { 1195 mutex_lock(&rdev->pm.mutex); 1196 /* disable dpm */ 1197 radeon_dpm_disable(rdev); 1198 /* reset the power state */ 1199 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1200 rdev->pm.dpm_enabled = false; 1201 mutex_unlock(&rdev->pm.mutex); 1202 } 1203 1204 void radeon_pm_suspend(struct radeon_device *rdev) 1205 { 1206 if (rdev->pm.pm_method == PM_METHOD_DPM) 1207 radeon_pm_suspend_dpm(rdev); 1208 else 1209 radeon_pm_suspend_old(rdev); 1210 } 1211 1212 static void radeon_pm_resume_old(struct radeon_device *rdev) 1213 { 1214 /* set up the default clocks if the MC ucode is loaded */ 1215 if ((rdev->family >= CHIP_BARTS) && 1216 (rdev->family <= CHIP_CAYMAN) && 1217 rdev->mc_fw) { 1218 if (rdev->pm.default_vddc) 1219 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1220 SET_VOLTAGE_TYPE_ASIC_VDDC); 1221 if (rdev->pm.default_vddci) 1222 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1223 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1224 if (rdev->pm.default_sclk) 1225 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1226 if (rdev->pm.default_mclk) 1227 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1228 } 1229 /* asic init will reset the default power state */ 1230 mutex_lock(&rdev->pm.mutex); 1231 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1232 rdev->pm.current_clock_mode_index = 0; 1233 rdev->pm.current_sclk = rdev->pm.default_sclk; 1234 rdev->pm.current_mclk = rdev->pm.default_mclk; 1235 if (rdev->pm.power_state) { 1236 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1237 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1238 } 1239 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1240 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1241 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1242 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1243 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1244 } 1245 mutex_unlock(&rdev->pm.mutex); 1246 radeon_pm_compute_clocks(rdev); 1247 } 1248 1249 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1250 { 1251 int ret; 1252 1253 /* asic init will reset to the boot state */ 1254 mutex_lock(&rdev->pm.mutex); 1255 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1256 radeon_dpm_setup_asic(rdev); 1257 ret = radeon_dpm_enable(rdev); 1258 mutex_unlock(&rdev->pm.mutex); 1259 if (ret) 1260 goto dpm_resume_fail; 1261 rdev->pm.dpm_enabled = true; 1262 return; 1263 1264 dpm_resume_fail: 1265 DRM_ERROR("radeon: dpm resume failed\n"); 1266 if ((rdev->family >= CHIP_BARTS) && 1267 (rdev->family <= CHIP_CAYMAN) && 1268 rdev->mc_fw) { 1269 if (rdev->pm.default_vddc) 1270 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1271 SET_VOLTAGE_TYPE_ASIC_VDDC); 1272 if (rdev->pm.default_vddci) 1273 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1274 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1275 if (rdev->pm.default_sclk) 1276 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1277 if (rdev->pm.default_mclk) 1278 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1279 } 1280 } 1281 1282 void radeon_pm_resume(struct radeon_device *rdev) 1283 { 1284 if (rdev->pm.pm_method == PM_METHOD_DPM) 1285 radeon_pm_resume_dpm(rdev); 1286 else 1287 radeon_pm_resume_old(rdev); 1288 } 1289 1290 static int radeon_pm_init_old(struct radeon_device *rdev) 1291 { 1292 int ret; 1293 1294 rdev->pm.profile = PM_PROFILE_DEFAULT; 1295 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1296 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1297 rdev->pm.dynpm_can_upclock = true; 1298 rdev->pm.dynpm_can_downclock = true; 1299 rdev->pm.default_sclk = rdev->clock.default_sclk; 1300 rdev->pm.default_mclk = rdev->clock.default_mclk; 1301 rdev->pm.current_sclk = rdev->clock.default_sclk; 1302 rdev->pm.current_mclk = rdev->clock.default_mclk; 1303 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1304 1305 if (rdev->bios) { 1306 if (rdev->is_atom_bios) 1307 radeon_atombios_get_power_modes(rdev); 1308 else 1309 radeon_combios_get_power_modes(rdev); 1310 radeon_pm_print_states(rdev); 1311 radeon_pm_init_profile(rdev); 1312 /* set up the default clocks if the MC ucode is loaded */ 1313 if ((rdev->family >= CHIP_BARTS) && 1314 (rdev->family <= CHIP_CAYMAN) && 1315 rdev->mc_fw) { 1316 if (rdev->pm.default_vddc) 1317 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1318 SET_VOLTAGE_TYPE_ASIC_VDDC); 1319 if (rdev->pm.default_vddci) 1320 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1321 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1322 if (rdev->pm.default_sclk) 1323 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1324 if (rdev->pm.default_mclk) 1325 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1326 } 1327 } 1328 1329 /* set up the internal thermal sensor if applicable */ 1330 ret = radeon_hwmon_init(rdev); 1331 if (ret) 1332 return ret; 1333 1334 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1335 1336 if (rdev->pm.num_power_states > 1) { 1337 if (radeon_debugfs_pm_init(rdev)) { 1338 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1339 } 1340 1341 DRM_INFO("radeon: power management initialized\n"); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1348 { 1349 int i; 1350 1351 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1352 printk("== power state %d ==\n", i); 1353 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1354 } 1355 } 1356 1357 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1358 { 1359 int ret; 1360 1361 /* default to balanced state */ 1362 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1363 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1364 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1365 rdev->pm.default_sclk = rdev->clock.default_sclk; 1366 rdev->pm.default_mclk = rdev->clock.default_mclk; 1367 rdev->pm.current_sclk = rdev->clock.default_sclk; 1368 rdev->pm.current_mclk = rdev->clock.default_mclk; 1369 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1370 1371 if (rdev->bios && rdev->is_atom_bios) 1372 radeon_atombios_get_power_modes(rdev); 1373 else 1374 return -EINVAL; 1375 1376 /* set up the internal thermal sensor if applicable */ 1377 ret = radeon_hwmon_init(rdev); 1378 if (ret) 1379 return ret; 1380 1381 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1382 mutex_lock(&rdev->pm.mutex); 1383 radeon_dpm_init(rdev); 1384 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1385 if (radeon_dpm == 1) 1386 radeon_dpm_print_power_states(rdev); 1387 radeon_dpm_setup_asic(rdev); 1388 ret = radeon_dpm_enable(rdev); 1389 mutex_unlock(&rdev->pm.mutex); 1390 if (ret) 1391 goto dpm_failed; 1392 rdev->pm.dpm_enabled = true; 1393 1394 if (radeon_debugfs_pm_init(rdev)) { 1395 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1396 } 1397 1398 DRM_INFO("radeon: dpm initialized\n"); 1399 1400 return 0; 1401 1402 dpm_failed: 1403 rdev->pm.dpm_enabled = false; 1404 if ((rdev->family >= CHIP_BARTS) && 1405 (rdev->family <= CHIP_CAYMAN) && 1406 rdev->mc_fw) { 1407 if (rdev->pm.default_vddc) 1408 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1409 SET_VOLTAGE_TYPE_ASIC_VDDC); 1410 if (rdev->pm.default_vddci) 1411 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1412 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1413 if (rdev->pm.default_sclk) 1414 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1415 if (rdev->pm.default_mclk) 1416 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1417 } 1418 DRM_ERROR("radeon: dpm initialization failed\n"); 1419 return ret; 1420 } 1421 1422 struct radeon_dpm_quirk { 1423 u32 chip_vendor; 1424 u32 chip_device; 1425 u32 subsys_vendor; 1426 u32 subsys_device; 1427 }; 1428 1429 /* cards with dpm stability problems */ 1430 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1431 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1432 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1433 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1434 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1435 { 0, 0, 0, 0 }, 1436 }; 1437 1438 int radeon_pm_init(struct radeon_device *rdev) 1439 { 1440 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1441 bool disable_dpm = false; 1442 1443 /* Apply dpm quirks */ 1444 while (p && p->chip_device != 0) { 1445 if (rdev->pdev->vendor == p->chip_vendor && 1446 rdev->pdev->device == p->chip_device && 1447 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1448 rdev->pdev->subsystem_device == p->subsys_device) { 1449 disable_dpm = true; 1450 break; 1451 } 1452 ++p; 1453 } 1454 1455 /* enable dpm on rv6xx+ */ 1456 switch (rdev->family) { 1457 case CHIP_RV610: 1458 case CHIP_RV630: 1459 case CHIP_RV620: 1460 case CHIP_RV635: 1461 case CHIP_RV670: 1462 case CHIP_RS780: 1463 case CHIP_RS880: 1464 case CHIP_RV770: 1465 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1466 if (!rdev->rlc_fw) 1467 rdev->pm.pm_method = PM_METHOD_PROFILE; 1468 else if ((rdev->family >= CHIP_RV770) && 1469 (!(rdev->flags & RADEON_IS_IGP)) && 1470 (!rdev->smc_fw)) 1471 rdev->pm.pm_method = PM_METHOD_PROFILE; 1472 else if (radeon_dpm == 1) 1473 rdev->pm.pm_method = PM_METHOD_DPM; 1474 else 1475 rdev->pm.pm_method = PM_METHOD_PROFILE; 1476 break; 1477 case CHIP_RV730: 1478 case CHIP_RV710: 1479 case CHIP_RV740: 1480 case CHIP_CEDAR: 1481 case CHIP_REDWOOD: 1482 case CHIP_JUNIPER: 1483 case CHIP_CYPRESS: 1484 case CHIP_HEMLOCK: 1485 case CHIP_PALM: 1486 case CHIP_SUMO: 1487 case CHIP_SUMO2: 1488 case CHIP_BARTS: 1489 case CHIP_TURKS: 1490 case CHIP_CAICOS: 1491 case CHIP_CAYMAN: 1492 case CHIP_ARUBA: 1493 case CHIP_TAHITI: 1494 case CHIP_PITCAIRN: 1495 case CHIP_VERDE: 1496 case CHIP_OLAND: 1497 case CHIP_HAINAN: 1498 case CHIP_BONAIRE: 1499 case CHIP_KABINI: 1500 case CHIP_KAVERI: 1501 case CHIP_HAWAII: 1502 case CHIP_MULLINS: 1503 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1504 if (!rdev->rlc_fw) 1505 rdev->pm.pm_method = PM_METHOD_PROFILE; 1506 else if ((rdev->family >= CHIP_RV770) && 1507 (!(rdev->flags & RADEON_IS_IGP)) && 1508 (!rdev->smc_fw)) 1509 rdev->pm.pm_method = PM_METHOD_PROFILE; 1510 else if (disable_dpm && (radeon_dpm == -1)) 1511 rdev->pm.pm_method = PM_METHOD_PROFILE; 1512 else if (radeon_dpm == 0) 1513 rdev->pm.pm_method = PM_METHOD_PROFILE; 1514 else 1515 rdev->pm.pm_method = PM_METHOD_DPM; 1516 break; 1517 default: 1518 /* default to profile method */ 1519 rdev->pm.pm_method = PM_METHOD_PROFILE; 1520 break; 1521 } 1522 1523 if (rdev->pm.pm_method == PM_METHOD_DPM) 1524 return radeon_pm_init_dpm(rdev); 1525 else 1526 return radeon_pm_init_old(rdev); 1527 } 1528 1529 int radeon_pm_late_init(struct radeon_device *rdev) 1530 { 1531 int ret = 0; 1532 1533 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1534 if (rdev->pm.dpm_enabled) { 1535 if (!rdev->pm.sysfs_initialized) { 1536 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1537 if (ret) 1538 DRM_ERROR("failed to create device file for dpm state\n"); 1539 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1540 if (ret) 1541 DRM_ERROR("failed to create device file for dpm state\n"); 1542 /* XXX: these are noops for dpm but are here for backwards compat */ 1543 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1544 if (ret) 1545 DRM_ERROR("failed to create device file for power profile\n"); 1546 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1547 if (ret) 1548 DRM_ERROR("failed to create device file for power method\n"); 1549 rdev->pm.sysfs_initialized = true; 1550 } 1551 1552 mutex_lock(&rdev->pm.mutex); 1553 ret = radeon_dpm_late_enable(rdev); 1554 mutex_unlock(&rdev->pm.mutex); 1555 if (ret) { 1556 rdev->pm.dpm_enabled = false; 1557 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1558 } else { 1559 /* set the dpm state for PX since there won't be 1560 * a modeset to call this. 1561 */ 1562 radeon_pm_compute_clocks(rdev); 1563 } 1564 } 1565 } else { 1566 if ((rdev->pm.num_power_states > 1) && 1567 (!rdev->pm.sysfs_initialized)) { 1568 /* where's the best place to put these? */ 1569 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1570 if (ret) 1571 DRM_ERROR("failed to create device file for power profile\n"); 1572 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1573 if (ret) 1574 DRM_ERROR("failed to create device file for power method\n"); 1575 if (!ret) 1576 rdev->pm.sysfs_initialized = true; 1577 } 1578 } 1579 return ret; 1580 } 1581 1582 static void radeon_pm_fini_old(struct radeon_device *rdev) 1583 { 1584 if (rdev->pm.num_power_states > 1) { 1585 mutex_lock(&rdev->pm.mutex); 1586 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1587 rdev->pm.profile = PM_PROFILE_DEFAULT; 1588 radeon_pm_update_profile(rdev); 1589 radeon_pm_set_clocks(rdev); 1590 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1591 /* reset default clocks */ 1592 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1593 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1594 radeon_pm_set_clocks(rdev); 1595 } 1596 mutex_unlock(&rdev->pm.mutex); 1597 1598 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1599 1600 device_remove_file(rdev->dev, &dev_attr_power_profile); 1601 device_remove_file(rdev->dev, &dev_attr_power_method); 1602 } 1603 1604 radeon_hwmon_fini(rdev); 1605 kfree(rdev->pm.power_state); 1606 } 1607 1608 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1609 { 1610 if (rdev->pm.num_power_states > 1) { 1611 mutex_lock(&rdev->pm.mutex); 1612 radeon_dpm_disable(rdev); 1613 mutex_unlock(&rdev->pm.mutex); 1614 1615 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1616 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1617 /* XXX backwards compat */ 1618 device_remove_file(rdev->dev, &dev_attr_power_profile); 1619 device_remove_file(rdev->dev, &dev_attr_power_method); 1620 } 1621 radeon_dpm_fini(rdev); 1622 1623 radeon_hwmon_fini(rdev); 1624 kfree(rdev->pm.power_state); 1625 } 1626 1627 void radeon_pm_fini(struct radeon_device *rdev) 1628 { 1629 if (rdev->pm.pm_method == PM_METHOD_DPM) 1630 radeon_pm_fini_dpm(rdev); 1631 else 1632 radeon_pm_fini_old(rdev); 1633 } 1634 1635 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1636 { 1637 struct drm_device *ddev = rdev->ddev; 1638 struct drm_crtc *crtc; 1639 struct radeon_crtc *radeon_crtc; 1640 1641 if (rdev->pm.num_power_states < 2) 1642 return; 1643 1644 mutex_lock(&rdev->pm.mutex); 1645 1646 rdev->pm.active_crtcs = 0; 1647 rdev->pm.active_crtc_count = 0; 1648 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1649 list_for_each_entry(crtc, 1650 &ddev->mode_config.crtc_list, head) { 1651 radeon_crtc = to_radeon_crtc(crtc); 1652 if (radeon_crtc->enabled) { 1653 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1654 rdev->pm.active_crtc_count++; 1655 } 1656 } 1657 } 1658 1659 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1660 radeon_pm_update_profile(rdev); 1661 radeon_pm_set_clocks(rdev); 1662 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1663 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1664 if (rdev->pm.active_crtc_count > 1) { 1665 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1666 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1667 1668 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1669 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1670 radeon_pm_get_dynpm_state(rdev); 1671 radeon_pm_set_clocks(rdev); 1672 1673 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1674 } 1675 } else if (rdev->pm.active_crtc_count == 1) { 1676 /* TODO: Increase clocks if needed for current mode */ 1677 1678 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1679 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1680 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1681 radeon_pm_get_dynpm_state(rdev); 1682 radeon_pm_set_clocks(rdev); 1683 1684 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1685 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1686 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1687 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1688 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1689 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1690 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1691 } 1692 } else { /* count == 0 */ 1693 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1694 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1695 1696 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1697 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1698 radeon_pm_get_dynpm_state(rdev); 1699 radeon_pm_set_clocks(rdev); 1700 } 1701 } 1702 } 1703 } 1704 1705 mutex_unlock(&rdev->pm.mutex); 1706 } 1707 1708 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1709 { 1710 struct drm_device *ddev = rdev->ddev; 1711 struct drm_crtc *crtc; 1712 struct radeon_crtc *radeon_crtc; 1713 1714 if (!rdev->pm.dpm_enabled) 1715 return; 1716 1717 mutex_lock(&rdev->pm.mutex); 1718 1719 /* update active crtc counts */ 1720 rdev->pm.dpm.new_active_crtcs = 0; 1721 rdev->pm.dpm.new_active_crtc_count = 0; 1722 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1723 list_for_each_entry(crtc, 1724 &ddev->mode_config.crtc_list, head) { 1725 radeon_crtc = to_radeon_crtc(crtc); 1726 if (crtc->enabled) { 1727 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1728 rdev->pm.dpm.new_active_crtc_count++; 1729 } 1730 } 1731 } 1732 1733 /* update battery/ac status */ 1734 if (power_supply_is_system_supplied() > 0) 1735 rdev->pm.dpm.ac_power = true; 1736 else 1737 rdev->pm.dpm.ac_power = false; 1738 1739 radeon_dpm_change_power_state_locked(rdev); 1740 1741 mutex_unlock(&rdev->pm.mutex); 1742 1743 } 1744 1745 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1746 { 1747 if (rdev->pm.pm_method == PM_METHOD_DPM) 1748 radeon_pm_compute_clocks_dpm(rdev); 1749 else 1750 radeon_pm_compute_clocks_old(rdev); 1751 } 1752 1753 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1754 { 1755 int crtc, vpos, hpos, vbl_status; 1756 bool in_vbl = true; 1757 1758 /* Iterate over all active crtc's. All crtc's must be in vblank, 1759 * otherwise return in_vbl == false. 1760 */ 1761 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1762 if (rdev->pm.active_crtcs & (1 << crtc)) { 1763 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1764 crtc, 1765 USE_REAL_VBLANKSTART, 1766 &vpos, &hpos, NULL, NULL, 1767 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1768 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1769 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1770 in_vbl = false; 1771 } 1772 } 1773 1774 return in_vbl; 1775 } 1776 1777 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1778 { 1779 u32 stat_crtc = 0; 1780 bool in_vbl = radeon_pm_in_vbl(rdev); 1781 1782 if (in_vbl == false) 1783 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1784 finish ? "exit" : "entry"); 1785 return in_vbl; 1786 } 1787 1788 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1789 { 1790 struct radeon_device *rdev; 1791 int resched; 1792 rdev = container_of(work, struct radeon_device, 1793 pm.dynpm_idle_work.work); 1794 1795 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1796 mutex_lock(&rdev->pm.mutex); 1797 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1798 int not_processed = 0; 1799 int i; 1800 1801 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1802 struct radeon_ring *ring = &rdev->ring[i]; 1803 1804 if (ring->ready) { 1805 not_processed += radeon_fence_count_emitted(rdev, i); 1806 if (not_processed >= 3) 1807 break; 1808 } 1809 } 1810 1811 if (not_processed >= 3) { /* should upclock */ 1812 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1813 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1814 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1815 rdev->pm.dynpm_can_upclock) { 1816 rdev->pm.dynpm_planned_action = 1817 DYNPM_ACTION_UPCLOCK; 1818 rdev->pm.dynpm_action_timeout = jiffies + 1819 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1820 } 1821 } else if (not_processed == 0) { /* should downclock */ 1822 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1823 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1824 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1825 rdev->pm.dynpm_can_downclock) { 1826 rdev->pm.dynpm_planned_action = 1827 DYNPM_ACTION_DOWNCLOCK; 1828 rdev->pm.dynpm_action_timeout = jiffies + 1829 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1830 } 1831 } 1832 1833 /* Note, radeon_pm_set_clocks is called with static_switch set 1834 * to false since we want to wait for vbl to avoid flicker. 1835 */ 1836 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1837 jiffies > rdev->pm.dynpm_action_timeout) { 1838 radeon_pm_get_dynpm_state(rdev); 1839 radeon_pm_set_clocks(rdev); 1840 } 1841 1842 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1843 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1844 } 1845 mutex_unlock(&rdev->pm.mutex); 1846 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1847 } 1848 1849 /* 1850 * Debugfs info 1851 */ 1852 #if defined(CONFIG_DEBUG_FS) 1853 1854 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1855 { 1856 struct drm_info_node *node = (struct drm_info_node *) m->private; 1857 struct drm_device *dev = node->minor->dev; 1858 struct radeon_device *rdev = dev->dev_private; 1859 struct drm_device *ddev = rdev->ddev; 1860 1861 if ((rdev->flags & RADEON_IS_PX) && 1862 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1863 seq_printf(m, "PX asic powered off\n"); 1864 } else if (rdev->pm.dpm_enabled) { 1865 mutex_lock(&rdev->pm.mutex); 1866 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1867 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1868 else 1869 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1870 mutex_unlock(&rdev->pm.mutex); 1871 } else { 1872 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1873 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1874 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1875 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1876 else 1877 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1878 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1879 if (rdev->asic->pm.get_memory_clock) 1880 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1881 if (rdev->pm.current_vddc) 1882 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1883 if (rdev->asic->pm.get_pcie_lanes) 1884 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1885 } 1886 1887 return 0; 1888 } 1889 1890 static struct drm_info_list radeon_pm_info_list[] = { 1891 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1892 }; 1893 #endif 1894 1895 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1896 { 1897 #if defined(CONFIG_DEBUG_FS) 1898 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1899 #else 1900 return 0; 1901 #endif 1902 } 1903