1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include "radeon_drm.h" 36 #include "radeon.h" 37 #include "radeon_trace.h" 38 39 40 int radeon_ttm_init(struct radeon_device *rdev); 41 void radeon_ttm_fini(struct radeon_device *rdev); 42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 43 44 /* 45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 46 * function are calling it. 47 */ 48 49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 50 { 51 struct radeon_bo *bo; 52 53 bo = container_of(tbo, struct radeon_bo, tbo); 54 mutex_lock(&bo->rdev->gem.mutex); 55 list_del_init(&bo->list); 56 mutex_unlock(&bo->rdev->gem.mutex); 57 radeon_bo_clear_surface_reg(bo); 58 kfree(bo); 59 } 60 61 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 62 { 63 if (bo->destroy == &radeon_ttm_bo_destroy) 64 return true; 65 return false; 66 } 67 68 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 69 { 70 u32 c = 0; 71 72 rbo->placement.fpfn = 0; 73 rbo->placement.lpfn = 0; 74 rbo->placement.placement = rbo->placements; 75 rbo->placement.busy_placement = rbo->placements; 76 if (domain & RADEON_GEM_DOMAIN_VRAM) 77 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 78 TTM_PL_FLAG_VRAM; 79 if (domain & RADEON_GEM_DOMAIN_GTT) 80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 81 if (domain & RADEON_GEM_DOMAIN_CPU) 82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 83 if (!c) 84 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 85 rbo->placement.num_placement = c; 86 rbo->placement.num_busy_placement = c; 87 } 88 89 int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, 90 unsigned long size, int byte_align, bool kernel, u32 domain, 91 struct radeon_bo **bo_ptr) 92 { 93 struct radeon_bo *bo; 94 enum ttm_bo_type type; 95 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 96 unsigned long max_size = 0; 97 int r; 98 99 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { 100 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 101 } 102 if (kernel) { 103 type = ttm_bo_type_kernel; 104 } else { 105 type = ttm_bo_type_device; 106 } 107 *bo_ptr = NULL; 108 109 /* maximun bo size is the minimun btw visible vram and gtt size */ 110 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size); 111 if ((page_align << PAGE_SHIFT) >= max_size) { 112 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n", 113 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20); 114 return -ENOMEM; 115 } 116 117 retry: 118 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 119 if (bo == NULL) 120 return -ENOMEM; 121 bo->rdev = rdev; 122 bo->gobj = gobj; 123 bo->surface_reg = -1; 124 INIT_LIST_HEAD(&bo->list); 125 radeon_ttm_placement_from_domain(bo, domain); 126 /* Kernel allocation are uninterruptible */ 127 mutex_lock(&rdev->vram_mutex); 128 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 129 &bo->placement, page_align, 0, !kernel, NULL, size, 130 &radeon_ttm_bo_destroy); 131 mutex_unlock(&rdev->vram_mutex); 132 if (unlikely(r != 0)) { 133 if (r != -ERESTARTSYS) { 134 if (domain == RADEON_GEM_DOMAIN_VRAM) { 135 domain |= RADEON_GEM_DOMAIN_GTT; 136 goto retry; 137 } 138 dev_err(rdev->dev, 139 "object_init failed for (%lu, 0x%08X)\n", 140 size, domain); 141 } 142 return r; 143 } 144 *bo_ptr = bo; 145 if (gobj) { 146 mutex_lock(&bo->rdev->gem.mutex); 147 list_add_tail(&bo->list, &rdev->gem.objects); 148 mutex_unlock(&bo->rdev->gem.mutex); 149 } 150 trace_radeon_bo_create(bo); 151 return 0; 152 } 153 154 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 155 { 156 bool is_iomem; 157 int r; 158 159 if (bo->kptr) { 160 if (ptr) { 161 *ptr = bo->kptr; 162 } 163 return 0; 164 } 165 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 166 if (r) { 167 return r; 168 } 169 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 170 if (ptr) { 171 *ptr = bo->kptr; 172 } 173 radeon_bo_check_tiling(bo, 0, 0); 174 return 0; 175 } 176 177 void radeon_bo_kunmap(struct radeon_bo *bo) 178 { 179 if (bo->kptr == NULL) 180 return; 181 bo->kptr = NULL; 182 radeon_bo_check_tiling(bo, 0, 0); 183 ttm_bo_kunmap(&bo->kmap); 184 } 185 186 void radeon_bo_unref(struct radeon_bo **bo) 187 { 188 struct ttm_buffer_object *tbo; 189 struct radeon_device *rdev; 190 191 if ((*bo) == NULL) 192 return; 193 rdev = (*bo)->rdev; 194 tbo = &((*bo)->tbo); 195 mutex_lock(&rdev->vram_mutex); 196 ttm_bo_unref(&tbo); 197 mutex_unlock(&rdev->vram_mutex); 198 if (tbo == NULL) 199 *bo = NULL; 200 } 201 202 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 203 { 204 int r, i; 205 206 if (bo->pin_count) { 207 bo->pin_count++; 208 if (gpu_addr) 209 *gpu_addr = radeon_bo_gpu_offset(bo); 210 return 0; 211 } 212 radeon_ttm_placement_from_domain(bo, domain); 213 if (domain == RADEON_GEM_DOMAIN_VRAM) { 214 /* force to pin into visible video ram */ 215 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 216 } 217 for (i = 0; i < bo->placement.num_placement; i++) 218 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 219 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 220 if (likely(r == 0)) { 221 bo->pin_count = 1; 222 if (gpu_addr != NULL) 223 *gpu_addr = radeon_bo_gpu_offset(bo); 224 } 225 if (unlikely(r != 0)) 226 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 227 return r; 228 } 229 230 int radeon_bo_unpin(struct radeon_bo *bo) 231 { 232 int r, i; 233 234 if (!bo->pin_count) { 235 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 236 return 0; 237 } 238 bo->pin_count--; 239 if (bo->pin_count) 240 return 0; 241 for (i = 0; i < bo->placement.num_placement; i++) 242 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 243 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 244 if (unlikely(r != 0)) 245 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 246 return r; 247 } 248 249 int radeon_bo_evict_vram(struct radeon_device *rdev) 250 { 251 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 252 if (0 && (rdev->flags & RADEON_IS_IGP)) { 253 if (rdev->mc.igp_sideport_enabled == false) 254 /* Useless to evict on IGP chips */ 255 return 0; 256 } 257 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 258 } 259 260 void radeon_bo_force_delete(struct radeon_device *rdev) 261 { 262 struct radeon_bo *bo, *n; 263 struct drm_gem_object *gobj; 264 265 if (list_empty(&rdev->gem.objects)) { 266 return; 267 } 268 dev_err(rdev->dev, "Userspace still has active objects !\n"); 269 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 270 mutex_lock(&rdev->ddev->struct_mutex); 271 gobj = bo->gobj; 272 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 273 gobj, bo, (unsigned long)gobj->size, 274 *((unsigned long *)&gobj->refcount)); 275 mutex_lock(&bo->rdev->gem.mutex); 276 list_del_init(&bo->list); 277 mutex_unlock(&bo->rdev->gem.mutex); 278 radeon_bo_unref(&bo); 279 gobj->driver_private = NULL; 280 drm_gem_object_unreference(gobj); 281 mutex_unlock(&rdev->ddev->struct_mutex); 282 } 283 } 284 285 int radeon_bo_init(struct radeon_device *rdev) 286 { 287 /* Add an MTRR for the VRAM */ 288 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 289 MTRR_TYPE_WRCOMB, 1); 290 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 291 rdev->mc.mc_vram_size >> 20, 292 (unsigned long long)rdev->mc.aper_size >> 20); 293 DRM_INFO("RAM width %dbits %cDR\n", 294 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 295 return radeon_ttm_init(rdev); 296 } 297 298 void radeon_bo_fini(struct radeon_device *rdev) 299 { 300 radeon_ttm_fini(rdev); 301 } 302 303 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 304 struct list_head *head) 305 { 306 if (lobj->wdomain) { 307 list_add(&lobj->tv.head, head); 308 } else { 309 list_add_tail(&lobj->tv.head, head); 310 } 311 } 312 313 int radeon_bo_list_validate(struct list_head *head) 314 { 315 struct radeon_bo_list *lobj; 316 struct radeon_bo *bo; 317 u32 domain; 318 int r; 319 320 r = ttm_eu_reserve_buffers(head); 321 if (unlikely(r != 0)) { 322 return r; 323 } 324 list_for_each_entry(lobj, head, tv.head) { 325 bo = lobj->bo; 326 if (!bo->pin_count) { 327 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 328 329 retry: 330 radeon_ttm_placement_from_domain(bo, domain); 331 r = ttm_bo_validate(&bo->tbo, &bo->placement, 332 true, false, false); 333 if (unlikely(r)) { 334 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 335 domain |= RADEON_GEM_DOMAIN_GTT; 336 goto retry; 337 } 338 return r; 339 } 340 } 341 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 342 lobj->tiling_flags = bo->tiling_flags; 343 } 344 return 0; 345 } 346 347 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 348 struct vm_area_struct *vma) 349 { 350 return ttm_fbdev_mmap(vma, &bo->tbo); 351 } 352 353 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 354 { 355 struct radeon_device *rdev = bo->rdev; 356 struct radeon_surface_reg *reg; 357 struct radeon_bo *old_object; 358 int steal; 359 int i; 360 361 BUG_ON(!atomic_read(&bo->tbo.reserved)); 362 363 if (!bo->tiling_flags) 364 return 0; 365 366 if (bo->surface_reg >= 0) { 367 reg = &rdev->surface_regs[bo->surface_reg]; 368 i = bo->surface_reg; 369 goto out; 370 } 371 372 steal = -1; 373 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 374 375 reg = &rdev->surface_regs[i]; 376 if (!reg->bo) 377 break; 378 379 old_object = reg->bo; 380 if (old_object->pin_count == 0) 381 steal = i; 382 } 383 384 /* if we are all out */ 385 if (i == RADEON_GEM_MAX_SURFACES) { 386 if (steal == -1) 387 return -ENOMEM; 388 /* find someone with a surface reg and nuke their BO */ 389 reg = &rdev->surface_regs[steal]; 390 old_object = reg->bo; 391 /* blow away the mapping */ 392 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 393 ttm_bo_unmap_virtual(&old_object->tbo); 394 old_object->surface_reg = -1; 395 i = steal; 396 } 397 398 bo->surface_reg = i; 399 reg->bo = bo; 400 401 out: 402 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 403 bo->tbo.mem.start << PAGE_SHIFT, 404 bo->tbo.num_pages << PAGE_SHIFT); 405 return 0; 406 } 407 408 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 409 { 410 struct radeon_device *rdev = bo->rdev; 411 struct radeon_surface_reg *reg; 412 413 if (bo->surface_reg == -1) 414 return; 415 416 reg = &rdev->surface_regs[bo->surface_reg]; 417 radeon_clear_surface_reg(rdev, bo->surface_reg); 418 419 reg->bo = NULL; 420 bo->surface_reg = -1; 421 } 422 423 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 424 uint32_t tiling_flags, uint32_t pitch) 425 { 426 int r; 427 428 r = radeon_bo_reserve(bo, false); 429 if (unlikely(r != 0)) 430 return r; 431 bo->tiling_flags = tiling_flags; 432 bo->pitch = pitch; 433 radeon_bo_unreserve(bo); 434 return 0; 435 } 436 437 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 438 uint32_t *tiling_flags, 439 uint32_t *pitch) 440 { 441 BUG_ON(!atomic_read(&bo->tbo.reserved)); 442 if (tiling_flags) 443 *tiling_flags = bo->tiling_flags; 444 if (pitch) 445 *pitch = bo->pitch; 446 } 447 448 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 449 bool force_drop) 450 { 451 BUG_ON(!atomic_read(&bo->tbo.reserved)); 452 453 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 454 return 0; 455 456 if (force_drop) { 457 radeon_bo_clear_surface_reg(bo); 458 return 0; 459 } 460 461 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 462 if (!has_moved) 463 return 0; 464 465 if (bo->surface_reg >= 0) 466 radeon_bo_clear_surface_reg(bo); 467 return 0; 468 } 469 470 if ((bo->surface_reg >= 0) && !has_moved) 471 return 0; 472 473 return radeon_bo_get_surface_reg(bo); 474 } 475 476 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 477 struct ttm_mem_reg *mem) 478 { 479 struct radeon_bo *rbo; 480 if (!radeon_ttm_bo_is_radeon_bo(bo)) 481 return; 482 rbo = container_of(bo, struct radeon_bo, tbo); 483 radeon_bo_check_tiling(rbo, 0, 1); 484 } 485 486 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 487 { 488 struct radeon_device *rdev; 489 struct radeon_bo *rbo; 490 unsigned long offset, size; 491 int r; 492 493 if (!radeon_ttm_bo_is_radeon_bo(bo)) 494 return 0; 495 rbo = container_of(bo, struct radeon_bo, tbo); 496 radeon_bo_check_tiling(rbo, 0, 0); 497 rdev = rbo->rdev; 498 if (bo->mem.mem_type == TTM_PL_VRAM) { 499 size = bo->mem.num_pages << PAGE_SHIFT; 500 offset = bo->mem.start << PAGE_SHIFT; 501 if ((offset + size) > rdev->mc.visible_vram_size) { 502 /* hurrah the memory is not visible ! */ 503 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 504 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 505 r = ttm_bo_validate(bo, &rbo->placement, false, true, false); 506 if (unlikely(r != 0)) 507 return r; 508 offset = bo->mem.start << PAGE_SHIFT; 509 /* this should not happen */ 510 if ((offset + size) > rdev->mc.visible_vram_size) 511 return -EINVAL; 512 } 513 } 514 return 0; 515 } 516