1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/radeon_drm.h> 36 #include <drm/drm_cache.h> 37 #include "radeon.h" 38 #include "radeon_trace.h" 39 40 41 int radeon_ttm_init(struct radeon_device *rdev); 42 void radeon_ttm_fini(struct radeon_device *rdev); 43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 44 45 /* 46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 47 * function are calling it. 48 */ 49 50 static void radeon_update_memory_usage(struct radeon_bo *bo, 51 unsigned mem_type, int sign) 52 { 53 struct radeon_device *rdev = bo->rdev; 54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 55 56 switch (mem_type) { 57 case TTM_PL_TT: 58 if (sign > 0) 59 atomic64_add(size, &rdev->gtt_usage); 60 else 61 atomic64_sub(size, &rdev->gtt_usage); 62 break; 63 case TTM_PL_VRAM: 64 if (sign > 0) 65 atomic64_add(size, &rdev->vram_usage); 66 else 67 atomic64_sub(size, &rdev->vram_usage); 68 break; 69 } 70 } 71 72 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 73 { 74 struct radeon_bo *bo; 75 76 bo = container_of(tbo, struct radeon_bo, tbo); 77 78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 79 80 mutex_lock(&bo->rdev->gem.mutex); 81 list_del_init(&bo->list); 82 mutex_unlock(&bo->rdev->gem.mutex); 83 radeon_bo_clear_surface_reg(bo); 84 WARN_ON_ONCE(!list_empty(&bo->va)); 85 if (bo->gem_base.import_attach) 86 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 87 drm_gem_object_release(&bo->gem_base); 88 kfree(bo); 89 } 90 91 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 92 { 93 if (bo->destroy == &radeon_ttm_bo_destroy) 94 return true; 95 return false; 96 } 97 98 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 99 { 100 u32 c = 0, i; 101 102 rbo->placement.placement = rbo->placements; 103 rbo->placement.busy_placement = rbo->placements; 104 if (domain & RADEON_GEM_DOMAIN_VRAM) { 105 /* Try placing BOs which don't need CPU access outside of the 106 * CPU accessible part of VRAM 107 */ 108 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 109 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 110 rbo->placements[c].fpfn = 111 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 112 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 113 TTM_PL_FLAG_UNCACHED | 114 TTM_PL_FLAG_VRAM; 115 } 116 117 rbo->placements[c].fpfn = 0; 118 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 119 TTM_PL_FLAG_UNCACHED | 120 TTM_PL_FLAG_VRAM; 121 } 122 123 if (domain & RADEON_GEM_DOMAIN_GTT) { 124 if (rbo->flags & RADEON_GEM_GTT_UC) { 125 rbo->placements[c].fpfn = 0; 126 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 127 TTM_PL_FLAG_TT; 128 129 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 130 (rbo->rdev->flags & RADEON_IS_AGP)) { 131 rbo->placements[c].fpfn = 0; 132 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 133 TTM_PL_FLAG_UNCACHED | 134 TTM_PL_FLAG_TT; 135 } else { 136 rbo->placements[c].fpfn = 0; 137 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 138 TTM_PL_FLAG_TT; 139 } 140 } 141 142 if (domain & RADEON_GEM_DOMAIN_CPU) { 143 if (rbo->flags & RADEON_GEM_GTT_UC) { 144 rbo->placements[c].fpfn = 0; 145 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 146 TTM_PL_FLAG_SYSTEM; 147 148 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 149 rbo->rdev->flags & RADEON_IS_AGP) { 150 rbo->placements[c].fpfn = 0; 151 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 152 TTM_PL_FLAG_UNCACHED | 153 TTM_PL_FLAG_SYSTEM; 154 } else { 155 rbo->placements[c].fpfn = 0; 156 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 157 TTM_PL_FLAG_SYSTEM; 158 } 159 } 160 if (!c) { 161 rbo->placements[c].fpfn = 0; 162 rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 163 TTM_PL_FLAG_SYSTEM; 164 } 165 166 rbo->placement.num_placement = c; 167 rbo->placement.num_busy_placement = c; 168 169 for (i = 0; i < c; ++i) { 170 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 171 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 172 !rbo->placements[i].fpfn) 173 rbo->placements[i].lpfn = 174 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 175 else 176 rbo->placements[i].lpfn = 0; 177 } 178 } 179 180 int radeon_bo_create(struct radeon_device *rdev, 181 unsigned long size, int byte_align, bool kernel, 182 u32 domain, u32 flags, struct sg_table *sg, 183 struct reservation_object *resv, 184 struct radeon_bo **bo_ptr) 185 { 186 struct radeon_bo *bo; 187 enum ttm_bo_type type; 188 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 189 size_t acc_size; 190 int r; 191 192 size = ALIGN(size, PAGE_SIZE); 193 194 if (kernel) { 195 type = ttm_bo_type_kernel; 196 } else if (sg) { 197 type = ttm_bo_type_sg; 198 } else { 199 type = ttm_bo_type_device; 200 } 201 *bo_ptr = NULL; 202 203 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 204 sizeof(struct radeon_bo)); 205 206 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 207 if (bo == NULL) 208 return -ENOMEM; 209 drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size); 210 bo->rdev = rdev; 211 bo->surface_reg = -1; 212 INIT_LIST_HEAD(&bo->list); 213 INIT_LIST_HEAD(&bo->va); 214 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 215 RADEON_GEM_DOMAIN_GTT | 216 RADEON_GEM_DOMAIN_CPU); 217 218 bo->flags = flags; 219 /* PCI GART is always snooped */ 220 if (!(rdev->flags & RADEON_IS_PCIE)) 221 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 222 223 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 224 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 225 */ 226 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 227 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 228 229 #ifdef CONFIG_X86_32 230 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 231 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 232 */ 233 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 234 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 235 /* Don't try to enable write-combining when it can't work, or things 236 * may be slow 237 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 238 */ 239 #ifndef CONFIG_COMPILE_TEST 240 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 241 thanks to write-combining 242 #endif 243 244 if (bo->flags & RADEON_GEM_GTT_WC) 245 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 246 "better performance thanks to write-combining\n"); 247 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 248 #else 249 /* For architectures that don't support WC memory, 250 * mask out the WC flag from the BO 251 */ 252 if (!drm_arch_can_wc_memory()) 253 bo->flags &= ~RADEON_GEM_GTT_WC; 254 #endif 255 256 radeon_ttm_placement_from_domain(bo, domain); 257 /* Kernel allocation are uninterruptible */ 258 down_read(&rdev->pm.mclk_lock); 259 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 260 &bo->placement, page_align, !kernel, acc_size, 261 sg, resv, &radeon_ttm_bo_destroy); 262 up_read(&rdev->pm.mclk_lock); 263 if (unlikely(r != 0)) { 264 return r; 265 } 266 *bo_ptr = bo; 267 268 trace_radeon_bo_create(bo); 269 270 return 0; 271 } 272 273 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 274 { 275 bool is_iomem; 276 int r; 277 278 if (bo->kptr) { 279 if (ptr) { 280 *ptr = bo->kptr; 281 } 282 return 0; 283 } 284 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 285 if (r) { 286 return r; 287 } 288 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 289 if (ptr) { 290 *ptr = bo->kptr; 291 } 292 radeon_bo_check_tiling(bo, 0, 0); 293 return 0; 294 } 295 296 void radeon_bo_kunmap(struct radeon_bo *bo) 297 { 298 if (bo->kptr == NULL) 299 return; 300 bo->kptr = NULL; 301 radeon_bo_check_tiling(bo, 0, 0); 302 ttm_bo_kunmap(&bo->kmap); 303 } 304 305 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 306 { 307 if (bo == NULL) 308 return NULL; 309 310 ttm_bo_get(&bo->tbo); 311 return bo; 312 } 313 314 void radeon_bo_unref(struct radeon_bo **bo) 315 { 316 struct ttm_buffer_object *tbo; 317 struct radeon_device *rdev; 318 319 if ((*bo) == NULL) 320 return; 321 rdev = (*bo)->rdev; 322 tbo = &((*bo)->tbo); 323 ttm_bo_put(tbo); 324 *bo = NULL; 325 } 326 327 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 328 u64 *gpu_addr) 329 { 330 struct ttm_operation_ctx ctx = { false, false }; 331 int r, i; 332 333 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) 334 return -EPERM; 335 336 if (bo->pin_count) { 337 bo->pin_count++; 338 if (gpu_addr) 339 *gpu_addr = radeon_bo_gpu_offset(bo); 340 341 if (max_offset != 0) { 342 u64 domain_start; 343 344 if (domain == RADEON_GEM_DOMAIN_VRAM) 345 domain_start = bo->rdev->mc.vram_start; 346 else 347 domain_start = bo->rdev->mc.gtt_start; 348 WARN_ON_ONCE(max_offset < 349 (radeon_bo_gpu_offset(bo) - domain_start)); 350 } 351 352 return 0; 353 } 354 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) { 355 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */ 356 return -EINVAL; 357 } 358 359 radeon_ttm_placement_from_domain(bo, domain); 360 for (i = 0; i < bo->placement.num_placement; i++) { 361 /* force to pin into visible video ram */ 362 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 363 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 364 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 365 bo->placements[i].lpfn = 366 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 367 else 368 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 369 370 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 371 } 372 373 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 374 if (likely(r == 0)) { 375 bo->pin_count = 1; 376 if (gpu_addr != NULL) 377 *gpu_addr = radeon_bo_gpu_offset(bo); 378 if (domain == RADEON_GEM_DOMAIN_VRAM) 379 bo->rdev->vram_pin_size += radeon_bo_size(bo); 380 else 381 bo->rdev->gart_pin_size += radeon_bo_size(bo); 382 } else { 383 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 384 } 385 return r; 386 } 387 388 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 389 { 390 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 391 } 392 393 int radeon_bo_unpin(struct radeon_bo *bo) 394 { 395 struct ttm_operation_ctx ctx = { false, false }; 396 int r, i; 397 398 if (!bo->pin_count) { 399 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 400 return 0; 401 } 402 bo->pin_count--; 403 if (bo->pin_count) 404 return 0; 405 for (i = 0; i < bo->placement.num_placement; i++) { 406 bo->placements[i].lpfn = 0; 407 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 408 } 409 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 410 if (likely(r == 0)) { 411 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 412 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 413 else 414 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 415 } else { 416 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 417 } 418 return r; 419 } 420 421 int radeon_bo_evict_vram(struct radeon_device *rdev) 422 { 423 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 424 #ifndef CONFIG_HIBERNATION 425 if (rdev->flags & RADEON_IS_IGP) { 426 if (rdev->mc.igp_sideport_enabled == false) 427 /* Useless to evict on IGP chips */ 428 return 0; 429 } 430 #endif 431 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 432 } 433 434 void radeon_bo_force_delete(struct radeon_device *rdev) 435 { 436 struct radeon_bo *bo, *n; 437 438 if (list_empty(&rdev->gem.objects)) { 439 return; 440 } 441 dev_err(rdev->dev, "Userspace still has active objects !\n"); 442 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 443 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 444 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 445 *((unsigned long *)&bo->gem_base.refcount)); 446 mutex_lock(&bo->rdev->gem.mutex); 447 list_del_init(&bo->list); 448 mutex_unlock(&bo->rdev->gem.mutex); 449 /* this should unref the ttm bo */ 450 drm_gem_object_put_unlocked(&bo->gem_base); 451 } 452 } 453 454 int radeon_bo_init(struct radeon_device *rdev) 455 { 456 /* reserve PAT memory space to WC for VRAM */ 457 arch_io_reserve_memtype_wc(rdev->mc.aper_base, 458 rdev->mc.aper_size); 459 460 /* Add an MTRR for the VRAM */ 461 if (!rdev->fastfb_working) { 462 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 463 rdev->mc.aper_size); 464 } 465 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 466 rdev->mc.mc_vram_size >> 20, 467 (unsigned long long)rdev->mc.aper_size >> 20); 468 DRM_INFO("RAM width %dbits %cDR\n", 469 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 470 return radeon_ttm_init(rdev); 471 } 472 473 void radeon_bo_fini(struct radeon_device *rdev) 474 { 475 radeon_ttm_fini(rdev); 476 arch_phys_wc_del(rdev->mc.vram_mtrr); 477 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size); 478 } 479 480 /* Returns how many bytes TTM can move per IB. 481 */ 482 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 483 { 484 u64 real_vram_size = rdev->mc.real_vram_size; 485 u64 vram_usage = atomic64_read(&rdev->vram_usage); 486 487 /* This function is based on the current VRAM usage. 488 * 489 * - If all of VRAM is free, allow relocating the number of bytes that 490 * is equal to 1/4 of the size of VRAM for this IB. 491 492 * - If more than one half of VRAM is occupied, only allow relocating 493 * 1 MB of data for this IB. 494 * 495 * - From 0 to one half of used VRAM, the threshold decreases 496 * linearly. 497 * __________________ 498 * 1/4 of -|\ | 499 * VRAM | \ | 500 * | \ | 501 * | \ | 502 * | \ | 503 * | \ | 504 * | \ | 505 * | \________|1 MB 506 * |----------------| 507 * VRAM 0 % 100 % 508 * used used 509 * 510 * Note: It's a threshold, not a limit. The threshold must be crossed 511 * for buffer relocations to stop, so any buffer of an arbitrary size 512 * can be moved as long as the threshold isn't crossed before 513 * the relocation takes place. We don't want to disable buffer 514 * relocations completely. 515 * 516 * The idea is that buffers should be placed in VRAM at creation time 517 * and TTM should only do a minimum number of relocations during 518 * command submission. In practice, you need to submit at least 519 * a dozen IBs to move all buffers to VRAM if they are in GTT. 520 * 521 * Also, things can get pretty crazy under memory pressure and actual 522 * VRAM usage can change a lot, so playing safe even at 50% does 523 * consistently increase performance. 524 */ 525 526 u64 half_vram = real_vram_size >> 1; 527 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 528 u64 bytes_moved_threshold = half_free_vram >> 1; 529 return max(bytes_moved_threshold, 1024*1024ull); 530 } 531 532 int radeon_bo_list_validate(struct radeon_device *rdev, 533 struct ww_acquire_ctx *ticket, 534 struct list_head *head, int ring) 535 { 536 struct ttm_operation_ctx ctx = { true, false }; 537 struct radeon_bo_list *lobj; 538 struct list_head duplicates; 539 int r; 540 u64 bytes_moved = 0, initial_bytes_moved; 541 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 542 543 INIT_LIST_HEAD(&duplicates); 544 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 545 if (unlikely(r != 0)) { 546 return r; 547 } 548 549 list_for_each_entry(lobj, head, tv.head) { 550 struct radeon_bo *bo = lobj->robj; 551 if (!bo->pin_count) { 552 u32 domain = lobj->preferred_domains; 553 u32 allowed = lobj->allowed_domains; 554 u32 current_domain = 555 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 556 557 /* Check if this buffer will be moved and don't move it 558 * if we have moved too many buffers for this IB already. 559 * 560 * Note that this allows moving at least one buffer of 561 * any size, because it doesn't take the current "bo" 562 * into account. We don't want to disallow buffer moves 563 * completely. 564 */ 565 if ((allowed & current_domain) != 0 && 566 (domain & current_domain) == 0 && /* will be moved */ 567 bytes_moved > bytes_moved_threshold) { 568 /* don't move it */ 569 domain = current_domain; 570 } 571 572 retry: 573 radeon_ttm_placement_from_domain(bo, domain); 574 if (ring == R600_RING_TYPE_UVD_INDEX) 575 radeon_uvd_force_into_uvd_segment(bo, allowed); 576 577 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 578 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 579 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 580 initial_bytes_moved; 581 582 if (unlikely(r)) { 583 if (r != -ERESTARTSYS && 584 domain != lobj->allowed_domains) { 585 domain = lobj->allowed_domains; 586 goto retry; 587 } 588 ttm_eu_backoff_reservation(ticket, head); 589 return r; 590 } 591 } 592 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 593 lobj->tiling_flags = bo->tiling_flags; 594 } 595 596 list_for_each_entry(lobj, &duplicates, tv.head) { 597 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 598 lobj->tiling_flags = lobj->robj->tiling_flags; 599 } 600 601 return 0; 602 } 603 604 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 605 { 606 struct radeon_device *rdev = bo->rdev; 607 struct radeon_surface_reg *reg; 608 struct radeon_bo *old_object; 609 int steal; 610 int i; 611 612 lockdep_assert_held(&bo->tbo.resv->lock.base); 613 614 if (!bo->tiling_flags) 615 return 0; 616 617 if (bo->surface_reg >= 0) { 618 reg = &rdev->surface_regs[bo->surface_reg]; 619 i = bo->surface_reg; 620 goto out; 621 } 622 623 steal = -1; 624 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 625 626 reg = &rdev->surface_regs[i]; 627 if (!reg->bo) 628 break; 629 630 old_object = reg->bo; 631 if (old_object->pin_count == 0) 632 steal = i; 633 } 634 635 /* if we are all out */ 636 if (i == RADEON_GEM_MAX_SURFACES) { 637 if (steal == -1) 638 return -ENOMEM; 639 /* find someone with a surface reg and nuke their BO */ 640 reg = &rdev->surface_regs[steal]; 641 old_object = reg->bo; 642 /* blow away the mapping */ 643 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 644 ttm_bo_unmap_virtual(&old_object->tbo); 645 old_object->surface_reg = -1; 646 i = steal; 647 } 648 649 bo->surface_reg = i; 650 reg->bo = bo; 651 652 out: 653 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 654 bo->tbo.mem.start << PAGE_SHIFT, 655 bo->tbo.num_pages << PAGE_SHIFT); 656 return 0; 657 } 658 659 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 660 { 661 struct radeon_device *rdev = bo->rdev; 662 struct radeon_surface_reg *reg; 663 664 if (bo->surface_reg == -1) 665 return; 666 667 reg = &rdev->surface_regs[bo->surface_reg]; 668 radeon_clear_surface_reg(rdev, bo->surface_reg); 669 670 reg->bo = NULL; 671 bo->surface_reg = -1; 672 } 673 674 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 675 uint32_t tiling_flags, uint32_t pitch) 676 { 677 struct radeon_device *rdev = bo->rdev; 678 int r; 679 680 if (rdev->family >= CHIP_CEDAR) { 681 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 682 683 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 684 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 685 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 686 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 687 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 688 switch (bankw) { 689 case 0: 690 case 1: 691 case 2: 692 case 4: 693 case 8: 694 break; 695 default: 696 return -EINVAL; 697 } 698 switch (bankh) { 699 case 0: 700 case 1: 701 case 2: 702 case 4: 703 case 8: 704 break; 705 default: 706 return -EINVAL; 707 } 708 switch (mtaspect) { 709 case 0: 710 case 1: 711 case 2: 712 case 4: 713 case 8: 714 break; 715 default: 716 return -EINVAL; 717 } 718 if (tilesplit > 6) { 719 return -EINVAL; 720 } 721 if (stilesplit > 6) { 722 return -EINVAL; 723 } 724 } 725 r = radeon_bo_reserve(bo, false); 726 if (unlikely(r != 0)) 727 return r; 728 bo->tiling_flags = tiling_flags; 729 bo->pitch = pitch; 730 radeon_bo_unreserve(bo); 731 return 0; 732 } 733 734 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 735 uint32_t *tiling_flags, 736 uint32_t *pitch) 737 { 738 lockdep_assert_held(&bo->tbo.resv->lock.base); 739 740 if (tiling_flags) 741 *tiling_flags = bo->tiling_flags; 742 if (pitch) 743 *pitch = bo->pitch; 744 } 745 746 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 747 bool force_drop) 748 { 749 if (!force_drop) 750 lockdep_assert_held(&bo->tbo.resv->lock.base); 751 752 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 753 return 0; 754 755 if (force_drop) { 756 radeon_bo_clear_surface_reg(bo); 757 return 0; 758 } 759 760 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 761 if (!has_moved) 762 return 0; 763 764 if (bo->surface_reg >= 0) 765 radeon_bo_clear_surface_reg(bo); 766 return 0; 767 } 768 769 if ((bo->surface_reg >= 0) && !has_moved) 770 return 0; 771 772 return radeon_bo_get_surface_reg(bo); 773 } 774 775 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 776 bool evict, 777 struct ttm_mem_reg *new_mem) 778 { 779 struct radeon_bo *rbo; 780 781 if (!radeon_ttm_bo_is_radeon_bo(bo)) 782 return; 783 784 rbo = container_of(bo, struct radeon_bo, tbo); 785 radeon_bo_check_tiling(rbo, 0, 1); 786 radeon_vm_bo_invalidate(rbo->rdev, rbo); 787 788 /* update statistics */ 789 if (!new_mem) 790 return; 791 792 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 793 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 794 } 795 796 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 797 { 798 struct ttm_operation_ctx ctx = { false, false }; 799 struct radeon_device *rdev; 800 struct radeon_bo *rbo; 801 unsigned long offset, size, lpfn; 802 int i, r; 803 804 if (!radeon_ttm_bo_is_radeon_bo(bo)) 805 return 0; 806 rbo = container_of(bo, struct radeon_bo, tbo); 807 radeon_bo_check_tiling(rbo, 0, 0); 808 rdev = rbo->rdev; 809 if (bo->mem.mem_type != TTM_PL_VRAM) 810 return 0; 811 812 size = bo->mem.num_pages << PAGE_SHIFT; 813 offset = bo->mem.start << PAGE_SHIFT; 814 if ((offset + size) <= rdev->mc.visible_vram_size) 815 return 0; 816 817 /* Can't move a pinned BO to visible VRAM */ 818 if (rbo->pin_count > 0) 819 return -EINVAL; 820 821 /* hurrah the memory is not visible ! */ 822 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 823 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 824 for (i = 0; i < rbo->placement.num_placement; i++) { 825 /* Force into visible VRAM */ 826 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 827 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 828 rbo->placements[i].lpfn = lpfn; 829 } 830 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 831 if (unlikely(r == -ENOMEM)) { 832 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 833 return ttm_bo_validate(bo, &rbo->placement, &ctx); 834 } else if (unlikely(r != 0)) { 835 return r; 836 } 837 838 offset = bo->mem.start << PAGE_SHIFT; 839 /* this should never happen */ 840 if ((offset + size) > rdev->mc.visible_vram_size) 841 return -EINVAL; 842 843 return 0; 844 } 845 846 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 847 { 848 int r; 849 850 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL); 851 if (unlikely(r != 0)) 852 return r; 853 if (mem_type) 854 *mem_type = bo->tbo.mem.mem_type; 855 856 r = ttm_bo_wait(&bo->tbo, true, no_wait); 857 ttm_bo_unreserve(&bo->tbo); 858 return r; 859 } 860 861 /** 862 * radeon_bo_fence - add fence to buffer object 863 * 864 * @bo: buffer object in question 865 * @fence: fence to add 866 * @shared: true if fence should be added shared 867 * 868 */ 869 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 870 bool shared) 871 { 872 struct reservation_object *resv = bo->tbo.resv; 873 874 if (shared) 875 reservation_object_add_shared_fence(resv, &fence->base); 876 else 877 reservation_object_add_excl_fence(resv, &fence->base); 878 } 879