1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/io.h> 34 #include <linux/list.h> 35 #include <linux/slab.h> 36 37 #include <drm/drm_cache.h> 38 #include <drm/drm_prime.h> 39 #include <drm/radeon_drm.h> 40 41 #include "radeon.h" 42 #include "radeon_trace.h" 43 #include "radeon_ttm.h" 44 45 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 46 47 /* 48 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 49 * function are calling it. 50 */ 51 52 static void radeon_update_memory_usage(struct radeon_bo *bo, 53 unsigned mem_type, int sign) 54 { 55 struct radeon_device *rdev = bo->rdev; 56 57 switch (mem_type) { 58 case TTM_PL_TT: 59 if (sign > 0) 60 atomic64_add(bo->tbo.base.size, &rdev->gtt_usage); 61 else 62 atomic64_sub(bo->tbo.base.size, &rdev->gtt_usage); 63 break; 64 case TTM_PL_VRAM: 65 if (sign > 0) 66 atomic64_add(bo->tbo.base.size, &rdev->vram_usage); 67 else 68 atomic64_sub(bo->tbo.base.size, &rdev->vram_usage); 69 break; 70 } 71 } 72 73 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 74 { 75 struct radeon_bo *bo; 76 77 bo = container_of(tbo, struct radeon_bo, tbo); 78 79 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 80 81 mutex_lock(&bo->rdev->gem.mutex); 82 list_del_init(&bo->list); 83 mutex_unlock(&bo->rdev->gem.mutex); 84 radeon_bo_clear_surface_reg(bo); 85 WARN_ON_ONCE(!list_empty(&bo->va)); 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 kfree(bo); 90 } 91 92 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 93 { 94 if (bo->destroy == &radeon_ttm_bo_destroy) 95 return true; 96 return false; 97 } 98 99 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 100 { 101 u32 c = 0, i; 102 103 rbo->placement.placement = rbo->placements; 104 rbo->placement.busy_placement = rbo->placements; 105 if (domain & RADEON_GEM_DOMAIN_VRAM) { 106 /* Try placing BOs which don't need CPU access outside of the 107 * CPU accessible part of VRAM 108 */ 109 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 110 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 111 rbo->placements[c].fpfn = 112 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 113 rbo->placements[c].mem_type = TTM_PL_VRAM; 114 rbo->placements[c++].flags = 0; 115 } 116 117 rbo->placements[c].fpfn = 0; 118 rbo->placements[c].mem_type = TTM_PL_VRAM; 119 rbo->placements[c++].flags = 0; 120 } 121 122 if (domain & RADEON_GEM_DOMAIN_GTT) { 123 rbo->placements[c].fpfn = 0; 124 rbo->placements[c].mem_type = TTM_PL_TT; 125 rbo->placements[c++].flags = 0; 126 } 127 128 if (domain & RADEON_GEM_DOMAIN_CPU) { 129 rbo->placements[c].fpfn = 0; 130 rbo->placements[c].mem_type = TTM_PL_SYSTEM; 131 rbo->placements[c++].flags = 0; 132 } 133 if (!c) { 134 rbo->placements[c].fpfn = 0; 135 rbo->placements[c].mem_type = TTM_PL_SYSTEM; 136 rbo->placements[c++].flags = 0; 137 } 138 139 rbo->placement.num_placement = c; 140 rbo->placement.num_busy_placement = c; 141 142 for (i = 0; i < c; ++i) { 143 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 144 (rbo->placements[i].mem_type == TTM_PL_VRAM) && 145 !rbo->placements[i].fpfn) 146 rbo->placements[i].lpfn = 147 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 148 else 149 rbo->placements[i].lpfn = 0; 150 } 151 } 152 153 int radeon_bo_create(struct radeon_device *rdev, 154 unsigned long size, int byte_align, bool kernel, 155 u32 domain, u32 flags, struct sg_table *sg, 156 struct dma_resv *resv, 157 struct radeon_bo **bo_ptr) 158 { 159 struct radeon_bo *bo; 160 enum ttm_bo_type type; 161 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 162 size_t acc_size; 163 int r; 164 165 size = ALIGN(size, PAGE_SIZE); 166 167 if (kernel) { 168 type = ttm_bo_type_kernel; 169 } else if (sg) { 170 type = ttm_bo_type_sg; 171 } else { 172 type = ttm_bo_type_device; 173 } 174 *bo_ptr = NULL; 175 176 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 177 sizeof(struct radeon_bo)); 178 179 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 180 if (bo == NULL) 181 return -ENOMEM; 182 drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size); 183 bo->rdev = rdev; 184 bo->surface_reg = -1; 185 INIT_LIST_HEAD(&bo->list); 186 INIT_LIST_HEAD(&bo->va); 187 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 188 RADEON_GEM_DOMAIN_GTT | 189 RADEON_GEM_DOMAIN_CPU); 190 191 bo->flags = flags; 192 /* PCI GART is always snooped */ 193 if (!(rdev->flags & RADEON_IS_PCIE)) 194 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 195 196 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 197 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 198 */ 199 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 200 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 201 202 #ifdef CONFIG_X86_32 203 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 204 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 205 */ 206 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 207 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 208 /* Don't try to enable write-combining when it can't work, or things 209 * may be slow 210 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 211 */ 212 #ifndef CONFIG_COMPILE_TEST 213 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 214 thanks to write-combining 215 #endif 216 217 if (bo->flags & RADEON_GEM_GTT_WC) 218 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 219 "better performance thanks to write-combining\n"); 220 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 221 #else 222 /* For architectures that don't support WC memory, 223 * mask out the WC flag from the BO 224 */ 225 if (!drm_arch_can_wc_memory()) 226 bo->flags &= ~RADEON_GEM_GTT_WC; 227 #endif 228 229 radeon_ttm_placement_from_domain(bo, domain); 230 /* Kernel allocation are uninterruptible */ 231 down_read(&rdev->pm.mclk_lock); 232 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 233 &bo->placement, page_align, !kernel, acc_size, 234 sg, resv, &radeon_ttm_bo_destroy); 235 up_read(&rdev->pm.mclk_lock); 236 if (unlikely(r != 0)) { 237 return r; 238 } 239 *bo_ptr = bo; 240 241 trace_radeon_bo_create(bo); 242 243 return 0; 244 } 245 246 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 247 { 248 bool is_iomem; 249 int r; 250 251 if (bo->kptr) { 252 if (ptr) { 253 *ptr = bo->kptr; 254 } 255 return 0; 256 } 257 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap); 258 if (r) { 259 return r; 260 } 261 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 262 if (ptr) { 263 *ptr = bo->kptr; 264 } 265 radeon_bo_check_tiling(bo, 0, 0); 266 return 0; 267 } 268 269 void radeon_bo_kunmap(struct radeon_bo *bo) 270 { 271 if (bo->kptr == NULL) 272 return; 273 bo->kptr = NULL; 274 radeon_bo_check_tiling(bo, 0, 0); 275 ttm_bo_kunmap(&bo->kmap); 276 } 277 278 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 279 { 280 if (bo == NULL) 281 return NULL; 282 283 ttm_bo_get(&bo->tbo); 284 return bo; 285 } 286 287 void radeon_bo_unref(struct radeon_bo **bo) 288 { 289 struct ttm_buffer_object *tbo; 290 291 if ((*bo) == NULL) 292 return; 293 tbo = &((*bo)->tbo); 294 ttm_bo_put(tbo); 295 *bo = NULL; 296 } 297 298 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 299 u64 *gpu_addr) 300 { 301 struct ttm_operation_ctx ctx = { false, false }; 302 int r, i; 303 304 if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm)) 305 return -EPERM; 306 307 if (bo->tbo.pin_count) { 308 ttm_bo_pin(&bo->tbo); 309 if (gpu_addr) 310 *gpu_addr = radeon_bo_gpu_offset(bo); 311 312 if (max_offset != 0) { 313 u64 domain_start; 314 315 if (domain == RADEON_GEM_DOMAIN_VRAM) 316 domain_start = bo->rdev->mc.vram_start; 317 else 318 domain_start = bo->rdev->mc.gtt_start; 319 WARN_ON_ONCE(max_offset < 320 (radeon_bo_gpu_offset(bo) - domain_start)); 321 } 322 323 return 0; 324 } 325 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) { 326 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */ 327 return -EINVAL; 328 } 329 330 radeon_ttm_placement_from_domain(bo, domain); 331 for (i = 0; i < bo->placement.num_placement; i++) { 332 /* force to pin into visible video ram */ 333 if ((bo->placements[i].mem_type == TTM_PL_VRAM) && 334 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 335 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 336 bo->placements[i].lpfn = 337 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 338 else 339 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 340 } 341 342 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 343 if (likely(r == 0)) { 344 ttm_bo_pin(&bo->tbo); 345 if (gpu_addr != NULL) 346 *gpu_addr = radeon_bo_gpu_offset(bo); 347 if (domain == RADEON_GEM_DOMAIN_VRAM) 348 bo->rdev->vram_pin_size += radeon_bo_size(bo); 349 else 350 bo->rdev->gart_pin_size += radeon_bo_size(bo); 351 } else { 352 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 353 } 354 return r; 355 } 356 357 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 358 { 359 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 360 } 361 362 void radeon_bo_unpin(struct radeon_bo *bo) 363 { 364 ttm_bo_unpin(&bo->tbo); 365 if (!bo->tbo.pin_count) { 366 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 367 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 368 else 369 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 370 } 371 } 372 373 int radeon_bo_evict_vram(struct radeon_device *rdev) 374 { 375 struct ttm_bo_device *bdev = &rdev->mman.bdev; 376 struct ttm_resource_manager *man; 377 378 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 379 #ifndef CONFIG_HIBERNATION 380 if (rdev->flags & RADEON_IS_IGP) { 381 if (rdev->mc.igp_sideport_enabled == false) 382 /* Useless to evict on IGP chips */ 383 return 0; 384 } 385 #endif 386 man = ttm_manager_type(bdev, TTM_PL_VRAM); 387 return ttm_resource_manager_evict_all(bdev, man); 388 } 389 390 void radeon_bo_force_delete(struct radeon_device *rdev) 391 { 392 struct radeon_bo *bo, *n; 393 394 if (list_empty(&rdev->gem.objects)) { 395 return; 396 } 397 dev_err(rdev->dev, "Userspace still has active objects !\n"); 398 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 399 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 400 &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size, 401 *((unsigned long *)&bo->tbo.base.refcount)); 402 mutex_lock(&bo->rdev->gem.mutex); 403 list_del_init(&bo->list); 404 mutex_unlock(&bo->rdev->gem.mutex); 405 /* this should unref the ttm bo */ 406 drm_gem_object_put(&bo->tbo.base); 407 } 408 } 409 410 int radeon_bo_init(struct radeon_device *rdev) 411 { 412 /* reserve PAT memory space to WC for VRAM */ 413 arch_io_reserve_memtype_wc(rdev->mc.aper_base, 414 rdev->mc.aper_size); 415 416 /* Add an MTRR for the VRAM */ 417 if (!rdev->fastfb_working) { 418 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 419 rdev->mc.aper_size); 420 } 421 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 422 rdev->mc.mc_vram_size >> 20, 423 (unsigned long long)rdev->mc.aper_size >> 20); 424 DRM_INFO("RAM width %dbits %cDR\n", 425 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 426 return radeon_ttm_init(rdev); 427 } 428 429 void radeon_bo_fini(struct radeon_device *rdev) 430 { 431 radeon_ttm_fini(rdev); 432 arch_phys_wc_del(rdev->mc.vram_mtrr); 433 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size); 434 } 435 436 /* Returns how many bytes TTM can move per IB. 437 */ 438 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 439 { 440 u64 real_vram_size = rdev->mc.real_vram_size; 441 u64 vram_usage = atomic64_read(&rdev->vram_usage); 442 443 /* This function is based on the current VRAM usage. 444 * 445 * - If all of VRAM is free, allow relocating the number of bytes that 446 * is equal to 1/4 of the size of VRAM for this IB. 447 448 * - If more than one half of VRAM is occupied, only allow relocating 449 * 1 MB of data for this IB. 450 * 451 * - From 0 to one half of used VRAM, the threshold decreases 452 * linearly. 453 * __________________ 454 * 1/4 of -|\ | 455 * VRAM | \ | 456 * | \ | 457 * | \ | 458 * | \ | 459 * | \ | 460 * | \ | 461 * | \________|1 MB 462 * |----------------| 463 * VRAM 0 % 100 % 464 * used used 465 * 466 * Note: It's a threshold, not a limit. The threshold must be crossed 467 * for buffer relocations to stop, so any buffer of an arbitrary size 468 * can be moved as long as the threshold isn't crossed before 469 * the relocation takes place. We don't want to disable buffer 470 * relocations completely. 471 * 472 * The idea is that buffers should be placed in VRAM at creation time 473 * and TTM should only do a minimum number of relocations during 474 * command submission. In practice, you need to submit at least 475 * a dozen IBs to move all buffers to VRAM if they are in GTT. 476 * 477 * Also, things can get pretty crazy under memory pressure and actual 478 * VRAM usage can change a lot, so playing safe even at 50% does 479 * consistently increase performance. 480 */ 481 482 u64 half_vram = real_vram_size >> 1; 483 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 484 u64 bytes_moved_threshold = half_free_vram >> 1; 485 return max(bytes_moved_threshold, 1024*1024ull); 486 } 487 488 int radeon_bo_list_validate(struct radeon_device *rdev, 489 struct ww_acquire_ctx *ticket, 490 struct list_head *head, int ring) 491 { 492 struct ttm_operation_ctx ctx = { true, false }; 493 struct radeon_bo_list *lobj; 494 struct list_head duplicates; 495 int r; 496 u64 bytes_moved = 0, initial_bytes_moved; 497 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 498 499 INIT_LIST_HEAD(&duplicates); 500 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 501 if (unlikely(r != 0)) { 502 return r; 503 } 504 505 list_for_each_entry(lobj, head, tv.head) { 506 struct radeon_bo *bo = lobj->robj; 507 if (!bo->tbo.pin_count) { 508 u32 domain = lobj->preferred_domains; 509 u32 allowed = lobj->allowed_domains; 510 u32 current_domain = 511 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 512 513 /* Check if this buffer will be moved and don't move it 514 * if we have moved too many buffers for this IB already. 515 * 516 * Note that this allows moving at least one buffer of 517 * any size, because it doesn't take the current "bo" 518 * into account. We don't want to disallow buffer moves 519 * completely. 520 */ 521 if ((allowed & current_domain) != 0 && 522 (domain & current_domain) == 0 && /* will be moved */ 523 bytes_moved > bytes_moved_threshold) { 524 /* don't move it */ 525 domain = current_domain; 526 } 527 528 retry: 529 radeon_ttm_placement_from_domain(bo, domain); 530 if (ring == R600_RING_TYPE_UVD_INDEX) 531 radeon_uvd_force_into_uvd_segment(bo, allowed); 532 533 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 534 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 535 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 536 initial_bytes_moved; 537 538 if (unlikely(r)) { 539 if (r != -ERESTARTSYS && 540 domain != lobj->allowed_domains) { 541 domain = lobj->allowed_domains; 542 goto retry; 543 } 544 ttm_eu_backoff_reservation(ticket, head); 545 return r; 546 } 547 } 548 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 549 lobj->tiling_flags = bo->tiling_flags; 550 } 551 552 list_for_each_entry(lobj, &duplicates, tv.head) { 553 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 554 lobj->tiling_flags = lobj->robj->tiling_flags; 555 } 556 557 return 0; 558 } 559 560 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 561 { 562 struct radeon_device *rdev = bo->rdev; 563 struct radeon_surface_reg *reg; 564 struct radeon_bo *old_object; 565 int steal; 566 int i; 567 568 dma_resv_assert_held(bo->tbo.base.resv); 569 570 if (!bo->tiling_flags) 571 return 0; 572 573 if (bo->surface_reg >= 0) { 574 reg = &rdev->surface_regs[bo->surface_reg]; 575 i = bo->surface_reg; 576 goto out; 577 } 578 579 steal = -1; 580 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 581 582 reg = &rdev->surface_regs[i]; 583 if (!reg->bo) 584 break; 585 586 old_object = reg->bo; 587 if (old_object->tbo.pin_count == 0) 588 steal = i; 589 } 590 591 /* if we are all out */ 592 if (i == RADEON_GEM_MAX_SURFACES) { 593 if (steal == -1) 594 return -ENOMEM; 595 /* find someone with a surface reg and nuke their BO */ 596 reg = &rdev->surface_regs[steal]; 597 old_object = reg->bo; 598 /* blow away the mapping */ 599 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 600 ttm_bo_unmap_virtual(&old_object->tbo); 601 old_object->surface_reg = -1; 602 i = steal; 603 } 604 605 bo->surface_reg = i; 606 reg->bo = bo; 607 608 out: 609 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 610 bo->tbo.mem.start << PAGE_SHIFT, 611 bo->tbo.base.size); 612 return 0; 613 } 614 615 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 616 { 617 struct radeon_device *rdev = bo->rdev; 618 struct radeon_surface_reg *reg; 619 620 if (bo->surface_reg == -1) 621 return; 622 623 reg = &rdev->surface_regs[bo->surface_reg]; 624 radeon_clear_surface_reg(rdev, bo->surface_reg); 625 626 reg->bo = NULL; 627 bo->surface_reg = -1; 628 } 629 630 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 631 uint32_t tiling_flags, uint32_t pitch) 632 { 633 struct radeon_device *rdev = bo->rdev; 634 int r; 635 636 if (rdev->family >= CHIP_CEDAR) { 637 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 638 639 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 640 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 641 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 642 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 643 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 644 switch (bankw) { 645 case 0: 646 case 1: 647 case 2: 648 case 4: 649 case 8: 650 break; 651 default: 652 return -EINVAL; 653 } 654 switch (bankh) { 655 case 0: 656 case 1: 657 case 2: 658 case 4: 659 case 8: 660 break; 661 default: 662 return -EINVAL; 663 } 664 switch (mtaspect) { 665 case 0: 666 case 1: 667 case 2: 668 case 4: 669 case 8: 670 break; 671 default: 672 return -EINVAL; 673 } 674 if (tilesplit > 6) { 675 return -EINVAL; 676 } 677 if (stilesplit > 6) { 678 return -EINVAL; 679 } 680 } 681 r = radeon_bo_reserve(bo, false); 682 if (unlikely(r != 0)) 683 return r; 684 bo->tiling_flags = tiling_flags; 685 bo->pitch = pitch; 686 radeon_bo_unreserve(bo); 687 return 0; 688 } 689 690 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 691 uint32_t *tiling_flags, 692 uint32_t *pitch) 693 { 694 dma_resv_assert_held(bo->tbo.base.resv); 695 696 if (tiling_flags) 697 *tiling_flags = bo->tiling_flags; 698 if (pitch) 699 *pitch = bo->pitch; 700 } 701 702 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 703 bool force_drop) 704 { 705 if (!force_drop) 706 dma_resv_assert_held(bo->tbo.base.resv); 707 708 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 709 return 0; 710 711 if (force_drop) { 712 radeon_bo_clear_surface_reg(bo); 713 return 0; 714 } 715 716 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 717 if (!has_moved) 718 return 0; 719 720 if (bo->surface_reg >= 0) 721 radeon_bo_clear_surface_reg(bo); 722 return 0; 723 } 724 725 if ((bo->surface_reg >= 0) && !has_moved) 726 return 0; 727 728 return radeon_bo_get_surface_reg(bo); 729 } 730 731 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 732 bool evict, 733 struct ttm_resource *new_mem) 734 { 735 struct radeon_bo *rbo; 736 737 if (!radeon_ttm_bo_is_radeon_bo(bo)) 738 return; 739 740 rbo = container_of(bo, struct radeon_bo, tbo); 741 radeon_bo_check_tiling(rbo, 0, 1); 742 radeon_vm_bo_invalidate(rbo->rdev, rbo); 743 744 /* update statistics */ 745 if (!new_mem) 746 return; 747 748 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 749 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 750 } 751 752 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 753 { 754 struct ttm_operation_ctx ctx = { false, false }; 755 struct radeon_device *rdev; 756 struct radeon_bo *rbo; 757 unsigned long offset, size, lpfn; 758 int i, r; 759 760 if (!radeon_ttm_bo_is_radeon_bo(bo)) 761 return 0; 762 rbo = container_of(bo, struct radeon_bo, tbo); 763 radeon_bo_check_tiling(rbo, 0, 0); 764 rdev = rbo->rdev; 765 if (bo->mem.mem_type != TTM_PL_VRAM) 766 return 0; 767 768 size = bo->mem.num_pages << PAGE_SHIFT; 769 offset = bo->mem.start << PAGE_SHIFT; 770 if ((offset + size) <= rdev->mc.visible_vram_size) 771 return 0; 772 773 /* Can't move a pinned BO to visible VRAM */ 774 if (rbo->tbo.pin_count > 0) 775 return VM_FAULT_SIGBUS; 776 777 /* hurrah the memory is not visible ! */ 778 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 779 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 780 for (i = 0; i < rbo->placement.num_placement; i++) { 781 /* Force into visible VRAM */ 782 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) && 783 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 784 rbo->placements[i].lpfn = lpfn; 785 } 786 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 787 if (unlikely(r == -ENOMEM)) { 788 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 789 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 790 } else if (likely(!r)) { 791 offset = bo->mem.start << PAGE_SHIFT; 792 /* this should never happen */ 793 if ((offset + size) > rdev->mc.visible_vram_size) 794 return VM_FAULT_SIGBUS; 795 } 796 797 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 798 return VM_FAULT_NOPAGE; 799 else if (unlikely(r)) 800 return VM_FAULT_SIGBUS; 801 802 ttm_bo_move_to_lru_tail_unlocked(bo); 803 return 0; 804 } 805 806 /** 807 * radeon_bo_fence - add fence to buffer object 808 * 809 * @bo: buffer object in question 810 * @fence: fence to add 811 * @shared: true if fence should be added shared 812 * 813 */ 814 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 815 bool shared) 816 { 817 struct dma_resv *resv = bo->tbo.base.resv; 818 819 if (shared) 820 dma_resv_add_shared_fence(resv, &fence->base); 821 else 822 dma_resv_add_excl_fence(resv, &fence->base); 823 } 824