1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/radeon_drm.h> 36 #include "radeon.h" 37 #include "radeon_trace.h" 38 39 40 int radeon_ttm_init(struct radeon_device *rdev); 41 void radeon_ttm_fini(struct radeon_device *rdev); 42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 43 44 /* 45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 46 * function are calling it. 47 */ 48 49 static void radeon_update_memory_usage(struct radeon_bo *bo, 50 unsigned mem_type, int sign) 51 { 52 struct radeon_device *rdev = bo->rdev; 53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 54 55 switch (mem_type) { 56 case TTM_PL_TT: 57 if (sign > 0) 58 atomic64_add(size, &rdev->gtt_usage); 59 else 60 atomic64_sub(size, &rdev->gtt_usage); 61 break; 62 case TTM_PL_VRAM: 63 if (sign > 0) 64 atomic64_add(size, &rdev->vram_usage); 65 else 66 atomic64_sub(size, &rdev->vram_usage); 67 break; 68 } 69 } 70 71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 72 { 73 struct radeon_bo *bo; 74 75 bo = container_of(tbo, struct radeon_bo, tbo); 76 77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 78 79 mutex_lock(&bo->rdev->gem.mutex); 80 list_del_init(&bo->list); 81 mutex_unlock(&bo->rdev->gem.mutex); 82 radeon_bo_clear_surface_reg(bo); 83 WARN_ON(!list_empty(&bo->va)); 84 drm_gem_object_release(&bo->gem_base); 85 kfree(bo); 86 } 87 88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 89 { 90 if (bo->destroy == &radeon_ttm_bo_destroy) 91 return true; 92 return false; 93 } 94 95 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 96 { 97 u32 c = 0, i; 98 99 rbo->placement.fpfn = 0; 100 rbo->placement.lpfn = 0; 101 rbo->placement.placement = rbo->placements; 102 rbo->placement.busy_placement = rbo->placements; 103 if (domain & RADEON_GEM_DOMAIN_VRAM) 104 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 105 TTM_PL_FLAG_VRAM; 106 if (domain & RADEON_GEM_DOMAIN_GTT) { 107 if (rbo->flags & RADEON_GEM_GTT_UC) { 108 rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT; 109 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 110 (rbo->rdev->flags & RADEON_IS_AGP)) { 111 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 112 TTM_PL_FLAG_TT; 113 } else { 114 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 115 } 116 } 117 if (domain & RADEON_GEM_DOMAIN_CPU) { 118 if (rbo->flags & RADEON_GEM_GTT_UC) { 119 rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM; 120 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 121 rbo->rdev->flags & RADEON_IS_AGP) { 122 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 123 TTM_PL_FLAG_SYSTEM; 124 } else { 125 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 126 } 127 } 128 if (!c) 129 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 130 rbo->placement.num_placement = c; 131 rbo->placement.num_busy_placement = c; 132 133 /* 134 * Use two-ended allocation depending on the buffer size to 135 * improve fragmentation quality. 136 * 512kb was measured as the most optimal number. 137 */ 138 if (rbo->tbo.mem.size > 512 * 1024) { 139 for (i = 0; i < c; i++) { 140 rbo->placements[i] |= TTM_PL_FLAG_TOPDOWN; 141 } 142 } 143 } 144 145 int radeon_bo_create(struct radeon_device *rdev, 146 unsigned long size, int byte_align, bool kernel, u32 domain, 147 u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr) 148 { 149 struct radeon_bo *bo; 150 enum ttm_bo_type type; 151 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 152 size_t acc_size; 153 int r; 154 155 size = ALIGN(size, PAGE_SIZE); 156 157 if (kernel) { 158 type = ttm_bo_type_kernel; 159 } else if (sg) { 160 type = ttm_bo_type_sg; 161 } else { 162 type = ttm_bo_type_device; 163 } 164 *bo_ptr = NULL; 165 166 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 167 sizeof(struct radeon_bo)); 168 169 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 170 if (bo == NULL) 171 return -ENOMEM; 172 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 173 if (unlikely(r)) { 174 kfree(bo); 175 return r; 176 } 177 bo->rdev = rdev; 178 bo->surface_reg = -1; 179 INIT_LIST_HEAD(&bo->list); 180 INIT_LIST_HEAD(&bo->va); 181 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 182 RADEON_GEM_DOMAIN_GTT | 183 RADEON_GEM_DOMAIN_CPU); 184 185 bo->flags = flags; 186 /* PCI GART is always snooped */ 187 if (!(rdev->flags & RADEON_IS_PCIE)) 188 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 189 190 radeon_ttm_placement_from_domain(bo, domain); 191 /* Kernel allocation are uninterruptible */ 192 down_read(&rdev->pm.mclk_lock); 193 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 194 &bo->placement, page_align, !kernel, NULL, 195 acc_size, sg, &radeon_ttm_bo_destroy); 196 up_read(&rdev->pm.mclk_lock); 197 if (unlikely(r != 0)) { 198 return r; 199 } 200 *bo_ptr = bo; 201 202 trace_radeon_bo_create(bo); 203 204 return 0; 205 } 206 207 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 208 { 209 bool is_iomem; 210 int r; 211 212 if (bo->kptr) { 213 if (ptr) { 214 *ptr = bo->kptr; 215 } 216 return 0; 217 } 218 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 219 if (r) { 220 return r; 221 } 222 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 223 if (ptr) { 224 *ptr = bo->kptr; 225 } 226 radeon_bo_check_tiling(bo, 0, 0); 227 return 0; 228 } 229 230 void radeon_bo_kunmap(struct radeon_bo *bo) 231 { 232 if (bo->kptr == NULL) 233 return; 234 bo->kptr = NULL; 235 radeon_bo_check_tiling(bo, 0, 0); 236 ttm_bo_kunmap(&bo->kmap); 237 } 238 239 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 240 { 241 if (bo == NULL) 242 return NULL; 243 244 ttm_bo_reference(&bo->tbo); 245 return bo; 246 } 247 248 void radeon_bo_unref(struct radeon_bo **bo) 249 { 250 struct ttm_buffer_object *tbo; 251 struct radeon_device *rdev; 252 253 if ((*bo) == NULL) 254 return; 255 rdev = (*bo)->rdev; 256 tbo = &((*bo)->tbo); 257 ttm_bo_unref(&tbo); 258 if (tbo == NULL) 259 *bo = NULL; 260 } 261 262 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 263 u64 *gpu_addr) 264 { 265 int r, i; 266 267 if (bo->pin_count) { 268 bo->pin_count++; 269 if (gpu_addr) 270 *gpu_addr = radeon_bo_gpu_offset(bo); 271 272 if (max_offset != 0) { 273 u64 domain_start; 274 275 if (domain == RADEON_GEM_DOMAIN_VRAM) 276 domain_start = bo->rdev->mc.vram_start; 277 else 278 domain_start = bo->rdev->mc.gtt_start; 279 WARN_ON_ONCE(max_offset < 280 (radeon_bo_gpu_offset(bo) - domain_start)); 281 } 282 283 return 0; 284 } 285 radeon_ttm_placement_from_domain(bo, domain); 286 if (domain == RADEON_GEM_DOMAIN_VRAM) { 287 /* force to pin into visible video ram */ 288 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 289 } 290 if (max_offset) { 291 u64 lpfn = max_offset >> PAGE_SHIFT; 292 293 if (!bo->placement.lpfn) 294 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 295 296 if (lpfn < bo->placement.lpfn) 297 bo->placement.lpfn = lpfn; 298 } 299 for (i = 0; i < bo->placement.num_placement; i++) 300 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 301 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 302 if (likely(r == 0)) { 303 bo->pin_count = 1; 304 if (gpu_addr != NULL) 305 *gpu_addr = radeon_bo_gpu_offset(bo); 306 if (domain == RADEON_GEM_DOMAIN_VRAM) 307 bo->rdev->vram_pin_size += radeon_bo_size(bo); 308 else 309 bo->rdev->gart_pin_size += radeon_bo_size(bo); 310 } else { 311 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 312 } 313 return r; 314 } 315 316 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 317 { 318 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 319 } 320 321 int radeon_bo_unpin(struct radeon_bo *bo) 322 { 323 int r, i; 324 325 if (!bo->pin_count) { 326 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 327 return 0; 328 } 329 bo->pin_count--; 330 if (bo->pin_count) 331 return 0; 332 for (i = 0; i < bo->placement.num_placement; i++) 333 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 334 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 335 if (likely(r == 0)) { 336 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 337 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 338 else 339 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 340 } else { 341 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 342 } 343 return r; 344 } 345 346 int radeon_bo_evict_vram(struct radeon_device *rdev) 347 { 348 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 349 if (0 && (rdev->flags & RADEON_IS_IGP)) { 350 if (rdev->mc.igp_sideport_enabled == false) 351 /* Useless to evict on IGP chips */ 352 return 0; 353 } 354 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 355 } 356 357 void radeon_bo_force_delete(struct radeon_device *rdev) 358 { 359 struct radeon_bo *bo, *n; 360 361 if (list_empty(&rdev->gem.objects)) { 362 return; 363 } 364 dev_err(rdev->dev, "Userspace still has active objects !\n"); 365 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 366 mutex_lock(&rdev->ddev->struct_mutex); 367 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 368 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 369 *((unsigned long *)&bo->gem_base.refcount)); 370 mutex_lock(&bo->rdev->gem.mutex); 371 list_del_init(&bo->list); 372 mutex_unlock(&bo->rdev->gem.mutex); 373 /* this should unref the ttm bo */ 374 drm_gem_object_unreference(&bo->gem_base); 375 mutex_unlock(&rdev->ddev->struct_mutex); 376 } 377 } 378 379 int radeon_bo_init(struct radeon_device *rdev) 380 { 381 /* Add an MTRR for the VRAM */ 382 if (!rdev->fastfb_working) { 383 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 384 rdev->mc.aper_size); 385 } 386 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 387 rdev->mc.mc_vram_size >> 20, 388 (unsigned long long)rdev->mc.aper_size >> 20); 389 DRM_INFO("RAM width %dbits %cDR\n", 390 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 391 return radeon_ttm_init(rdev); 392 } 393 394 void radeon_bo_fini(struct radeon_device *rdev) 395 { 396 radeon_ttm_fini(rdev); 397 arch_phys_wc_del(rdev->mc.vram_mtrr); 398 } 399 400 /* Returns how many bytes TTM can move per IB. 401 */ 402 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 403 { 404 u64 real_vram_size = rdev->mc.real_vram_size; 405 u64 vram_usage = atomic64_read(&rdev->vram_usage); 406 407 /* This function is based on the current VRAM usage. 408 * 409 * - If all of VRAM is free, allow relocating the number of bytes that 410 * is equal to 1/4 of the size of VRAM for this IB. 411 412 * - If more than one half of VRAM is occupied, only allow relocating 413 * 1 MB of data for this IB. 414 * 415 * - From 0 to one half of used VRAM, the threshold decreases 416 * linearly. 417 * __________________ 418 * 1/4 of -|\ | 419 * VRAM | \ | 420 * | \ | 421 * | \ | 422 * | \ | 423 * | \ | 424 * | \ | 425 * | \________|1 MB 426 * |----------------| 427 * VRAM 0 % 100 % 428 * used used 429 * 430 * Note: It's a threshold, not a limit. The threshold must be crossed 431 * for buffer relocations to stop, so any buffer of an arbitrary size 432 * can be moved as long as the threshold isn't crossed before 433 * the relocation takes place. We don't want to disable buffer 434 * relocations completely. 435 * 436 * The idea is that buffers should be placed in VRAM at creation time 437 * and TTM should only do a minimum number of relocations during 438 * command submission. In practice, you need to submit at least 439 * a dozen IBs to move all buffers to VRAM if they are in GTT. 440 * 441 * Also, things can get pretty crazy under memory pressure and actual 442 * VRAM usage can change a lot, so playing safe even at 50% does 443 * consistently increase performance. 444 */ 445 446 u64 half_vram = real_vram_size >> 1; 447 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 448 u64 bytes_moved_threshold = half_free_vram >> 1; 449 return max(bytes_moved_threshold, 1024*1024ull); 450 } 451 452 int radeon_bo_list_validate(struct radeon_device *rdev, 453 struct ww_acquire_ctx *ticket, 454 struct list_head *head, int ring) 455 { 456 struct radeon_cs_reloc *lobj; 457 struct radeon_bo *bo; 458 int r; 459 u64 bytes_moved = 0, initial_bytes_moved; 460 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 461 462 r = ttm_eu_reserve_buffers(ticket, head); 463 if (unlikely(r != 0)) { 464 return r; 465 } 466 467 list_for_each_entry(lobj, head, tv.head) { 468 bo = lobj->robj; 469 if (!bo->pin_count) { 470 u32 domain = lobj->prefered_domains; 471 u32 current_domain = 472 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 473 474 /* Check if this buffer will be moved and don't move it 475 * if we have moved too many buffers for this IB already. 476 * 477 * Note that this allows moving at least one buffer of 478 * any size, because it doesn't take the current "bo" 479 * into account. We don't want to disallow buffer moves 480 * completely. 481 */ 482 if ((lobj->allowed_domains & current_domain) != 0 && 483 (domain & current_domain) == 0 && /* will be moved */ 484 bytes_moved > bytes_moved_threshold) { 485 /* don't move it */ 486 domain = current_domain; 487 } 488 489 retry: 490 radeon_ttm_placement_from_domain(bo, domain); 491 if (ring == R600_RING_TYPE_UVD_INDEX) 492 radeon_uvd_force_into_uvd_segment(bo); 493 494 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 495 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 496 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 497 initial_bytes_moved; 498 499 if (unlikely(r)) { 500 if (r != -ERESTARTSYS && 501 domain != lobj->allowed_domains) { 502 domain = lobj->allowed_domains; 503 goto retry; 504 } 505 ttm_eu_backoff_reservation(ticket, head); 506 return r; 507 } 508 } 509 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 510 lobj->tiling_flags = bo->tiling_flags; 511 } 512 return 0; 513 } 514 515 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 516 struct vm_area_struct *vma) 517 { 518 return ttm_fbdev_mmap(vma, &bo->tbo); 519 } 520 521 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 522 { 523 struct radeon_device *rdev = bo->rdev; 524 struct radeon_surface_reg *reg; 525 struct radeon_bo *old_object; 526 int steal; 527 int i; 528 529 lockdep_assert_held(&bo->tbo.resv->lock.base); 530 531 if (!bo->tiling_flags) 532 return 0; 533 534 if (bo->surface_reg >= 0) { 535 reg = &rdev->surface_regs[bo->surface_reg]; 536 i = bo->surface_reg; 537 goto out; 538 } 539 540 steal = -1; 541 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 542 543 reg = &rdev->surface_regs[i]; 544 if (!reg->bo) 545 break; 546 547 old_object = reg->bo; 548 if (old_object->pin_count == 0) 549 steal = i; 550 } 551 552 /* if we are all out */ 553 if (i == RADEON_GEM_MAX_SURFACES) { 554 if (steal == -1) 555 return -ENOMEM; 556 /* find someone with a surface reg and nuke their BO */ 557 reg = &rdev->surface_regs[steal]; 558 old_object = reg->bo; 559 /* blow away the mapping */ 560 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 561 ttm_bo_unmap_virtual(&old_object->tbo); 562 old_object->surface_reg = -1; 563 i = steal; 564 } 565 566 bo->surface_reg = i; 567 reg->bo = bo; 568 569 out: 570 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 571 bo->tbo.mem.start << PAGE_SHIFT, 572 bo->tbo.num_pages << PAGE_SHIFT); 573 return 0; 574 } 575 576 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 577 { 578 struct radeon_device *rdev = bo->rdev; 579 struct radeon_surface_reg *reg; 580 581 if (bo->surface_reg == -1) 582 return; 583 584 reg = &rdev->surface_regs[bo->surface_reg]; 585 radeon_clear_surface_reg(rdev, bo->surface_reg); 586 587 reg->bo = NULL; 588 bo->surface_reg = -1; 589 } 590 591 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 592 uint32_t tiling_flags, uint32_t pitch) 593 { 594 struct radeon_device *rdev = bo->rdev; 595 int r; 596 597 if (rdev->family >= CHIP_CEDAR) { 598 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 599 600 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 601 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 602 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 603 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 604 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 605 switch (bankw) { 606 case 0: 607 case 1: 608 case 2: 609 case 4: 610 case 8: 611 break; 612 default: 613 return -EINVAL; 614 } 615 switch (bankh) { 616 case 0: 617 case 1: 618 case 2: 619 case 4: 620 case 8: 621 break; 622 default: 623 return -EINVAL; 624 } 625 switch (mtaspect) { 626 case 0: 627 case 1: 628 case 2: 629 case 4: 630 case 8: 631 break; 632 default: 633 return -EINVAL; 634 } 635 if (tilesplit > 6) { 636 return -EINVAL; 637 } 638 if (stilesplit > 6) { 639 return -EINVAL; 640 } 641 } 642 r = radeon_bo_reserve(bo, false); 643 if (unlikely(r != 0)) 644 return r; 645 bo->tiling_flags = tiling_flags; 646 bo->pitch = pitch; 647 radeon_bo_unreserve(bo); 648 return 0; 649 } 650 651 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 652 uint32_t *tiling_flags, 653 uint32_t *pitch) 654 { 655 lockdep_assert_held(&bo->tbo.resv->lock.base); 656 657 if (tiling_flags) 658 *tiling_flags = bo->tiling_flags; 659 if (pitch) 660 *pitch = bo->pitch; 661 } 662 663 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 664 bool force_drop) 665 { 666 if (!force_drop) 667 lockdep_assert_held(&bo->tbo.resv->lock.base); 668 669 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 670 return 0; 671 672 if (force_drop) { 673 radeon_bo_clear_surface_reg(bo); 674 return 0; 675 } 676 677 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 678 if (!has_moved) 679 return 0; 680 681 if (bo->surface_reg >= 0) 682 radeon_bo_clear_surface_reg(bo); 683 return 0; 684 } 685 686 if ((bo->surface_reg >= 0) && !has_moved) 687 return 0; 688 689 return radeon_bo_get_surface_reg(bo); 690 } 691 692 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 693 struct ttm_mem_reg *new_mem) 694 { 695 struct radeon_bo *rbo; 696 697 if (!radeon_ttm_bo_is_radeon_bo(bo)) 698 return; 699 700 rbo = container_of(bo, struct radeon_bo, tbo); 701 radeon_bo_check_tiling(rbo, 0, 1); 702 radeon_vm_bo_invalidate(rbo->rdev, rbo); 703 704 /* update statistics */ 705 if (!new_mem) 706 return; 707 708 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 709 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 710 } 711 712 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 713 { 714 struct radeon_device *rdev; 715 struct radeon_bo *rbo; 716 unsigned long offset, size; 717 int r; 718 719 if (!radeon_ttm_bo_is_radeon_bo(bo)) 720 return 0; 721 rbo = container_of(bo, struct radeon_bo, tbo); 722 radeon_bo_check_tiling(rbo, 0, 0); 723 rdev = rbo->rdev; 724 if (bo->mem.mem_type != TTM_PL_VRAM) 725 return 0; 726 727 size = bo->mem.num_pages << PAGE_SHIFT; 728 offset = bo->mem.start << PAGE_SHIFT; 729 if ((offset + size) <= rdev->mc.visible_vram_size) 730 return 0; 731 732 /* hurrah the memory is not visible ! */ 733 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 734 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 735 r = ttm_bo_validate(bo, &rbo->placement, false, false); 736 if (unlikely(r == -ENOMEM)) { 737 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 738 return ttm_bo_validate(bo, &rbo->placement, false, false); 739 } else if (unlikely(r != 0)) { 740 return r; 741 } 742 743 offset = bo->mem.start << PAGE_SHIFT; 744 /* this should never happen */ 745 if ((offset + size) > rdev->mc.visible_vram_size) 746 return -EINVAL; 747 748 return 0; 749 } 750 751 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 752 { 753 int r; 754 755 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); 756 if (unlikely(r != 0)) 757 return r; 758 spin_lock(&bo->tbo.bdev->fence_lock); 759 if (mem_type) 760 *mem_type = bo->tbo.mem.mem_type; 761 if (bo->tbo.sync_obj) 762 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 763 spin_unlock(&bo->tbo.bdev->fence_lock); 764 ttm_bo_unreserve(&bo->tbo); 765 return r; 766 } 767