1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm_crtc.h> 34 #include <drm_mode.h> 35 #include <drm_edid.h> 36 #include <drm_dp_helper.h> 37 #include <drm_fixed.h> 38 #include <drm_crtc_helper.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 42 struct radeon_bo; 43 struct radeon_device; 44 45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49 50 enum radeon_rmx_type { 51 RMX_OFF, 52 RMX_FULL, 53 RMX_CENTER, 54 RMX_ASPECT 55 }; 56 57 enum radeon_tv_std { 58 TV_STD_NTSC, 59 TV_STD_PAL, 60 TV_STD_PAL_M, 61 TV_STD_PAL_60, 62 TV_STD_NTSC_J, 63 TV_STD_SCART_PAL, 64 TV_STD_SECAM, 65 TV_STD_PAL_CN, 66 TV_STD_PAL_N, 67 }; 68 69 enum radeon_underscan_type { 70 UNDERSCAN_OFF, 71 UNDERSCAN_ON, 72 UNDERSCAN_AUTO, 73 }; 74 75 enum radeon_hpd_id { 76 RADEON_HPD_1 = 0, 77 RADEON_HPD_2, 78 RADEON_HPD_3, 79 RADEON_HPD_4, 80 RADEON_HPD_5, 81 RADEON_HPD_6, 82 RADEON_HPD_NONE = 0xff, 83 }; 84 85 #define RADEON_MAX_I2C_BUS 16 86 87 /* radeon gpio-based i2c 88 * 1. "mask" reg and bits 89 * grabs the gpio pins for software use 90 * 0=not held 1=held 91 * 2. "a" reg and bits 92 * output pin value 93 * 0=low 1=high 94 * 3. "en" reg and bits 95 * sets the pin direction 96 * 0=input 1=output 97 * 4. "y" reg and bits 98 * input pin value 99 * 0=low 1=high 100 */ 101 struct radeon_i2c_bus_rec { 102 bool valid; 103 /* id used by atom */ 104 uint8_t i2c_id; 105 /* id used by atom */ 106 enum radeon_hpd_id hpd; 107 /* can be used with hw i2c engine */ 108 bool hw_capable; 109 /* uses multi-media i2c engine */ 110 bool mm_i2c; 111 /* regs and bits */ 112 uint32_t mask_clk_reg; 113 uint32_t mask_data_reg; 114 uint32_t a_clk_reg; 115 uint32_t a_data_reg; 116 uint32_t en_clk_reg; 117 uint32_t en_data_reg; 118 uint32_t y_clk_reg; 119 uint32_t y_data_reg; 120 uint32_t mask_clk_mask; 121 uint32_t mask_data_mask; 122 uint32_t a_clk_mask; 123 uint32_t a_data_mask; 124 uint32_t en_clk_mask; 125 uint32_t en_data_mask; 126 uint32_t y_clk_mask; 127 uint32_t y_data_mask; 128 }; 129 130 struct radeon_tmds_pll { 131 uint32_t freq; 132 uint32_t value; 133 }; 134 135 #define RADEON_MAX_BIOS_CONNECTOR 16 136 137 /* pll flags */ 138 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140 #define RADEON_PLL_USE_REF_DIV (1 << 2) 141 #define RADEON_PLL_LEGACY (1 << 3) 142 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150 #define RADEON_PLL_USE_POST_DIV (1 << 12) 151 #define RADEON_PLL_IS_LCD (1 << 13) 152 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 153 154 struct radeon_pll { 155 /* reference frequency */ 156 uint32_t reference_freq; 157 158 /* fixed dividers */ 159 uint32_t reference_div; 160 uint32_t post_div; 161 162 /* pll in/out limits */ 163 uint32_t pll_in_min; 164 uint32_t pll_in_max; 165 uint32_t pll_out_min; 166 uint32_t pll_out_max; 167 uint32_t lcd_pll_out_min; 168 uint32_t lcd_pll_out_max; 169 uint32_t best_vco; 170 171 /* divider limits */ 172 uint32_t min_ref_div; 173 uint32_t max_ref_div; 174 uint32_t min_post_div; 175 uint32_t max_post_div; 176 uint32_t min_feedback_div; 177 uint32_t max_feedback_div; 178 uint32_t min_frac_feedback_div; 179 uint32_t max_frac_feedback_div; 180 181 /* flags for the current clock */ 182 uint32_t flags; 183 184 /* pll id */ 185 uint32_t id; 186 }; 187 188 struct radeon_i2c_chan { 189 struct i2c_adapter adapter; 190 struct drm_device *dev; 191 union { 192 struct i2c_algo_bit_data bit; 193 struct i2c_algo_dp_aux_data dp; 194 } algo; 195 struct radeon_i2c_bus_rec rec; 196 }; 197 198 /* mostly for macs, but really any system without connector tables */ 199 enum radeon_connector_table { 200 CT_NONE = 0, 201 CT_GENERIC, 202 CT_IBOOK, 203 CT_POWERBOOK_EXTERNAL, 204 CT_POWERBOOK_INTERNAL, 205 CT_POWERBOOK_VGA, 206 CT_MINI_EXTERNAL, 207 CT_MINI_INTERNAL, 208 CT_IMAC_G5_ISIGHT, 209 CT_EMAC, 210 CT_RN50_POWER, 211 CT_MAC_X800, 212 CT_MAC_G5_9600, 213 }; 214 215 enum radeon_dvo_chip { 216 DVO_SIL164, 217 DVO_SIL1178, 218 }; 219 220 struct radeon_fbdev; 221 222 struct radeon_mode_info { 223 struct atom_context *atom_context; 224 struct card_info *atom_card_info; 225 enum radeon_connector_table connector_table; 226 bool mode_config_initialized; 227 struct radeon_crtc *crtcs[6]; 228 /* DVI-I properties */ 229 struct drm_property *coherent_mode_property; 230 /* DAC enable load detect */ 231 struct drm_property *load_detect_property; 232 /* TV standard */ 233 struct drm_property *tv_std_property; 234 /* legacy TMDS PLL detect */ 235 struct drm_property *tmds_pll_property; 236 /* underscan */ 237 struct drm_property *underscan_property; 238 struct drm_property *underscan_hborder_property; 239 struct drm_property *underscan_vborder_property; 240 /* hardcoded DFP edid from BIOS */ 241 struct edid *bios_hardcoded_edid; 242 int bios_hardcoded_edid_size; 243 244 /* pointer to fbdev info structure */ 245 struct radeon_fbdev *rfbdev; 246 }; 247 248 #define MAX_H_CODE_TIMING_LEN 32 249 #define MAX_V_CODE_TIMING_LEN 32 250 251 /* need to store these as reading 252 back code tables is excessive */ 253 struct radeon_tv_regs { 254 uint32_t tv_uv_adr; 255 uint32_t timing_cntl; 256 uint32_t hrestart; 257 uint32_t vrestart; 258 uint32_t frestart; 259 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 260 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 261 }; 262 263 struct radeon_crtc { 264 struct drm_crtc base; 265 int crtc_id; 266 u16 lut_r[256], lut_g[256], lut_b[256]; 267 bool enabled; 268 bool can_tile; 269 uint32_t crtc_offset; 270 struct drm_gem_object *cursor_bo; 271 uint64_t cursor_addr; 272 int cursor_width; 273 int cursor_height; 274 uint32_t legacy_display_base_addr; 275 uint32_t legacy_cursor_offset; 276 enum radeon_rmx_type rmx_type; 277 u8 h_border; 278 u8 v_border; 279 fixed20_12 vsc; 280 fixed20_12 hsc; 281 struct drm_display_mode native_mode; 282 int pll_id; 283 /* page flipping */ 284 struct radeon_unpin_work *unpin_work; 285 int deferred_flip_completion; 286 }; 287 288 struct radeon_encoder_primary_dac { 289 /* legacy primary dac */ 290 uint32_t ps2_pdac_adj; 291 }; 292 293 struct radeon_encoder_lvds { 294 /* legacy lvds */ 295 uint16_t panel_vcc_delay; 296 uint8_t panel_pwr_delay; 297 uint8_t panel_digon_delay; 298 uint8_t panel_blon_delay; 299 uint16_t panel_ref_divider; 300 uint8_t panel_post_divider; 301 uint16_t panel_fb_divider; 302 bool use_bios_dividers; 303 uint32_t lvds_gen_cntl; 304 /* panel mode */ 305 struct drm_display_mode native_mode; 306 struct backlight_device *bl_dev; 307 int dpms_mode; 308 uint8_t backlight_level; 309 }; 310 311 struct radeon_encoder_tv_dac { 312 /* legacy tv dac */ 313 uint32_t ps2_tvdac_adj; 314 uint32_t ntsc_tvdac_adj; 315 uint32_t pal_tvdac_adj; 316 317 int h_pos; 318 int v_pos; 319 int h_size; 320 int supported_tv_stds; 321 bool tv_on; 322 enum radeon_tv_std tv_std; 323 struct radeon_tv_regs tv; 324 }; 325 326 struct radeon_encoder_int_tmds { 327 /* legacy int tmds */ 328 struct radeon_tmds_pll tmds_pll[4]; 329 }; 330 331 struct radeon_encoder_ext_tmds { 332 /* tmds over dvo */ 333 struct radeon_i2c_chan *i2c_bus; 334 uint8_t slave_addr; 335 enum radeon_dvo_chip dvo_chip; 336 }; 337 338 /* spread spectrum */ 339 struct radeon_atom_ss { 340 uint16_t percentage; 341 uint8_t type; 342 uint16_t step; 343 uint8_t delay; 344 uint8_t range; 345 uint8_t refdiv; 346 /* asic_ss */ 347 uint16_t rate; 348 uint16_t amount; 349 }; 350 351 struct radeon_encoder_atom_dig { 352 bool linkb; 353 /* atom dig */ 354 bool coherent_mode; 355 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 356 /* atom lvds/edp */ 357 uint32_t lcd_misc; 358 uint16_t panel_pwr_delay; 359 uint32_t lcd_ss_id; 360 /* panel mode */ 361 struct drm_display_mode native_mode; 362 struct backlight_device *bl_dev; 363 int dpms_mode; 364 uint8_t backlight_level; 365 int panel_mode; 366 }; 367 368 struct radeon_encoder_atom_dac { 369 enum radeon_tv_std tv_std; 370 }; 371 372 struct radeon_encoder { 373 struct drm_encoder base; 374 uint32_t encoder_enum; 375 uint32_t encoder_id; 376 uint32_t devices; 377 uint32_t active_device; 378 uint32_t flags; 379 uint32_t pixel_clock; 380 enum radeon_rmx_type rmx_type; 381 enum radeon_underscan_type underscan_type; 382 uint32_t underscan_hborder; 383 uint32_t underscan_vborder; 384 struct drm_display_mode native_mode; 385 void *enc_priv; 386 int audio_polling_active; 387 int hdmi_offset; 388 int hdmi_config_offset; 389 int hdmi_audio_workaround; 390 int hdmi_buffer_status; 391 bool is_ext_encoder; 392 u16 caps; 393 }; 394 395 struct radeon_connector_atom_dig { 396 uint32_t igp_lane_info; 397 /* displayport */ 398 struct radeon_i2c_chan *dp_i2c_bus; 399 u8 dpcd[8]; 400 u8 dp_sink_type; 401 int dp_clock; 402 int dp_lane_count; 403 bool edp_on; 404 }; 405 406 struct radeon_gpio_rec { 407 bool valid; 408 u8 id; 409 u32 reg; 410 u32 mask; 411 }; 412 413 struct radeon_hpd { 414 enum radeon_hpd_id hpd; 415 u8 plugged_state; 416 struct radeon_gpio_rec gpio; 417 }; 418 419 struct radeon_router { 420 u32 router_id; 421 struct radeon_i2c_bus_rec i2c_info; 422 u8 i2c_addr; 423 /* i2c mux */ 424 bool ddc_valid; 425 u8 ddc_mux_type; 426 u8 ddc_mux_control_pin; 427 u8 ddc_mux_state; 428 /* clock/data mux */ 429 bool cd_valid; 430 u8 cd_mux_type; 431 u8 cd_mux_control_pin; 432 u8 cd_mux_state; 433 }; 434 435 struct radeon_connector { 436 struct drm_connector base; 437 uint32_t connector_id; 438 uint32_t devices; 439 struct radeon_i2c_chan *ddc_bus; 440 /* some systems have an hdmi and vga port with a shared ddc line */ 441 bool shared_ddc; 442 bool use_digital; 443 /* we need to mind the EDID between detect 444 and get modes due to analog/digital/tvencoder */ 445 struct edid *edid; 446 void *con_priv; 447 bool dac_load_detect; 448 bool detected_by_load; /* if the connection status was determined by load */ 449 uint16_t connector_object_id; 450 struct radeon_hpd hpd; 451 struct radeon_router router; 452 struct radeon_i2c_chan *router_bus; 453 }; 454 455 struct radeon_framebuffer { 456 struct drm_framebuffer base; 457 struct drm_gem_object *obj; 458 }; 459 460 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 461 ((em) == ATOM_ENCODER_MODE_DP_MST)) 462 463 extern enum radeon_tv_std 464 radeon_combios_get_tv_info(struct radeon_device *rdev); 465 extern enum radeon_tv_std 466 radeon_atombios_get_tv_info(struct radeon_device *rdev); 467 468 extern struct drm_connector * 469 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 470 extern struct drm_connector * 471 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 472 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 473 u32 pixel_clock); 474 475 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 476 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 477 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 478 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 479 480 extern void radeon_connector_hotplug(struct drm_connector *connector); 481 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 482 struct drm_display_mode *mode); 483 extern void radeon_dp_set_link_config(struct drm_connector *connector, 484 struct drm_display_mode *mode); 485 extern void radeon_dp_link_train(struct drm_encoder *encoder, 486 struct drm_connector *connector); 487 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 488 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 489 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 490 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 491 struct drm_connector *connector); 492 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 493 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 494 extern void radeon_atom_dcpll_init(struct radeon_device *rdev); 495 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 496 int action, uint8_t lane_num, 497 uint8_t lane_set); 498 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 499 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 500 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 501 u8 write_byte, u8 *read_byte); 502 503 extern void radeon_i2c_init(struct radeon_device *rdev); 504 extern void radeon_i2c_fini(struct radeon_device *rdev); 505 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 506 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 507 extern void radeon_i2c_add(struct radeon_device *rdev, 508 struct radeon_i2c_bus_rec *rec, 509 const char *name); 510 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 511 struct radeon_i2c_bus_rec *i2c_bus); 512 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 513 struct radeon_i2c_bus_rec *rec, 514 const char *name); 515 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 516 struct radeon_i2c_bus_rec *rec, 517 const char *name); 518 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 519 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 520 u8 slave_addr, 521 u8 addr, 522 u8 *val); 523 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 524 u8 slave_addr, 525 u8 addr, 526 u8 val); 527 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 528 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 529 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 530 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 531 532 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 533 534 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 535 struct radeon_atom_ss *ss, 536 int id); 537 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 538 struct radeon_atom_ss *ss, 539 int id, u32 clock); 540 541 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 542 uint64_t freq, 543 uint32_t *dot_clock_p, 544 uint32_t *fb_div_p, 545 uint32_t *frac_fb_div_p, 546 uint32_t *ref_div_p, 547 uint32_t *post_div_p); 548 549 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 550 u32 freq, 551 u32 *dot_clock_p, 552 u32 *fb_div_p, 553 u32 *frac_fb_div_p, 554 u32 *ref_div_p, 555 u32 *post_div_p); 556 557 extern void radeon_setup_encoder_clones(struct drm_device *dev); 558 559 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 560 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 561 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 562 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 563 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 564 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 565 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 566 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 567 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 568 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 569 570 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 571 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 572 struct drm_framebuffer *old_fb); 573 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 574 struct drm_framebuffer *fb, 575 int x, int y, 576 enum mode_set_atomic state); 577 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 578 struct drm_display_mode *mode, 579 struct drm_display_mode *adjusted_mode, 580 int x, int y, 581 struct drm_framebuffer *old_fb); 582 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 583 584 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 585 struct drm_framebuffer *old_fb); 586 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 587 struct drm_framebuffer *fb, 588 int x, int y, 589 enum mode_set_atomic state); 590 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 591 struct drm_framebuffer *fb, 592 int x, int y, int atomic); 593 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 594 struct drm_file *file_priv, 595 uint32_t handle, 596 uint32_t width, 597 uint32_t height); 598 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 599 int x, int y); 600 601 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 602 int *vpos, int *hpos); 603 604 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 605 extern struct edid * 606 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 607 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 608 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 609 extern struct radeon_encoder_atom_dig * 610 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 611 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 612 struct radeon_encoder_int_tmds *tmds); 613 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 614 struct radeon_encoder_int_tmds *tmds); 615 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 616 struct radeon_encoder_int_tmds *tmds); 617 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 618 struct radeon_encoder_ext_tmds *tmds); 619 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 620 struct radeon_encoder_ext_tmds *tmds); 621 extern struct radeon_encoder_primary_dac * 622 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 623 extern struct radeon_encoder_tv_dac * 624 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 625 extern struct radeon_encoder_lvds * 626 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 627 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 628 extern struct radeon_encoder_tv_dac * 629 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 630 extern struct radeon_encoder_primary_dac * 631 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 632 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 633 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 634 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 635 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 636 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 637 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 638 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 639 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 640 extern void 641 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 642 extern void 643 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 644 extern void 645 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 646 extern void 647 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 648 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 649 u16 blue, int regno); 650 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 651 u16 *blue, int regno); 652 void radeon_framebuffer_init(struct drm_device *dev, 653 struct radeon_framebuffer *rfb, 654 struct drm_mode_fb_cmd2 *mode_cmd, 655 struct drm_gem_object *obj); 656 657 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 658 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 659 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 660 void radeon_atombios_init_crtc(struct drm_device *dev, 661 struct radeon_crtc *radeon_crtc); 662 void radeon_legacy_init_crtc(struct drm_device *dev, 663 struct radeon_crtc *radeon_crtc); 664 665 void radeon_get_clock_info(struct drm_device *dev); 666 667 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 668 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 669 670 void radeon_enc_destroy(struct drm_encoder *encoder); 671 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 672 void radeon_combios_asic_init(struct drm_device *dev); 673 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 674 struct drm_display_mode *mode, 675 struct drm_display_mode *adjusted_mode); 676 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 677 struct drm_display_mode *adjusted_mode); 678 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 679 680 /* legacy tv */ 681 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 682 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 683 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 684 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 685 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 686 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 687 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 688 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 689 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 690 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 691 struct drm_display_mode *mode, 692 struct drm_display_mode *adjusted_mode); 693 694 /* fbdev layer */ 695 int radeon_fbdev_init(struct radeon_device *rdev); 696 void radeon_fbdev_fini(struct radeon_device *rdev); 697 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 698 int radeon_fbdev_total_size(struct radeon_device *rdev); 699 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 700 701 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 702 703 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 704 705 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 706 #endif 707