1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm_crtc.h> 34 #include <drm_mode.h> 35 #include <drm_edid.h> 36 #include <drm_dp_helper.h> 37 #include <drm_fixed.h> 38 #include <drm_crtc_helper.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 42 struct radeon_bo; 43 struct radeon_device; 44 45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49 50 enum radeon_rmx_type { 51 RMX_OFF, 52 RMX_FULL, 53 RMX_CENTER, 54 RMX_ASPECT 55 }; 56 57 enum radeon_tv_std { 58 TV_STD_NTSC, 59 TV_STD_PAL, 60 TV_STD_PAL_M, 61 TV_STD_PAL_60, 62 TV_STD_NTSC_J, 63 TV_STD_SCART_PAL, 64 TV_STD_SECAM, 65 TV_STD_PAL_CN, 66 TV_STD_PAL_N, 67 }; 68 69 enum radeon_underscan_type { 70 UNDERSCAN_OFF, 71 UNDERSCAN_ON, 72 UNDERSCAN_AUTO, 73 }; 74 75 enum radeon_hpd_id { 76 RADEON_HPD_1 = 0, 77 RADEON_HPD_2, 78 RADEON_HPD_3, 79 RADEON_HPD_4, 80 RADEON_HPD_5, 81 RADEON_HPD_6, 82 RADEON_HPD_NONE = 0xff, 83 }; 84 85 #define RADEON_MAX_I2C_BUS 16 86 87 /* radeon gpio-based i2c 88 * 1. "mask" reg and bits 89 * grabs the gpio pins for software use 90 * 0=not held 1=held 91 * 2. "a" reg and bits 92 * output pin value 93 * 0=low 1=high 94 * 3. "en" reg and bits 95 * sets the pin direction 96 * 0=input 1=output 97 * 4. "y" reg and bits 98 * input pin value 99 * 0=low 1=high 100 */ 101 struct radeon_i2c_bus_rec { 102 bool valid; 103 /* id used by atom */ 104 uint8_t i2c_id; 105 /* id used by atom */ 106 enum radeon_hpd_id hpd; 107 /* can be used with hw i2c engine */ 108 bool hw_capable; 109 /* uses multi-media i2c engine */ 110 bool mm_i2c; 111 /* regs and bits */ 112 uint32_t mask_clk_reg; 113 uint32_t mask_data_reg; 114 uint32_t a_clk_reg; 115 uint32_t a_data_reg; 116 uint32_t en_clk_reg; 117 uint32_t en_data_reg; 118 uint32_t y_clk_reg; 119 uint32_t y_data_reg; 120 uint32_t mask_clk_mask; 121 uint32_t mask_data_mask; 122 uint32_t a_clk_mask; 123 uint32_t a_data_mask; 124 uint32_t en_clk_mask; 125 uint32_t en_data_mask; 126 uint32_t y_clk_mask; 127 uint32_t y_data_mask; 128 }; 129 130 struct radeon_tmds_pll { 131 uint32_t freq; 132 uint32_t value; 133 }; 134 135 #define RADEON_MAX_BIOS_CONNECTOR 16 136 137 /* pll flags */ 138 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140 #define RADEON_PLL_USE_REF_DIV (1 << 2) 141 #define RADEON_PLL_LEGACY (1 << 3) 142 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150 #define RADEON_PLL_USE_POST_DIV (1 << 12) 151 #define RADEON_PLL_IS_LCD (1 << 13) 152 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 153 154 struct radeon_pll { 155 /* reference frequency */ 156 uint32_t reference_freq; 157 158 /* fixed dividers */ 159 uint32_t reference_div; 160 uint32_t post_div; 161 162 /* pll in/out limits */ 163 uint32_t pll_in_min; 164 uint32_t pll_in_max; 165 uint32_t pll_out_min; 166 uint32_t pll_out_max; 167 uint32_t lcd_pll_out_min; 168 uint32_t lcd_pll_out_max; 169 uint32_t best_vco; 170 171 /* divider limits */ 172 uint32_t min_ref_div; 173 uint32_t max_ref_div; 174 uint32_t min_post_div; 175 uint32_t max_post_div; 176 uint32_t min_feedback_div; 177 uint32_t max_feedback_div; 178 uint32_t min_frac_feedback_div; 179 uint32_t max_frac_feedback_div; 180 181 /* flags for the current clock */ 182 uint32_t flags; 183 184 /* pll id */ 185 uint32_t id; 186 }; 187 188 struct radeon_i2c_chan { 189 struct i2c_adapter adapter; 190 struct drm_device *dev; 191 union { 192 struct i2c_algo_bit_data bit; 193 struct i2c_algo_dp_aux_data dp; 194 } algo; 195 struct radeon_i2c_bus_rec rec; 196 }; 197 198 /* mostly for macs, but really any system without connector tables */ 199 enum radeon_connector_table { 200 CT_NONE = 0, 201 CT_GENERIC, 202 CT_IBOOK, 203 CT_POWERBOOK_EXTERNAL, 204 CT_POWERBOOK_INTERNAL, 205 CT_POWERBOOK_VGA, 206 CT_MINI_EXTERNAL, 207 CT_MINI_INTERNAL, 208 CT_IMAC_G5_ISIGHT, 209 CT_EMAC, 210 CT_RN50_POWER, 211 CT_MAC_X800, 212 CT_MAC_G5_9600, 213 CT_SAM440EP 214 }; 215 216 enum radeon_dvo_chip { 217 DVO_SIL164, 218 DVO_SIL1178, 219 }; 220 221 struct radeon_fbdev; 222 223 struct radeon_afmt { 224 bool enabled; 225 int offset; 226 bool last_buffer_filled_status; 227 int id; 228 }; 229 230 struct radeon_mode_info { 231 struct atom_context *atom_context; 232 struct card_info *atom_card_info; 233 enum radeon_connector_table connector_table; 234 bool mode_config_initialized; 235 struct radeon_crtc *crtcs[6]; 236 struct radeon_afmt *afmt[6]; 237 /* DVI-I properties */ 238 struct drm_property *coherent_mode_property; 239 /* DAC enable load detect */ 240 struct drm_property *load_detect_property; 241 /* TV standard */ 242 struct drm_property *tv_std_property; 243 /* legacy TMDS PLL detect */ 244 struct drm_property *tmds_pll_property; 245 /* underscan */ 246 struct drm_property *underscan_property; 247 struct drm_property *underscan_hborder_property; 248 struct drm_property *underscan_vborder_property; 249 /* hardcoded DFP edid from BIOS */ 250 struct edid *bios_hardcoded_edid; 251 int bios_hardcoded_edid_size; 252 253 /* pointer to fbdev info structure */ 254 struct radeon_fbdev *rfbdev; 255 }; 256 257 #define MAX_H_CODE_TIMING_LEN 32 258 #define MAX_V_CODE_TIMING_LEN 32 259 260 /* need to store these as reading 261 back code tables is excessive */ 262 struct radeon_tv_regs { 263 uint32_t tv_uv_adr; 264 uint32_t timing_cntl; 265 uint32_t hrestart; 266 uint32_t vrestart; 267 uint32_t frestart; 268 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 269 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 270 }; 271 272 struct radeon_crtc { 273 struct drm_crtc base; 274 int crtc_id; 275 u16 lut_r[256], lut_g[256], lut_b[256]; 276 bool enabled; 277 bool can_tile; 278 bool in_mode_set; 279 uint32_t crtc_offset; 280 struct drm_gem_object *cursor_bo; 281 uint64_t cursor_addr; 282 int cursor_width; 283 int cursor_height; 284 uint32_t legacy_display_base_addr; 285 uint32_t legacy_cursor_offset; 286 enum radeon_rmx_type rmx_type; 287 u8 h_border; 288 u8 v_border; 289 fixed20_12 vsc; 290 fixed20_12 hsc; 291 struct drm_display_mode native_mode; 292 int pll_id; 293 /* page flipping */ 294 struct radeon_unpin_work *unpin_work; 295 int deferred_flip_completion; 296 }; 297 298 struct radeon_encoder_primary_dac { 299 /* legacy primary dac */ 300 uint32_t ps2_pdac_adj; 301 }; 302 303 struct radeon_encoder_lvds { 304 /* legacy lvds */ 305 uint16_t panel_vcc_delay; 306 uint8_t panel_pwr_delay; 307 uint8_t panel_digon_delay; 308 uint8_t panel_blon_delay; 309 uint16_t panel_ref_divider; 310 uint8_t panel_post_divider; 311 uint16_t panel_fb_divider; 312 bool use_bios_dividers; 313 uint32_t lvds_gen_cntl; 314 /* panel mode */ 315 struct drm_display_mode native_mode; 316 struct backlight_device *bl_dev; 317 int dpms_mode; 318 uint8_t backlight_level; 319 }; 320 321 struct radeon_encoder_tv_dac { 322 /* legacy tv dac */ 323 uint32_t ps2_tvdac_adj; 324 uint32_t ntsc_tvdac_adj; 325 uint32_t pal_tvdac_adj; 326 327 int h_pos; 328 int v_pos; 329 int h_size; 330 int supported_tv_stds; 331 bool tv_on; 332 enum radeon_tv_std tv_std; 333 struct radeon_tv_regs tv; 334 }; 335 336 struct radeon_encoder_int_tmds { 337 /* legacy int tmds */ 338 struct radeon_tmds_pll tmds_pll[4]; 339 }; 340 341 struct radeon_encoder_ext_tmds { 342 /* tmds over dvo */ 343 struct radeon_i2c_chan *i2c_bus; 344 uint8_t slave_addr; 345 enum radeon_dvo_chip dvo_chip; 346 }; 347 348 /* spread spectrum */ 349 struct radeon_atom_ss { 350 uint16_t percentage; 351 uint8_t type; 352 uint16_t step; 353 uint8_t delay; 354 uint8_t range; 355 uint8_t refdiv; 356 /* asic_ss */ 357 uint16_t rate; 358 uint16_t amount; 359 }; 360 361 struct radeon_encoder_atom_dig { 362 bool linkb; 363 /* atom dig */ 364 bool coherent_mode; 365 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 366 /* atom lvds/edp */ 367 uint32_t lcd_misc; 368 uint16_t panel_pwr_delay; 369 uint32_t lcd_ss_id; 370 /* panel mode */ 371 struct drm_display_mode native_mode; 372 struct backlight_device *bl_dev; 373 int dpms_mode; 374 uint8_t backlight_level; 375 int panel_mode; 376 struct radeon_afmt *afmt; 377 }; 378 379 struct radeon_encoder_atom_dac { 380 enum radeon_tv_std tv_std; 381 }; 382 383 struct radeon_encoder { 384 struct drm_encoder base; 385 uint32_t encoder_enum; 386 uint32_t encoder_id; 387 uint32_t devices; 388 uint32_t active_device; 389 uint32_t flags; 390 uint32_t pixel_clock; 391 enum radeon_rmx_type rmx_type; 392 enum radeon_underscan_type underscan_type; 393 uint32_t underscan_hborder; 394 uint32_t underscan_vborder; 395 struct drm_display_mode native_mode; 396 void *enc_priv; 397 int audio_polling_active; 398 bool is_ext_encoder; 399 u16 caps; 400 }; 401 402 struct radeon_connector_atom_dig { 403 uint32_t igp_lane_info; 404 /* displayport */ 405 struct radeon_i2c_chan *dp_i2c_bus; 406 u8 dpcd[8]; 407 u8 dp_sink_type; 408 int dp_clock; 409 int dp_lane_count; 410 bool edp_on; 411 }; 412 413 struct radeon_gpio_rec { 414 bool valid; 415 u8 id; 416 u32 reg; 417 u32 mask; 418 }; 419 420 struct radeon_hpd { 421 enum radeon_hpd_id hpd; 422 u8 plugged_state; 423 struct radeon_gpio_rec gpio; 424 }; 425 426 struct radeon_router { 427 u32 router_id; 428 struct radeon_i2c_bus_rec i2c_info; 429 u8 i2c_addr; 430 /* i2c mux */ 431 bool ddc_valid; 432 u8 ddc_mux_type; 433 u8 ddc_mux_control_pin; 434 u8 ddc_mux_state; 435 /* clock/data mux */ 436 bool cd_valid; 437 u8 cd_mux_type; 438 u8 cd_mux_control_pin; 439 u8 cd_mux_state; 440 }; 441 442 struct radeon_connector { 443 struct drm_connector base; 444 uint32_t connector_id; 445 uint32_t devices; 446 struct radeon_i2c_chan *ddc_bus; 447 /* some systems have an hdmi and vga port with a shared ddc line */ 448 bool shared_ddc; 449 bool use_digital; 450 /* we need to mind the EDID between detect 451 and get modes due to analog/digital/tvencoder */ 452 struct edid *edid; 453 void *con_priv; 454 bool dac_load_detect; 455 bool detected_by_load; /* if the connection status was determined by load */ 456 uint16_t connector_object_id; 457 struct radeon_hpd hpd; 458 struct radeon_router router; 459 struct radeon_i2c_chan *router_bus; 460 }; 461 462 struct radeon_framebuffer { 463 struct drm_framebuffer base; 464 struct drm_gem_object *obj; 465 }; 466 467 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 468 ((em) == ATOM_ENCODER_MODE_DP_MST)) 469 470 extern enum radeon_tv_std 471 radeon_combios_get_tv_info(struct radeon_device *rdev); 472 extern enum radeon_tv_std 473 radeon_atombios_get_tv_info(struct radeon_device *rdev); 474 475 extern struct drm_connector * 476 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 477 extern struct drm_connector * 478 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 479 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 480 u32 pixel_clock); 481 482 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 483 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 484 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 485 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 486 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 487 488 extern void radeon_connector_hotplug(struct drm_connector *connector); 489 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 490 struct drm_display_mode *mode); 491 extern void radeon_dp_set_link_config(struct drm_connector *connector, 492 const struct drm_display_mode *mode); 493 extern void radeon_dp_link_train(struct drm_encoder *encoder, 494 struct drm_connector *connector); 495 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 496 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 497 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 498 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 499 struct drm_connector *connector); 500 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 501 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 502 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 503 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 504 int action, uint8_t lane_num, 505 uint8_t lane_set); 506 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 507 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 508 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 509 u8 write_byte, u8 *read_byte); 510 511 extern void radeon_i2c_init(struct radeon_device *rdev); 512 extern void radeon_i2c_fini(struct radeon_device *rdev); 513 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 514 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 515 extern void radeon_i2c_add(struct radeon_device *rdev, 516 struct radeon_i2c_bus_rec *rec, 517 const char *name); 518 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 519 struct radeon_i2c_bus_rec *i2c_bus); 520 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 521 struct radeon_i2c_bus_rec *rec, 522 const char *name); 523 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 524 struct radeon_i2c_bus_rec *rec, 525 const char *name); 526 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 527 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 528 u8 slave_addr, 529 u8 addr, 530 u8 *val); 531 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 532 u8 slave_addr, 533 u8 addr, 534 u8 val); 535 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 536 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 537 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 538 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 539 540 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 541 542 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 543 struct radeon_atom_ss *ss, 544 int id); 545 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 546 struct radeon_atom_ss *ss, 547 int id, u32 clock); 548 549 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 550 uint64_t freq, 551 uint32_t *dot_clock_p, 552 uint32_t *fb_div_p, 553 uint32_t *frac_fb_div_p, 554 uint32_t *ref_div_p, 555 uint32_t *post_div_p); 556 557 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 558 u32 freq, 559 u32 *dot_clock_p, 560 u32 *fb_div_p, 561 u32 *frac_fb_div_p, 562 u32 *ref_div_p, 563 u32 *post_div_p); 564 565 extern void radeon_setup_encoder_clones(struct drm_device *dev); 566 567 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 568 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 569 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 570 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 571 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 572 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 573 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 574 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 575 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 576 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 577 578 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 579 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 580 struct drm_framebuffer *old_fb); 581 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 582 struct drm_framebuffer *fb, 583 int x, int y, 584 enum mode_set_atomic state); 585 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 586 struct drm_display_mode *mode, 587 struct drm_display_mode *adjusted_mode, 588 int x, int y, 589 struct drm_framebuffer *old_fb); 590 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 591 592 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 593 struct drm_framebuffer *old_fb); 594 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 595 struct drm_framebuffer *fb, 596 int x, int y, 597 enum mode_set_atomic state); 598 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 599 struct drm_framebuffer *fb, 600 int x, int y, int atomic); 601 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 602 struct drm_file *file_priv, 603 uint32_t handle, 604 uint32_t width, 605 uint32_t height); 606 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 607 int x, int y); 608 609 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 610 int *vpos, int *hpos); 611 612 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 613 extern struct edid * 614 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 615 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 616 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 617 extern struct radeon_encoder_atom_dig * 618 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 619 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 620 struct radeon_encoder_int_tmds *tmds); 621 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 622 struct radeon_encoder_int_tmds *tmds); 623 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 624 struct radeon_encoder_int_tmds *tmds); 625 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 626 struct radeon_encoder_ext_tmds *tmds); 627 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 628 struct radeon_encoder_ext_tmds *tmds); 629 extern struct radeon_encoder_primary_dac * 630 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 631 extern struct radeon_encoder_tv_dac * 632 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 633 extern struct radeon_encoder_lvds * 634 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 635 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 636 extern struct radeon_encoder_tv_dac * 637 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 638 extern struct radeon_encoder_primary_dac * 639 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 640 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 641 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 642 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 643 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 644 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 645 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 646 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 647 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 648 extern void 649 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 650 extern void 651 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 652 extern void 653 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 654 extern void 655 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 656 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 657 u16 blue, int regno); 658 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 659 u16 *blue, int regno); 660 int radeon_framebuffer_init(struct drm_device *dev, 661 struct radeon_framebuffer *rfb, 662 struct drm_mode_fb_cmd2 *mode_cmd, 663 struct drm_gem_object *obj); 664 665 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 666 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 667 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 668 void radeon_atombios_init_crtc(struct drm_device *dev, 669 struct radeon_crtc *radeon_crtc); 670 void radeon_legacy_init_crtc(struct drm_device *dev, 671 struct radeon_crtc *radeon_crtc); 672 673 void radeon_get_clock_info(struct drm_device *dev); 674 675 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 676 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 677 678 void radeon_enc_destroy(struct drm_encoder *encoder); 679 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 680 void radeon_combios_asic_init(struct drm_device *dev); 681 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 682 const struct drm_display_mode *mode, 683 struct drm_display_mode *adjusted_mode); 684 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 685 struct drm_display_mode *adjusted_mode); 686 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 687 688 /* legacy tv */ 689 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 690 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 691 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 692 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 693 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 694 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 695 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 696 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 697 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 698 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 699 struct drm_display_mode *mode, 700 struct drm_display_mode *adjusted_mode); 701 702 /* fbdev layer */ 703 int radeon_fbdev_init(struct radeon_device *rdev); 704 void radeon_fbdev_fini(struct radeon_device *rdev); 705 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 706 int radeon_fbdev_total_size(struct radeon_device *rdev); 707 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 708 709 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 710 711 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 712 713 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 714 #endif 715