1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef RADEON_MODE_H
31 #define RADEON_MODE_H
32 
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 
42 struct radeon_bo;
43 struct radeon_device;
44 
45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48 
49 #define RADEON_MAX_HPD_PINS 7
50 #define RADEON_MAX_CRTCS 6
51 #define RADEON_MAX_AFMT_BLOCKS 7
52 
53 enum radeon_rmx_type {
54 	RMX_OFF,
55 	RMX_FULL,
56 	RMX_CENTER,
57 	RMX_ASPECT
58 };
59 
60 enum radeon_tv_std {
61 	TV_STD_NTSC,
62 	TV_STD_PAL,
63 	TV_STD_PAL_M,
64 	TV_STD_PAL_60,
65 	TV_STD_NTSC_J,
66 	TV_STD_SCART_PAL,
67 	TV_STD_SECAM,
68 	TV_STD_PAL_CN,
69 	TV_STD_PAL_N,
70 };
71 
72 enum radeon_underscan_type {
73 	UNDERSCAN_OFF,
74 	UNDERSCAN_ON,
75 	UNDERSCAN_AUTO,
76 };
77 
78 enum radeon_hpd_id {
79 	RADEON_HPD_1 = 0,
80 	RADEON_HPD_2,
81 	RADEON_HPD_3,
82 	RADEON_HPD_4,
83 	RADEON_HPD_5,
84 	RADEON_HPD_6,
85 	RADEON_HPD_NONE = 0xff,
86 };
87 
88 enum radeon_output_csc {
89 	RADEON_OUTPUT_CSC_BYPASS = 0,
90 	RADEON_OUTPUT_CSC_TVRGB = 1,
91 	RADEON_OUTPUT_CSC_YCBCR601 = 2,
92 	RADEON_OUTPUT_CSC_YCBCR709 = 3,
93 };
94 
95 #define RADEON_MAX_I2C_BUS 16
96 
97 /* radeon gpio-based i2c
98  * 1. "mask" reg and bits
99  *    grabs the gpio pins for software use
100  *    0=not held  1=held
101  * 2. "a" reg and bits
102  *    output pin value
103  *    0=low 1=high
104  * 3. "en" reg and bits
105  *    sets the pin direction
106  *    0=input 1=output
107  * 4. "y" reg and bits
108  *    input pin value
109  *    0=low 1=high
110  */
111 struct radeon_i2c_bus_rec {
112 	bool valid;
113 	/* id used by atom */
114 	uint8_t i2c_id;
115 	/* id used by atom */
116 	enum radeon_hpd_id hpd;
117 	/* can be used with hw i2c engine */
118 	bool hw_capable;
119 	/* uses multi-media i2c engine */
120 	bool mm_i2c;
121 	/* regs and bits */
122 	uint32_t mask_clk_reg;
123 	uint32_t mask_data_reg;
124 	uint32_t a_clk_reg;
125 	uint32_t a_data_reg;
126 	uint32_t en_clk_reg;
127 	uint32_t en_data_reg;
128 	uint32_t y_clk_reg;
129 	uint32_t y_data_reg;
130 	uint32_t mask_clk_mask;
131 	uint32_t mask_data_mask;
132 	uint32_t a_clk_mask;
133 	uint32_t a_data_mask;
134 	uint32_t en_clk_mask;
135 	uint32_t en_data_mask;
136 	uint32_t y_clk_mask;
137 	uint32_t y_data_mask;
138 };
139 
140 struct radeon_tmds_pll {
141     uint32_t freq;
142     uint32_t value;
143 };
144 
145 #define RADEON_MAX_BIOS_CONNECTOR 16
146 
147 /* pll flags */
148 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
149 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
150 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
151 #define RADEON_PLL_LEGACY               (1 << 3)
152 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
153 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
154 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
155 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
156 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
157 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
158 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
159 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
160 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
161 #define RADEON_PLL_IS_LCD               (1 << 13)
162 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
163 
164 struct radeon_pll {
165 	/* reference frequency */
166 	uint32_t reference_freq;
167 
168 	/* fixed dividers */
169 	uint32_t reference_div;
170 	uint32_t post_div;
171 
172 	/* pll in/out limits */
173 	uint32_t pll_in_min;
174 	uint32_t pll_in_max;
175 	uint32_t pll_out_min;
176 	uint32_t pll_out_max;
177 	uint32_t lcd_pll_out_min;
178 	uint32_t lcd_pll_out_max;
179 	uint32_t best_vco;
180 
181 	/* divider limits */
182 	uint32_t min_ref_div;
183 	uint32_t max_ref_div;
184 	uint32_t min_post_div;
185 	uint32_t max_post_div;
186 	uint32_t min_feedback_div;
187 	uint32_t max_feedback_div;
188 	uint32_t min_frac_feedback_div;
189 	uint32_t max_frac_feedback_div;
190 
191 	/* flags for the current clock */
192 	uint32_t flags;
193 
194 	/* pll id */
195 	uint32_t id;
196 };
197 
198 struct radeon_i2c_chan {
199 	struct i2c_adapter adapter;
200 	struct drm_device *dev;
201 	struct i2c_algo_bit_data bit;
202 	struct radeon_i2c_bus_rec rec;
203 	struct drm_dp_aux aux;
204 	bool has_aux;
205 	struct mutex mutex;
206 };
207 
208 /* mostly for macs, but really any system without connector tables */
209 enum radeon_connector_table {
210 	CT_NONE = 0,
211 	CT_GENERIC,
212 	CT_IBOOK,
213 	CT_POWERBOOK_EXTERNAL,
214 	CT_POWERBOOK_INTERNAL,
215 	CT_POWERBOOK_VGA,
216 	CT_MINI_EXTERNAL,
217 	CT_MINI_INTERNAL,
218 	CT_IMAC_G5_ISIGHT,
219 	CT_EMAC,
220 	CT_RN50_POWER,
221 	CT_MAC_X800,
222 	CT_MAC_G5_9600,
223 	CT_SAM440EP,
224 	CT_MAC_G4_SILVER
225 };
226 
227 enum radeon_dvo_chip {
228 	DVO_SIL164,
229 	DVO_SIL1178,
230 };
231 
232 struct radeon_fbdev;
233 
234 struct radeon_afmt {
235 	bool enabled;
236 	int offset;
237 	bool last_buffer_filled_status;
238 	int id;
239 };
240 
241 struct radeon_mode_info {
242 	struct atom_context *atom_context;
243 	struct card_info *atom_card_info;
244 	enum radeon_connector_table connector_table;
245 	bool mode_config_initialized;
246 	struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
247 	struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
248 	/* DVI-I properties */
249 	struct drm_property *coherent_mode_property;
250 	/* DAC enable load detect */
251 	struct drm_property *load_detect_property;
252 	/* TV standard */
253 	struct drm_property *tv_std_property;
254 	/* legacy TMDS PLL detect */
255 	struct drm_property *tmds_pll_property;
256 	/* underscan */
257 	struct drm_property *underscan_property;
258 	struct drm_property *underscan_hborder_property;
259 	struct drm_property *underscan_vborder_property;
260 	/* audio */
261 	struct drm_property *audio_property;
262 	/* FMT dithering */
263 	struct drm_property *dither_property;
264 	/* Output CSC */
265 	struct drm_property *output_csc_property;
266 	/* hardcoded DFP edid from BIOS */
267 	struct edid *bios_hardcoded_edid;
268 	int bios_hardcoded_edid_size;
269 
270 	/* pointer to fbdev info structure */
271 	struct radeon_fbdev *rfbdev;
272 	/* firmware flags */
273 	u16 firmware_flags;
274 	/* pointer to backlight encoder */
275 	struct radeon_encoder *bl_encoder;
276 
277 	/* bitmask for active encoder frontends */
278 	uint32_t active_encoders;
279 };
280 
281 #define RADEON_MAX_BL_LEVEL 0xFF
282 
283 struct radeon_backlight_privdata {
284 	struct radeon_encoder *encoder;
285 	uint8_t negative;
286 };
287 
288 #define MAX_H_CODE_TIMING_LEN 32
289 #define MAX_V_CODE_TIMING_LEN 32
290 
291 /* need to store these as reading
292    back code tables is excessive */
293 struct radeon_tv_regs {
294 	uint32_t tv_uv_adr;
295 	uint32_t timing_cntl;
296 	uint32_t hrestart;
297 	uint32_t vrestart;
298 	uint32_t frestart;
299 	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
300 	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
301 };
302 
303 struct radeon_atom_ss {
304 	uint16_t percentage;
305 	uint16_t percentage_divider;
306 	uint8_t type;
307 	uint16_t step;
308 	uint8_t delay;
309 	uint8_t range;
310 	uint8_t refdiv;
311 	/* asic_ss */
312 	uint16_t rate;
313 	uint16_t amount;
314 };
315 
316 enum radeon_flip_status {
317 	RADEON_FLIP_NONE,
318 	RADEON_FLIP_PENDING,
319 	RADEON_FLIP_SUBMITTED
320 };
321 
322 struct radeon_crtc {
323 	struct drm_crtc base;
324 	int crtc_id;
325 	bool enabled;
326 	bool can_tile;
327 	bool cursor_out_of_bounds;
328 	uint32_t crtc_offset;
329 	struct drm_gem_object *cursor_bo;
330 	uint64_t cursor_addr;
331 	int cursor_x;
332 	int cursor_y;
333 	int cursor_hot_x;
334 	int cursor_hot_y;
335 	int cursor_width;
336 	int cursor_height;
337 	int max_cursor_width;
338 	int max_cursor_height;
339 	uint32_t legacy_display_base_addr;
340 	enum radeon_rmx_type rmx_type;
341 	u8 h_border;
342 	u8 v_border;
343 	fixed20_12 vsc;
344 	fixed20_12 hsc;
345 	struct drm_display_mode native_mode;
346 	int pll_id;
347 	/* page flipping */
348 	struct workqueue_struct *flip_queue;
349 	struct radeon_flip_work *flip_work;
350 	enum radeon_flip_status flip_status;
351 	/* pll sharing */
352 	struct radeon_atom_ss ss;
353 	bool ss_enabled;
354 	u32 adjusted_clock;
355 	int bpc;
356 	u32 pll_reference_div;
357 	u32 pll_post_div;
358 	u32 pll_flags;
359 	struct drm_encoder *encoder;
360 	struct drm_connector *connector;
361 	/* for dpm */
362 	u32 line_time;
363 	u32 wm_low;
364 	u32 wm_high;
365 	u32 lb_vblank_lead_lines;
366 	struct drm_display_mode hw_mode;
367 	enum radeon_output_csc output_csc;
368 };
369 
370 struct radeon_encoder_primary_dac {
371 	/* legacy primary dac */
372 	uint32_t ps2_pdac_adj;
373 };
374 
375 struct radeon_encoder_lvds {
376 	/* legacy lvds */
377 	uint16_t panel_vcc_delay;
378 	uint8_t  panel_pwr_delay;
379 	uint8_t  panel_digon_delay;
380 	uint8_t  panel_blon_delay;
381 	uint16_t panel_ref_divider;
382 	uint8_t  panel_post_divider;
383 	uint16_t panel_fb_divider;
384 	bool     use_bios_dividers;
385 	uint32_t lvds_gen_cntl;
386 	/* panel mode */
387 	struct drm_display_mode native_mode;
388 	struct backlight_device *bl_dev;
389 	int      dpms_mode;
390 	uint8_t  backlight_level;
391 };
392 
393 struct radeon_encoder_tv_dac {
394 	/* legacy tv dac */
395 	uint32_t ps2_tvdac_adj;
396 	uint32_t ntsc_tvdac_adj;
397 	uint32_t pal_tvdac_adj;
398 
399 	int               h_pos;
400 	int               v_pos;
401 	int               h_size;
402 	int               supported_tv_stds;
403 	bool              tv_on;
404 	enum radeon_tv_std tv_std;
405 	struct radeon_tv_regs tv;
406 };
407 
408 struct radeon_encoder_int_tmds {
409 	/* legacy int tmds */
410 	struct radeon_tmds_pll tmds_pll[4];
411 };
412 
413 struct radeon_encoder_ext_tmds {
414 	/* tmds over dvo */
415 	struct radeon_i2c_chan *i2c_bus;
416 	uint8_t slave_addr;
417 	enum radeon_dvo_chip dvo_chip;
418 };
419 
420 /* spread spectrum */
421 struct radeon_encoder_atom_dig {
422 	bool linkb;
423 	/* atom dig */
424 	bool coherent_mode;
425 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
426 	/* atom lvds/edp */
427 	uint32_t lcd_misc;
428 	uint16_t panel_pwr_delay;
429 	uint32_t lcd_ss_id;
430 	/* panel mode */
431 	struct drm_display_mode native_mode;
432 	struct backlight_device *bl_dev;
433 	int dpms_mode;
434 	uint8_t backlight_level;
435 	int panel_mode;
436 	struct radeon_afmt *afmt;
437 	struct r600_audio_pin *pin;
438 };
439 
440 struct radeon_encoder_atom_dac {
441 	enum radeon_tv_std tv_std;
442 };
443 
444 struct radeon_encoder {
445 	struct drm_encoder base;
446 	uint32_t encoder_enum;
447 	uint32_t encoder_id;
448 	uint32_t devices;
449 	uint32_t active_device;
450 	uint32_t flags;
451 	uint32_t pixel_clock;
452 	enum radeon_rmx_type rmx_type;
453 	enum radeon_underscan_type underscan_type;
454 	uint32_t underscan_hborder;
455 	uint32_t underscan_vborder;
456 	struct drm_display_mode native_mode;
457 	void *enc_priv;
458 	int audio_polling_active;
459 	bool is_ext_encoder;
460 	u16 caps;
461 	struct radeon_audio_funcs *audio;
462 	enum radeon_output_csc output_csc;
463 	bool can_mst;
464 	uint32_t offset;
465 };
466 
467 struct radeon_connector_atom_dig {
468 	uint32_t igp_lane_info;
469 	/* displayport */
470 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
471 	u8 dp_sink_type;
472 	int dp_clock;
473 	int dp_lane_count;
474 	bool edp_on;
475 };
476 
477 struct radeon_gpio_rec {
478 	bool valid;
479 	u8 id;
480 	u32 reg;
481 	u32 mask;
482 	u32 shift;
483 };
484 
485 struct radeon_hpd {
486 	enum radeon_hpd_id hpd;
487 	u8 plugged_state;
488 	struct radeon_gpio_rec gpio;
489 };
490 
491 struct radeon_router {
492 	u32 router_id;
493 	struct radeon_i2c_bus_rec i2c_info;
494 	u8 i2c_addr;
495 	/* i2c mux */
496 	bool ddc_valid;
497 	u8 ddc_mux_type;
498 	u8 ddc_mux_control_pin;
499 	u8 ddc_mux_state;
500 	/* clock/data mux */
501 	bool cd_valid;
502 	u8 cd_mux_type;
503 	u8 cd_mux_control_pin;
504 	u8 cd_mux_state;
505 };
506 
507 enum radeon_connector_audio {
508 	RADEON_AUDIO_DISABLE = 0,
509 	RADEON_AUDIO_ENABLE = 1,
510 	RADEON_AUDIO_AUTO = 2
511 };
512 
513 enum radeon_connector_dither {
514 	RADEON_FMT_DITHER_DISABLE = 0,
515 	RADEON_FMT_DITHER_ENABLE = 1,
516 };
517 
518 struct radeon_connector {
519 	struct drm_connector base;
520 	uint32_t connector_id;
521 	uint32_t devices;
522 	struct radeon_i2c_chan *ddc_bus;
523 	/* some systems have an hdmi and vga port with a shared ddc line */
524 	bool shared_ddc;
525 	bool use_digital;
526 	/* we need to mind the EDID between detect
527 	   and get modes due to analog/digital/tvencoder */
528 	struct edid *edid;
529 	void *con_priv;
530 	bool dac_load_detect;
531 	bool detected_by_load; /* if the connection status was determined by load */
532 	bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
533 	uint16_t connector_object_id;
534 	struct radeon_hpd hpd;
535 	struct radeon_router router;
536 	struct radeon_i2c_chan *router_bus;
537 	enum radeon_connector_audio audio;
538 	enum radeon_connector_dither dither;
539 	int pixelclock_for_modeset;
540 };
541 
542 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
543 				((em) == ATOM_ENCODER_MODE_DP_MST))
544 
545 struct atom_clock_dividers {
546 	u32 post_div;
547 	union {
548 		struct {
549 #ifdef __BIG_ENDIAN
550 			u32 reserved : 6;
551 			u32 whole_fb_div : 12;
552 			u32 frac_fb_div : 14;
553 #else
554 			u32 frac_fb_div : 14;
555 			u32 whole_fb_div : 12;
556 			u32 reserved : 6;
557 #endif
558 		};
559 		u32 fb_div;
560 	};
561 	u32 ref_div;
562 	bool enable_post_div;
563 	bool enable_dithen;
564 	u32 vco_mode;
565 	u32 real_clock;
566 	/* added for CI */
567 	u32 post_divider;
568 	u32 flags;
569 };
570 
571 struct atom_mpll_param {
572 	union {
573 		struct {
574 #ifdef __BIG_ENDIAN
575 			u32 reserved : 8;
576 			u32 clkfrac : 12;
577 			u32 clkf : 12;
578 #else
579 			u32 clkf : 12;
580 			u32 clkfrac : 12;
581 			u32 reserved : 8;
582 #endif
583 		};
584 		u32 fb_div;
585 	};
586 	u32 post_div;
587 	u32 bwcntl;
588 	u32 dll_speed;
589 	u32 vco_mode;
590 	u32 yclk_sel;
591 	u32 qdr;
592 	u32 half_rate;
593 };
594 
595 #define MEM_TYPE_GDDR5  0x50
596 #define MEM_TYPE_GDDR4  0x40
597 #define MEM_TYPE_GDDR3  0x30
598 #define MEM_TYPE_DDR2   0x20
599 #define MEM_TYPE_GDDR1  0x10
600 #define MEM_TYPE_DDR3   0xb0
601 #define MEM_TYPE_MASK   0xf0
602 
603 struct atom_memory_info {
604 	u8 mem_vendor;
605 	u8 mem_type;
606 };
607 
608 #define MAX_AC_TIMING_ENTRIES 16
609 
610 struct atom_memory_clock_range_table
611 {
612 	u8 num_entries;
613 	u8 rsv[3];
614 	u32 mclk[MAX_AC_TIMING_ENTRIES];
615 };
616 
617 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
618 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
619 
620 struct atom_mc_reg_entry {
621 	u32 mclk_max;
622 	u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
623 };
624 
625 struct atom_mc_register_address {
626 	u16 s1;
627 	u8 pre_reg_data;
628 };
629 
630 struct atom_mc_reg_table {
631 	u8 last;
632 	u8 num_entries;
633 	struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
634 	struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
635 };
636 
637 #define MAX_VOLTAGE_ENTRIES 32
638 
639 struct atom_voltage_table_entry
640 {
641 	u16 value;
642 	u32 smio_low;
643 };
644 
645 struct atom_voltage_table
646 {
647 	u32 count;
648 	u32 mask_low;
649 	u32 phase_delay;
650 	struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
651 };
652 
653 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
654 #define DRM_SCANOUTPOS_VALID        (1 << 0)
655 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
656 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
657 #define USE_REAL_VBLANKSTART 		(1 << 30)
658 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
659 
660 extern void
661 radeon_add_atom_connector(struct drm_device *dev,
662 			  uint32_t connector_id,
663 			  uint32_t supported_device,
664 			  int connector_type,
665 			  struct radeon_i2c_bus_rec *i2c_bus,
666 			  uint32_t igp_lane_info,
667 			  uint16_t connector_object_id,
668 			  struct radeon_hpd *hpd,
669 			  struct radeon_router *router);
670 extern void
671 radeon_add_legacy_connector(struct drm_device *dev,
672 			    uint32_t connector_id,
673 			    uint32_t supported_device,
674 			    int connector_type,
675 			    struct radeon_i2c_bus_rec *i2c_bus,
676 			    uint16_t connector_object_id,
677 			    struct radeon_hpd *hpd);
678 extern uint32_t
679 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
680 			uint8_t dac);
681 extern void radeon_link_encoder_connector(struct drm_device *dev);
682 
683 extern enum radeon_tv_std
684 radeon_combios_get_tv_info(struct radeon_device *rdev);
685 extern enum radeon_tv_std
686 radeon_atombios_get_tv_info(struct radeon_device *rdev);
687 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
688 						 u16 *vddc, u16 *vddci, u16 *mvdd);
689 
690 extern void
691 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
692 				      struct drm_encoder *encoder,
693 				      bool connected);
694 extern void
695 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
696 				       struct drm_encoder *encoder,
697 				       bool connected);
698 
699 extern struct drm_connector *
700 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
701 extern struct drm_connector *
702 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
703 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
704 				    u32 pixel_clock);
705 
706 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
707 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
708 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
709 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
710 
711 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
712 
713 extern void radeon_connector_hotplug(struct drm_connector *connector);
714 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
715 				       struct drm_display_mode *mode);
716 extern void radeon_dp_set_link_config(struct drm_connector *connector,
717 				      const struct drm_display_mode *mode);
718 extern void radeon_dp_link_train(struct drm_encoder *encoder,
719 				 struct drm_connector *connector);
720 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
721 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
722 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
723 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
724 				    struct drm_connector *connector);
725 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
726 					 u8 power_state);
727 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
728 extern ssize_t
729 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
730 
731 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
732 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
733 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
734 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
735 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
736 					   int action, uint8_t lane_num,
737 					   uint8_t lane_set);
738 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
739 					    int action, uint8_t lane_num,
740 					    uint8_t lane_set, int fe);
741 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
742 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
743 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
744 
745 extern void radeon_i2c_init(struct radeon_device *rdev);
746 extern void radeon_i2c_fini(struct radeon_device *rdev);
747 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
748 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
749 extern void radeon_i2c_add(struct radeon_device *rdev,
750 			   struct radeon_i2c_bus_rec *rec,
751 			   const char *name);
752 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
753 						 struct radeon_i2c_bus_rec *i2c_bus);
754 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
755 						 struct radeon_i2c_bus_rec *rec,
756 						 const char *name);
757 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
758 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
759 				u8 slave_addr,
760 				u8 addr,
761 				u8 *val);
762 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
763 				u8 slave_addr,
764 				u8 addr,
765 				u8 val);
766 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
767 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
768 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
769 
770 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
771 					     struct radeon_atom_ss *ss,
772 					     int id);
773 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
774 					     struct radeon_atom_ss *ss,
775 					     int id, u32 clock);
776 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
777 							  u8 id);
778 
779 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
780 				      uint64_t freq,
781 				      uint32_t *dot_clock_p,
782 				      uint32_t *fb_div_p,
783 				      uint32_t *frac_fb_div_p,
784 				      uint32_t *ref_div_p,
785 				      uint32_t *post_div_p);
786 
787 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
788 				     u32 freq,
789 				     u32 *dot_clock_p,
790 				     u32 *fb_div_p,
791 				     u32 *frac_fb_div_p,
792 				     u32 *ref_div_p,
793 				     u32 *post_div_p);
794 
795 extern void radeon_setup_encoder_clones(struct drm_device *dev);
796 
797 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
798 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
799 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
800 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
801 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
802 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
803 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
804 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
805 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
806 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
807 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
808 
809 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
810 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
811 				   struct drm_framebuffer *old_fb);
812 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
813 					 struct drm_framebuffer *fb,
814 					 int x, int y,
815 					 enum mode_set_atomic state);
816 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
817 				   struct drm_display_mode *mode,
818 				   struct drm_display_mode *adjusted_mode,
819 				   int x, int y,
820 				   struct drm_framebuffer *old_fb);
821 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
822 
823 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
824 				 struct drm_framebuffer *old_fb);
825 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
826 				       struct drm_framebuffer *fb,
827 				       int x, int y,
828 				       enum mode_set_atomic state);
829 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
830 				   struct drm_framebuffer *fb,
831 				   int x, int y, int atomic);
832 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
833 				   struct drm_file *file_priv,
834 				   uint32_t handle,
835 				   uint32_t width,
836 				   uint32_t height,
837 				   int32_t hot_x,
838 				   int32_t hot_y);
839 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
840 				   int x, int y);
841 extern void radeon_cursor_reset(struct drm_crtc *crtc);
842 
843 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
844 				      unsigned int flags, int *vpos, int *hpos,
845 				      ktime_t *stime, ktime_t *etime,
846 				      const struct drm_display_mode *mode);
847 
848 extern bool
849 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
850 				 int *vpos, int *hpos,
851 				 ktime_t *stime, ktime_t *etime,
852 				 const struct drm_display_mode *mode);
853 
854 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
855 extern struct edid *
856 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
857 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
858 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
859 extern struct radeon_encoder_atom_dig *
860 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
861 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
862 					  struct radeon_encoder_int_tmds *tmds);
863 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
864 						     struct radeon_encoder_int_tmds *tmds);
865 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
866 						   struct radeon_encoder_int_tmds *tmds);
867 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
868 							 struct radeon_encoder_ext_tmds *tmds);
869 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
870 						       struct radeon_encoder_ext_tmds *tmds);
871 extern struct radeon_encoder_primary_dac *
872 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
873 extern struct radeon_encoder_tv_dac *
874 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
875 extern struct radeon_encoder_lvds *
876 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
877 extern struct radeon_encoder_tv_dac *
878 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
879 extern struct radeon_encoder_primary_dac *
880 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
881 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
882 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
883 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
884 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
885 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
886 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
887 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
888 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
889 extern void
890 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
891 extern void
892 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
893 extern void
894 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
895 extern void
896 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
897 int radeon_framebuffer_init(struct drm_device *dev,
898 			     struct drm_framebuffer *rfb,
899 			     const struct drm_mode_fb_cmd2 *mode_cmd,
900 			     struct drm_gem_object *obj);
901 
902 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
903 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
904 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
905 void radeon_atombios_init_crtc(struct drm_device *dev,
906 			       struct radeon_crtc *radeon_crtc);
907 void radeon_legacy_init_crtc(struct drm_device *dev,
908 			     struct radeon_crtc *radeon_crtc);
909 
910 void radeon_get_clock_info(struct drm_device *dev);
911 
912 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
913 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
914 
915 void radeon_enc_destroy(struct drm_encoder *encoder);
916 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
917 void radeon_combios_asic_init(struct drm_device *dev);
918 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
919 					const struct drm_display_mode *mode,
920 					struct drm_display_mode *adjusted_mode);
921 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
922 			     struct drm_display_mode *adjusted_mode);
923 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
924 
925 /* legacy tv */
926 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
927 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
928 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
929 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
930 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
931 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
932 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
933 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
934 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
935 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
936 			       struct drm_display_mode *mode,
937 			       struct drm_display_mode *adjusted_mode);
938 
939 /* fmt blocks */
940 void avivo_program_fmt(struct drm_encoder *encoder);
941 void dce3_program_fmt(struct drm_encoder *encoder);
942 void dce4_program_fmt(struct drm_encoder *encoder);
943 void dce8_program_fmt(struct drm_encoder *encoder);
944 
945 /* fbdev layer */
946 int radeon_fbdev_init(struct radeon_device *rdev);
947 void radeon_fbdev_fini(struct radeon_device *rdev);
948 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
949 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
950 
951 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
952 
953 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
954 
955 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
956 
957 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
958 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
959 #endif
960