1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/display/drm_dp_mst_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_fixed.h> 39 #include <drm/drm_crtc_helper.h> 40 #include <linux/i2c.h> 41 #include <linux/i2c-algo-bit.h> 42 43 struct radeon_bo; 44 struct radeon_device; 45 46 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 47 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 48 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 49 50 #define RADEON_MAX_HPD_PINS 7 51 #define RADEON_MAX_CRTCS 6 52 #define RADEON_MAX_AFMT_BLOCKS 7 53 54 enum radeon_rmx_type { 55 RMX_OFF, 56 RMX_FULL, 57 RMX_CENTER, 58 RMX_ASPECT 59 }; 60 61 enum radeon_tv_std { 62 TV_STD_NTSC, 63 TV_STD_PAL, 64 TV_STD_PAL_M, 65 TV_STD_PAL_60, 66 TV_STD_NTSC_J, 67 TV_STD_SCART_PAL, 68 TV_STD_SECAM, 69 TV_STD_PAL_CN, 70 TV_STD_PAL_N, 71 }; 72 73 enum radeon_underscan_type { 74 UNDERSCAN_OFF, 75 UNDERSCAN_ON, 76 UNDERSCAN_AUTO, 77 }; 78 79 enum radeon_hpd_id { 80 RADEON_HPD_1 = 0, 81 RADEON_HPD_2, 82 RADEON_HPD_3, 83 RADEON_HPD_4, 84 RADEON_HPD_5, 85 RADEON_HPD_6, 86 RADEON_HPD_NONE = 0xff, 87 }; 88 89 enum radeon_output_csc { 90 RADEON_OUTPUT_CSC_BYPASS = 0, 91 RADEON_OUTPUT_CSC_TVRGB = 1, 92 RADEON_OUTPUT_CSC_YCBCR601 = 2, 93 RADEON_OUTPUT_CSC_YCBCR709 = 3, 94 }; 95 96 #define RADEON_MAX_I2C_BUS 16 97 98 /* radeon gpio-based i2c 99 * 1. "mask" reg and bits 100 * grabs the gpio pins for software use 101 * 0=not held 1=held 102 * 2. "a" reg and bits 103 * output pin value 104 * 0=low 1=high 105 * 3. "en" reg and bits 106 * sets the pin direction 107 * 0=input 1=output 108 * 4. "y" reg and bits 109 * input pin value 110 * 0=low 1=high 111 */ 112 struct radeon_i2c_bus_rec { 113 bool valid; 114 /* id used by atom */ 115 uint8_t i2c_id; 116 /* id used by atom */ 117 enum radeon_hpd_id hpd; 118 /* can be used with hw i2c engine */ 119 bool hw_capable; 120 /* uses multi-media i2c engine */ 121 bool mm_i2c; 122 /* regs and bits */ 123 uint32_t mask_clk_reg; 124 uint32_t mask_data_reg; 125 uint32_t a_clk_reg; 126 uint32_t a_data_reg; 127 uint32_t en_clk_reg; 128 uint32_t en_data_reg; 129 uint32_t y_clk_reg; 130 uint32_t y_data_reg; 131 uint32_t mask_clk_mask; 132 uint32_t mask_data_mask; 133 uint32_t a_clk_mask; 134 uint32_t a_data_mask; 135 uint32_t en_clk_mask; 136 uint32_t en_data_mask; 137 uint32_t y_clk_mask; 138 uint32_t y_data_mask; 139 }; 140 141 struct radeon_tmds_pll { 142 uint32_t freq; 143 uint32_t value; 144 }; 145 146 #define RADEON_MAX_BIOS_CONNECTOR 16 147 148 /* pll flags */ 149 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 150 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 151 #define RADEON_PLL_USE_REF_DIV (1 << 2) 152 #define RADEON_PLL_LEGACY (1 << 3) 153 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 154 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 155 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 156 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 157 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 159 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 161 #define RADEON_PLL_USE_POST_DIV (1 << 12) 162 #define RADEON_PLL_IS_LCD (1 << 13) 163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 164 165 struct radeon_pll { 166 /* reference frequency */ 167 uint32_t reference_freq; 168 169 /* fixed dividers */ 170 uint32_t reference_div; 171 uint32_t post_div; 172 173 /* pll in/out limits */ 174 uint32_t pll_in_min; 175 uint32_t pll_in_max; 176 uint32_t pll_out_min; 177 uint32_t pll_out_max; 178 uint32_t lcd_pll_out_min; 179 uint32_t lcd_pll_out_max; 180 uint32_t best_vco; 181 182 /* divider limits */ 183 uint32_t min_ref_div; 184 uint32_t max_ref_div; 185 uint32_t min_post_div; 186 uint32_t max_post_div; 187 uint32_t min_feedback_div; 188 uint32_t max_feedback_div; 189 uint32_t min_frac_feedback_div; 190 uint32_t max_frac_feedback_div; 191 192 /* flags for the current clock */ 193 uint32_t flags; 194 195 /* pll id */ 196 uint32_t id; 197 }; 198 199 struct radeon_i2c_chan { 200 struct i2c_adapter adapter; 201 struct drm_device *dev; 202 struct i2c_algo_bit_data bit; 203 struct radeon_i2c_bus_rec rec; 204 struct drm_dp_aux aux; 205 bool has_aux; 206 struct mutex mutex; 207 }; 208 209 /* mostly for macs, but really any system without connector tables */ 210 enum radeon_connector_table { 211 CT_NONE = 0, 212 CT_GENERIC, 213 CT_IBOOK, 214 CT_POWERBOOK_EXTERNAL, 215 CT_POWERBOOK_INTERNAL, 216 CT_POWERBOOK_VGA, 217 CT_MINI_EXTERNAL, 218 CT_MINI_INTERNAL, 219 CT_IMAC_G5_ISIGHT, 220 CT_EMAC, 221 CT_RN50_POWER, 222 CT_MAC_X800, 223 CT_MAC_G5_9600, 224 CT_SAM440EP, 225 CT_MAC_G4_SILVER 226 }; 227 228 enum radeon_dvo_chip { 229 DVO_SIL164, 230 DVO_SIL1178, 231 }; 232 233 struct radeon_fbdev; 234 235 struct radeon_afmt { 236 bool enabled; 237 int offset; 238 bool last_buffer_filled_status; 239 int id; 240 }; 241 242 struct radeon_mode_info { 243 struct atom_context *atom_context; 244 struct card_info *atom_card_info; 245 enum radeon_connector_table connector_table; 246 bool mode_config_initialized; 247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 248 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 249 /* DVI-I properties */ 250 struct drm_property *coherent_mode_property; 251 /* DAC enable load detect */ 252 struct drm_property *load_detect_property; 253 /* TV standard */ 254 struct drm_property *tv_std_property; 255 /* legacy TMDS PLL detect */ 256 struct drm_property *tmds_pll_property; 257 /* underscan */ 258 struct drm_property *underscan_property; 259 struct drm_property *underscan_hborder_property; 260 struct drm_property *underscan_vborder_property; 261 /* audio */ 262 struct drm_property *audio_property; 263 /* FMT dithering */ 264 struct drm_property *dither_property; 265 /* Output CSC */ 266 struct drm_property *output_csc_property; 267 /* hardcoded DFP edid from BIOS */ 268 struct edid *bios_hardcoded_edid; 269 int bios_hardcoded_edid_size; 270 271 /* pointer to fbdev info structure */ 272 struct radeon_fbdev *rfbdev; 273 /* firmware flags */ 274 u16 firmware_flags; 275 /* pointer to backlight encoder */ 276 struct radeon_encoder *bl_encoder; 277 278 /* bitmask for active encoder frontends */ 279 uint32_t active_encoders; 280 }; 281 282 #define RADEON_MAX_BL_LEVEL 0xFF 283 284 struct radeon_backlight_privdata { 285 struct radeon_encoder *encoder; 286 uint8_t negative; 287 }; 288 289 #define MAX_H_CODE_TIMING_LEN 32 290 #define MAX_V_CODE_TIMING_LEN 32 291 292 /* need to store these as reading 293 back code tables is excessive */ 294 struct radeon_tv_regs { 295 uint32_t tv_uv_adr; 296 uint32_t timing_cntl; 297 uint32_t hrestart; 298 uint32_t vrestart; 299 uint32_t frestart; 300 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 301 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 302 }; 303 304 struct radeon_atom_ss { 305 uint16_t percentage; 306 uint16_t percentage_divider; 307 uint8_t type; 308 uint16_t step; 309 uint8_t delay; 310 uint8_t range; 311 uint8_t refdiv; 312 /* asic_ss */ 313 uint16_t rate; 314 uint16_t amount; 315 }; 316 317 enum radeon_flip_status { 318 RADEON_FLIP_NONE, 319 RADEON_FLIP_PENDING, 320 RADEON_FLIP_SUBMITTED 321 }; 322 323 struct radeon_crtc { 324 struct drm_crtc base; 325 int crtc_id; 326 bool enabled; 327 bool can_tile; 328 bool cursor_out_of_bounds; 329 uint32_t crtc_offset; 330 struct drm_gem_object *cursor_bo; 331 uint64_t cursor_addr; 332 int cursor_x; 333 int cursor_y; 334 int cursor_hot_x; 335 int cursor_hot_y; 336 int cursor_width; 337 int cursor_height; 338 int max_cursor_width; 339 int max_cursor_height; 340 uint32_t legacy_display_base_addr; 341 enum radeon_rmx_type rmx_type; 342 u8 h_border; 343 u8 v_border; 344 fixed20_12 vsc; 345 fixed20_12 hsc; 346 struct drm_display_mode native_mode; 347 int pll_id; 348 /* page flipping */ 349 struct workqueue_struct *flip_queue; 350 struct radeon_flip_work *flip_work; 351 enum radeon_flip_status flip_status; 352 /* pll sharing */ 353 struct radeon_atom_ss ss; 354 bool ss_enabled; 355 u32 adjusted_clock; 356 int bpc; 357 u32 pll_reference_div; 358 u32 pll_post_div; 359 u32 pll_flags; 360 struct drm_encoder *encoder; 361 struct drm_connector *connector; 362 /* for dpm */ 363 u32 line_time; 364 u32 wm_low; 365 u32 wm_high; 366 u32 lb_vblank_lead_lines; 367 struct drm_display_mode hw_mode; 368 enum radeon_output_csc output_csc; 369 }; 370 371 struct radeon_encoder_primary_dac { 372 /* legacy primary dac */ 373 uint32_t ps2_pdac_adj; 374 }; 375 376 struct radeon_encoder_lvds { 377 /* legacy lvds */ 378 uint16_t panel_vcc_delay; 379 uint8_t panel_pwr_delay; 380 uint8_t panel_digon_delay; 381 uint8_t panel_blon_delay; 382 uint16_t panel_ref_divider; 383 uint8_t panel_post_divider; 384 uint16_t panel_fb_divider; 385 bool use_bios_dividers; 386 uint32_t lvds_gen_cntl; 387 /* panel mode */ 388 struct drm_display_mode native_mode; 389 struct backlight_device *bl_dev; 390 int dpms_mode; 391 uint8_t backlight_level; 392 }; 393 394 struct radeon_encoder_tv_dac { 395 /* legacy tv dac */ 396 uint32_t ps2_tvdac_adj; 397 uint32_t ntsc_tvdac_adj; 398 uint32_t pal_tvdac_adj; 399 400 int h_pos; 401 int v_pos; 402 int h_size; 403 int supported_tv_stds; 404 bool tv_on; 405 enum radeon_tv_std tv_std; 406 struct radeon_tv_regs tv; 407 }; 408 409 struct radeon_encoder_int_tmds { 410 /* legacy int tmds */ 411 struct radeon_tmds_pll tmds_pll[4]; 412 }; 413 414 struct radeon_encoder_ext_tmds { 415 /* tmds over dvo */ 416 struct radeon_i2c_chan *i2c_bus; 417 uint8_t slave_addr; 418 enum radeon_dvo_chip dvo_chip; 419 }; 420 421 /* spread spectrum */ 422 struct radeon_encoder_atom_dig { 423 bool linkb; 424 /* atom dig */ 425 bool coherent_mode; 426 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 427 /* atom lvds/edp */ 428 uint32_t lcd_misc; 429 uint16_t panel_pwr_delay; 430 uint32_t lcd_ss_id; 431 /* panel mode */ 432 struct drm_display_mode native_mode; 433 struct backlight_device *bl_dev; 434 int dpms_mode; 435 uint8_t backlight_level; 436 int panel_mode; 437 struct radeon_afmt *afmt; 438 struct r600_audio_pin *pin; 439 int active_mst_links; 440 }; 441 442 struct radeon_encoder_atom_dac { 443 enum radeon_tv_std tv_std; 444 }; 445 446 struct radeon_encoder_mst { 447 int crtc; 448 struct radeon_encoder *primary; 449 struct radeon_connector *connector; 450 struct drm_dp_mst_port *port; 451 int pbn; 452 int fe; 453 bool fe_from_be; 454 bool enc_active; 455 }; 456 457 struct radeon_encoder { 458 struct drm_encoder base; 459 uint32_t encoder_enum; 460 uint32_t encoder_id; 461 uint32_t devices; 462 uint32_t active_device; 463 uint32_t flags; 464 uint32_t pixel_clock; 465 enum radeon_rmx_type rmx_type; 466 enum radeon_underscan_type underscan_type; 467 uint32_t underscan_hborder; 468 uint32_t underscan_vborder; 469 struct drm_display_mode native_mode; 470 void *enc_priv; 471 int audio_polling_active; 472 bool is_ext_encoder; 473 u16 caps; 474 struct radeon_audio_funcs *audio; 475 enum radeon_output_csc output_csc; 476 bool can_mst; 477 uint32_t offset; 478 bool is_mst_encoder; 479 /* front end for this mst encoder */ 480 }; 481 482 struct radeon_connector_atom_dig { 483 uint32_t igp_lane_info; 484 /* displayport */ 485 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 486 u8 dp_sink_type; 487 int dp_clock; 488 int dp_lane_count; 489 bool edp_on; 490 bool is_mst; 491 }; 492 493 struct radeon_gpio_rec { 494 bool valid; 495 u8 id; 496 u32 reg; 497 u32 mask; 498 u32 shift; 499 }; 500 501 struct radeon_hpd { 502 enum radeon_hpd_id hpd; 503 u8 plugged_state; 504 struct radeon_gpio_rec gpio; 505 }; 506 507 struct radeon_router { 508 u32 router_id; 509 struct radeon_i2c_bus_rec i2c_info; 510 u8 i2c_addr; 511 /* i2c mux */ 512 bool ddc_valid; 513 u8 ddc_mux_type; 514 u8 ddc_mux_control_pin; 515 u8 ddc_mux_state; 516 /* clock/data mux */ 517 bool cd_valid; 518 u8 cd_mux_type; 519 u8 cd_mux_control_pin; 520 u8 cd_mux_state; 521 }; 522 523 enum radeon_connector_audio { 524 RADEON_AUDIO_DISABLE = 0, 525 RADEON_AUDIO_ENABLE = 1, 526 RADEON_AUDIO_AUTO = 2 527 }; 528 529 enum radeon_connector_dither { 530 RADEON_FMT_DITHER_DISABLE = 0, 531 RADEON_FMT_DITHER_ENABLE = 1, 532 }; 533 534 struct stream_attribs { 535 uint16_t fe; 536 uint16_t slots; 537 }; 538 539 struct radeon_connector { 540 struct drm_connector base; 541 uint32_t connector_id; 542 uint32_t devices; 543 struct radeon_i2c_chan *ddc_bus; 544 /* some systems have an hdmi and vga port with a shared ddc line */ 545 bool shared_ddc; 546 bool use_digital; 547 /* we need to mind the EDID between detect 548 and get modes due to analog/digital/tvencoder */ 549 struct edid *edid; 550 void *con_priv; 551 bool dac_load_detect; 552 bool detected_by_load; /* if the connection status was determined by load */ 553 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 554 uint16_t connector_object_id; 555 struct radeon_hpd hpd; 556 struct radeon_router router; 557 struct radeon_i2c_chan *router_bus; 558 enum radeon_connector_audio audio; 559 enum radeon_connector_dither dither; 560 int pixelclock_for_modeset; 561 bool is_mst_connector; 562 struct radeon_connector *mst_port; 563 struct drm_dp_mst_port *port; 564 struct drm_dp_mst_topology_mgr mst_mgr; 565 566 struct radeon_encoder *mst_encoder; 567 struct stream_attribs cur_stream_attribs[6]; 568 int enabled_attribs; 569 }; 570 571 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 572 ((em) == ATOM_ENCODER_MODE_DP_MST)) 573 574 struct atom_clock_dividers { 575 u32 post_div; 576 union { 577 struct { 578 #ifdef __BIG_ENDIAN 579 u32 reserved : 6; 580 u32 whole_fb_div : 12; 581 u32 frac_fb_div : 14; 582 #else 583 u32 frac_fb_div : 14; 584 u32 whole_fb_div : 12; 585 u32 reserved : 6; 586 #endif 587 }; 588 u32 fb_div; 589 }; 590 u32 ref_div; 591 bool enable_post_div; 592 bool enable_dithen; 593 u32 vco_mode; 594 u32 real_clock; 595 /* added for CI */ 596 u32 post_divider; 597 u32 flags; 598 }; 599 600 struct atom_mpll_param { 601 union { 602 struct { 603 #ifdef __BIG_ENDIAN 604 u32 reserved : 8; 605 u32 clkfrac : 12; 606 u32 clkf : 12; 607 #else 608 u32 clkf : 12; 609 u32 clkfrac : 12; 610 u32 reserved : 8; 611 #endif 612 }; 613 u32 fb_div; 614 }; 615 u32 post_div; 616 u32 bwcntl; 617 u32 dll_speed; 618 u32 vco_mode; 619 u32 yclk_sel; 620 u32 qdr; 621 u32 half_rate; 622 }; 623 624 #define MEM_TYPE_GDDR5 0x50 625 #define MEM_TYPE_GDDR4 0x40 626 #define MEM_TYPE_GDDR3 0x30 627 #define MEM_TYPE_DDR2 0x20 628 #define MEM_TYPE_GDDR1 0x10 629 #define MEM_TYPE_DDR3 0xb0 630 #define MEM_TYPE_MASK 0xf0 631 632 struct atom_memory_info { 633 u8 mem_vendor; 634 u8 mem_type; 635 }; 636 637 #define MAX_AC_TIMING_ENTRIES 16 638 639 struct atom_memory_clock_range_table 640 { 641 u8 num_entries; 642 u8 rsv[3]; 643 u32 mclk[MAX_AC_TIMING_ENTRIES]; 644 }; 645 646 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 647 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 648 649 struct atom_mc_reg_entry { 650 u32 mclk_max; 651 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 652 }; 653 654 struct atom_mc_register_address { 655 u16 s1; 656 u8 pre_reg_data; 657 }; 658 659 struct atom_mc_reg_table { 660 u8 last; 661 u8 num_entries; 662 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 663 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 664 }; 665 666 #define MAX_VOLTAGE_ENTRIES 32 667 668 struct atom_voltage_table_entry 669 { 670 u16 value; 671 u32 smio_low; 672 }; 673 674 struct atom_voltage_table 675 { 676 u32 count; 677 u32 mask_low; 678 u32 phase_delay; 679 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 680 }; 681 682 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 683 #define DRM_SCANOUTPOS_VALID (1 << 0) 684 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 685 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 686 #define USE_REAL_VBLANKSTART (1 << 30) 687 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 688 689 extern void 690 radeon_add_atom_connector(struct drm_device *dev, 691 uint32_t connector_id, 692 uint32_t supported_device, 693 int connector_type, 694 struct radeon_i2c_bus_rec *i2c_bus, 695 uint32_t igp_lane_info, 696 uint16_t connector_object_id, 697 struct radeon_hpd *hpd, 698 struct radeon_router *router); 699 extern void 700 radeon_add_legacy_connector(struct drm_device *dev, 701 uint32_t connector_id, 702 uint32_t supported_device, 703 int connector_type, 704 struct radeon_i2c_bus_rec *i2c_bus, 705 uint16_t connector_object_id, 706 struct radeon_hpd *hpd); 707 extern uint32_t 708 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 709 uint8_t dac); 710 extern void radeon_link_encoder_connector(struct drm_device *dev); 711 712 extern enum radeon_tv_std 713 radeon_combios_get_tv_info(struct radeon_device *rdev); 714 extern enum radeon_tv_std 715 radeon_atombios_get_tv_info(struct radeon_device *rdev); 716 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 717 u16 *vddc, u16 *vddci, u16 *mvdd); 718 719 extern void 720 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 721 struct drm_encoder *encoder, 722 bool connected); 723 extern void 724 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 725 struct drm_encoder *encoder, 726 bool connected); 727 728 extern struct drm_connector * 729 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 730 extern struct drm_connector * 731 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 732 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 733 u32 pixel_clock); 734 735 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 736 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 737 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 738 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 739 740 extern struct edid *radeon_connector_edid(struct drm_connector *connector); 741 742 extern void radeon_connector_hotplug(struct drm_connector *connector); 743 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 744 struct drm_display_mode *mode); 745 extern void radeon_dp_set_link_config(struct drm_connector *connector, 746 const struct drm_display_mode *mode); 747 extern void radeon_dp_link_train(struct drm_encoder *encoder, 748 struct drm_connector *connector); 749 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 750 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 751 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 752 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 753 struct drm_connector *connector); 754 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 755 u8 power_state); 756 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 757 extern ssize_t 758 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 759 760 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 761 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 762 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 763 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 764 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 765 int action, uint8_t lane_num, 766 uint8_t lane_set); 767 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 768 int action, uint8_t lane_num, 769 uint8_t lane_set, int fe); 770 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 771 int fe); 772 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 773 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 774 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 775 776 extern void radeon_i2c_init(struct radeon_device *rdev); 777 extern void radeon_i2c_fini(struct radeon_device *rdev); 778 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 779 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 780 extern void radeon_i2c_add(struct radeon_device *rdev, 781 struct radeon_i2c_bus_rec *rec, 782 const char *name); 783 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 784 struct radeon_i2c_bus_rec *i2c_bus); 785 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 786 struct radeon_i2c_bus_rec *rec, 787 const char *name); 788 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 789 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 790 u8 slave_addr, 791 u8 addr, 792 u8 *val); 793 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 794 u8 slave_addr, 795 u8 addr, 796 u8 val); 797 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 798 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 799 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 800 801 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 802 struct radeon_atom_ss *ss, 803 int id); 804 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 805 struct radeon_atom_ss *ss, 806 int id, u32 clock); 807 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 808 u8 id); 809 810 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 811 uint64_t freq, 812 uint32_t *dot_clock_p, 813 uint32_t *fb_div_p, 814 uint32_t *frac_fb_div_p, 815 uint32_t *ref_div_p, 816 uint32_t *post_div_p); 817 818 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 819 u32 freq, 820 u32 *dot_clock_p, 821 u32 *fb_div_p, 822 u32 *frac_fb_div_p, 823 u32 *ref_div_p, 824 u32 *post_div_p); 825 826 extern void radeon_setup_encoder_clones(struct drm_device *dev); 827 828 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 829 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 830 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 831 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 832 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 833 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 834 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 835 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 836 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 837 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 838 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 839 840 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 841 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 842 struct drm_framebuffer *old_fb); 843 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 844 struct drm_framebuffer *fb, 845 int x, int y, 846 enum mode_set_atomic state); 847 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 848 struct drm_display_mode *mode, 849 struct drm_display_mode *adjusted_mode, 850 int x, int y, 851 struct drm_framebuffer *old_fb); 852 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 853 854 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 855 struct drm_framebuffer *old_fb); 856 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 857 struct drm_framebuffer *fb, 858 int x, int y, 859 enum mode_set_atomic state); 860 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 861 struct drm_framebuffer *fb, 862 int x, int y, int atomic); 863 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 864 struct drm_file *file_priv, 865 uint32_t handle, 866 uint32_t width, 867 uint32_t height, 868 int32_t hot_x, 869 int32_t hot_y); 870 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 871 int x, int y); 872 extern void radeon_cursor_reset(struct drm_crtc *crtc); 873 874 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 875 unsigned int flags, int *vpos, int *hpos, 876 ktime_t *stime, ktime_t *etime, 877 const struct drm_display_mode *mode); 878 879 extern bool 880 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, 881 int *vpos, int *hpos, 882 ktime_t *stime, ktime_t *etime, 883 const struct drm_display_mode *mode); 884 885 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 886 extern struct edid * 887 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 888 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 889 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 890 extern struct radeon_encoder_atom_dig * 891 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 892 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 893 struct radeon_encoder_int_tmds *tmds); 894 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 895 struct radeon_encoder_int_tmds *tmds); 896 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 897 struct radeon_encoder_int_tmds *tmds); 898 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 899 struct radeon_encoder_ext_tmds *tmds); 900 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 901 struct radeon_encoder_ext_tmds *tmds); 902 extern struct radeon_encoder_primary_dac * 903 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 904 extern struct radeon_encoder_tv_dac * 905 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 906 extern struct radeon_encoder_lvds * 907 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 908 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 909 extern struct radeon_encoder_tv_dac * 910 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 911 extern struct radeon_encoder_primary_dac * 912 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 913 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 914 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 915 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 916 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 917 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 918 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 919 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 920 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 921 extern void 922 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 923 extern void 924 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 925 extern void 926 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 927 extern void 928 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 929 int radeon_framebuffer_init(struct drm_device *dev, 930 struct drm_framebuffer *rfb, 931 const struct drm_mode_fb_cmd2 *mode_cmd, 932 struct drm_gem_object *obj); 933 934 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 935 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 936 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 937 void radeon_atombios_init_crtc(struct drm_device *dev, 938 struct radeon_crtc *radeon_crtc); 939 void radeon_legacy_init_crtc(struct drm_device *dev, 940 struct radeon_crtc *radeon_crtc); 941 942 void radeon_get_clock_info(struct drm_device *dev); 943 944 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 945 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 946 947 void radeon_enc_destroy(struct drm_encoder *encoder); 948 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 949 void radeon_combios_asic_init(struct drm_device *dev); 950 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 951 const struct drm_display_mode *mode, 952 struct drm_display_mode *adjusted_mode); 953 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 954 struct drm_display_mode *adjusted_mode); 955 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 956 957 /* legacy tv */ 958 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 959 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 960 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 961 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 962 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 963 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 964 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 965 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 966 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 967 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 968 struct drm_display_mode *mode, 969 struct drm_display_mode *adjusted_mode); 970 971 /* fmt blocks */ 972 void avivo_program_fmt(struct drm_encoder *encoder); 973 void dce3_program_fmt(struct drm_encoder *encoder); 974 void dce4_program_fmt(struct drm_encoder *encoder); 975 void dce8_program_fmt(struct drm_encoder *encoder); 976 977 /* fbdev layer */ 978 int radeon_fbdev_init(struct radeon_device *rdev); 979 void radeon_fbdev_fini(struct radeon_device *rdev); 980 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 981 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 982 983 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 984 985 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 986 987 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 988 989 /* mst */ 990 int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 991 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 992 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 993 void radeon_mst_debugfs_init(struct radeon_device *rdev); 994 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 995 996 void radeon_setup_mst_connector(struct drm_device *dev); 997 998 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 999 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1000 #endif 1001