1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 struct i2c_adapter adapter; 189 struct drm_device *dev; 190 union { 191 struct i2c_algo_bit_data bit; 192 struct i2c_algo_dp_aux_data dp; 193 } algo; 194 struct radeon_i2c_bus_rec rec; 195 struct drm_dp_aux aux; 196 }; 197 198 /* mostly for macs, but really any system without connector tables */ 199 enum radeon_connector_table { 200 CT_NONE = 0, 201 CT_GENERIC, 202 CT_IBOOK, 203 CT_POWERBOOK_EXTERNAL, 204 CT_POWERBOOK_INTERNAL, 205 CT_POWERBOOK_VGA, 206 CT_MINI_EXTERNAL, 207 CT_MINI_INTERNAL, 208 CT_IMAC_G5_ISIGHT, 209 CT_EMAC, 210 CT_RN50_POWER, 211 CT_MAC_X800, 212 CT_MAC_G5_9600, 213 CT_SAM440EP, 214 CT_MAC_G4_SILVER 215 }; 216 217 enum radeon_dvo_chip { 218 DVO_SIL164, 219 DVO_SIL1178, 220 }; 221 222 struct radeon_fbdev; 223 224 struct radeon_afmt { 225 bool enabled; 226 int offset; 227 bool last_buffer_filled_status; 228 int id; 229 struct r600_audio_pin *pin; 230 }; 231 232 struct radeon_mode_info { 233 struct atom_context *atom_context; 234 struct card_info *atom_card_info; 235 enum radeon_connector_table connector_table; 236 bool mode_config_initialized; 237 struct radeon_crtc *crtcs[6]; 238 struct radeon_afmt *afmt[7]; 239 /* DVI-I properties */ 240 struct drm_property *coherent_mode_property; 241 /* DAC enable load detect */ 242 struct drm_property *load_detect_property; 243 /* TV standard */ 244 struct drm_property *tv_std_property; 245 /* legacy TMDS PLL detect */ 246 struct drm_property *tmds_pll_property; 247 /* underscan */ 248 struct drm_property *underscan_property; 249 struct drm_property *underscan_hborder_property; 250 struct drm_property *underscan_vborder_property; 251 /* audio */ 252 struct drm_property *audio_property; 253 /* FMT dithering */ 254 struct drm_property *dither_property; 255 /* hardcoded DFP edid from BIOS */ 256 struct edid *bios_hardcoded_edid; 257 int bios_hardcoded_edid_size; 258 259 /* pointer to fbdev info structure */ 260 struct radeon_fbdev *rfbdev; 261 /* firmware flags */ 262 u16 firmware_flags; 263 /* pointer to backlight encoder */ 264 struct radeon_encoder *bl_encoder; 265 }; 266 267 #define RADEON_MAX_BL_LEVEL 0xFF 268 269 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 270 271 struct radeon_backlight_privdata { 272 struct radeon_encoder *encoder; 273 uint8_t negative; 274 }; 275 276 #endif 277 278 #define MAX_H_CODE_TIMING_LEN 32 279 #define MAX_V_CODE_TIMING_LEN 32 280 281 /* need to store these as reading 282 back code tables is excessive */ 283 struct radeon_tv_regs { 284 uint32_t tv_uv_adr; 285 uint32_t timing_cntl; 286 uint32_t hrestart; 287 uint32_t vrestart; 288 uint32_t frestart; 289 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 290 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 291 }; 292 293 struct radeon_atom_ss { 294 uint16_t percentage; 295 uint16_t percentage_divider; 296 uint8_t type; 297 uint16_t step; 298 uint8_t delay; 299 uint8_t range; 300 uint8_t refdiv; 301 /* asic_ss */ 302 uint16_t rate; 303 uint16_t amount; 304 }; 305 306 struct radeon_crtc { 307 struct drm_crtc base; 308 int crtc_id; 309 u16 lut_r[256], lut_g[256], lut_b[256]; 310 bool enabled; 311 bool can_tile; 312 uint32_t crtc_offset; 313 struct drm_gem_object *cursor_bo; 314 uint64_t cursor_addr; 315 int cursor_width; 316 int cursor_height; 317 int max_cursor_width; 318 int max_cursor_height; 319 uint32_t legacy_display_base_addr; 320 uint32_t legacy_cursor_offset; 321 enum radeon_rmx_type rmx_type; 322 u8 h_border; 323 u8 v_border; 324 fixed20_12 vsc; 325 fixed20_12 hsc; 326 struct drm_display_mode native_mode; 327 int pll_id; 328 /* page flipping */ 329 struct radeon_unpin_work *unpin_work; 330 int deferred_flip_completion; 331 /* pll sharing */ 332 struct radeon_atom_ss ss; 333 bool ss_enabled; 334 u32 adjusted_clock; 335 int bpc; 336 u32 pll_reference_div; 337 u32 pll_post_div; 338 u32 pll_flags; 339 struct drm_encoder *encoder; 340 struct drm_connector *connector; 341 /* for dpm */ 342 u32 line_time; 343 u32 wm_low; 344 u32 wm_high; 345 struct drm_display_mode hw_mode; 346 }; 347 348 struct radeon_encoder_primary_dac { 349 /* legacy primary dac */ 350 uint32_t ps2_pdac_adj; 351 }; 352 353 struct radeon_encoder_lvds { 354 /* legacy lvds */ 355 uint16_t panel_vcc_delay; 356 uint8_t panel_pwr_delay; 357 uint8_t panel_digon_delay; 358 uint8_t panel_blon_delay; 359 uint16_t panel_ref_divider; 360 uint8_t panel_post_divider; 361 uint16_t panel_fb_divider; 362 bool use_bios_dividers; 363 uint32_t lvds_gen_cntl; 364 /* panel mode */ 365 struct drm_display_mode native_mode; 366 struct backlight_device *bl_dev; 367 int dpms_mode; 368 uint8_t backlight_level; 369 }; 370 371 struct radeon_encoder_tv_dac { 372 /* legacy tv dac */ 373 uint32_t ps2_tvdac_adj; 374 uint32_t ntsc_tvdac_adj; 375 uint32_t pal_tvdac_adj; 376 377 int h_pos; 378 int v_pos; 379 int h_size; 380 int supported_tv_stds; 381 bool tv_on; 382 enum radeon_tv_std tv_std; 383 struct radeon_tv_regs tv; 384 }; 385 386 struct radeon_encoder_int_tmds { 387 /* legacy int tmds */ 388 struct radeon_tmds_pll tmds_pll[4]; 389 }; 390 391 struct radeon_encoder_ext_tmds { 392 /* tmds over dvo */ 393 struct radeon_i2c_chan *i2c_bus; 394 uint8_t slave_addr; 395 enum radeon_dvo_chip dvo_chip; 396 }; 397 398 /* spread spectrum */ 399 struct radeon_encoder_atom_dig { 400 bool linkb; 401 /* atom dig */ 402 bool coherent_mode; 403 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 404 /* atom lvds/edp */ 405 uint32_t lcd_misc; 406 uint16_t panel_pwr_delay; 407 uint32_t lcd_ss_id; 408 /* panel mode */ 409 struct drm_display_mode native_mode; 410 struct backlight_device *bl_dev; 411 int dpms_mode; 412 uint8_t backlight_level; 413 int panel_mode; 414 struct radeon_afmt *afmt; 415 }; 416 417 struct radeon_encoder_atom_dac { 418 enum radeon_tv_std tv_std; 419 }; 420 421 struct radeon_encoder { 422 struct drm_encoder base; 423 uint32_t encoder_enum; 424 uint32_t encoder_id; 425 uint32_t devices; 426 uint32_t active_device; 427 uint32_t flags; 428 uint32_t pixel_clock; 429 enum radeon_rmx_type rmx_type; 430 enum radeon_underscan_type underscan_type; 431 uint32_t underscan_hborder; 432 uint32_t underscan_vborder; 433 struct drm_display_mode native_mode; 434 void *enc_priv; 435 int audio_polling_active; 436 bool is_ext_encoder; 437 u16 caps; 438 }; 439 440 struct radeon_connector_atom_dig { 441 uint32_t igp_lane_info; 442 /* displayport */ 443 struct radeon_i2c_chan *dp_i2c_bus; 444 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 445 u8 dp_sink_type; 446 int dp_clock; 447 int dp_lane_count; 448 bool edp_on; 449 }; 450 451 struct radeon_gpio_rec { 452 bool valid; 453 u8 id; 454 u32 reg; 455 u32 mask; 456 }; 457 458 struct radeon_hpd { 459 enum radeon_hpd_id hpd; 460 u8 plugged_state; 461 struct radeon_gpio_rec gpio; 462 }; 463 464 struct radeon_router { 465 u32 router_id; 466 struct radeon_i2c_bus_rec i2c_info; 467 u8 i2c_addr; 468 /* i2c mux */ 469 bool ddc_valid; 470 u8 ddc_mux_type; 471 u8 ddc_mux_control_pin; 472 u8 ddc_mux_state; 473 /* clock/data mux */ 474 bool cd_valid; 475 u8 cd_mux_type; 476 u8 cd_mux_control_pin; 477 u8 cd_mux_state; 478 }; 479 480 enum radeon_connector_audio { 481 RADEON_AUDIO_DISABLE = 0, 482 RADEON_AUDIO_ENABLE = 1, 483 RADEON_AUDIO_AUTO = 2 484 }; 485 486 enum radeon_connector_dither { 487 RADEON_FMT_DITHER_DISABLE = 0, 488 RADEON_FMT_DITHER_ENABLE = 1, 489 }; 490 491 struct radeon_connector { 492 struct drm_connector base; 493 uint32_t connector_id; 494 uint32_t devices; 495 struct radeon_i2c_chan *ddc_bus; 496 /* some systems have an hdmi and vga port with a shared ddc line */ 497 bool shared_ddc; 498 bool use_digital; 499 /* we need to mind the EDID between detect 500 and get modes due to analog/digital/tvencoder */ 501 struct edid *edid; 502 void *con_priv; 503 bool dac_load_detect; 504 bool detected_by_load; /* if the connection status was determined by load */ 505 uint16_t connector_object_id; 506 struct radeon_hpd hpd; 507 struct radeon_router router; 508 struct radeon_i2c_chan *router_bus; 509 enum radeon_connector_audio audio; 510 enum radeon_connector_dither dither; 511 }; 512 513 struct radeon_framebuffer { 514 struct drm_framebuffer base; 515 struct drm_gem_object *obj; 516 }; 517 518 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 519 ((em) == ATOM_ENCODER_MODE_DP_MST)) 520 521 struct atom_clock_dividers { 522 u32 post_div; 523 union { 524 struct { 525 #ifdef __BIG_ENDIAN 526 u32 reserved : 6; 527 u32 whole_fb_div : 12; 528 u32 frac_fb_div : 14; 529 #else 530 u32 frac_fb_div : 14; 531 u32 whole_fb_div : 12; 532 u32 reserved : 6; 533 #endif 534 }; 535 u32 fb_div; 536 }; 537 u32 ref_div; 538 bool enable_post_div; 539 bool enable_dithen; 540 u32 vco_mode; 541 u32 real_clock; 542 /* added for CI */ 543 u32 post_divider; 544 u32 flags; 545 }; 546 547 struct atom_mpll_param { 548 union { 549 struct { 550 #ifdef __BIG_ENDIAN 551 u32 reserved : 8; 552 u32 clkfrac : 12; 553 u32 clkf : 12; 554 #else 555 u32 clkf : 12; 556 u32 clkfrac : 12; 557 u32 reserved : 8; 558 #endif 559 }; 560 u32 fb_div; 561 }; 562 u32 post_div; 563 u32 bwcntl; 564 u32 dll_speed; 565 u32 vco_mode; 566 u32 yclk_sel; 567 u32 qdr; 568 u32 half_rate; 569 }; 570 571 #define MEM_TYPE_GDDR5 0x50 572 #define MEM_TYPE_GDDR4 0x40 573 #define MEM_TYPE_GDDR3 0x30 574 #define MEM_TYPE_DDR2 0x20 575 #define MEM_TYPE_GDDR1 0x10 576 #define MEM_TYPE_DDR3 0xb0 577 #define MEM_TYPE_MASK 0xf0 578 579 struct atom_memory_info { 580 u8 mem_vendor; 581 u8 mem_type; 582 }; 583 584 #define MAX_AC_TIMING_ENTRIES 16 585 586 struct atom_memory_clock_range_table 587 { 588 u8 num_entries; 589 u8 rsv[3]; 590 u32 mclk[MAX_AC_TIMING_ENTRIES]; 591 }; 592 593 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 594 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 595 596 struct atom_mc_reg_entry { 597 u32 mclk_max; 598 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 599 }; 600 601 struct atom_mc_register_address { 602 u16 s1; 603 u8 pre_reg_data; 604 }; 605 606 struct atom_mc_reg_table { 607 u8 last; 608 u8 num_entries; 609 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 610 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 611 }; 612 613 #define MAX_VOLTAGE_ENTRIES 32 614 615 struct atom_voltage_table_entry 616 { 617 u16 value; 618 u32 smio_low; 619 }; 620 621 struct atom_voltage_table 622 { 623 u32 count; 624 u32 mask_low; 625 u32 phase_delay; 626 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 627 }; 628 629 630 extern void 631 radeon_add_atom_connector(struct drm_device *dev, 632 uint32_t connector_id, 633 uint32_t supported_device, 634 int connector_type, 635 struct radeon_i2c_bus_rec *i2c_bus, 636 uint32_t igp_lane_info, 637 uint16_t connector_object_id, 638 struct radeon_hpd *hpd, 639 struct radeon_router *router); 640 extern void 641 radeon_add_legacy_connector(struct drm_device *dev, 642 uint32_t connector_id, 643 uint32_t supported_device, 644 int connector_type, 645 struct radeon_i2c_bus_rec *i2c_bus, 646 uint16_t connector_object_id, 647 struct radeon_hpd *hpd); 648 extern uint32_t 649 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 650 uint8_t dac); 651 extern void radeon_link_encoder_connector(struct drm_device *dev); 652 653 extern enum radeon_tv_std 654 radeon_combios_get_tv_info(struct radeon_device *rdev); 655 extern enum radeon_tv_std 656 radeon_atombios_get_tv_info(struct radeon_device *rdev); 657 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 658 u16 *vddc, u16 *vddci, u16 *mvdd); 659 660 extern void 661 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 662 struct drm_encoder *encoder, 663 bool connected); 664 extern void 665 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 666 struct drm_encoder *encoder, 667 bool connected); 668 669 extern struct drm_connector * 670 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 671 extern struct drm_connector * 672 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 673 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 674 u32 pixel_clock); 675 676 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 677 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 678 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 679 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 680 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 681 682 extern void radeon_connector_hotplug(struct drm_connector *connector); 683 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 684 struct drm_display_mode *mode); 685 extern void radeon_dp_set_link_config(struct drm_connector *connector, 686 const struct drm_display_mode *mode); 687 extern void radeon_dp_link_train(struct drm_encoder *encoder, 688 struct drm_connector *connector); 689 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 690 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 691 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 692 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 693 struct drm_connector *connector); 694 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 695 u8 power_state); 696 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 697 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 698 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 699 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 700 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 701 int action, uint8_t lane_num, 702 uint8_t lane_set); 703 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 704 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 705 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 706 u8 write_byte, u8 *read_byte); 707 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 708 709 extern void radeon_i2c_init(struct radeon_device *rdev); 710 extern void radeon_i2c_fini(struct radeon_device *rdev); 711 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 712 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 713 extern void radeon_i2c_add(struct radeon_device *rdev, 714 struct radeon_i2c_bus_rec *rec, 715 const char *name); 716 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 717 struct radeon_i2c_bus_rec *i2c_bus); 718 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 719 struct radeon_i2c_bus_rec *rec, 720 const char *name); 721 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 722 struct radeon_i2c_bus_rec *rec, 723 const char *name); 724 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 725 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 726 u8 slave_addr, 727 u8 addr, 728 u8 *val); 729 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 730 u8 slave_addr, 731 u8 addr, 732 u8 val); 733 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 734 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 735 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 736 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 737 738 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 739 740 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 741 struct radeon_atom_ss *ss, 742 int id); 743 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 744 struct radeon_atom_ss *ss, 745 int id, u32 clock); 746 747 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 748 uint64_t freq, 749 uint32_t *dot_clock_p, 750 uint32_t *fb_div_p, 751 uint32_t *frac_fb_div_p, 752 uint32_t *ref_div_p, 753 uint32_t *post_div_p); 754 755 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 756 u32 freq, 757 u32 *dot_clock_p, 758 u32 *fb_div_p, 759 u32 *frac_fb_div_p, 760 u32 *ref_div_p, 761 u32 *post_div_p); 762 763 extern void radeon_setup_encoder_clones(struct drm_device *dev); 764 765 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 766 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 767 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 768 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 769 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 770 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 771 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 772 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 773 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 774 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 775 776 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 777 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 778 struct drm_framebuffer *old_fb); 779 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 780 struct drm_framebuffer *fb, 781 int x, int y, 782 enum mode_set_atomic state); 783 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 784 struct drm_display_mode *mode, 785 struct drm_display_mode *adjusted_mode, 786 int x, int y, 787 struct drm_framebuffer *old_fb); 788 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 789 790 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 791 struct drm_framebuffer *old_fb); 792 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 793 struct drm_framebuffer *fb, 794 int x, int y, 795 enum mode_set_atomic state); 796 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 797 struct drm_framebuffer *fb, 798 int x, int y, int atomic); 799 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 800 struct drm_file *file_priv, 801 uint32_t handle, 802 uint32_t width, 803 uint32_t height); 804 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 805 int x, int y); 806 807 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 808 unsigned int flags, 809 int *vpos, int *hpos, ktime_t *stime, 810 ktime_t *etime); 811 812 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 813 extern struct edid * 814 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 815 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 816 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 817 extern struct radeon_encoder_atom_dig * 818 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 819 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 820 struct radeon_encoder_int_tmds *tmds); 821 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 822 struct radeon_encoder_int_tmds *tmds); 823 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 824 struct radeon_encoder_int_tmds *tmds); 825 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 826 struct radeon_encoder_ext_tmds *tmds); 827 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 828 struct radeon_encoder_ext_tmds *tmds); 829 extern struct radeon_encoder_primary_dac * 830 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 831 extern struct radeon_encoder_tv_dac * 832 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 833 extern struct radeon_encoder_lvds * 834 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 835 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 836 extern struct radeon_encoder_tv_dac * 837 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 838 extern struct radeon_encoder_primary_dac * 839 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 840 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 841 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 842 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 843 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 844 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 845 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 846 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 847 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 848 extern void 849 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 850 extern void 851 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 852 extern void 853 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 854 extern void 855 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 856 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 857 u16 blue, int regno); 858 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 859 u16 *blue, int regno); 860 int radeon_framebuffer_init(struct drm_device *dev, 861 struct radeon_framebuffer *rfb, 862 struct drm_mode_fb_cmd2 *mode_cmd, 863 struct drm_gem_object *obj); 864 865 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 866 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 867 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 868 void radeon_atombios_init_crtc(struct drm_device *dev, 869 struct radeon_crtc *radeon_crtc); 870 void radeon_legacy_init_crtc(struct drm_device *dev, 871 struct radeon_crtc *radeon_crtc); 872 873 void radeon_get_clock_info(struct drm_device *dev); 874 875 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 876 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 877 878 void radeon_enc_destroy(struct drm_encoder *encoder); 879 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 880 void radeon_combios_asic_init(struct drm_device *dev); 881 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 882 const struct drm_display_mode *mode, 883 struct drm_display_mode *adjusted_mode); 884 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 885 struct drm_display_mode *adjusted_mode); 886 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 887 888 /* legacy tv */ 889 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 890 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 891 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 892 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 893 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 894 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 895 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 896 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 897 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 898 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 899 struct drm_display_mode *mode, 900 struct drm_display_mode *adjusted_mode); 901 902 /* fmt blocks */ 903 void avivo_program_fmt(struct drm_encoder *encoder); 904 void dce3_program_fmt(struct drm_encoder *encoder); 905 void dce4_program_fmt(struct drm_encoder *encoder); 906 void dce8_program_fmt(struct drm_encoder *encoder); 907 908 /* fbdev layer */ 909 int radeon_fbdev_init(struct radeon_device *rdev); 910 void radeon_fbdev_fini(struct radeon_device *rdev); 911 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 912 int radeon_fbdev_total_size(struct radeon_device *rdev); 913 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 914 915 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 916 917 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 918 919 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 920 #endif 921