1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 struct i2c_adapter adapter; 189 struct drm_device *dev; 190 union { 191 struct i2c_algo_bit_data bit; 192 struct i2c_algo_dp_aux_data dp; 193 } algo; 194 struct radeon_i2c_bus_rec rec; 195 }; 196 197 /* mostly for macs, but really any system without connector tables */ 198 enum radeon_connector_table { 199 CT_NONE = 0, 200 CT_GENERIC, 201 CT_IBOOK, 202 CT_POWERBOOK_EXTERNAL, 203 CT_POWERBOOK_INTERNAL, 204 CT_POWERBOOK_VGA, 205 CT_MINI_EXTERNAL, 206 CT_MINI_INTERNAL, 207 CT_IMAC_G5_ISIGHT, 208 CT_EMAC, 209 CT_RN50_POWER, 210 CT_MAC_X800, 211 CT_MAC_G5_9600, 212 CT_SAM440EP, 213 CT_MAC_G4_SILVER 214 }; 215 216 enum radeon_dvo_chip { 217 DVO_SIL164, 218 DVO_SIL1178, 219 }; 220 221 struct radeon_fbdev; 222 223 struct radeon_afmt { 224 bool enabled; 225 int offset; 226 bool last_buffer_filled_status; 227 int id; 228 struct r600_audio_pin *pin; 229 }; 230 231 struct radeon_mode_info { 232 struct atom_context *atom_context; 233 struct card_info *atom_card_info; 234 enum radeon_connector_table connector_table; 235 bool mode_config_initialized; 236 struct radeon_crtc *crtcs[6]; 237 struct radeon_afmt *afmt[7]; 238 /* DVI-I properties */ 239 struct drm_property *coherent_mode_property; 240 /* DAC enable load detect */ 241 struct drm_property *load_detect_property; 242 /* TV standard */ 243 struct drm_property *tv_std_property; 244 /* legacy TMDS PLL detect */ 245 struct drm_property *tmds_pll_property; 246 /* underscan */ 247 struct drm_property *underscan_property; 248 struct drm_property *underscan_hborder_property; 249 struct drm_property *underscan_vborder_property; 250 /* audio */ 251 struct drm_property *audio_property; 252 /* FMT dithering */ 253 struct drm_property *dither_property; 254 /* hardcoded DFP edid from BIOS */ 255 struct edid *bios_hardcoded_edid; 256 int bios_hardcoded_edid_size; 257 258 /* pointer to fbdev info structure */ 259 struct radeon_fbdev *rfbdev; 260 /* firmware flags */ 261 u16 firmware_flags; 262 /* pointer to backlight encoder */ 263 struct radeon_encoder *bl_encoder; 264 }; 265 266 #define RADEON_MAX_BL_LEVEL 0xFF 267 268 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 269 270 struct radeon_backlight_privdata { 271 struct radeon_encoder *encoder; 272 uint8_t negative; 273 }; 274 275 #endif 276 277 #define MAX_H_CODE_TIMING_LEN 32 278 #define MAX_V_CODE_TIMING_LEN 32 279 280 /* need to store these as reading 281 back code tables is excessive */ 282 struct radeon_tv_regs { 283 uint32_t tv_uv_adr; 284 uint32_t timing_cntl; 285 uint32_t hrestart; 286 uint32_t vrestart; 287 uint32_t frestart; 288 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 289 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 290 }; 291 292 struct radeon_atom_ss { 293 uint16_t percentage; 294 uint16_t percentage_divider; 295 uint8_t type; 296 uint16_t step; 297 uint8_t delay; 298 uint8_t range; 299 uint8_t refdiv; 300 /* asic_ss */ 301 uint16_t rate; 302 uint16_t amount; 303 }; 304 305 struct radeon_crtc { 306 struct drm_crtc base; 307 int crtc_id; 308 u16 lut_r[256], lut_g[256], lut_b[256]; 309 bool enabled; 310 bool can_tile; 311 uint32_t crtc_offset; 312 struct drm_gem_object *cursor_bo; 313 uint64_t cursor_addr; 314 int cursor_width; 315 int cursor_height; 316 int max_cursor_width; 317 int max_cursor_height; 318 uint32_t legacy_display_base_addr; 319 uint32_t legacy_cursor_offset; 320 enum radeon_rmx_type rmx_type; 321 u8 h_border; 322 u8 v_border; 323 fixed20_12 vsc; 324 fixed20_12 hsc; 325 struct drm_display_mode native_mode; 326 int pll_id; 327 /* page flipping */ 328 struct radeon_unpin_work *unpin_work; 329 int deferred_flip_completion; 330 /* pll sharing */ 331 struct radeon_atom_ss ss; 332 bool ss_enabled; 333 u32 adjusted_clock; 334 int bpc; 335 u32 pll_reference_div; 336 u32 pll_post_div; 337 u32 pll_flags; 338 struct drm_encoder *encoder; 339 struct drm_connector *connector; 340 /* for dpm */ 341 u32 line_time; 342 u32 wm_low; 343 u32 wm_high; 344 struct drm_display_mode hw_mode; 345 }; 346 347 struct radeon_encoder_primary_dac { 348 /* legacy primary dac */ 349 uint32_t ps2_pdac_adj; 350 }; 351 352 struct radeon_encoder_lvds { 353 /* legacy lvds */ 354 uint16_t panel_vcc_delay; 355 uint8_t panel_pwr_delay; 356 uint8_t panel_digon_delay; 357 uint8_t panel_blon_delay; 358 uint16_t panel_ref_divider; 359 uint8_t panel_post_divider; 360 uint16_t panel_fb_divider; 361 bool use_bios_dividers; 362 uint32_t lvds_gen_cntl; 363 /* panel mode */ 364 struct drm_display_mode native_mode; 365 struct backlight_device *bl_dev; 366 int dpms_mode; 367 uint8_t backlight_level; 368 }; 369 370 struct radeon_encoder_tv_dac { 371 /* legacy tv dac */ 372 uint32_t ps2_tvdac_adj; 373 uint32_t ntsc_tvdac_adj; 374 uint32_t pal_tvdac_adj; 375 376 int h_pos; 377 int v_pos; 378 int h_size; 379 int supported_tv_stds; 380 bool tv_on; 381 enum radeon_tv_std tv_std; 382 struct radeon_tv_regs tv; 383 }; 384 385 struct radeon_encoder_int_tmds { 386 /* legacy int tmds */ 387 struct radeon_tmds_pll tmds_pll[4]; 388 }; 389 390 struct radeon_encoder_ext_tmds { 391 /* tmds over dvo */ 392 struct radeon_i2c_chan *i2c_bus; 393 uint8_t slave_addr; 394 enum radeon_dvo_chip dvo_chip; 395 }; 396 397 /* spread spectrum */ 398 struct radeon_encoder_atom_dig { 399 bool linkb; 400 /* atom dig */ 401 bool coherent_mode; 402 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 403 /* atom lvds/edp */ 404 uint32_t lcd_misc; 405 uint16_t panel_pwr_delay; 406 uint32_t lcd_ss_id; 407 /* panel mode */ 408 struct drm_display_mode native_mode; 409 struct backlight_device *bl_dev; 410 int dpms_mode; 411 uint8_t backlight_level; 412 int panel_mode; 413 struct radeon_afmt *afmt; 414 }; 415 416 struct radeon_encoder_atom_dac { 417 enum radeon_tv_std tv_std; 418 }; 419 420 struct radeon_encoder { 421 struct drm_encoder base; 422 uint32_t encoder_enum; 423 uint32_t encoder_id; 424 uint32_t devices; 425 uint32_t active_device; 426 uint32_t flags; 427 uint32_t pixel_clock; 428 enum radeon_rmx_type rmx_type; 429 enum radeon_underscan_type underscan_type; 430 uint32_t underscan_hborder; 431 uint32_t underscan_vborder; 432 struct drm_display_mode native_mode; 433 void *enc_priv; 434 int audio_polling_active; 435 bool is_ext_encoder; 436 u16 caps; 437 }; 438 439 struct radeon_connector_atom_dig { 440 uint32_t igp_lane_info; 441 /* displayport */ 442 struct radeon_i2c_chan *dp_i2c_bus; 443 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 444 u8 dp_sink_type; 445 int dp_clock; 446 int dp_lane_count; 447 bool edp_on; 448 }; 449 450 struct radeon_gpio_rec { 451 bool valid; 452 u8 id; 453 u32 reg; 454 u32 mask; 455 }; 456 457 struct radeon_hpd { 458 enum radeon_hpd_id hpd; 459 u8 plugged_state; 460 struct radeon_gpio_rec gpio; 461 }; 462 463 struct radeon_router { 464 u32 router_id; 465 struct radeon_i2c_bus_rec i2c_info; 466 u8 i2c_addr; 467 /* i2c mux */ 468 bool ddc_valid; 469 u8 ddc_mux_type; 470 u8 ddc_mux_control_pin; 471 u8 ddc_mux_state; 472 /* clock/data mux */ 473 bool cd_valid; 474 u8 cd_mux_type; 475 u8 cd_mux_control_pin; 476 u8 cd_mux_state; 477 }; 478 479 enum radeon_connector_audio { 480 RADEON_AUDIO_DISABLE = 0, 481 RADEON_AUDIO_ENABLE = 1, 482 RADEON_AUDIO_AUTO = 2 483 }; 484 485 enum radeon_connector_dither { 486 RADEON_FMT_DITHER_DISABLE = 0, 487 RADEON_FMT_DITHER_ENABLE = 1, 488 }; 489 490 struct radeon_connector { 491 struct drm_connector base; 492 uint32_t connector_id; 493 uint32_t devices; 494 struct radeon_i2c_chan *ddc_bus; 495 /* some systems have an hdmi and vga port with a shared ddc line */ 496 bool shared_ddc; 497 bool use_digital; 498 /* we need to mind the EDID between detect 499 and get modes due to analog/digital/tvencoder */ 500 struct edid *edid; 501 void *con_priv; 502 bool dac_load_detect; 503 bool detected_by_load; /* if the connection status was determined by load */ 504 uint16_t connector_object_id; 505 struct radeon_hpd hpd; 506 struct radeon_router router; 507 struct radeon_i2c_chan *router_bus; 508 enum radeon_connector_audio audio; 509 enum radeon_connector_dither dither; 510 }; 511 512 struct radeon_framebuffer { 513 struct drm_framebuffer base; 514 struct drm_gem_object *obj; 515 }; 516 517 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 518 ((em) == ATOM_ENCODER_MODE_DP_MST)) 519 520 struct atom_clock_dividers { 521 u32 post_div; 522 union { 523 struct { 524 #ifdef __BIG_ENDIAN 525 u32 reserved : 6; 526 u32 whole_fb_div : 12; 527 u32 frac_fb_div : 14; 528 #else 529 u32 frac_fb_div : 14; 530 u32 whole_fb_div : 12; 531 u32 reserved : 6; 532 #endif 533 }; 534 u32 fb_div; 535 }; 536 u32 ref_div; 537 bool enable_post_div; 538 bool enable_dithen; 539 u32 vco_mode; 540 u32 real_clock; 541 /* added for CI */ 542 u32 post_divider; 543 u32 flags; 544 }; 545 546 struct atom_mpll_param { 547 union { 548 struct { 549 #ifdef __BIG_ENDIAN 550 u32 reserved : 8; 551 u32 clkfrac : 12; 552 u32 clkf : 12; 553 #else 554 u32 clkf : 12; 555 u32 clkfrac : 12; 556 u32 reserved : 8; 557 #endif 558 }; 559 u32 fb_div; 560 }; 561 u32 post_div; 562 u32 bwcntl; 563 u32 dll_speed; 564 u32 vco_mode; 565 u32 yclk_sel; 566 u32 qdr; 567 u32 half_rate; 568 }; 569 570 #define MEM_TYPE_GDDR5 0x50 571 #define MEM_TYPE_GDDR4 0x40 572 #define MEM_TYPE_GDDR3 0x30 573 #define MEM_TYPE_DDR2 0x20 574 #define MEM_TYPE_GDDR1 0x10 575 #define MEM_TYPE_DDR3 0xb0 576 #define MEM_TYPE_MASK 0xf0 577 578 struct atom_memory_info { 579 u8 mem_vendor; 580 u8 mem_type; 581 }; 582 583 #define MAX_AC_TIMING_ENTRIES 16 584 585 struct atom_memory_clock_range_table 586 { 587 u8 num_entries; 588 u8 rsv[3]; 589 u32 mclk[MAX_AC_TIMING_ENTRIES]; 590 }; 591 592 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 593 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 594 595 struct atom_mc_reg_entry { 596 u32 mclk_max; 597 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 598 }; 599 600 struct atom_mc_register_address { 601 u16 s1; 602 u8 pre_reg_data; 603 }; 604 605 struct atom_mc_reg_table { 606 u8 last; 607 u8 num_entries; 608 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 609 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 610 }; 611 612 #define MAX_VOLTAGE_ENTRIES 32 613 614 struct atom_voltage_table_entry 615 { 616 u16 value; 617 u32 smio_low; 618 }; 619 620 struct atom_voltage_table 621 { 622 u32 count; 623 u32 mask_low; 624 u32 phase_delay; 625 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 626 }; 627 628 629 extern void 630 radeon_add_atom_connector(struct drm_device *dev, 631 uint32_t connector_id, 632 uint32_t supported_device, 633 int connector_type, 634 struct radeon_i2c_bus_rec *i2c_bus, 635 uint32_t igp_lane_info, 636 uint16_t connector_object_id, 637 struct radeon_hpd *hpd, 638 struct radeon_router *router); 639 extern void 640 radeon_add_legacy_connector(struct drm_device *dev, 641 uint32_t connector_id, 642 uint32_t supported_device, 643 int connector_type, 644 struct radeon_i2c_bus_rec *i2c_bus, 645 uint16_t connector_object_id, 646 struct radeon_hpd *hpd); 647 extern uint32_t 648 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 649 uint8_t dac); 650 extern void radeon_link_encoder_connector(struct drm_device *dev); 651 652 extern enum radeon_tv_std 653 radeon_combios_get_tv_info(struct radeon_device *rdev); 654 extern enum radeon_tv_std 655 radeon_atombios_get_tv_info(struct radeon_device *rdev); 656 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 657 u16 *vddc, u16 *vddci, u16 *mvdd); 658 659 extern void 660 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 661 struct drm_encoder *encoder, 662 bool connected); 663 extern void 664 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 665 struct drm_encoder *encoder, 666 bool connected); 667 668 extern struct drm_connector * 669 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 670 extern struct drm_connector * 671 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 672 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 673 u32 pixel_clock); 674 675 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 676 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 677 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 678 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 679 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 680 681 extern void radeon_connector_hotplug(struct drm_connector *connector); 682 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 683 struct drm_display_mode *mode); 684 extern void radeon_dp_set_link_config(struct drm_connector *connector, 685 const struct drm_display_mode *mode); 686 extern void radeon_dp_link_train(struct drm_encoder *encoder, 687 struct drm_connector *connector); 688 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 689 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 690 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 691 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 692 struct drm_connector *connector); 693 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 694 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 695 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 696 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 697 int action, uint8_t lane_num, 698 uint8_t lane_set); 699 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 700 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 701 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 702 u8 write_byte, u8 *read_byte); 703 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 704 705 extern void radeon_i2c_init(struct radeon_device *rdev); 706 extern void radeon_i2c_fini(struct radeon_device *rdev); 707 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 708 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 709 extern void radeon_i2c_add(struct radeon_device *rdev, 710 struct radeon_i2c_bus_rec *rec, 711 const char *name); 712 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 713 struct radeon_i2c_bus_rec *i2c_bus); 714 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 715 struct radeon_i2c_bus_rec *rec, 716 const char *name); 717 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 718 struct radeon_i2c_bus_rec *rec, 719 const char *name); 720 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 721 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 722 u8 slave_addr, 723 u8 addr, 724 u8 *val); 725 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 726 u8 slave_addr, 727 u8 addr, 728 u8 val); 729 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 730 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 731 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 732 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 733 734 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 735 736 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 737 struct radeon_atom_ss *ss, 738 int id); 739 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 740 struct radeon_atom_ss *ss, 741 int id, u32 clock); 742 743 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 744 uint64_t freq, 745 uint32_t *dot_clock_p, 746 uint32_t *fb_div_p, 747 uint32_t *frac_fb_div_p, 748 uint32_t *ref_div_p, 749 uint32_t *post_div_p); 750 751 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 752 u32 freq, 753 u32 *dot_clock_p, 754 u32 *fb_div_p, 755 u32 *frac_fb_div_p, 756 u32 *ref_div_p, 757 u32 *post_div_p); 758 759 extern void radeon_setup_encoder_clones(struct drm_device *dev); 760 761 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 762 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 763 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 764 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 765 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 766 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 767 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 768 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 769 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 770 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 771 772 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 773 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 774 struct drm_framebuffer *old_fb); 775 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 776 struct drm_framebuffer *fb, 777 int x, int y, 778 enum mode_set_atomic state); 779 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 780 struct drm_display_mode *mode, 781 struct drm_display_mode *adjusted_mode, 782 int x, int y, 783 struct drm_framebuffer *old_fb); 784 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 785 786 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 787 struct drm_framebuffer *old_fb); 788 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 789 struct drm_framebuffer *fb, 790 int x, int y, 791 enum mode_set_atomic state); 792 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 793 struct drm_framebuffer *fb, 794 int x, int y, int atomic); 795 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 796 struct drm_file *file_priv, 797 uint32_t handle, 798 uint32_t width, 799 uint32_t height); 800 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 801 int x, int y); 802 803 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 804 int *vpos, int *hpos, ktime_t *stime, 805 ktime_t *etime); 806 807 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 808 extern struct edid * 809 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 810 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 811 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 812 extern struct radeon_encoder_atom_dig * 813 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 814 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 815 struct radeon_encoder_int_tmds *tmds); 816 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 817 struct radeon_encoder_int_tmds *tmds); 818 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 819 struct radeon_encoder_int_tmds *tmds); 820 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 821 struct radeon_encoder_ext_tmds *tmds); 822 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 823 struct radeon_encoder_ext_tmds *tmds); 824 extern struct radeon_encoder_primary_dac * 825 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 826 extern struct radeon_encoder_tv_dac * 827 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 828 extern struct radeon_encoder_lvds * 829 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 830 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 831 extern struct radeon_encoder_tv_dac * 832 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 833 extern struct radeon_encoder_primary_dac * 834 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 835 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 836 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 837 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 838 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 839 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 840 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 841 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 842 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 843 extern void 844 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 845 extern void 846 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 847 extern void 848 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 849 extern void 850 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 851 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 852 u16 blue, int regno); 853 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 854 u16 *blue, int regno); 855 int radeon_framebuffer_init(struct drm_device *dev, 856 struct radeon_framebuffer *rfb, 857 struct drm_mode_fb_cmd2 *mode_cmd, 858 struct drm_gem_object *obj); 859 860 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 861 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 862 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 863 void radeon_atombios_init_crtc(struct drm_device *dev, 864 struct radeon_crtc *radeon_crtc); 865 void radeon_legacy_init_crtc(struct drm_device *dev, 866 struct radeon_crtc *radeon_crtc); 867 868 void radeon_get_clock_info(struct drm_device *dev); 869 870 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 871 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 872 873 void radeon_enc_destroy(struct drm_encoder *encoder); 874 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 875 void radeon_combios_asic_init(struct drm_device *dev); 876 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 877 const struct drm_display_mode *mode, 878 struct drm_display_mode *adjusted_mode); 879 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 880 struct drm_display_mode *adjusted_mode); 881 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 882 883 /* legacy tv */ 884 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 885 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 886 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 887 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 888 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 889 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 890 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 891 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 892 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 893 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 894 struct drm_display_mode *mode, 895 struct drm_display_mode *adjusted_mode); 896 897 /* fmt blocks */ 898 void avivo_program_fmt(struct drm_encoder *encoder); 899 void dce3_program_fmt(struct drm_encoder *encoder); 900 void dce4_program_fmt(struct drm_encoder *encoder); 901 void dce8_program_fmt(struct drm_encoder *encoder); 902 903 /* fbdev layer */ 904 int radeon_fbdev_init(struct radeon_device *rdev); 905 void radeon_fbdev_fini(struct radeon_device *rdev); 906 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 907 int radeon_fbdev_total_size(struct radeon_device *rdev); 908 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 909 910 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 911 912 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 913 914 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 915 #endif 916