1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 struct i2c_adapter adapter; 189 struct drm_device *dev; 190 union { 191 struct i2c_algo_bit_data bit; 192 struct i2c_algo_dp_aux_data dp; 193 } algo; 194 struct radeon_i2c_bus_rec rec; 195 }; 196 197 /* mostly for macs, but really any system without connector tables */ 198 enum radeon_connector_table { 199 CT_NONE = 0, 200 CT_GENERIC, 201 CT_IBOOK, 202 CT_POWERBOOK_EXTERNAL, 203 CT_POWERBOOK_INTERNAL, 204 CT_POWERBOOK_VGA, 205 CT_MINI_EXTERNAL, 206 CT_MINI_INTERNAL, 207 CT_IMAC_G5_ISIGHT, 208 CT_EMAC, 209 CT_RN50_POWER, 210 CT_MAC_X800, 211 CT_MAC_G5_9600, 212 CT_SAM440EP, 213 CT_MAC_G4_SILVER 214 }; 215 216 enum radeon_dvo_chip { 217 DVO_SIL164, 218 DVO_SIL1178, 219 }; 220 221 struct radeon_fbdev; 222 223 struct radeon_afmt { 224 bool enabled; 225 int offset; 226 bool last_buffer_filled_status; 227 int id; 228 struct r600_audio_pin *pin; 229 }; 230 231 struct radeon_mode_info { 232 struct atom_context *atom_context; 233 struct card_info *atom_card_info; 234 enum radeon_connector_table connector_table; 235 bool mode_config_initialized; 236 struct radeon_crtc *crtcs[6]; 237 struct radeon_afmt *afmt[7]; 238 /* DVI-I properties */ 239 struct drm_property *coherent_mode_property; 240 /* DAC enable load detect */ 241 struct drm_property *load_detect_property; 242 /* TV standard */ 243 struct drm_property *tv_std_property; 244 /* legacy TMDS PLL detect */ 245 struct drm_property *tmds_pll_property; 246 /* underscan */ 247 struct drm_property *underscan_property; 248 struct drm_property *underscan_hborder_property; 249 struct drm_property *underscan_vborder_property; 250 /* audio */ 251 struct drm_property *audio_property; 252 /* hardcoded DFP edid from BIOS */ 253 struct edid *bios_hardcoded_edid; 254 int bios_hardcoded_edid_size; 255 256 /* pointer to fbdev info structure */ 257 struct radeon_fbdev *rfbdev; 258 /* firmware flags */ 259 u16 firmware_flags; 260 /* pointer to backlight encoder */ 261 struct radeon_encoder *bl_encoder; 262 }; 263 264 #define RADEON_MAX_BL_LEVEL 0xFF 265 266 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 267 268 struct radeon_backlight_privdata { 269 struct radeon_encoder *encoder; 270 uint8_t negative; 271 }; 272 273 #endif 274 275 #define MAX_H_CODE_TIMING_LEN 32 276 #define MAX_V_CODE_TIMING_LEN 32 277 278 /* need to store these as reading 279 back code tables is excessive */ 280 struct radeon_tv_regs { 281 uint32_t tv_uv_adr; 282 uint32_t timing_cntl; 283 uint32_t hrestart; 284 uint32_t vrestart; 285 uint32_t frestart; 286 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 287 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 288 }; 289 290 struct radeon_atom_ss { 291 uint16_t percentage; 292 uint8_t type; 293 uint16_t step; 294 uint8_t delay; 295 uint8_t range; 296 uint8_t refdiv; 297 /* asic_ss */ 298 uint16_t rate; 299 uint16_t amount; 300 }; 301 302 struct radeon_crtc { 303 struct drm_crtc base; 304 int crtc_id; 305 u16 lut_r[256], lut_g[256], lut_b[256]; 306 bool enabled; 307 bool can_tile; 308 uint32_t crtc_offset; 309 struct drm_gem_object *cursor_bo; 310 uint64_t cursor_addr; 311 int cursor_width; 312 int cursor_height; 313 int max_cursor_width; 314 int max_cursor_height; 315 uint32_t legacy_display_base_addr; 316 uint32_t legacy_cursor_offset; 317 enum radeon_rmx_type rmx_type; 318 u8 h_border; 319 u8 v_border; 320 fixed20_12 vsc; 321 fixed20_12 hsc; 322 struct drm_display_mode native_mode; 323 int pll_id; 324 /* page flipping */ 325 struct radeon_unpin_work *unpin_work; 326 int deferred_flip_completion; 327 /* pll sharing */ 328 struct radeon_atom_ss ss; 329 bool ss_enabled; 330 u32 adjusted_clock; 331 int bpc; 332 u32 pll_reference_div; 333 u32 pll_post_div; 334 u32 pll_flags; 335 struct drm_encoder *encoder; 336 struct drm_connector *connector; 337 /* for dpm */ 338 u32 line_time; 339 u32 wm_low; 340 u32 wm_high; 341 struct drm_display_mode hw_mode; 342 }; 343 344 struct radeon_encoder_primary_dac { 345 /* legacy primary dac */ 346 uint32_t ps2_pdac_adj; 347 }; 348 349 struct radeon_encoder_lvds { 350 /* legacy lvds */ 351 uint16_t panel_vcc_delay; 352 uint8_t panel_pwr_delay; 353 uint8_t panel_digon_delay; 354 uint8_t panel_blon_delay; 355 uint16_t panel_ref_divider; 356 uint8_t panel_post_divider; 357 uint16_t panel_fb_divider; 358 bool use_bios_dividers; 359 uint32_t lvds_gen_cntl; 360 /* panel mode */ 361 struct drm_display_mode native_mode; 362 struct backlight_device *bl_dev; 363 int dpms_mode; 364 uint8_t backlight_level; 365 }; 366 367 struct radeon_encoder_tv_dac { 368 /* legacy tv dac */ 369 uint32_t ps2_tvdac_adj; 370 uint32_t ntsc_tvdac_adj; 371 uint32_t pal_tvdac_adj; 372 373 int h_pos; 374 int v_pos; 375 int h_size; 376 int supported_tv_stds; 377 bool tv_on; 378 enum radeon_tv_std tv_std; 379 struct radeon_tv_regs tv; 380 }; 381 382 struct radeon_encoder_int_tmds { 383 /* legacy int tmds */ 384 struct radeon_tmds_pll tmds_pll[4]; 385 }; 386 387 struct radeon_encoder_ext_tmds { 388 /* tmds over dvo */ 389 struct radeon_i2c_chan *i2c_bus; 390 uint8_t slave_addr; 391 enum radeon_dvo_chip dvo_chip; 392 }; 393 394 /* spread spectrum */ 395 struct radeon_encoder_atom_dig { 396 bool linkb; 397 /* atom dig */ 398 bool coherent_mode; 399 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 400 /* atom lvds/edp */ 401 uint32_t lcd_misc; 402 uint16_t panel_pwr_delay; 403 uint32_t lcd_ss_id; 404 /* panel mode */ 405 struct drm_display_mode native_mode; 406 struct backlight_device *bl_dev; 407 int dpms_mode; 408 uint8_t backlight_level; 409 int panel_mode; 410 struct radeon_afmt *afmt; 411 }; 412 413 struct radeon_encoder_atom_dac { 414 enum radeon_tv_std tv_std; 415 }; 416 417 struct radeon_encoder { 418 struct drm_encoder base; 419 uint32_t encoder_enum; 420 uint32_t encoder_id; 421 uint32_t devices; 422 uint32_t active_device; 423 uint32_t flags; 424 uint32_t pixel_clock; 425 enum radeon_rmx_type rmx_type; 426 enum radeon_underscan_type underscan_type; 427 uint32_t underscan_hborder; 428 uint32_t underscan_vborder; 429 struct drm_display_mode native_mode; 430 void *enc_priv; 431 int audio_polling_active; 432 bool is_ext_encoder; 433 u16 caps; 434 }; 435 436 struct radeon_connector_atom_dig { 437 uint32_t igp_lane_info; 438 /* displayport */ 439 struct radeon_i2c_chan *dp_i2c_bus; 440 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 441 u8 dp_sink_type; 442 int dp_clock; 443 int dp_lane_count; 444 bool edp_on; 445 }; 446 447 struct radeon_gpio_rec { 448 bool valid; 449 u8 id; 450 u32 reg; 451 u32 mask; 452 }; 453 454 struct radeon_hpd { 455 enum radeon_hpd_id hpd; 456 u8 plugged_state; 457 struct radeon_gpio_rec gpio; 458 }; 459 460 struct radeon_router { 461 u32 router_id; 462 struct radeon_i2c_bus_rec i2c_info; 463 u8 i2c_addr; 464 /* i2c mux */ 465 bool ddc_valid; 466 u8 ddc_mux_type; 467 u8 ddc_mux_control_pin; 468 u8 ddc_mux_state; 469 /* clock/data mux */ 470 bool cd_valid; 471 u8 cd_mux_type; 472 u8 cd_mux_control_pin; 473 u8 cd_mux_state; 474 }; 475 476 enum radeon_connector_audio { 477 RADEON_AUDIO_DISABLE = 0, 478 RADEON_AUDIO_ENABLE = 1, 479 RADEON_AUDIO_AUTO = 2 480 }; 481 482 struct radeon_connector { 483 struct drm_connector base; 484 uint32_t connector_id; 485 uint32_t devices; 486 struct radeon_i2c_chan *ddc_bus; 487 /* some systems have an hdmi and vga port with a shared ddc line */ 488 bool shared_ddc; 489 bool use_digital; 490 /* we need to mind the EDID between detect 491 and get modes due to analog/digital/tvencoder */ 492 struct edid *edid; 493 void *con_priv; 494 bool dac_load_detect; 495 bool detected_by_load; /* if the connection status was determined by load */ 496 uint16_t connector_object_id; 497 struct radeon_hpd hpd; 498 struct radeon_router router; 499 struct radeon_i2c_chan *router_bus; 500 enum radeon_connector_audio audio; 501 }; 502 503 struct radeon_framebuffer { 504 struct drm_framebuffer base; 505 struct drm_gem_object *obj; 506 }; 507 508 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 509 ((em) == ATOM_ENCODER_MODE_DP_MST)) 510 511 struct atom_clock_dividers { 512 u32 post_div; 513 union { 514 struct { 515 #ifdef __BIG_ENDIAN 516 u32 reserved : 6; 517 u32 whole_fb_div : 12; 518 u32 frac_fb_div : 14; 519 #else 520 u32 frac_fb_div : 14; 521 u32 whole_fb_div : 12; 522 u32 reserved : 6; 523 #endif 524 }; 525 u32 fb_div; 526 }; 527 u32 ref_div; 528 bool enable_post_div; 529 bool enable_dithen; 530 u32 vco_mode; 531 u32 real_clock; 532 /* added for CI */ 533 u32 post_divider; 534 u32 flags; 535 }; 536 537 struct atom_mpll_param { 538 union { 539 struct { 540 #ifdef __BIG_ENDIAN 541 u32 reserved : 8; 542 u32 clkfrac : 12; 543 u32 clkf : 12; 544 #else 545 u32 clkf : 12; 546 u32 clkfrac : 12; 547 u32 reserved : 8; 548 #endif 549 }; 550 u32 fb_div; 551 }; 552 u32 post_div; 553 u32 bwcntl; 554 u32 dll_speed; 555 u32 vco_mode; 556 u32 yclk_sel; 557 u32 qdr; 558 u32 half_rate; 559 }; 560 561 #define MEM_TYPE_GDDR5 0x50 562 #define MEM_TYPE_GDDR4 0x40 563 #define MEM_TYPE_GDDR3 0x30 564 #define MEM_TYPE_DDR2 0x20 565 #define MEM_TYPE_GDDR1 0x10 566 #define MEM_TYPE_DDR3 0xb0 567 #define MEM_TYPE_MASK 0xf0 568 569 struct atom_memory_info { 570 u8 mem_vendor; 571 u8 mem_type; 572 }; 573 574 #define MAX_AC_TIMING_ENTRIES 16 575 576 struct atom_memory_clock_range_table 577 { 578 u8 num_entries; 579 u8 rsv[3]; 580 u32 mclk[MAX_AC_TIMING_ENTRIES]; 581 }; 582 583 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 584 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 585 586 struct atom_mc_reg_entry { 587 u32 mclk_max; 588 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 589 }; 590 591 struct atom_mc_register_address { 592 u16 s1; 593 u8 pre_reg_data; 594 }; 595 596 struct atom_mc_reg_table { 597 u8 last; 598 u8 num_entries; 599 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 600 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 601 }; 602 603 #define MAX_VOLTAGE_ENTRIES 32 604 605 struct atom_voltage_table_entry 606 { 607 u16 value; 608 u32 smio_low; 609 }; 610 611 struct atom_voltage_table 612 { 613 u32 count; 614 u32 mask_low; 615 u32 phase_delay; 616 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 617 }; 618 619 extern enum radeon_tv_std 620 radeon_combios_get_tv_info(struct radeon_device *rdev); 621 extern enum radeon_tv_std 622 radeon_atombios_get_tv_info(struct radeon_device *rdev); 623 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 624 u16 *vddc, u16 *vddci, u16 *mvdd); 625 626 extern struct drm_connector * 627 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 628 extern struct drm_connector * 629 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 630 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 631 u32 pixel_clock); 632 633 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 634 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 635 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 636 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 637 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 638 639 extern void radeon_connector_hotplug(struct drm_connector *connector); 640 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 641 struct drm_display_mode *mode); 642 extern void radeon_dp_set_link_config(struct drm_connector *connector, 643 const struct drm_display_mode *mode); 644 extern void radeon_dp_link_train(struct drm_encoder *encoder, 645 struct drm_connector *connector); 646 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 647 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 648 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 649 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 650 struct drm_connector *connector); 651 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 652 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 653 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 654 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 655 int action, uint8_t lane_num, 656 uint8_t lane_set); 657 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 658 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 659 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 660 u8 write_byte, u8 *read_byte); 661 662 extern void radeon_i2c_init(struct radeon_device *rdev); 663 extern void radeon_i2c_fini(struct radeon_device *rdev); 664 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 665 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 666 extern void radeon_i2c_add(struct radeon_device *rdev, 667 struct radeon_i2c_bus_rec *rec, 668 const char *name); 669 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 670 struct radeon_i2c_bus_rec *i2c_bus); 671 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 672 struct radeon_i2c_bus_rec *rec, 673 const char *name); 674 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 675 struct radeon_i2c_bus_rec *rec, 676 const char *name); 677 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 678 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 679 u8 slave_addr, 680 u8 addr, 681 u8 *val); 682 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 683 u8 slave_addr, 684 u8 addr, 685 u8 val); 686 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 687 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 688 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 689 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 690 691 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 692 693 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 694 struct radeon_atom_ss *ss, 695 int id); 696 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 697 struct radeon_atom_ss *ss, 698 int id, u32 clock); 699 700 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 701 uint64_t freq, 702 uint32_t *dot_clock_p, 703 uint32_t *fb_div_p, 704 uint32_t *frac_fb_div_p, 705 uint32_t *ref_div_p, 706 uint32_t *post_div_p); 707 708 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 709 u32 freq, 710 u32 *dot_clock_p, 711 u32 *fb_div_p, 712 u32 *frac_fb_div_p, 713 u32 *ref_div_p, 714 u32 *post_div_p); 715 716 extern void radeon_setup_encoder_clones(struct drm_device *dev); 717 718 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 719 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 720 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 721 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 722 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 723 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 724 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 725 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 726 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 727 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 728 729 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 730 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 731 struct drm_framebuffer *old_fb); 732 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 733 struct drm_framebuffer *fb, 734 int x, int y, 735 enum mode_set_atomic state); 736 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 737 struct drm_display_mode *mode, 738 struct drm_display_mode *adjusted_mode, 739 int x, int y, 740 struct drm_framebuffer *old_fb); 741 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 742 743 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 744 struct drm_framebuffer *old_fb); 745 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 746 struct drm_framebuffer *fb, 747 int x, int y, 748 enum mode_set_atomic state); 749 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 750 struct drm_framebuffer *fb, 751 int x, int y, int atomic); 752 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 753 struct drm_file *file_priv, 754 uint32_t handle, 755 uint32_t width, 756 uint32_t height); 757 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 758 int x, int y); 759 760 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 761 int *vpos, int *hpos); 762 763 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 764 extern struct edid * 765 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 766 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 767 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 768 extern struct radeon_encoder_atom_dig * 769 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 770 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 771 struct radeon_encoder_int_tmds *tmds); 772 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 773 struct radeon_encoder_int_tmds *tmds); 774 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 775 struct radeon_encoder_int_tmds *tmds); 776 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 777 struct radeon_encoder_ext_tmds *tmds); 778 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 779 struct radeon_encoder_ext_tmds *tmds); 780 extern struct radeon_encoder_primary_dac * 781 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 782 extern struct radeon_encoder_tv_dac * 783 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 784 extern struct radeon_encoder_lvds * 785 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 786 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 787 extern struct radeon_encoder_tv_dac * 788 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 789 extern struct radeon_encoder_primary_dac * 790 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 791 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 792 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 793 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 794 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 795 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 796 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 797 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 798 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 799 extern void 800 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 801 extern void 802 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 803 extern void 804 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 805 extern void 806 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 807 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 808 u16 blue, int regno); 809 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 810 u16 *blue, int regno); 811 int radeon_framebuffer_init(struct drm_device *dev, 812 struct radeon_framebuffer *rfb, 813 struct drm_mode_fb_cmd2 *mode_cmd, 814 struct drm_gem_object *obj); 815 816 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 817 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 818 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 819 void radeon_atombios_init_crtc(struct drm_device *dev, 820 struct radeon_crtc *radeon_crtc); 821 void radeon_legacy_init_crtc(struct drm_device *dev, 822 struct radeon_crtc *radeon_crtc); 823 824 void radeon_get_clock_info(struct drm_device *dev); 825 826 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 827 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 828 829 void radeon_enc_destroy(struct drm_encoder *encoder); 830 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 831 void radeon_combios_asic_init(struct drm_device *dev); 832 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 833 const struct drm_display_mode *mode, 834 struct drm_display_mode *adjusted_mode); 835 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 836 struct drm_display_mode *adjusted_mode); 837 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 838 839 /* legacy tv */ 840 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 841 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 842 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 843 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 844 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 845 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 846 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 847 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 848 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 849 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 850 struct drm_display_mode *mode, 851 struct drm_display_mode *adjusted_mode); 852 853 /* fbdev layer */ 854 int radeon_fbdev_init(struct radeon_device *rdev); 855 void radeon_fbdev_fini(struct radeon_device *rdev); 856 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 857 int radeon_fbdev_total_size(struct radeon_device *rdev); 858 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 859 860 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 861 862 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 863 864 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 865 #endif 866