1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 3768adac5eSBen Skeggs #include <drm_fixed.h> 3821c74a8eSJason Wessel #include <drm_crtc_helper.h> 39771fe6b9SJerome Glisse #include <linux/i2c.h> 40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 41c93bb85bSJerome Glisse 4238651674SDave Airlie struct radeon_bo; 43c93bb85bSJerome Glisse struct radeon_device; 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49771fe6b9SJerome Glisse 50771fe6b9SJerome Glisse enum radeon_rmx_type { 51771fe6b9SJerome Glisse RMX_OFF, 52771fe6b9SJerome Glisse RMX_FULL, 53771fe6b9SJerome Glisse RMX_CENTER, 54771fe6b9SJerome Glisse RMX_ASPECT 55771fe6b9SJerome Glisse }; 56771fe6b9SJerome Glisse 57771fe6b9SJerome Glisse enum radeon_tv_std { 58771fe6b9SJerome Glisse TV_STD_NTSC, 59771fe6b9SJerome Glisse TV_STD_PAL, 60771fe6b9SJerome Glisse TV_STD_PAL_M, 61771fe6b9SJerome Glisse TV_STD_PAL_60, 62771fe6b9SJerome Glisse TV_STD_NTSC_J, 63771fe6b9SJerome Glisse TV_STD_SCART_PAL, 64771fe6b9SJerome Glisse TV_STD_SECAM, 65771fe6b9SJerome Glisse TV_STD_PAL_CN, 66d79766faSAlex Deucher TV_STD_PAL_N, 67771fe6b9SJerome Glisse }; 68771fe6b9SJerome Glisse 695b1714d3SAlex Deucher enum radeon_underscan_type { 705b1714d3SAlex Deucher UNDERSCAN_OFF, 715b1714d3SAlex Deucher UNDERSCAN_ON, 725b1714d3SAlex Deucher UNDERSCAN_AUTO, 735b1714d3SAlex Deucher }; 745b1714d3SAlex Deucher 758e36ed00SAlex Deucher enum radeon_hpd_id { 768e36ed00SAlex Deucher RADEON_HPD_1 = 0, 778e36ed00SAlex Deucher RADEON_HPD_2, 788e36ed00SAlex Deucher RADEON_HPD_3, 798e36ed00SAlex Deucher RADEON_HPD_4, 808e36ed00SAlex Deucher RADEON_HPD_5, 818e36ed00SAlex Deucher RADEON_HPD_6, 828e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 838e36ed00SAlex Deucher }; 848e36ed00SAlex Deucher 85f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 86f376b94fSAlex Deucher 879b9fe724SAlex Deucher /* radeon gpio-based i2c 889b9fe724SAlex Deucher * 1. "mask" reg and bits 899b9fe724SAlex Deucher * grabs the gpio pins for software use 909b9fe724SAlex Deucher * 0=not held 1=held 919b9fe724SAlex Deucher * 2. "a" reg and bits 929b9fe724SAlex Deucher * output pin value 939b9fe724SAlex Deucher * 0=low 1=high 949b9fe724SAlex Deucher * 3. "en" reg and bits 959b9fe724SAlex Deucher * sets the pin direction 969b9fe724SAlex Deucher * 0=input 1=output 979b9fe724SAlex Deucher * 4. "y" reg and bits 989b9fe724SAlex Deucher * input pin value 999b9fe724SAlex Deucher * 0=low 1=high 1009b9fe724SAlex Deucher */ 101771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 102771fe6b9SJerome Glisse bool valid; 1036a93cb25SAlex Deucher /* id used by atom */ 1046a93cb25SAlex Deucher uint8_t i2c_id; 105bcc1c2a1SAlex Deucher /* id used by atom */ 1068e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1076a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1086a93cb25SAlex Deucher bool hw_capable; 1096a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1106a93cb25SAlex Deucher bool mm_i2c; 1116a93cb25SAlex Deucher /* regs and bits */ 112771fe6b9SJerome Glisse uint32_t mask_clk_reg; 113771fe6b9SJerome Glisse uint32_t mask_data_reg; 114771fe6b9SJerome Glisse uint32_t a_clk_reg; 115771fe6b9SJerome Glisse uint32_t a_data_reg; 1169b9fe724SAlex Deucher uint32_t en_clk_reg; 1179b9fe724SAlex Deucher uint32_t en_data_reg; 1189b9fe724SAlex Deucher uint32_t y_clk_reg; 1199b9fe724SAlex Deucher uint32_t y_data_reg; 120771fe6b9SJerome Glisse uint32_t mask_clk_mask; 121771fe6b9SJerome Glisse uint32_t mask_data_mask; 122771fe6b9SJerome Glisse uint32_t a_clk_mask; 123771fe6b9SJerome Glisse uint32_t a_data_mask; 1249b9fe724SAlex Deucher uint32_t en_clk_mask; 1259b9fe724SAlex Deucher uint32_t en_data_mask; 1269b9fe724SAlex Deucher uint32_t y_clk_mask; 1279b9fe724SAlex Deucher uint32_t y_data_mask; 128771fe6b9SJerome Glisse }; 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse struct radeon_tmds_pll { 131771fe6b9SJerome Glisse uint32_t freq; 132771fe6b9SJerome Glisse uint32_t value; 133771fe6b9SJerome Glisse }; 134771fe6b9SJerome Glisse 135771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 136771fe6b9SJerome Glisse 1377c27f87dSAlex Deucher /* pll flags */ 138771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 141771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15186cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 152771fe6b9SJerome Glisse 153771fe6b9SJerome Glisse struct radeon_pll { 154fc10332bSAlex Deucher /* reference frequency */ 155fc10332bSAlex Deucher uint32_t reference_freq; 156fc10332bSAlex Deucher 157fc10332bSAlex Deucher /* fixed dividers */ 158fc10332bSAlex Deucher uint32_t reference_div; 159fc10332bSAlex Deucher uint32_t post_div; 160fc10332bSAlex Deucher 161fc10332bSAlex Deucher /* pll in/out limits */ 162771fe6b9SJerome Glisse uint32_t pll_in_min; 163771fe6b9SJerome Glisse uint32_t pll_in_max; 164771fe6b9SJerome Glisse uint32_t pll_out_min; 165771fe6b9SJerome Glisse uint32_t pll_out_max; 16686cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 168fc10332bSAlex Deucher uint32_t best_vco; 169771fe6b9SJerome Glisse 170fc10332bSAlex Deucher /* divider limits */ 171771fe6b9SJerome Glisse uint32_t min_ref_div; 172771fe6b9SJerome Glisse uint32_t max_ref_div; 173771fe6b9SJerome Glisse uint32_t min_post_div; 174771fe6b9SJerome Glisse uint32_t max_post_div; 175771fe6b9SJerome Glisse uint32_t min_feedback_div; 176771fe6b9SJerome Glisse uint32_t max_feedback_div; 177771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 178771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 179fc10332bSAlex Deucher 180fc10332bSAlex Deucher /* flags for the current clock */ 181fc10332bSAlex Deucher uint32_t flags; 182fc10332bSAlex Deucher 183fc10332bSAlex Deucher /* pll id */ 184fc10332bSAlex Deucher uint32_t id; 185771fe6b9SJerome Glisse }; 186771fe6b9SJerome Glisse 187771fe6b9SJerome Glisse struct radeon_i2c_chan { 188771fe6b9SJerome Glisse struct i2c_adapter adapter; 189746c1aa4SDave Airlie struct drm_device *dev; 190746c1aa4SDave Airlie union { 191ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 192746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 193746c1aa4SDave Airlie } algo; 194771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 195771fe6b9SJerome Glisse }; 196771fe6b9SJerome Glisse 197771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 198771fe6b9SJerome Glisse enum radeon_connector_table { 199aa74fbb4SAlex Deucher CT_NONE = 0, 200771fe6b9SJerome Glisse CT_GENERIC, 201771fe6b9SJerome Glisse CT_IBOOK, 202771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 203771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 205771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 206771fe6b9SJerome Glisse CT_MINI_INTERNAL, 207771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 208771fe6b9SJerome Glisse CT_EMAC, 20976a7142aSDave Airlie CT_RN50_POWER, 210aa74fbb4SAlex Deucher CT_MAC_X800, 211771fe6b9SJerome Glisse }; 212771fe6b9SJerome Glisse 213fcec570bSAlex Deucher enum radeon_dvo_chip { 214fcec570bSAlex Deucher DVO_SIL164, 215fcec570bSAlex Deucher DVO_SIL1178, 216fcec570bSAlex Deucher }; 217fcec570bSAlex Deucher 2188be48d92SDave Airlie struct radeon_fbdev; 21938651674SDave Airlie 220771fe6b9SJerome Glisse struct radeon_mode_info { 221771fe6b9SJerome Glisse struct atom_context *atom_context; 22261c4b24bSMathias Fröhlich struct card_info *atom_card_info; 223771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 224771fe6b9SJerome Glisse bool mode_config_initialized; 225bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 226445282dbSDave Airlie /* DVI-I properties */ 227445282dbSDave Airlie struct drm_property *coherent_mode_property; 228445282dbSDave Airlie /* DAC enable load detect */ 229445282dbSDave Airlie struct drm_property *load_detect_property; 2305b1714d3SAlex Deucher /* TV standard */ 231445282dbSDave Airlie struct drm_property *tv_std_property; 232445282dbSDave Airlie /* legacy TMDS PLL detect */ 233445282dbSDave Airlie struct drm_property *tmds_pll_property; 2345b1714d3SAlex Deucher /* underscan */ 2355b1714d3SAlex Deucher struct drm_property *underscan_property; 2365bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2375bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2383c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2393c537889SAlex Deucher struct edid *bios_hardcoded_edid; 24038651674SDave Airlie 24138651674SDave Airlie /* pointer to fbdev info structure */ 2428be48d92SDave Airlie struct radeon_fbdev *rfbdev; 243c93bb85bSJerome Glisse }; 244c93bb85bSJerome Glisse 2454ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2464ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2474ce001abSDave Airlie 2484ce001abSDave Airlie /* need to store these as reading 2494ce001abSDave Airlie back code tables is excessive */ 2504ce001abSDave Airlie struct radeon_tv_regs { 2514ce001abSDave Airlie uint32_t tv_uv_adr; 2524ce001abSDave Airlie uint32_t timing_cntl; 2534ce001abSDave Airlie uint32_t hrestart; 2544ce001abSDave Airlie uint32_t vrestart; 2554ce001abSDave Airlie uint32_t frestart; 2564ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2574ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2584ce001abSDave Airlie }; 2594ce001abSDave Airlie 260771fe6b9SJerome Glisse struct radeon_crtc { 261771fe6b9SJerome Glisse struct drm_crtc base; 262771fe6b9SJerome Glisse int crtc_id; 263771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 264771fe6b9SJerome Glisse bool enabled; 265771fe6b9SJerome Glisse bool can_tile; 266771fe6b9SJerome Glisse uint32_t crtc_offset; 267771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 268771fe6b9SJerome Glisse uint64_t cursor_addr; 269771fe6b9SJerome Glisse int cursor_width; 270771fe6b9SJerome Glisse int cursor_height; 2714162338aSDave Airlie uint32_t legacy_display_base_addr; 272c836e862SAlex Deucher uint32_t legacy_cursor_offset; 273c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 2745b1714d3SAlex Deucher u8 h_border; 2755b1714d3SAlex Deucher u8 v_border; 276c93bb85bSJerome Glisse fixed20_12 vsc; 277c93bb85bSJerome Glisse fixed20_12 hsc; 278de2103e4SAlex Deucher struct drm_display_mode native_mode; 279bcc1c2a1SAlex Deucher int pll_id; 280771fe6b9SJerome Glisse }; 281771fe6b9SJerome Glisse 282771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 283771fe6b9SJerome Glisse /* legacy primary dac */ 284771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 285771fe6b9SJerome Glisse }; 286771fe6b9SJerome Glisse 287771fe6b9SJerome Glisse struct radeon_encoder_lvds { 288771fe6b9SJerome Glisse /* legacy lvds */ 289771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 290771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 291771fe6b9SJerome Glisse uint8_t panel_digon_delay; 292771fe6b9SJerome Glisse uint8_t panel_blon_delay; 293771fe6b9SJerome Glisse uint16_t panel_ref_divider; 294771fe6b9SJerome Glisse uint8_t panel_post_divider; 295771fe6b9SJerome Glisse uint16_t panel_fb_divider; 296771fe6b9SJerome Glisse bool use_bios_dividers; 297771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 298771fe6b9SJerome Glisse /* panel mode */ 299de2103e4SAlex Deucher struct drm_display_mode native_mode; 300771fe6b9SJerome Glisse }; 301771fe6b9SJerome Glisse 302771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 303771fe6b9SJerome Glisse /* legacy tv dac */ 304771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 305771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 306771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 307771fe6b9SJerome Glisse 3084ce001abSDave Airlie int h_pos; 3094ce001abSDave Airlie int v_pos; 3104ce001abSDave Airlie int h_size; 3114ce001abSDave Airlie int supported_tv_stds; 3124ce001abSDave Airlie bool tv_on; 313771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3144ce001abSDave Airlie struct radeon_tv_regs tv; 315771fe6b9SJerome Glisse }; 316771fe6b9SJerome Glisse 317771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 318771fe6b9SJerome Glisse /* legacy int tmds */ 319771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 320771fe6b9SJerome Glisse }; 321771fe6b9SJerome Glisse 322fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 323fcec570bSAlex Deucher /* tmds over dvo */ 324fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 325fcec570bSAlex Deucher uint8_t slave_addr; 326fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 327fcec570bSAlex Deucher }; 328fcec570bSAlex Deucher 329ebbe1cb9SAlex Deucher /* spread spectrum */ 330ebbe1cb9SAlex Deucher struct radeon_atom_ss { 331ebbe1cb9SAlex Deucher uint16_t percentage; 332ebbe1cb9SAlex Deucher uint8_t type; 333ba032a58SAlex Deucher uint16_t step; 334ebbe1cb9SAlex Deucher uint8_t delay; 335ebbe1cb9SAlex Deucher uint8_t range; 336ebbe1cb9SAlex Deucher uint8_t refdiv; 337ba032a58SAlex Deucher /* asic_ss */ 338ba032a58SAlex Deucher uint16_t rate; 339ba032a58SAlex Deucher uint16_t amount; 340ebbe1cb9SAlex Deucher }; 341ebbe1cb9SAlex Deucher 342771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3435137ee94SAlex Deucher bool linkb; 344771fe6b9SJerome Glisse /* atom dig */ 345771fe6b9SJerome Glisse bool coherent_mode; 346ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 347ba032a58SAlex Deucher /* atom lvds/edp */ 348ba032a58SAlex Deucher uint32_t lcd_misc; 349771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 350ba032a58SAlex Deucher uint32_t lcd_ss_id; 351771fe6b9SJerome Glisse /* panel mode */ 352de2103e4SAlex Deucher struct drm_display_mode native_mode; 353771fe6b9SJerome Glisse }; 354771fe6b9SJerome Glisse 3554ce001abSDave Airlie struct radeon_encoder_atom_dac { 3564ce001abSDave Airlie enum radeon_tv_std tv_std; 3574ce001abSDave Airlie }; 3584ce001abSDave Airlie 359771fe6b9SJerome Glisse struct radeon_encoder { 360771fe6b9SJerome Glisse struct drm_encoder base; 3615137ee94SAlex Deucher uint32_t encoder_enum; 362771fe6b9SJerome Glisse uint32_t encoder_id; 363771fe6b9SJerome Glisse uint32_t devices; 3644ce001abSDave Airlie uint32_t active_device; 365771fe6b9SJerome Glisse uint32_t flags; 366771fe6b9SJerome Glisse uint32_t pixel_clock; 367771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 3685b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 3695bccf5e3SMarius Gröger uint32_t underscan_hborder; 3705bccf5e3SMarius Gröger uint32_t underscan_vborder; 371de2103e4SAlex Deucher struct drm_display_mode native_mode; 372771fe6b9SJerome Glisse void *enc_priv; 37358bd0863SChristian König int audio_polling_active; 374dafc3bd5SChristian Koenig int hdmi_offset; 375808032eeSRafał Miłecki int hdmi_config_offset; 376dafc3bd5SChristian Koenig int hdmi_audio_workaround; 377dafc3bd5SChristian Koenig int hdmi_buffer_status; 378771fe6b9SJerome Glisse }; 379771fe6b9SJerome Glisse 380771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 381771fe6b9SJerome Glisse uint32_t igp_lane_info; 3824143e919SAlex Deucher /* displayport */ 383746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 3841a66c95aSAlex Deucher u8 dpcd[8]; 3854143e919SAlex Deucher u8 dp_sink_type; 3865801ead6SAlex Deucher int dp_clock; 3875801ead6SAlex Deucher int dp_lane_count; 388771fe6b9SJerome Glisse }; 389771fe6b9SJerome Glisse 390eed45b30SAlex Deucher struct radeon_gpio_rec { 391eed45b30SAlex Deucher bool valid; 392eed45b30SAlex Deucher u8 id; 393eed45b30SAlex Deucher u32 reg; 394eed45b30SAlex Deucher u32 mask; 395eed45b30SAlex Deucher }; 396eed45b30SAlex Deucher 397eed45b30SAlex Deucher struct radeon_hpd { 398eed45b30SAlex Deucher enum radeon_hpd_id hpd; 399eed45b30SAlex Deucher u8 plugged_state; 400eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 401eed45b30SAlex Deucher }; 402eed45b30SAlex Deucher 40326b5bc98SAlex Deucher struct radeon_router { 40426b5bc98SAlex Deucher u32 router_id; 40526b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 40626b5bc98SAlex Deucher u8 i2c_addr; 407fb939dfcSAlex Deucher /* i2c mux */ 408fb939dfcSAlex Deucher bool ddc_valid; 409fb939dfcSAlex Deucher u8 ddc_mux_type; 410fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 411fb939dfcSAlex Deucher u8 ddc_mux_state; 412fb939dfcSAlex Deucher /* clock/data mux */ 413fb939dfcSAlex Deucher bool cd_valid; 414fb939dfcSAlex Deucher u8 cd_mux_type; 415fb939dfcSAlex Deucher u8 cd_mux_control_pin; 416fb939dfcSAlex Deucher u8 cd_mux_state; 41726b5bc98SAlex Deucher }; 41826b5bc98SAlex Deucher 419771fe6b9SJerome Glisse struct radeon_connector { 420771fe6b9SJerome Glisse struct drm_connector base; 421771fe6b9SJerome Glisse uint32_t connector_id; 422771fe6b9SJerome Glisse uint32_t devices; 423771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4245b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4250294cf4fSAlex Deucher bool shared_ddc; 4264ce001abSDave Airlie bool use_digital; 4274ce001abSDave Airlie /* we need to mind the EDID between detect 4284ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4294ce001abSDave Airlie struct edid *edid; 430771fe6b9SJerome Glisse void *con_priv; 431445282dbSDave Airlie bool dac_load_detect; 432b75fad06SAlex Deucher uint16_t connector_object_id; 433eed45b30SAlex Deucher struct radeon_hpd hpd; 43426b5bc98SAlex Deucher struct radeon_router router; 43526b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 436771fe6b9SJerome Glisse }; 437771fe6b9SJerome Glisse 438771fe6b9SJerome Glisse struct radeon_framebuffer { 439771fe6b9SJerome Glisse struct drm_framebuffer base; 440771fe6b9SJerome Glisse struct drm_gem_object *obj; 441771fe6b9SJerome Glisse }; 442771fe6b9SJerome Glisse 4436383cf7dSMario Kleiner /* radeon_get_crtc_scanoutpos() return flags */ 4446383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_VALID (1 << 0) 4456383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_INVBL (1 << 1) 4466383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_ACCURATE (1 << 2) 4476383cf7dSMario Kleiner 448d79766faSAlex Deucher extern enum radeon_tv_std 449d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 450d79766faSAlex Deucher extern enum radeon_tv_std 451d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 452d79766faSAlex Deucher 4535b1714d3SAlex Deucher extern struct drm_connector * 4545b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 4555b1714d3SAlex Deucher 456d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 457d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 4585801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 4595801ead6SAlex Deucher struct drm_display_mode *mode); 4605801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 4615801ead6SAlex Deucher struct drm_display_mode *mode); 4625801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder, 4635801ead6SAlex Deucher struct drm_connector *connector); 4644143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 4659fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 466bcc1c2a1SAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); 4675801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 4685801ead6SAlex Deucher int action, uint8_t lane_num, 4695801ead6SAlex Deucher uint8_t lane_set); 470746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 471746c1aa4SDave Airlie uint8_t write_byte, uint8_t *read_byte); 472746c1aa4SDave Airlie 473f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 474f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 475f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 476f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 477f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 478f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 479f376b94fSAlex Deucher const char *name); 480f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 481f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 482746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 4836a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 4846a93cb25SAlex Deucher const char *name); 485771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 486771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 487771fe6b9SJerome Glisse const char *name); 488771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 4895a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 490fcec570bSAlex Deucher u8 slave_addr, 491fcec570bSAlex Deucher u8 addr, 492fcec570bSAlex Deucher u8 *val); 4935a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 494fcec570bSAlex Deucher u8 slave_addr, 495fcec570bSAlex Deucher u8 addr, 496fcec570bSAlex Deucher u8 val); 497fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 498fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 499771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 500771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 501771fe6b9SJerome Glisse 502771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 503771fe6b9SJerome Glisse 504ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 505ba032a58SAlex Deucher struct radeon_atom_ss *ss, 506ba032a58SAlex Deucher int id); 507ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 508ba032a58SAlex Deucher struct radeon_atom_ss *ss, 509ba032a58SAlex Deucher int id, u32 clock); 510ba032a58SAlex Deucher 511771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 512771fe6b9SJerome Glisse uint64_t freq, 513771fe6b9SJerome Glisse uint32_t *dot_clock_p, 514771fe6b9SJerome Glisse uint32_t *fb_div_p, 515771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 516771fe6b9SJerome Glisse uint32_t *ref_div_p, 517fc10332bSAlex Deucher uint32_t *post_div_p); 518771fe6b9SJerome Glisse 5191f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 5201f3b6a45SDave Airlie 521771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 522771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 523771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 524771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 525771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 526771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 52732f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 528771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 5294ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 530771fe6b9SJerome Glisse 531771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 532771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 533771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 5344dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 5354dd19b0dSChris Ball struct drm_framebuffer *fb, 53621c74a8eSJason Wessel int x, int y, 53721c74a8eSJason Wessel enum mode_set_atomic state); 538771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 539771fe6b9SJerome Glisse struct drm_display_mode *mode, 540771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 541771fe6b9SJerome Glisse int x, int y, 542771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 543771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 544771fe6b9SJerome Glisse 545771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 546771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 5474dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 5484dd19b0dSChris Ball struct drm_framebuffer *fb, 54921c74a8eSJason Wessel int x, int y, 55021c74a8eSJason Wessel enum mode_set_atomic state); 5514dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 5524dd19b0dSChris Ball struct drm_framebuffer *fb, 5534dd19b0dSChris Ball int x, int y, int atomic); 554771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 555771fe6b9SJerome Glisse struct drm_file *file_priv, 556771fe6b9SJerome Glisse uint32_t handle, 557771fe6b9SJerome Glisse uint32_t width, 558771fe6b9SJerome Glisse uint32_t height); 559771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 560771fe6b9SJerome Glisse int x, int y); 561771fe6b9SJerome Glisse 5626383cf7dSMario Kleiner extern int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos); 5636383cf7dSMario Kleiner 5643c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 5653c537889SAlex Deucher extern struct edid * 5663c537889SAlex Deucher radeon_combios_get_hardcoded_edid(struct radeon_device *rdev); 567771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 568771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 569771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 570771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 571fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 572445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 573fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 574445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 575fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 576445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 577fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 578fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 579fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 580fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 5816fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 5826fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 5836fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 5846fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 585771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 586771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 587771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 588771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 589771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 590771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 591771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 592fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 593fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 594771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 595771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 596771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 597771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 598f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 599f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 600771fe6b9SJerome Glisse extern void 601771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 602771fe6b9SJerome Glisse extern void 603771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 604771fe6b9SJerome Glisse extern void 605771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 606771fe6b9SJerome Glisse extern void 607771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 608771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 609771fe6b9SJerome Glisse u16 blue, int regno); 610b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 611b8c00ac5SDave Airlie u16 *blue, int regno); 61238651674SDave Airlie void radeon_framebuffer_init(struct drm_device *dev, 61338651674SDave Airlie struct radeon_framebuffer *rfb, 614771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 615771fe6b9SJerome Glisse struct drm_gem_object *obj); 616771fe6b9SJerome Glisse 617771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 618771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 619771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 620771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 621771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 622771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 623771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 624771fe6b9SJerome Glisse 625771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 626771fe6b9SJerome Glisse 627771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 628771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 629771fe6b9SJerome Glisse 630771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 631771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 632771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 633c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 634c93bb85bSJerome Glisse struct drm_display_mode *mode, 635c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 6363515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 6373515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 6384ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 639771fe6b9SJerome Glisse 6404ce001abSDave Airlie /* legacy tv */ 6414ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 6424ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 6434ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 6444ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 6454ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 6464ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 6474ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 6484ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 6494ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 6504ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 6514ce001abSDave Airlie struct drm_display_mode *mode, 6524ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 65338651674SDave Airlie 65438651674SDave Airlie /* fbdev layer */ 65538651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 65638651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 65738651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 65838651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 65938651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 660eb1f8e4fSDave Airlie 661eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 662771fe6b9SJerome Glisse #endif 663