1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 3768adac5eSBen Skeggs #include <drm_fixed.h> 3821c74a8eSJason Wessel #include <drm_crtc_helper.h> 39771fe6b9SJerome Glisse #include <linux/i2c.h> 40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 41c93bb85bSJerome Glisse 4238651674SDave Airlie struct radeon_bo; 43c93bb85bSJerome Glisse struct radeon_device; 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49771fe6b9SJerome Glisse 50771fe6b9SJerome Glisse enum radeon_rmx_type { 51771fe6b9SJerome Glisse RMX_OFF, 52771fe6b9SJerome Glisse RMX_FULL, 53771fe6b9SJerome Glisse RMX_CENTER, 54771fe6b9SJerome Glisse RMX_ASPECT 55771fe6b9SJerome Glisse }; 56771fe6b9SJerome Glisse 57771fe6b9SJerome Glisse enum radeon_tv_std { 58771fe6b9SJerome Glisse TV_STD_NTSC, 59771fe6b9SJerome Glisse TV_STD_PAL, 60771fe6b9SJerome Glisse TV_STD_PAL_M, 61771fe6b9SJerome Glisse TV_STD_PAL_60, 62771fe6b9SJerome Glisse TV_STD_NTSC_J, 63771fe6b9SJerome Glisse TV_STD_SCART_PAL, 64771fe6b9SJerome Glisse TV_STD_SECAM, 65771fe6b9SJerome Glisse TV_STD_PAL_CN, 66d79766faSAlex Deucher TV_STD_PAL_N, 67771fe6b9SJerome Glisse }; 68771fe6b9SJerome Glisse 695b1714d3SAlex Deucher enum radeon_underscan_type { 705b1714d3SAlex Deucher UNDERSCAN_OFF, 715b1714d3SAlex Deucher UNDERSCAN_ON, 725b1714d3SAlex Deucher UNDERSCAN_AUTO, 735b1714d3SAlex Deucher }; 745b1714d3SAlex Deucher 758e36ed00SAlex Deucher enum radeon_hpd_id { 768e36ed00SAlex Deucher RADEON_HPD_1 = 0, 778e36ed00SAlex Deucher RADEON_HPD_2, 788e36ed00SAlex Deucher RADEON_HPD_3, 798e36ed00SAlex Deucher RADEON_HPD_4, 808e36ed00SAlex Deucher RADEON_HPD_5, 818e36ed00SAlex Deucher RADEON_HPD_6, 828e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 838e36ed00SAlex Deucher }; 848e36ed00SAlex Deucher 85f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 86f376b94fSAlex Deucher 879b9fe724SAlex Deucher /* radeon gpio-based i2c 889b9fe724SAlex Deucher * 1. "mask" reg and bits 899b9fe724SAlex Deucher * grabs the gpio pins for software use 909b9fe724SAlex Deucher * 0=not held 1=held 919b9fe724SAlex Deucher * 2. "a" reg and bits 929b9fe724SAlex Deucher * output pin value 939b9fe724SAlex Deucher * 0=low 1=high 949b9fe724SAlex Deucher * 3. "en" reg and bits 959b9fe724SAlex Deucher * sets the pin direction 969b9fe724SAlex Deucher * 0=input 1=output 979b9fe724SAlex Deucher * 4. "y" reg and bits 989b9fe724SAlex Deucher * input pin value 999b9fe724SAlex Deucher * 0=low 1=high 1009b9fe724SAlex Deucher */ 101771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 102771fe6b9SJerome Glisse bool valid; 1036a93cb25SAlex Deucher /* id used by atom */ 1046a93cb25SAlex Deucher uint8_t i2c_id; 105bcc1c2a1SAlex Deucher /* id used by atom */ 1068e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1076a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1086a93cb25SAlex Deucher bool hw_capable; 1096a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1106a93cb25SAlex Deucher bool mm_i2c; 1116a93cb25SAlex Deucher /* regs and bits */ 112771fe6b9SJerome Glisse uint32_t mask_clk_reg; 113771fe6b9SJerome Glisse uint32_t mask_data_reg; 114771fe6b9SJerome Glisse uint32_t a_clk_reg; 115771fe6b9SJerome Glisse uint32_t a_data_reg; 1169b9fe724SAlex Deucher uint32_t en_clk_reg; 1179b9fe724SAlex Deucher uint32_t en_data_reg; 1189b9fe724SAlex Deucher uint32_t y_clk_reg; 1199b9fe724SAlex Deucher uint32_t y_data_reg; 120771fe6b9SJerome Glisse uint32_t mask_clk_mask; 121771fe6b9SJerome Glisse uint32_t mask_data_mask; 122771fe6b9SJerome Glisse uint32_t a_clk_mask; 123771fe6b9SJerome Glisse uint32_t a_data_mask; 1249b9fe724SAlex Deucher uint32_t en_clk_mask; 1259b9fe724SAlex Deucher uint32_t en_data_mask; 1269b9fe724SAlex Deucher uint32_t y_clk_mask; 1279b9fe724SAlex Deucher uint32_t y_data_mask; 128771fe6b9SJerome Glisse }; 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse struct radeon_tmds_pll { 131771fe6b9SJerome Glisse uint32_t freq; 132771fe6b9SJerome Glisse uint32_t value; 133771fe6b9SJerome Glisse }; 134771fe6b9SJerome Glisse 135771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 136771fe6b9SJerome Glisse 1377c27f87dSAlex Deucher /* pll flags */ 138771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 141771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15186cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 152f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 153771fe6b9SJerome Glisse 154771fe6b9SJerome Glisse struct radeon_pll { 155fc10332bSAlex Deucher /* reference frequency */ 156fc10332bSAlex Deucher uint32_t reference_freq; 157fc10332bSAlex Deucher 158fc10332bSAlex Deucher /* fixed dividers */ 159fc10332bSAlex Deucher uint32_t reference_div; 160fc10332bSAlex Deucher uint32_t post_div; 161fc10332bSAlex Deucher 162fc10332bSAlex Deucher /* pll in/out limits */ 163771fe6b9SJerome Glisse uint32_t pll_in_min; 164771fe6b9SJerome Glisse uint32_t pll_in_max; 165771fe6b9SJerome Glisse uint32_t pll_out_min; 166771fe6b9SJerome Glisse uint32_t pll_out_max; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16886cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 169fc10332bSAlex Deucher uint32_t best_vco; 170771fe6b9SJerome Glisse 171fc10332bSAlex Deucher /* divider limits */ 172771fe6b9SJerome Glisse uint32_t min_ref_div; 173771fe6b9SJerome Glisse uint32_t max_ref_div; 174771fe6b9SJerome Glisse uint32_t min_post_div; 175771fe6b9SJerome Glisse uint32_t max_post_div; 176771fe6b9SJerome Glisse uint32_t min_feedback_div; 177771fe6b9SJerome Glisse uint32_t max_feedback_div; 178771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 179771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 180fc10332bSAlex Deucher 181fc10332bSAlex Deucher /* flags for the current clock */ 182fc10332bSAlex Deucher uint32_t flags; 183fc10332bSAlex Deucher 184fc10332bSAlex Deucher /* pll id */ 185fc10332bSAlex Deucher uint32_t id; 186771fe6b9SJerome Glisse }; 187771fe6b9SJerome Glisse 188771fe6b9SJerome Glisse struct radeon_i2c_chan { 189771fe6b9SJerome Glisse struct i2c_adapter adapter; 190746c1aa4SDave Airlie struct drm_device *dev; 191746c1aa4SDave Airlie union { 192ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 193746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 194746c1aa4SDave Airlie } algo; 195771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 196771fe6b9SJerome Glisse }; 197771fe6b9SJerome Glisse 198771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 199771fe6b9SJerome Glisse enum radeon_connector_table { 200aa74fbb4SAlex Deucher CT_NONE = 0, 201771fe6b9SJerome Glisse CT_GENERIC, 202771fe6b9SJerome Glisse CT_IBOOK, 203771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 205771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 206771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 207771fe6b9SJerome Glisse CT_MINI_INTERNAL, 208771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 209771fe6b9SJerome Glisse CT_EMAC, 21076a7142aSDave Airlie CT_RN50_POWER, 211aa74fbb4SAlex Deucher CT_MAC_X800, 2129fad321aSAlex Deucher CT_MAC_G5_9600, 213771fe6b9SJerome Glisse }; 214771fe6b9SJerome Glisse 215fcec570bSAlex Deucher enum radeon_dvo_chip { 216fcec570bSAlex Deucher DVO_SIL164, 217fcec570bSAlex Deucher DVO_SIL1178, 218fcec570bSAlex Deucher }; 219fcec570bSAlex Deucher 2208be48d92SDave Airlie struct radeon_fbdev; 22138651674SDave Airlie 222771fe6b9SJerome Glisse struct radeon_mode_info { 223771fe6b9SJerome Glisse struct atom_context *atom_context; 22461c4b24bSMathias Fröhlich struct card_info *atom_card_info; 225771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 226771fe6b9SJerome Glisse bool mode_config_initialized; 227bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 228445282dbSDave Airlie /* DVI-I properties */ 229445282dbSDave Airlie struct drm_property *coherent_mode_property; 230445282dbSDave Airlie /* DAC enable load detect */ 231445282dbSDave Airlie struct drm_property *load_detect_property; 2325b1714d3SAlex Deucher /* TV standard */ 233445282dbSDave Airlie struct drm_property *tv_std_property; 234445282dbSDave Airlie /* legacy TMDS PLL detect */ 235445282dbSDave Airlie struct drm_property *tmds_pll_property; 2365b1714d3SAlex Deucher /* underscan */ 2375b1714d3SAlex Deucher struct drm_property *underscan_property; 2385bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2395bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2403c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2413c537889SAlex Deucher struct edid *bios_hardcoded_edid; 242fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 24338651674SDave Airlie 24438651674SDave Airlie /* pointer to fbdev info structure */ 2458be48d92SDave Airlie struct radeon_fbdev *rfbdev; 246c93bb85bSJerome Glisse }; 247c93bb85bSJerome Glisse 2484ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2494ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2504ce001abSDave Airlie 2514ce001abSDave Airlie /* need to store these as reading 2524ce001abSDave Airlie back code tables is excessive */ 2534ce001abSDave Airlie struct radeon_tv_regs { 2544ce001abSDave Airlie uint32_t tv_uv_adr; 2554ce001abSDave Airlie uint32_t timing_cntl; 2564ce001abSDave Airlie uint32_t hrestart; 2574ce001abSDave Airlie uint32_t vrestart; 2584ce001abSDave Airlie uint32_t frestart; 2594ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2604ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2614ce001abSDave Airlie }; 2624ce001abSDave Airlie 263771fe6b9SJerome Glisse struct radeon_crtc { 264771fe6b9SJerome Glisse struct drm_crtc base; 265771fe6b9SJerome Glisse int crtc_id; 266771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 267771fe6b9SJerome Glisse bool enabled; 268771fe6b9SJerome Glisse bool can_tile; 269771fe6b9SJerome Glisse uint32_t crtc_offset; 270771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 271771fe6b9SJerome Glisse uint64_t cursor_addr; 272771fe6b9SJerome Glisse int cursor_width; 273771fe6b9SJerome Glisse int cursor_height; 2744162338aSDave Airlie uint32_t legacy_display_base_addr; 275c836e862SAlex Deucher uint32_t legacy_cursor_offset; 276c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 2775b1714d3SAlex Deucher u8 h_border; 2785b1714d3SAlex Deucher u8 v_border; 279c93bb85bSJerome Glisse fixed20_12 vsc; 280c93bb85bSJerome Glisse fixed20_12 hsc; 281de2103e4SAlex Deucher struct drm_display_mode native_mode; 282bcc1c2a1SAlex Deucher int pll_id; 2836f34be50SAlex Deucher /* page flipping */ 2846f34be50SAlex Deucher struct radeon_unpin_work *unpin_work; 2856f34be50SAlex Deucher int deferred_flip_completion; 286771fe6b9SJerome Glisse }; 287771fe6b9SJerome Glisse 288771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 289771fe6b9SJerome Glisse /* legacy primary dac */ 290771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 291771fe6b9SJerome Glisse }; 292771fe6b9SJerome Glisse 293771fe6b9SJerome Glisse struct radeon_encoder_lvds { 294771fe6b9SJerome Glisse /* legacy lvds */ 295771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 296771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 297771fe6b9SJerome Glisse uint8_t panel_digon_delay; 298771fe6b9SJerome Glisse uint8_t panel_blon_delay; 299771fe6b9SJerome Glisse uint16_t panel_ref_divider; 300771fe6b9SJerome Glisse uint8_t panel_post_divider; 301771fe6b9SJerome Glisse uint16_t panel_fb_divider; 302771fe6b9SJerome Glisse bool use_bios_dividers; 303771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 304771fe6b9SJerome Glisse /* panel mode */ 305de2103e4SAlex Deucher struct drm_display_mode native_mode; 306771fe6b9SJerome Glisse }; 307771fe6b9SJerome Glisse 308771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 309771fe6b9SJerome Glisse /* legacy tv dac */ 310771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 311771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 312771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 313771fe6b9SJerome Glisse 3144ce001abSDave Airlie int h_pos; 3154ce001abSDave Airlie int v_pos; 3164ce001abSDave Airlie int h_size; 3174ce001abSDave Airlie int supported_tv_stds; 3184ce001abSDave Airlie bool tv_on; 319771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3204ce001abSDave Airlie struct radeon_tv_regs tv; 321771fe6b9SJerome Glisse }; 322771fe6b9SJerome Glisse 323771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 324771fe6b9SJerome Glisse /* legacy int tmds */ 325771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 326771fe6b9SJerome Glisse }; 327771fe6b9SJerome Glisse 328fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 329fcec570bSAlex Deucher /* tmds over dvo */ 330fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 331fcec570bSAlex Deucher uint8_t slave_addr; 332fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 333fcec570bSAlex Deucher }; 334fcec570bSAlex Deucher 335ebbe1cb9SAlex Deucher /* spread spectrum */ 336ebbe1cb9SAlex Deucher struct radeon_atom_ss { 337ebbe1cb9SAlex Deucher uint16_t percentage; 338ebbe1cb9SAlex Deucher uint8_t type; 339ba032a58SAlex Deucher uint16_t step; 340ebbe1cb9SAlex Deucher uint8_t delay; 341ebbe1cb9SAlex Deucher uint8_t range; 342ebbe1cb9SAlex Deucher uint8_t refdiv; 343ba032a58SAlex Deucher /* asic_ss */ 344ba032a58SAlex Deucher uint16_t rate; 345ba032a58SAlex Deucher uint16_t amount; 346ebbe1cb9SAlex Deucher }; 347ebbe1cb9SAlex Deucher 348771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3495137ee94SAlex Deucher bool linkb; 350771fe6b9SJerome Glisse /* atom dig */ 351771fe6b9SJerome Glisse bool coherent_mode; 352ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 353ba032a58SAlex Deucher /* atom lvds/edp */ 354ba032a58SAlex Deucher uint32_t lcd_misc; 355771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 356ba032a58SAlex Deucher uint32_t lcd_ss_id; 357771fe6b9SJerome Glisse /* panel mode */ 358de2103e4SAlex Deucher struct drm_display_mode native_mode; 359771fe6b9SJerome Glisse }; 360771fe6b9SJerome Glisse 3614ce001abSDave Airlie struct radeon_encoder_atom_dac { 3624ce001abSDave Airlie enum radeon_tv_std tv_std; 3634ce001abSDave Airlie }; 3644ce001abSDave Airlie 365771fe6b9SJerome Glisse struct radeon_encoder { 366771fe6b9SJerome Glisse struct drm_encoder base; 3675137ee94SAlex Deucher uint32_t encoder_enum; 368771fe6b9SJerome Glisse uint32_t encoder_id; 369771fe6b9SJerome Glisse uint32_t devices; 3704ce001abSDave Airlie uint32_t active_device; 371771fe6b9SJerome Glisse uint32_t flags; 372771fe6b9SJerome Glisse uint32_t pixel_clock; 373771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 3745b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 3755bccf5e3SMarius Gröger uint32_t underscan_hborder; 3765bccf5e3SMarius Gröger uint32_t underscan_vborder; 377de2103e4SAlex Deucher struct drm_display_mode native_mode; 378771fe6b9SJerome Glisse void *enc_priv; 37958bd0863SChristian König int audio_polling_active; 380dafc3bd5SChristian Koenig int hdmi_offset; 381808032eeSRafał Miłecki int hdmi_config_offset; 382dafc3bd5SChristian Koenig int hdmi_audio_workaround; 383dafc3bd5SChristian Koenig int hdmi_buffer_status; 3843e4b9982SAlex Deucher bool is_ext_encoder; 38536868bdaSAlex Deucher u16 caps; 386771fe6b9SJerome Glisse }; 387771fe6b9SJerome Glisse 388771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 389771fe6b9SJerome Glisse uint32_t igp_lane_info; 3904143e919SAlex Deucher /* displayport */ 391746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 3921a66c95aSAlex Deucher u8 dpcd[8]; 3934143e919SAlex Deucher u8 dp_sink_type; 3945801ead6SAlex Deucher int dp_clock; 3955801ead6SAlex Deucher int dp_lane_count; 3968b834852SAlex Deucher bool edp_on; 397771fe6b9SJerome Glisse }; 398771fe6b9SJerome Glisse 399eed45b30SAlex Deucher struct radeon_gpio_rec { 400eed45b30SAlex Deucher bool valid; 401eed45b30SAlex Deucher u8 id; 402eed45b30SAlex Deucher u32 reg; 403eed45b30SAlex Deucher u32 mask; 404eed45b30SAlex Deucher }; 405eed45b30SAlex Deucher 406eed45b30SAlex Deucher struct radeon_hpd { 407eed45b30SAlex Deucher enum radeon_hpd_id hpd; 408eed45b30SAlex Deucher u8 plugged_state; 409eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 410eed45b30SAlex Deucher }; 411eed45b30SAlex Deucher 41226b5bc98SAlex Deucher struct radeon_router { 41326b5bc98SAlex Deucher u32 router_id; 41426b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 41526b5bc98SAlex Deucher u8 i2c_addr; 416fb939dfcSAlex Deucher /* i2c mux */ 417fb939dfcSAlex Deucher bool ddc_valid; 418fb939dfcSAlex Deucher u8 ddc_mux_type; 419fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 420fb939dfcSAlex Deucher u8 ddc_mux_state; 421fb939dfcSAlex Deucher /* clock/data mux */ 422fb939dfcSAlex Deucher bool cd_valid; 423fb939dfcSAlex Deucher u8 cd_mux_type; 424fb939dfcSAlex Deucher u8 cd_mux_control_pin; 425fb939dfcSAlex Deucher u8 cd_mux_state; 42626b5bc98SAlex Deucher }; 42726b5bc98SAlex Deucher 428771fe6b9SJerome Glisse struct radeon_connector { 429771fe6b9SJerome Glisse struct drm_connector base; 430771fe6b9SJerome Glisse uint32_t connector_id; 431771fe6b9SJerome Glisse uint32_t devices; 432771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4335b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4340294cf4fSAlex Deucher bool shared_ddc; 4354ce001abSDave Airlie bool use_digital; 4364ce001abSDave Airlie /* we need to mind the EDID between detect 4374ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4384ce001abSDave Airlie struct edid *edid; 439771fe6b9SJerome Glisse void *con_priv; 440445282dbSDave Airlie bool dac_load_detect; 441b75fad06SAlex Deucher uint16_t connector_object_id; 442eed45b30SAlex Deucher struct radeon_hpd hpd; 44326b5bc98SAlex Deucher struct radeon_router router; 44426b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 445771fe6b9SJerome Glisse }; 446771fe6b9SJerome Glisse 447771fe6b9SJerome Glisse struct radeon_framebuffer { 448771fe6b9SJerome Glisse struct drm_framebuffer base; 449771fe6b9SJerome Glisse struct drm_gem_object *obj; 450771fe6b9SJerome Glisse }; 451771fe6b9SJerome Glisse 4526383cf7dSMario Kleiner 453d79766faSAlex Deucher extern enum radeon_tv_std 454d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 455d79766faSAlex Deucher extern enum radeon_tv_std 456d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 457d79766faSAlex Deucher 4585b1714d3SAlex Deucher extern struct drm_connector * 4595b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 4605b1714d3SAlex Deucher 461d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 462d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 4635801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 4645801ead6SAlex Deucher struct drm_display_mode *mode); 4655801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 4665801ead6SAlex Deucher struct drm_display_mode *mode); 4675801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder, 4685801ead6SAlex Deucher struct drm_connector *connector); 4694143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 4709fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 471bcc1c2a1SAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); 4725801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 4735801ead6SAlex Deucher int action, uint8_t lane_num, 4745801ead6SAlex Deucher uint8_t lane_set); 475746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 476746c1aa4SDave Airlie uint8_t write_byte, uint8_t *read_byte); 477746c1aa4SDave Airlie 478f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 479f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 480f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 481f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 482f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 483f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 484f376b94fSAlex Deucher const char *name); 485f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 486f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 487746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 4886a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 4896a93cb25SAlex Deucher const char *name); 490771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 491771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 492771fe6b9SJerome Glisse const char *name); 493771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 4945a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 495fcec570bSAlex Deucher u8 slave_addr, 496fcec570bSAlex Deucher u8 addr, 497fcec570bSAlex Deucher u8 *val); 4985a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 499fcec570bSAlex Deucher u8 slave_addr, 500fcec570bSAlex Deucher u8 addr, 501fcec570bSAlex Deucher u8 val); 502fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 503fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 504771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 505771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 506771fe6b9SJerome Glisse 507771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 508771fe6b9SJerome Glisse 509ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 510ba032a58SAlex Deucher struct radeon_atom_ss *ss, 511ba032a58SAlex Deucher int id); 512ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 513ba032a58SAlex Deucher struct radeon_atom_ss *ss, 514ba032a58SAlex Deucher int id, u32 clock); 515ba032a58SAlex Deucher 516f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 517771fe6b9SJerome Glisse uint64_t freq, 518771fe6b9SJerome Glisse uint32_t *dot_clock_p, 519771fe6b9SJerome Glisse uint32_t *fb_div_p, 520771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 521771fe6b9SJerome Glisse uint32_t *ref_div_p, 522fc10332bSAlex Deucher uint32_t *post_div_p); 523771fe6b9SJerome Glisse 524f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 525f523f74eSAlex Deucher u32 freq, 526f523f74eSAlex Deucher u32 *dot_clock_p, 527f523f74eSAlex Deucher u32 *fb_div_p, 528f523f74eSAlex Deucher u32 *frac_fb_div_p, 529f523f74eSAlex Deucher u32 *ref_div_p, 530f523f74eSAlex Deucher u32 *post_div_p); 531f523f74eSAlex Deucher 5321f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 5331f3b6a45SDave Airlie 534771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 535771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 536771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 537771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 538771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 53999999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 54032f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 541771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 5428b834852SAlex Deucher extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action); 5434ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 544771fe6b9SJerome Glisse 545771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 546771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 547771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 5484dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 5494dd19b0dSChris Ball struct drm_framebuffer *fb, 55021c74a8eSJason Wessel int x, int y, 55121c74a8eSJason Wessel enum mode_set_atomic state); 552771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 553771fe6b9SJerome Glisse struct drm_display_mode *mode, 554771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 555771fe6b9SJerome Glisse int x, int y, 556771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 557771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 558771fe6b9SJerome Glisse 559771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 560771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 5614dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 5624dd19b0dSChris Ball struct drm_framebuffer *fb, 56321c74a8eSJason Wessel int x, int y, 56421c74a8eSJason Wessel enum mode_set_atomic state); 5654dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 5664dd19b0dSChris Ball struct drm_framebuffer *fb, 5674dd19b0dSChris Ball int x, int y, int atomic); 568771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 569771fe6b9SJerome Glisse struct drm_file *file_priv, 570771fe6b9SJerome Glisse uint32_t handle, 571771fe6b9SJerome Glisse uint32_t width, 572771fe6b9SJerome Glisse uint32_t height); 573771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 574771fe6b9SJerome Glisse int x, int y); 575771fe6b9SJerome Glisse 576f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 577f5a80209SMario Kleiner int *vpos, int *hpos); 5786383cf7dSMario Kleiner 5793c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 5803c537889SAlex Deucher extern struct edid * 581c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 582771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 583771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 584771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 585771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 586fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 587445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 588fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 589445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 590fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 591445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 592fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 593fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 594fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 595fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 5966fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 5976fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 5986fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 5996fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 600771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 601771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 602771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 603771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 604771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 605771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 606771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 607fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 608fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 609771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 610771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 611771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 612771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 613f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 614f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 615771fe6b9SJerome Glisse extern void 616771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 617771fe6b9SJerome Glisse extern void 618771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 619771fe6b9SJerome Glisse extern void 620771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 621771fe6b9SJerome Glisse extern void 622771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 623771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 624771fe6b9SJerome Glisse u16 blue, int regno); 625b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 626b8c00ac5SDave Airlie u16 *blue, int regno); 62738651674SDave Airlie void radeon_framebuffer_init(struct drm_device *dev, 62838651674SDave Airlie struct radeon_framebuffer *rfb, 629771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 630771fe6b9SJerome Glisse struct drm_gem_object *obj); 631771fe6b9SJerome Glisse 632771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 633771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 634771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 635771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 636771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 637771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 638771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 639771fe6b9SJerome Glisse 640771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 641771fe6b9SJerome Glisse 642771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 643771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 644771fe6b9SJerome Glisse 645771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 646771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 647771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 648c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 649c93bb85bSJerome Glisse struct drm_display_mode *mode, 650c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 6513515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 6523515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 6534ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 654771fe6b9SJerome Glisse 6554ce001abSDave Airlie /* legacy tv */ 6564ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 6574ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 6584ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 6594ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 6604ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 6614ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 6624ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 6634ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 6644ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 6654ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 6664ce001abSDave Airlie struct drm_display_mode *mode, 6674ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 66838651674SDave Airlie 66938651674SDave Airlie /* fbdev layer */ 67038651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 67138651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 67238651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 67338651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 67438651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 675eb1f8e4fSDave Airlie 676eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 6776f34be50SAlex Deucher 6786f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 6796f34be50SAlex Deucher 680ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 681771fe6b9SJerome Glisse #endif 682