1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h> 34760285e7SDavid Howells #include <drm/drm_crtc.h> 35760285e7SDavid Howells #include <drm/drm_edid.h> 369338203cSLaurent Pinchart #include <drm/drm_encoder.h> 37760285e7SDavid Howells #include <drm/drm_fixed.h> 38*f7d17cd4SThomas Zimmermann #include <drm/drm_modeset_helper_vtables.h> 39771fe6b9SJerome Glisse #include <linux/i2c.h> 40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 41c93bb85bSJerome Glisse 4238651674SDave Airlie struct radeon_bo; 43c93bb85bSJerome Glisse struct radeon_device; 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48771fe6b9SJerome Glisse 4988f39063SStefan Brüns #define RADEON_MAX_HPD_PINS 7 5088f39063SStefan Brüns #define RADEON_MAX_CRTCS 6 5188f39063SStefan Brüns #define RADEON_MAX_AFMT_BLOCKS 7 5288f39063SStefan Brüns 53771fe6b9SJerome Glisse enum radeon_rmx_type { 54771fe6b9SJerome Glisse RMX_OFF, 55771fe6b9SJerome Glisse RMX_FULL, 56771fe6b9SJerome Glisse RMX_CENTER, 57771fe6b9SJerome Glisse RMX_ASPECT 58771fe6b9SJerome Glisse }; 59771fe6b9SJerome Glisse 60771fe6b9SJerome Glisse enum radeon_tv_std { 61771fe6b9SJerome Glisse TV_STD_NTSC, 62771fe6b9SJerome Glisse TV_STD_PAL, 63771fe6b9SJerome Glisse TV_STD_PAL_M, 64771fe6b9SJerome Glisse TV_STD_PAL_60, 65771fe6b9SJerome Glisse TV_STD_NTSC_J, 66771fe6b9SJerome Glisse TV_STD_SCART_PAL, 67771fe6b9SJerome Glisse TV_STD_SECAM, 68771fe6b9SJerome Glisse TV_STD_PAL_CN, 69d79766faSAlex Deucher TV_STD_PAL_N, 70771fe6b9SJerome Glisse }; 71771fe6b9SJerome Glisse 725b1714d3SAlex Deucher enum radeon_underscan_type { 735b1714d3SAlex Deucher UNDERSCAN_OFF, 745b1714d3SAlex Deucher UNDERSCAN_ON, 755b1714d3SAlex Deucher UNDERSCAN_AUTO, 765b1714d3SAlex Deucher }; 775b1714d3SAlex Deucher 788e36ed00SAlex Deucher enum radeon_hpd_id { 798e36ed00SAlex Deucher RADEON_HPD_1 = 0, 808e36ed00SAlex Deucher RADEON_HPD_2, 818e36ed00SAlex Deucher RADEON_HPD_3, 828e36ed00SAlex Deucher RADEON_HPD_4, 838e36ed00SAlex Deucher RADEON_HPD_5, 848e36ed00SAlex Deucher RADEON_HPD_6, 858e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 868e36ed00SAlex Deucher }; 878e36ed00SAlex Deucher 8867ba31d3SAlex Deucher enum radeon_output_csc { 8967ba31d3SAlex Deucher RADEON_OUTPUT_CSC_BYPASS = 0, 9067ba31d3SAlex Deucher RADEON_OUTPUT_CSC_TVRGB = 1, 9167ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR601 = 2, 9267ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR709 = 3, 9367ba31d3SAlex Deucher }; 9467ba31d3SAlex Deucher 95f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 96f376b94fSAlex Deucher 979b9fe724SAlex Deucher /* radeon gpio-based i2c 989b9fe724SAlex Deucher * 1. "mask" reg and bits 999b9fe724SAlex Deucher * grabs the gpio pins for software use 1009b9fe724SAlex Deucher * 0=not held 1=held 1019b9fe724SAlex Deucher * 2. "a" reg and bits 1029b9fe724SAlex Deucher * output pin value 1039b9fe724SAlex Deucher * 0=low 1=high 1049b9fe724SAlex Deucher * 3. "en" reg and bits 1059b9fe724SAlex Deucher * sets the pin direction 1069b9fe724SAlex Deucher * 0=input 1=output 1079b9fe724SAlex Deucher * 4. "y" reg and bits 1089b9fe724SAlex Deucher * input pin value 1099b9fe724SAlex Deucher * 0=low 1=high 1109b9fe724SAlex Deucher */ 111771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 112771fe6b9SJerome Glisse bool valid; 1136a93cb25SAlex Deucher /* id used by atom */ 1146a93cb25SAlex Deucher uint8_t i2c_id; 115bcc1c2a1SAlex Deucher /* id used by atom */ 1168e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1176a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1186a93cb25SAlex Deucher bool hw_capable; 1196a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1206a93cb25SAlex Deucher bool mm_i2c; 1216a93cb25SAlex Deucher /* regs and bits */ 122771fe6b9SJerome Glisse uint32_t mask_clk_reg; 123771fe6b9SJerome Glisse uint32_t mask_data_reg; 124771fe6b9SJerome Glisse uint32_t a_clk_reg; 125771fe6b9SJerome Glisse uint32_t a_data_reg; 1269b9fe724SAlex Deucher uint32_t en_clk_reg; 1279b9fe724SAlex Deucher uint32_t en_data_reg; 1289b9fe724SAlex Deucher uint32_t y_clk_reg; 1299b9fe724SAlex Deucher uint32_t y_data_reg; 130771fe6b9SJerome Glisse uint32_t mask_clk_mask; 131771fe6b9SJerome Glisse uint32_t mask_data_mask; 132771fe6b9SJerome Glisse uint32_t a_clk_mask; 133771fe6b9SJerome Glisse uint32_t a_data_mask; 1349b9fe724SAlex Deucher uint32_t en_clk_mask; 1359b9fe724SAlex Deucher uint32_t en_data_mask; 1369b9fe724SAlex Deucher uint32_t y_clk_mask; 1379b9fe724SAlex Deucher uint32_t y_data_mask; 138771fe6b9SJerome Glisse }; 139771fe6b9SJerome Glisse 140771fe6b9SJerome Glisse struct radeon_tmds_pll { 141771fe6b9SJerome Glisse uint32_t freq; 142771fe6b9SJerome Glisse uint32_t value; 143771fe6b9SJerome Glisse }; 144771fe6b9SJerome Glisse 145771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 146771fe6b9SJerome Glisse 1477c27f87dSAlex Deucher /* pll flags */ 148771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 149771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 150771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 151771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 152771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 153771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 154771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 155771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 156771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 157771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 158771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 159d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 160fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 16186cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 162f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 163771fe6b9SJerome Glisse 164771fe6b9SJerome Glisse struct radeon_pll { 165fc10332bSAlex Deucher /* reference frequency */ 166fc10332bSAlex Deucher uint32_t reference_freq; 167fc10332bSAlex Deucher 168fc10332bSAlex Deucher /* fixed dividers */ 169fc10332bSAlex Deucher uint32_t reference_div; 170fc10332bSAlex Deucher uint32_t post_div; 171fc10332bSAlex Deucher 172fc10332bSAlex Deucher /* pll in/out limits */ 173771fe6b9SJerome Glisse uint32_t pll_in_min; 174771fe6b9SJerome Glisse uint32_t pll_in_max; 175771fe6b9SJerome Glisse uint32_t pll_out_min; 176771fe6b9SJerome Glisse uint32_t pll_out_max; 17786cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 17886cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 179fc10332bSAlex Deucher uint32_t best_vco; 180771fe6b9SJerome Glisse 181fc10332bSAlex Deucher /* divider limits */ 182771fe6b9SJerome Glisse uint32_t min_ref_div; 183771fe6b9SJerome Glisse uint32_t max_ref_div; 184771fe6b9SJerome Glisse uint32_t min_post_div; 185771fe6b9SJerome Glisse uint32_t max_post_div; 186771fe6b9SJerome Glisse uint32_t min_feedback_div; 187771fe6b9SJerome Glisse uint32_t max_feedback_div; 188771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 189771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 190fc10332bSAlex Deucher 191fc10332bSAlex Deucher /* flags for the current clock */ 192fc10332bSAlex Deucher uint32_t flags; 193fc10332bSAlex Deucher 194fc10332bSAlex Deucher /* pll id */ 195fc10332bSAlex Deucher uint32_t id; 196771fe6b9SJerome Glisse }; 197771fe6b9SJerome Glisse 198771fe6b9SJerome Glisse struct radeon_i2c_chan { 199771fe6b9SJerome Glisse struct i2c_adapter adapter; 200746c1aa4SDave Airlie struct drm_device *dev; 201ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 202771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 203496263bfSAlex Deucher struct drm_dp_aux aux; 204379dfc25SAlex Deucher bool has_aux; 205831719d6SAlex Deucher struct mutex mutex; 206771fe6b9SJerome Glisse }; 207771fe6b9SJerome Glisse 208771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 209771fe6b9SJerome Glisse enum radeon_connector_table { 210aa74fbb4SAlex Deucher CT_NONE = 0, 211771fe6b9SJerome Glisse CT_GENERIC, 212771fe6b9SJerome Glisse CT_IBOOK, 213771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 214771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 215771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 216771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 217771fe6b9SJerome Glisse CT_MINI_INTERNAL, 218771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 219771fe6b9SJerome Glisse CT_EMAC, 22076a7142aSDave Airlie CT_RN50_POWER, 221aa74fbb4SAlex Deucher CT_MAC_X800, 2229fad321aSAlex Deucher CT_MAC_G5_9600, 223cafa59b9SAlex Deucher CT_SAM440EP, 224cafa59b9SAlex Deucher CT_MAC_G4_SILVER 225771fe6b9SJerome Glisse }; 226771fe6b9SJerome Glisse 227fcec570bSAlex Deucher enum radeon_dvo_chip { 228fcec570bSAlex Deucher DVO_SIL164, 229fcec570bSAlex Deucher DVO_SIL1178, 230fcec570bSAlex Deucher }; 231fcec570bSAlex Deucher 2328be48d92SDave Airlie struct radeon_fbdev; 23338651674SDave Airlie 2340783986aSAlex Deucher struct radeon_afmt { 2350783986aSAlex Deucher bool enabled; 2360783986aSAlex Deucher int offset; 2370783986aSAlex Deucher bool last_buffer_filled_status; 2380783986aSAlex Deucher int id; 2390783986aSAlex Deucher }; 2400783986aSAlex Deucher 241771fe6b9SJerome Glisse struct radeon_mode_info { 242771fe6b9SJerome Glisse struct atom_context *atom_context; 24361c4b24bSMathias Fröhlich struct card_info *atom_card_info; 244771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 245771fe6b9SJerome Glisse bool mode_config_initialized; 24688f39063SStefan Brüns struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 24788f39063SStefan Brüns struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 248445282dbSDave Airlie /* DVI-I properties */ 249445282dbSDave Airlie struct drm_property *coherent_mode_property; 250445282dbSDave Airlie /* DAC enable load detect */ 251445282dbSDave Airlie struct drm_property *load_detect_property; 2525b1714d3SAlex Deucher /* TV standard */ 253445282dbSDave Airlie struct drm_property *tv_std_property; 254445282dbSDave Airlie /* legacy TMDS PLL detect */ 255445282dbSDave Airlie struct drm_property *tmds_pll_property; 2565b1714d3SAlex Deucher /* underscan */ 2575b1714d3SAlex Deucher struct drm_property *underscan_property; 2585bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2595bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2608666c076SAlex Deucher /* audio */ 2618666c076SAlex Deucher struct drm_property *audio_property; 2626214bb74SAlex Deucher /* FMT dithering */ 2636214bb74SAlex Deucher struct drm_property *dither_property; 26467ba31d3SAlex Deucher /* Output CSC */ 26567ba31d3SAlex Deucher struct drm_property *output_csc_property; 2663c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2673c537889SAlex Deucher struct edid *bios_hardcoded_edid; 268fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 26938651674SDave Airlie 27038651674SDave Airlie /* pointer to fbdev info structure */ 2718be48d92SDave Airlie struct radeon_fbdev *rfbdev; 272af7912e5SAlex Deucher /* firmware flags */ 273af7912e5SAlex Deucher u16 firmware_flags; 274bced76f2SAlex Deucher /* pointer to backlight encoder */ 275bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 2768f0fc088SDave Airlie 2778f0fc088SDave Airlie /* bitmask for active encoder frontends */ 2788f0fc088SDave Airlie uint32_t active_encoders; 279c93bb85bSJerome Glisse }; 280c93bb85bSJerome Glisse 28191030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 28291030880SAlex Deucher 28391030880SAlex Deucher struct radeon_backlight_privdata { 28491030880SAlex Deucher struct radeon_encoder *encoder; 28591030880SAlex Deucher uint8_t negative; 28691030880SAlex Deucher }; 28791030880SAlex Deucher 2884ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2894ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2904ce001abSDave Airlie 2914ce001abSDave Airlie /* need to store these as reading 2924ce001abSDave Airlie back code tables is excessive */ 2934ce001abSDave Airlie struct radeon_tv_regs { 2944ce001abSDave Airlie uint32_t tv_uv_adr; 2954ce001abSDave Airlie uint32_t timing_cntl; 2964ce001abSDave Airlie uint32_t hrestart; 2974ce001abSDave Airlie uint32_t vrestart; 2984ce001abSDave Airlie uint32_t frestart; 2994ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 3004ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 3014ce001abSDave Airlie }; 3024ce001abSDave Airlie 30319eca43eSAlex Deucher struct radeon_atom_ss { 30419eca43eSAlex Deucher uint16_t percentage; 30518f8f52bSAlex Deucher uint16_t percentage_divider; 30619eca43eSAlex Deucher uint8_t type; 30719eca43eSAlex Deucher uint16_t step; 30819eca43eSAlex Deucher uint8_t delay; 30919eca43eSAlex Deucher uint8_t range; 31019eca43eSAlex Deucher uint8_t refdiv; 31119eca43eSAlex Deucher /* asic_ss */ 31219eca43eSAlex Deucher uint16_t rate; 31319eca43eSAlex Deucher uint16_t amount; 31419eca43eSAlex Deucher }; 31519eca43eSAlex Deucher 316a2b6d3b3SMichel Dänzer enum radeon_flip_status { 317a2b6d3b3SMichel Dänzer RADEON_FLIP_NONE, 318a2b6d3b3SMichel Dänzer RADEON_FLIP_PENDING, 319a2b6d3b3SMichel Dänzer RADEON_FLIP_SUBMITTED 320a2b6d3b3SMichel Dänzer }; 321a2b6d3b3SMichel Dänzer 322771fe6b9SJerome Glisse struct radeon_crtc { 323771fe6b9SJerome Glisse struct drm_crtc base; 324771fe6b9SJerome Glisse int crtc_id; 325771fe6b9SJerome Glisse bool enabled; 326771fe6b9SJerome Glisse bool can_tile; 3276b16cf77SMichel Dänzer bool cursor_out_of_bounds; 328771fe6b9SJerome Glisse uint32_t crtc_offset; 329771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 330771fe6b9SJerome Glisse uint64_t cursor_addr; 33178b1a601SMichel Dänzer int cursor_x; 33278b1a601SMichel Dänzer int cursor_y; 33378b1a601SMichel Dänzer int cursor_hot_x; 33478b1a601SMichel Dänzer int cursor_hot_y; 335771fe6b9SJerome Glisse int cursor_width; 336771fe6b9SJerome Glisse int cursor_height; 3379e05fa1dSAlex Deucher int max_cursor_width; 3389e05fa1dSAlex Deucher int max_cursor_height; 3394162338aSDave Airlie uint32_t legacy_display_base_addr; 340c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3415b1714d3SAlex Deucher u8 h_border; 3425b1714d3SAlex Deucher u8 v_border; 343c93bb85bSJerome Glisse fixed20_12 vsc; 344c93bb85bSJerome Glisse fixed20_12 hsc; 345de2103e4SAlex Deucher struct drm_display_mode native_mode; 346bcc1c2a1SAlex Deucher int pll_id; 3476f34be50SAlex Deucher /* page flipping */ 348fa7f517cSChristian König struct workqueue_struct *flip_queue; 349fa7f517cSChristian König struct radeon_flip_work *flip_work; 350a2b6d3b3SMichel Dänzer enum radeon_flip_status flip_status; 35119eca43eSAlex Deucher /* pll sharing */ 35219eca43eSAlex Deucher struct radeon_atom_ss ss; 35319eca43eSAlex Deucher bool ss_enabled; 35419eca43eSAlex Deucher u32 adjusted_clock; 35519eca43eSAlex Deucher int bpc; 35619eca43eSAlex Deucher u32 pll_reference_div; 35719eca43eSAlex Deucher u32 pll_post_div; 35819eca43eSAlex Deucher u32 pll_flags; 3595df3196bSAlex Deucher struct drm_encoder *encoder; 36057b35e29SAlex Deucher struct drm_connector *connector; 3617178d2a6SAlex Deucher /* for dpm */ 3627178d2a6SAlex Deucher u32 line_time; 3637178d2a6SAlex Deucher u32 wm_low; 3647178d2a6SAlex Deucher u32 wm_high; 3655b5561b3SMario Kleiner u32 lb_vblank_lead_lines; 36666edc1c9SAlex Deucher struct drm_display_mode hw_mode; 367643b1f56SAlex Deucher enum radeon_output_csc output_csc; 368771fe6b9SJerome Glisse }; 369771fe6b9SJerome Glisse 370771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 371771fe6b9SJerome Glisse /* legacy primary dac */ 372771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 373771fe6b9SJerome Glisse }; 374771fe6b9SJerome Glisse 375771fe6b9SJerome Glisse struct radeon_encoder_lvds { 376771fe6b9SJerome Glisse /* legacy lvds */ 377771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 378771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 379771fe6b9SJerome Glisse uint8_t panel_digon_delay; 380771fe6b9SJerome Glisse uint8_t panel_blon_delay; 381771fe6b9SJerome Glisse uint16_t panel_ref_divider; 382771fe6b9SJerome Glisse uint8_t panel_post_divider; 383771fe6b9SJerome Glisse uint16_t panel_fb_divider; 384771fe6b9SJerome Glisse bool use_bios_dividers; 385771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 386771fe6b9SJerome Glisse /* panel mode */ 387de2103e4SAlex Deucher struct drm_display_mode native_mode; 38863ec0119SMichel Dänzer struct backlight_device *bl_dev; 38963ec0119SMichel Dänzer int dpms_mode; 39063ec0119SMichel Dänzer uint8_t backlight_level; 391771fe6b9SJerome Glisse }; 392771fe6b9SJerome Glisse 393771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 394771fe6b9SJerome Glisse /* legacy tv dac */ 395771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 396771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 397771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 398771fe6b9SJerome Glisse 3994ce001abSDave Airlie int h_pos; 4004ce001abSDave Airlie int v_pos; 4014ce001abSDave Airlie int h_size; 4024ce001abSDave Airlie int supported_tv_stds; 4034ce001abSDave Airlie bool tv_on; 404771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 4054ce001abSDave Airlie struct radeon_tv_regs tv; 406771fe6b9SJerome Glisse }; 407771fe6b9SJerome Glisse 408771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 409771fe6b9SJerome Glisse /* legacy int tmds */ 410771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 411771fe6b9SJerome Glisse }; 412771fe6b9SJerome Glisse 413fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 414fcec570bSAlex Deucher /* tmds over dvo */ 415fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 416fcec570bSAlex Deucher uint8_t slave_addr; 417fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 418fcec570bSAlex Deucher }; 419fcec570bSAlex Deucher 420ebbe1cb9SAlex Deucher /* spread spectrum */ 421771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 4225137ee94SAlex Deucher bool linkb; 423771fe6b9SJerome Glisse /* atom dig */ 424771fe6b9SJerome Glisse bool coherent_mode; 425ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 426ba032a58SAlex Deucher /* atom lvds/edp */ 427ba032a58SAlex Deucher uint32_t lcd_misc; 428771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 429ba032a58SAlex Deucher uint32_t lcd_ss_id; 430771fe6b9SJerome Glisse /* panel mode */ 431de2103e4SAlex Deucher struct drm_display_mode native_mode; 43263ec0119SMichel Dänzer struct backlight_device *bl_dev; 43363ec0119SMichel Dänzer int dpms_mode; 43463ec0119SMichel Dänzer uint8_t backlight_level; 435386d4d75SAlex Deucher int panel_mode; 4360783986aSAlex Deucher struct radeon_afmt *afmt; 437d0ea397eSAlex Deucher struct r600_audio_pin *pin; 438771fe6b9SJerome Glisse }; 439771fe6b9SJerome Glisse 4404ce001abSDave Airlie struct radeon_encoder_atom_dac { 4414ce001abSDave Airlie enum radeon_tv_std tv_std; 4424ce001abSDave Airlie }; 4434ce001abSDave Airlie 444771fe6b9SJerome Glisse struct radeon_encoder { 445771fe6b9SJerome Glisse struct drm_encoder base; 4465137ee94SAlex Deucher uint32_t encoder_enum; 447771fe6b9SJerome Glisse uint32_t encoder_id; 448771fe6b9SJerome Glisse uint32_t devices; 4494ce001abSDave Airlie uint32_t active_device; 450771fe6b9SJerome Glisse uint32_t flags; 451771fe6b9SJerome Glisse uint32_t pixel_clock; 452771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4535b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4545bccf5e3SMarius Gröger uint32_t underscan_hborder; 4555bccf5e3SMarius Gröger uint32_t underscan_vborder; 456de2103e4SAlex Deucher struct drm_display_mode native_mode; 457771fe6b9SJerome Glisse void *enc_priv; 45858bd0863SChristian König int audio_polling_active; 4593e4b9982SAlex Deucher bool is_ext_encoder; 46036868bdaSAlex Deucher u16 caps; 4611a626b68SSlava Grigorev struct radeon_audio_funcs *audio; 462643b1f56SAlex Deucher enum radeon_output_csc output_csc; 4639843ead0SDave Airlie bool can_mst; 4649843ead0SDave Airlie uint32_t offset; 465771fe6b9SJerome Glisse }; 466771fe6b9SJerome Glisse 467771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 468771fe6b9SJerome Glisse uint32_t igp_lane_info; 4694143e919SAlex Deucher /* displayport */ 4701a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4714143e919SAlex Deucher u8 dp_sink_type; 4725801ead6SAlex Deucher int dp_clock; 4735801ead6SAlex Deucher int dp_lane_count; 4748b834852SAlex Deucher bool edp_on; 475771fe6b9SJerome Glisse }; 476771fe6b9SJerome Glisse 477eed45b30SAlex Deucher struct radeon_gpio_rec { 478eed45b30SAlex Deucher bool valid; 479eed45b30SAlex Deucher u8 id; 480eed45b30SAlex Deucher u32 reg; 481eed45b30SAlex Deucher u32 mask; 482727b3d25SAlex Deucher u32 shift; 483eed45b30SAlex Deucher }; 484eed45b30SAlex Deucher 485eed45b30SAlex Deucher struct radeon_hpd { 486eed45b30SAlex Deucher enum radeon_hpd_id hpd; 487eed45b30SAlex Deucher u8 plugged_state; 488eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 489eed45b30SAlex Deucher }; 490eed45b30SAlex Deucher 49126b5bc98SAlex Deucher struct radeon_router { 49226b5bc98SAlex Deucher u32 router_id; 49326b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 49426b5bc98SAlex Deucher u8 i2c_addr; 495fb939dfcSAlex Deucher /* i2c mux */ 496fb939dfcSAlex Deucher bool ddc_valid; 497fb939dfcSAlex Deucher u8 ddc_mux_type; 498fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 499fb939dfcSAlex Deucher u8 ddc_mux_state; 500fb939dfcSAlex Deucher /* clock/data mux */ 501fb939dfcSAlex Deucher bool cd_valid; 502fb939dfcSAlex Deucher u8 cd_mux_type; 503fb939dfcSAlex Deucher u8 cd_mux_control_pin; 504fb939dfcSAlex Deucher u8 cd_mux_state; 50526b5bc98SAlex Deucher }; 50626b5bc98SAlex Deucher 5078666c076SAlex Deucher enum radeon_connector_audio { 5088666c076SAlex Deucher RADEON_AUDIO_DISABLE = 0, 5098666c076SAlex Deucher RADEON_AUDIO_ENABLE = 1, 5108666c076SAlex Deucher RADEON_AUDIO_AUTO = 2 5118666c076SAlex Deucher }; 5128666c076SAlex Deucher 5136214bb74SAlex Deucher enum radeon_connector_dither { 5146214bb74SAlex Deucher RADEON_FMT_DITHER_DISABLE = 0, 5156214bb74SAlex Deucher RADEON_FMT_DITHER_ENABLE = 1, 5166214bb74SAlex Deucher }; 5176214bb74SAlex Deucher 518771fe6b9SJerome Glisse struct radeon_connector { 519771fe6b9SJerome Glisse struct drm_connector base; 520771fe6b9SJerome Glisse uint32_t connector_id; 521771fe6b9SJerome Glisse uint32_t devices; 522771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 5235b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 5240294cf4fSAlex Deucher bool shared_ddc; 5254ce001abSDave Airlie bool use_digital; 5264ce001abSDave Airlie /* we need to mind the EDID between detect 5274ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 5284ce001abSDave Airlie struct edid *edid; 529771fe6b9SJerome Glisse void *con_priv; 530445282dbSDave Airlie bool dac_load_detect; 531d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 532cb5d4166SLyude bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 533b75fad06SAlex Deucher uint16_t connector_object_id; 534eed45b30SAlex Deucher struct radeon_hpd hpd; 53526b5bc98SAlex Deucher struct radeon_router router; 53626b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 5378666c076SAlex Deucher enum radeon_connector_audio audio; 5386214bb74SAlex Deucher enum radeon_connector_dither dither; 539ea292861SMario Kleiner int pixelclock_for_modeset; 540771fe6b9SJerome Glisse }; 541771fe6b9SJerome Glisse 542996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 543996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 5446383cf7dSMario Kleiner 5457062ab67SChristian König struct atom_clock_dividers { 5467062ab67SChristian König u32 post_div; 5477062ab67SChristian König union { 5487062ab67SChristian König struct { 5497062ab67SChristian König #ifdef __BIG_ENDIAN 5507062ab67SChristian König u32 reserved : 6; 5517062ab67SChristian König u32 whole_fb_div : 12; 5527062ab67SChristian König u32 frac_fb_div : 14; 5537062ab67SChristian König #else 5547062ab67SChristian König u32 frac_fb_div : 14; 5557062ab67SChristian König u32 whole_fb_div : 12; 5567062ab67SChristian König u32 reserved : 6; 5577062ab67SChristian König #endif 5587062ab67SChristian König }; 5597062ab67SChristian König u32 fb_div; 5607062ab67SChristian König }; 5617062ab67SChristian König u32 ref_div; 5627062ab67SChristian König bool enable_post_div; 5637062ab67SChristian König bool enable_dithen; 5647062ab67SChristian König u32 vco_mode; 5657062ab67SChristian König u32 real_clock; 5669219ed65SAlex Deucher /* added for CI */ 5679219ed65SAlex Deucher u32 post_divider; 5689219ed65SAlex Deucher u32 flags; 5697062ab67SChristian König }; 5707062ab67SChristian König 571eaa778afSAlex Deucher struct atom_mpll_param { 572eaa778afSAlex Deucher union { 573eaa778afSAlex Deucher struct { 574eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 575eaa778afSAlex Deucher u32 reserved : 8; 576eaa778afSAlex Deucher u32 clkfrac : 12; 577eaa778afSAlex Deucher u32 clkf : 12; 578eaa778afSAlex Deucher #else 579eaa778afSAlex Deucher u32 clkf : 12; 580eaa778afSAlex Deucher u32 clkfrac : 12; 581eaa778afSAlex Deucher u32 reserved : 8; 582eaa778afSAlex Deucher #endif 583eaa778afSAlex Deucher }; 584eaa778afSAlex Deucher u32 fb_div; 585eaa778afSAlex Deucher }; 586eaa778afSAlex Deucher u32 post_div; 587eaa778afSAlex Deucher u32 bwcntl; 588eaa778afSAlex Deucher u32 dll_speed; 589eaa778afSAlex Deucher u32 vco_mode; 590eaa778afSAlex Deucher u32 yclk_sel; 591eaa778afSAlex Deucher u32 qdr; 592eaa778afSAlex Deucher u32 half_rate; 593eaa778afSAlex Deucher }; 594eaa778afSAlex Deucher 595ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 596ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 597ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 598ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 599ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 600ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 601ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 602ae5b0abbSAlex Deucher 603ae5b0abbSAlex Deucher struct atom_memory_info { 604ae5b0abbSAlex Deucher u8 mem_vendor; 605ae5b0abbSAlex Deucher u8 mem_type; 606ae5b0abbSAlex Deucher }; 607ae5b0abbSAlex Deucher 608ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 609ae5b0abbSAlex Deucher 610ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 611ae5b0abbSAlex Deucher { 612ae5b0abbSAlex Deucher u8 num_entries; 613ae5b0abbSAlex Deucher u8 rsv[3]; 614ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 615ae5b0abbSAlex Deucher }; 616ae5b0abbSAlex Deucher 617ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 618ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 619ae5b0abbSAlex Deucher 620ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 621ae5b0abbSAlex Deucher u32 mclk_max; 622ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 623ae5b0abbSAlex Deucher }; 624ae5b0abbSAlex Deucher 625ae5b0abbSAlex Deucher struct atom_mc_register_address { 626ae5b0abbSAlex Deucher u16 s1; 627ae5b0abbSAlex Deucher u8 pre_reg_data; 628ae5b0abbSAlex Deucher }; 629ae5b0abbSAlex Deucher 630ae5b0abbSAlex Deucher struct atom_mc_reg_table { 631ae5b0abbSAlex Deucher u8 last; 632ae5b0abbSAlex Deucher u8 num_entries; 633ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 634ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 635ae5b0abbSAlex Deucher }; 636ae5b0abbSAlex Deucher 637ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 638ae5b0abbSAlex Deucher 639ae5b0abbSAlex Deucher struct atom_voltage_table_entry 640ae5b0abbSAlex Deucher { 641ae5b0abbSAlex Deucher u16 value; 642ae5b0abbSAlex Deucher u32 smio_low; 643ae5b0abbSAlex Deucher }; 644ae5b0abbSAlex Deucher 645ae5b0abbSAlex Deucher struct atom_voltage_table 646ae5b0abbSAlex Deucher { 647ae5b0abbSAlex Deucher u32 count; 648ae5b0abbSAlex Deucher u32 mask_low; 64965171944SAlex Deucher u32 phase_delay; 650ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 651ae5b0abbSAlex Deucher }; 652ae5b0abbSAlex Deucher 6535b5561b3SMario Kleiner /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 6541bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_VALID (1 << 0) 6551bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 6561bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 6575b5561b3SMario Kleiner #define USE_REAL_VBLANKSTART (1 << 30) 6585b5561b3SMario Kleiner #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 659a38eab52SRashika Kheria 660a38eab52SRashika Kheria extern void 661a38eab52SRashika Kheria radeon_add_atom_connector(struct drm_device *dev, 662a38eab52SRashika Kheria uint32_t connector_id, 663a38eab52SRashika Kheria uint32_t supported_device, 664a38eab52SRashika Kheria int connector_type, 665a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 666a38eab52SRashika Kheria uint32_t igp_lane_info, 667a38eab52SRashika Kheria uint16_t connector_object_id, 668a38eab52SRashika Kheria struct radeon_hpd *hpd, 669a38eab52SRashika Kheria struct radeon_router *router); 670a38eab52SRashika Kheria extern void 671a38eab52SRashika Kheria radeon_add_legacy_connector(struct drm_device *dev, 672a38eab52SRashika Kheria uint32_t connector_id, 673a38eab52SRashika Kheria uint32_t supported_device, 674a38eab52SRashika Kheria int connector_type, 675a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 676a38eab52SRashika Kheria uint16_t connector_object_id, 677a38eab52SRashika Kheria struct radeon_hpd *hpd); 6780091fc13SRashika Kheria extern uint32_t 6790091fc13SRashika Kheria radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 6800091fc13SRashika Kheria uint8_t dac); 6810091fc13SRashika Kheria extern void radeon_link_encoder_connector(struct drm_device *dev); 682a38eab52SRashika Kheria 683d79766faSAlex Deucher extern enum radeon_tv_std 684d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 685d79766faSAlex Deucher extern enum radeon_tv_std 686d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 6874a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 6882abba66eSAlex Deucher u16 *vddc, u16 *vddci, u16 *mvdd); 689d79766faSAlex Deucher 69084ac68e0SAlex Deucher extern void 69184ac68e0SAlex Deucher radeon_combios_connected_scratch_regs(struct drm_connector *connector, 69284ac68e0SAlex Deucher struct drm_encoder *encoder, 69384ac68e0SAlex Deucher bool connected); 69484ac68e0SAlex Deucher extern void 69584ac68e0SAlex Deucher radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 69684ac68e0SAlex Deucher struct drm_encoder *encoder, 69784ac68e0SAlex Deucher bool connected); 69884ac68e0SAlex Deucher 6995b1714d3SAlex Deucher extern struct drm_connector * 7005b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 7019aa59993SAlex Deucher extern struct drm_connector * 7029aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 7039aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 7049aa59993SAlex Deucher u32 pixel_clock); 7055b1714d3SAlex Deucher 7061d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 7071d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 708d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 709eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 710d7fa8bb3SAlex Deucher 711377bd8a9SAlex Deucher extern struct edid *radeon_connector_edid(struct drm_connector *connector); 712377bd8a9SAlex Deucher 713d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 714224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 7155801ead6SAlex Deucher struct drm_display_mode *mode); 7165801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 717e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 718224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 7195801ead6SAlex Deucher struct drm_connector *connector); 720d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 7214143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 7229fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 723386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 724386d4d75SAlex Deucher struct drm_connector *connector); 7252953da15SAlex Deucher extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 7262953da15SAlex Deucher u8 power_state); 727496263bfSAlex Deucher extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 728875711f0SDave Airlie extern ssize_t 729875711f0SDave Airlie radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 730875711f0SDave Airlie 731558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 732bf071900SDave Airlie extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 733ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 734f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 7355801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 7365801ead6SAlex Deucher int action, uint8_t lane_num, 7375801ead6SAlex Deucher uint8_t lane_set); 738bf071900SDave Airlie extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 739bf071900SDave Airlie int action, uint8_t lane_num, 740bf071900SDave Airlie uint8_t lane_set, int fe); 741591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 7423f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 7434cf3b494SRashika Kheria void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 744746c1aa4SDave Airlie 745f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 746f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 747f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 748f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 749f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 750f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 751f376b94fSAlex Deucher const char *name); 752f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 753f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 754771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 755771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 756771fe6b9SJerome Glisse const char *name); 757771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 7585a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 759fcec570bSAlex Deucher u8 slave_addr, 760fcec570bSAlex Deucher u8 addr, 761fcec570bSAlex Deucher u8 *val); 7625a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 763fcec570bSAlex Deucher u8 slave_addr, 764fcec570bSAlex Deucher u8 addr, 765fcec570bSAlex Deucher u8 val); 766fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 767fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 7680a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 769771fe6b9SJerome Glisse 770ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 771ba032a58SAlex Deucher struct radeon_atom_ss *ss, 772ba032a58SAlex Deucher int id); 773ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 774ba032a58SAlex Deucher struct radeon_atom_ss *ss, 775ba032a58SAlex Deucher int id, u32 clock); 77609e619c0SAlex Deucher extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 77709e619c0SAlex Deucher u8 id); 778ba032a58SAlex Deucher 779f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 780771fe6b9SJerome Glisse uint64_t freq, 781771fe6b9SJerome Glisse uint32_t *dot_clock_p, 782771fe6b9SJerome Glisse uint32_t *fb_div_p, 783771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 784771fe6b9SJerome Glisse uint32_t *ref_div_p, 785fc10332bSAlex Deucher uint32_t *post_div_p); 786771fe6b9SJerome Glisse 787f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 788f523f74eSAlex Deucher u32 freq, 789f523f74eSAlex Deucher u32 *dot_clock_p, 790f523f74eSAlex Deucher u32 *fb_div_p, 791f523f74eSAlex Deucher u32 *frac_fb_div_p, 792f523f74eSAlex Deucher u32 *ref_div_p, 793f523f74eSAlex Deucher u32 *post_div_p); 794f523f74eSAlex Deucher 7951f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 7961f3b6a45SDave Airlie 797771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 798771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 799771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 800771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 801771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 80299999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 80332f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 804771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 8052dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 8064ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 807d740a933SAlex Deucher extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 808771fe6b9SJerome Glisse 809771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 810771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 811771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8124dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 8134dd19b0dSChris Ball struct drm_framebuffer *fb, 81421c74a8eSJason Wessel int x, int y, 81521c74a8eSJason Wessel enum mode_set_atomic state); 816771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 817771fe6b9SJerome Glisse struct drm_display_mode *mode, 818771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 819771fe6b9SJerome Glisse int x, int y, 820771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 821771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 822771fe6b9SJerome Glisse 823771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 824771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8254dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 8264dd19b0dSChris Ball struct drm_framebuffer *fb, 82721c74a8eSJason Wessel int x, int y, 82821c74a8eSJason Wessel enum mode_set_atomic state); 8294dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 8304dd19b0dSChris Ball struct drm_framebuffer *fb, 8314dd19b0dSChris Ball int x, int y, int atomic); 83278b1a601SMichel Dänzer extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 833771fe6b9SJerome Glisse struct drm_file *file_priv, 834771fe6b9SJerome Glisse uint32_t handle, 835771fe6b9SJerome Glisse uint32_t width, 83678b1a601SMichel Dänzer uint32_t height, 83778b1a601SMichel Dänzer int32_t hot_x, 83878b1a601SMichel Dänzer int32_t hot_y); 839771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 840771fe6b9SJerome Glisse int x, int y); 8416d3759faSMichel Dänzer extern void radeon_cursor_reset(struct drm_crtc *crtc); 842771fe6b9SJerome Glisse 84388e72717SThierry Reding extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 84488e72717SThierry Reding unsigned int flags, int *vpos, int *hpos, 8453bb403bfSVille Syrjälä ktime_t *stime, ktime_t *etime, 8463bb403bfSVille Syrjälä const struct drm_display_mode *mode); 8476383cf7dSMario Kleiner 84827b4118dSThomas Zimmermann extern bool 84927b4118dSThomas Zimmermann radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, 85027b4118dSThomas Zimmermann int *vpos, int *hpos, 85127b4118dSThomas Zimmermann ktime_t *stime, ktime_t *etime, 85227b4118dSThomas Zimmermann const struct drm_display_mode *mode); 85327b4118dSThomas Zimmermann 8543c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 8553c537889SAlex Deucher extern struct edid * 856c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 857771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 858771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 859771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 860771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 861fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 862445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 863fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 864445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 865fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 866445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 867fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 868fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 869fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 870fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 8716fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 8726fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 8736fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 8746fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 875771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 876771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 877771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 878771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 879771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 880771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 881fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 882fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 883771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 884771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 885771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 886771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 887f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 888f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 889771fe6b9SJerome Glisse extern void 890771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 891771fe6b9SJerome Glisse extern void 892771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 893771fe6b9SJerome Glisse extern void 894771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 895771fe6b9SJerome Glisse extern void 896771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 897aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 8989a0f0c9dSDaniel Stone struct drm_framebuffer *rfb, 8991eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd, 900771fe6b9SJerome Glisse struct drm_gem_object *obj); 901771fe6b9SJerome Glisse 902771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 903771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 904771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 905771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 906771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 907771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 908771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 909771fe6b9SJerome Glisse 910771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 911771fe6b9SJerome Glisse 912771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 913771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 914771fe6b9SJerome Glisse 915771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 916771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 917771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 918c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 919e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 920c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 9213515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 9223515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 9234ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 924771fe6b9SJerome Glisse 9254ce001abSDave Airlie /* legacy tv */ 9264ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 9274ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 9284ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 9294ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 9304ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 9314ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 9324ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 9334ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 9344ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 9354ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 9364ce001abSDave Airlie struct drm_display_mode *mode, 9374ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 93838651674SDave Airlie 939134b480fSAlex Deucher /* fmt blocks */ 940134b480fSAlex Deucher void avivo_program_fmt(struct drm_encoder *encoder); 941134b480fSAlex Deucher void dce3_program_fmt(struct drm_encoder *encoder); 942134b480fSAlex Deucher void dce4_program_fmt(struct drm_encoder *encoder); 943134b480fSAlex Deucher void dce8_program_fmt(struct drm_encoder *encoder); 944134b480fSAlex Deucher 94538651674SDave Airlie /* fbdev layer */ 94638651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 94738651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 94838651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 94938651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 9506f34be50SAlex Deucher 9511a0e7918SChristian König void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 952bb26270eSDave Airlie 9536f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 9546f34be50SAlex Deucher 955ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 9568f0fc088SDave Airlie 9578f0fc088SDave Airlie int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 9588f0fc088SDave Airlie void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 959771fe6b9SJerome Glisse #endif 960