1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 35760285e7SDavid Howells #include <drm/drm_dp_helper.h> 36760285e7SDavid Howells #include <drm/drm_fixed.h> 37760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 38771fe6b9SJerome Glisse #include <linux/i2c.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse 4138651674SDave Airlie struct radeon_bo; 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_rmx_type { 50771fe6b9SJerome Glisse RMX_OFF, 51771fe6b9SJerome Glisse RMX_FULL, 52771fe6b9SJerome Glisse RMX_CENTER, 53771fe6b9SJerome Glisse RMX_ASPECT 54771fe6b9SJerome Glisse }; 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse enum radeon_tv_std { 57771fe6b9SJerome Glisse TV_STD_NTSC, 58771fe6b9SJerome Glisse TV_STD_PAL, 59771fe6b9SJerome Glisse TV_STD_PAL_M, 60771fe6b9SJerome Glisse TV_STD_PAL_60, 61771fe6b9SJerome Glisse TV_STD_NTSC_J, 62771fe6b9SJerome Glisse TV_STD_SCART_PAL, 63771fe6b9SJerome Glisse TV_STD_SECAM, 64771fe6b9SJerome Glisse TV_STD_PAL_CN, 65d79766faSAlex Deucher TV_STD_PAL_N, 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 685b1714d3SAlex Deucher enum radeon_underscan_type { 695b1714d3SAlex Deucher UNDERSCAN_OFF, 705b1714d3SAlex Deucher UNDERSCAN_ON, 715b1714d3SAlex Deucher UNDERSCAN_AUTO, 725b1714d3SAlex Deucher }; 735b1714d3SAlex Deucher 748e36ed00SAlex Deucher enum radeon_hpd_id { 758e36ed00SAlex Deucher RADEON_HPD_1 = 0, 768e36ed00SAlex Deucher RADEON_HPD_2, 778e36ed00SAlex Deucher RADEON_HPD_3, 788e36ed00SAlex Deucher RADEON_HPD_4, 798e36ed00SAlex Deucher RADEON_HPD_5, 808e36ed00SAlex Deucher RADEON_HPD_6, 818e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 828e36ed00SAlex Deucher }; 838e36ed00SAlex Deucher 84f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 85f376b94fSAlex Deucher 869b9fe724SAlex Deucher /* radeon gpio-based i2c 879b9fe724SAlex Deucher * 1. "mask" reg and bits 889b9fe724SAlex Deucher * grabs the gpio pins for software use 899b9fe724SAlex Deucher * 0=not held 1=held 909b9fe724SAlex Deucher * 2. "a" reg and bits 919b9fe724SAlex Deucher * output pin value 929b9fe724SAlex Deucher * 0=low 1=high 939b9fe724SAlex Deucher * 3. "en" reg and bits 949b9fe724SAlex Deucher * sets the pin direction 959b9fe724SAlex Deucher * 0=input 1=output 969b9fe724SAlex Deucher * 4. "y" reg and bits 979b9fe724SAlex Deucher * input pin value 989b9fe724SAlex Deucher * 0=low 1=high 999b9fe724SAlex Deucher */ 100771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 101771fe6b9SJerome Glisse bool valid; 1026a93cb25SAlex Deucher /* id used by atom */ 1036a93cb25SAlex Deucher uint8_t i2c_id; 104bcc1c2a1SAlex Deucher /* id used by atom */ 1058e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1066a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1076a93cb25SAlex Deucher bool hw_capable; 1086a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1096a93cb25SAlex Deucher bool mm_i2c; 1106a93cb25SAlex Deucher /* regs and bits */ 111771fe6b9SJerome Glisse uint32_t mask_clk_reg; 112771fe6b9SJerome Glisse uint32_t mask_data_reg; 113771fe6b9SJerome Glisse uint32_t a_clk_reg; 114771fe6b9SJerome Glisse uint32_t a_data_reg; 1159b9fe724SAlex Deucher uint32_t en_clk_reg; 1169b9fe724SAlex Deucher uint32_t en_data_reg; 1179b9fe724SAlex Deucher uint32_t y_clk_reg; 1189b9fe724SAlex Deucher uint32_t y_data_reg; 119771fe6b9SJerome Glisse uint32_t mask_clk_mask; 120771fe6b9SJerome Glisse uint32_t mask_data_mask; 121771fe6b9SJerome Glisse uint32_t a_clk_mask; 122771fe6b9SJerome Glisse uint32_t a_data_mask; 1239b9fe724SAlex Deucher uint32_t en_clk_mask; 1249b9fe724SAlex Deucher uint32_t en_data_mask; 1259b9fe724SAlex Deucher uint32_t y_clk_mask; 1269b9fe724SAlex Deucher uint32_t y_data_mask; 127771fe6b9SJerome Glisse }; 128771fe6b9SJerome Glisse 129771fe6b9SJerome Glisse struct radeon_tmds_pll { 130771fe6b9SJerome Glisse uint32_t freq; 131771fe6b9SJerome Glisse uint32_t value; 132771fe6b9SJerome Glisse }; 133771fe6b9SJerome Glisse 134771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 135771fe6b9SJerome Glisse 1367c27f87dSAlex Deucher /* pll flags */ 137771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 140771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 141771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15086cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 151f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152771fe6b9SJerome Glisse 153771fe6b9SJerome Glisse struct radeon_pll { 154fc10332bSAlex Deucher /* reference frequency */ 155fc10332bSAlex Deucher uint32_t reference_freq; 156fc10332bSAlex Deucher 157fc10332bSAlex Deucher /* fixed dividers */ 158fc10332bSAlex Deucher uint32_t reference_div; 159fc10332bSAlex Deucher uint32_t post_div; 160fc10332bSAlex Deucher 161fc10332bSAlex Deucher /* pll in/out limits */ 162771fe6b9SJerome Glisse uint32_t pll_in_min; 163771fe6b9SJerome Glisse uint32_t pll_in_max; 164771fe6b9SJerome Glisse uint32_t pll_out_min; 165771fe6b9SJerome Glisse uint32_t pll_out_max; 16686cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 168fc10332bSAlex Deucher uint32_t best_vco; 169771fe6b9SJerome Glisse 170fc10332bSAlex Deucher /* divider limits */ 171771fe6b9SJerome Glisse uint32_t min_ref_div; 172771fe6b9SJerome Glisse uint32_t max_ref_div; 173771fe6b9SJerome Glisse uint32_t min_post_div; 174771fe6b9SJerome Glisse uint32_t max_post_div; 175771fe6b9SJerome Glisse uint32_t min_feedback_div; 176771fe6b9SJerome Glisse uint32_t max_feedback_div; 177771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 178771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 179fc10332bSAlex Deucher 180fc10332bSAlex Deucher /* flags for the current clock */ 181fc10332bSAlex Deucher uint32_t flags; 182fc10332bSAlex Deucher 183fc10332bSAlex Deucher /* pll id */ 184fc10332bSAlex Deucher uint32_t id; 185771fe6b9SJerome Glisse }; 186771fe6b9SJerome Glisse 187771fe6b9SJerome Glisse struct radeon_i2c_chan { 188771fe6b9SJerome Glisse struct i2c_adapter adapter; 189746c1aa4SDave Airlie struct drm_device *dev; 190746c1aa4SDave Airlie union { 191ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 192746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 193746c1aa4SDave Airlie } algo; 194771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 195771fe6b9SJerome Glisse }; 196771fe6b9SJerome Glisse 197771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 198771fe6b9SJerome Glisse enum radeon_connector_table { 199aa74fbb4SAlex Deucher CT_NONE = 0, 200771fe6b9SJerome Glisse CT_GENERIC, 201771fe6b9SJerome Glisse CT_IBOOK, 202771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 203771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 205771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 206771fe6b9SJerome Glisse CT_MINI_INTERNAL, 207771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 208771fe6b9SJerome Glisse CT_EMAC, 20976a7142aSDave Airlie CT_RN50_POWER, 210aa74fbb4SAlex Deucher CT_MAC_X800, 2119fad321aSAlex Deucher CT_MAC_G5_9600, 212cafa59b9SAlex Deucher CT_SAM440EP, 213cafa59b9SAlex Deucher CT_MAC_G4_SILVER 214771fe6b9SJerome Glisse }; 215771fe6b9SJerome Glisse 216fcec570bSAlex Deucher enum radeon_dvo_chip { 217fcec570bSAlex Deucher DVO_SIL164, 218fcec570bSAlex Deucher DVO_SIL1178, 219fcec570bSAlex Deucher }; 220fcec570bSAlex Deucher 2218be48d92SDave Airlie struct radeon_fbdev; 22238651674SDave Airlie 2230783986aSAlex Deucher struct radeon_afmt { 2240783986aSAlex Deucher bool enabled; 2250783986aSAlex Deucher int offset; 2260783986aSAlex Deucher bool last_buffer_filled_status; 2270783986aSAlex Deucher int id; 2280783986aSAlex Deucher }; 2290783986aSAlex Deucher 230771fe6b9SJerome Glisse struct radeon_mode_info { 231771fe6b9SJerome Glisse struct atom_context *atom_context; 23261c4b24bSMathias Fröhlich struct card_info *atom_card_info; 233771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 234771fe6b9SJerome Glisse bool mode_config_initialized; 235bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 2360783986aSAlex Deucher struct radeon_afmt *afmt[6]; 237445282dbSDave Airlie /* DVI-I properties */ 238445282dbSDave Airlie struct drm_property *coherent_mode_property; 239445282dbSDave Airlie /* DAC enable load detect */ 240445282dbSDave Airlie struct drm_property *load_detect_property; 2415b1714d3SAlex Deucher /* TV standard */ 242445282dbSDave Airlie struct drm_property *tv_std_property; 243445282dbSDave Airlie /* legacy TMDS PLL detect */ 244445282dbSDave Airlie struct drm_property *tmds_pll_property; 2455b1714d3SAlex Deucher /* underscan */ 2465b1714d3SAlex Deucher struct drm_property *underscan_property; 2475bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2485bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2493c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2503c537889SAlex Deucher struct edid *bios_hardcoded_edid; 251fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 25238651674SDave Airlie 25338651674SDave Airlie /* pointer to fbdev info structure */ 2548be48d92SDave Airlie struct radeon_fbdev *rfbdev; 255af7912e5SAlex Deucher /* firmware flags */ 256af7912e5SAlex Deucher u16 firmware_flags; 257bced76f2SAlex Deucher /* pointer to backlight encoder */ 258bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 259c93bb85bSJerome Glisse }; 260c93bb85bSJerome Glisse 26191030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 26291030880SAlex Deucher 263bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 264bced76f2SAlex Deucher 26591030880SAlex Deucher struct radeon_backlight_privdata { 26691030880SAlex Deucher struct radeon_encoder *encoder; 26791030880SAlex Deucher uint8_t negative; 26891030880SAlex Deucher }; 26991030880SAlex Deucher 27091030880SAlex Deucher #endif 27191030880SAlex Deucher 2724ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2734ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2744ce001abSDave Airlie 2754ce001abSDave Airlie /* need to store these as reading 2764ce001abSDave Airlie back code tables is excessive */ 2774ce001abSDave Airlie struct radeon_tv_regs { 2784ce001abSDave Airlie uint32_t tv_uv_adr; 2794ce001abSDave Airlie uint32_t timing_cntl; 2804ce001abSDave Airlie uint32_t hrestart; 2814ce001abSDave Airlie uint32_t vrestart; 2824ce001abSDave Airlie uint32_t frestart; 2834ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2844ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2854ce001abSDave Airlie }; 2864ce001abSDave Airlie 28719eca43eSAlex Deucher struct radeon_atom_ss { 28819eca43eSAlex Deucher uint16_t percentage; 28919eca43eSAlex Deucher uint8_t type; 29019eca43eSAlex Deucher uint16_t step; 29119eca43eSAlex Deucher uint8_t delay; 29219eca43eSAlex Deucher uint8_t range; 29319eca43eSAlex Deucher uint8_t refdiv; 29419eca43eSAlex Deucher /* asic_ss */ 29519eca43eSAlex Deucher uint16_t rate; 29619eca43eSAlex Deucher uint16_t amount; 29719eca43eSAlex Deucher }; 29819eca43eSAlex Deucher 299771fe6b9SJerome Glisse struct radeon_crtc { 300771fe6b9SJerome Glisse struct drm_crtc base; 301771fe6b9SJerome Glisse int crtc_id; 302771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 303771fe6b9SJerome Glisse bool enabled; 304771fe6b9SJerome Glisse bool can_tile; 305771fe6b9SJerome Glisse uint32_t crtc_offset; 306771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 307771fe6b9SJerome Glisse uint64_t cursor_addr; 308771fe6b9SJerome Glisse int cursor_width; 309771fe6b9SJerome Glisse int cursor_height; 3109e05fa1dSAlex Deucher int max_cursor_width; 3119e05fa1dSAlex Deucher int max_cursor_height; 3124162338aSDave Airlie uint32_t legacy_display_base_addr; 313c836e862SAlex Deucher uint32_t legacy_cursor_offset; 314c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3155b1714d3SAlex Deucher u8 h_border; 3165b1714d3SAlex Deucher u8 v_border; 317c93bb85bSJerome Glisse fixed20_12 vsc; 318c93bb85bSJerome Glisse fixed20_12 hsc; 319de2103e4SAlex Deucher struct drm_display_mode native_mode; 320bcc1c2a1SAlex Deucher int pll_id; 3216f34be50SAlex Deucher /* page flipping */ 3226f34be50SAlex Deucher struct radeon_unpin_work *unpin_work; 3236f34be50SAlex Deucher int deferred_flip_completion; 32419eca43eSAlex Deucher /* pll sharing */ 32519eca43eSAlex Deucher struct radeon_atom_ss ss; 32619eca43eSAlex Deucher bool ss_enabled; 32719eca43eSAlex Deucher u32 adjusted_clock; 32819eca43eSAlex Deucher int bpc; 32919eca43eSAlex Deucher u32 pll_reference_div; 33019eca43eSAlex Deucher u32 pll_post_div; 33119eca43eSAlex Deucher u32 pll_flags; 3325df3196bSAlex Deucher struct drm_encoder *encoder; 33357b35e29SAlex Deucher struct drm_connector *connector; 334771fe6b9SJerome Glisse }; 335771fe6b9SJerome Glisse 336771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 337771fe6b9SJerome Glisse /* legacy primary dac */ 338771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 339771fe6b9SJerome Glisse }; 340771fe6b9SJerome Glisse 341771fe6b9SJerome Glisse struct radeon_encoder_lvds { 342771fe6b9SJerome Glisse /* legacy lvds */ 343771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 344771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 345771fe6b9SJerome Glisse uint8_t panel_digon_delay; 346771fe6b9SJerome Glisse uint8_t panel_blon_delay; 347771fe6b9SJerome Glisse uint16_t panel_ref_divider; 348771fe6b9SJerome Glisse uint8_t panel_post_divider; 349771fe6b9SJerome Glisse uint16_t panel_fb_divider; 350771fe6b9SJerome Glisse bool use_bios_dividers; 351771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 352771fe6b9SJerome Glisse /* panel mode */ 353de2103e4SAlex Deucher struct drm_display_mode native_mode; 35463ec0119SMichel Dänzer struct backlight_device *bl_dev; 35563ec0119SMichel Dänzer int dpms_mode; 35663ec0119SMichel Dänzer uint8_t backlight_level; 357771fe6b9SJerome Glisse }; 358771fe6b9SJerome Glisse 359771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 360771fe6b9SJerome Glisse /* legacy tv dac */ 361771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 362771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 363771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 364771fe6b9SJerome Glisse 3654ce001abSDave Airlie int h_pos; 3664ce001abSDave Airlie int v_pos; 3674ce001abSDave Airlie int h_size; 3684ce001abSDave Airlie int supported_tv_stds; 3694ce001abSDave Airlie bool tv_on; 370771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3714ce001abSDave Airlie struct radeon_tv_regs tv; 372771fe6b9SJerome Glisse }; 373771fe6b9SJerome Glisse 374771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 375771fe6b9SJerome Glisse /* legacy int tmds */ 376771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 377771fe6b9SJerome Glisse }; 378771fe6b9SJerome Glisse 379fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 380fcec570bSAlex Deucher /* tmds over dvo */ 381fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 382fcec570bSAlex Deucher uint8_t slave_addr; 383fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 384fcec570bSAlex Deucher }; 385fcec570bSAlex Deucher 386ebbe1cb9SAlex Deucher /* spread spectrum */ 387771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3885137ee94SAlex Deucher bool linkb; 389771fe6b9SJerome Glisse /* atom dig */ 390771fe6b9SJerome Glisse bool coherent_mode; 391ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 392ba032a58SAlex Deucher /* atom lvds/edp */ 393ba032a58SAlex Deucher uint32_t lcd_misc; 394771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 395ba032a58SAlex Deucher uint32_t lcd_ss_id; 396771fe6b9SJerome Glisse /* panel mode */ 397de2103e4SAlex Deucher struct drm_display_mode native_mode; 39863ec0119SMichel Dänzer struct backlight_device *bl_dev; 39963ec0119SMichel Dänzer int dpms_mode; 40063ec0119SMichel Dänzer uint8_t backlight_level; 401386d4d75SAlex Deucher int panel_mode; 4020783986aSAlex Deucher struct radeon_afmt *afmt; 403771fe6b9SJerome Glisse }; 404771fe6b9SJerome Glisse 4054ce001abSDave Airlie struct radeon_encoder_atom_dac { 4064ce001abSDave Airlie enum radeon_tv_std tv_std; 4074ce001abSDave Airlie }; 4084ce001abSDave Airlie 409771fe6b9SJerome Glisse struct radeon_encoder { 410771fe6b9SJerome Glisse struct drm_encoder base; 4115137ee94SAlex Deucher uint32_t encoder_enum; 412771fe6b9SJerome Glisse uint32_t encoder_id; 413771fe6b9SJerome Glisse uint32_t devices; 4144ce001abSDave Airlie uint32_t active_device; 415771fe6b9SJerome Glisse uint32_t flags; 416771fe6b9SJerome Glisse uint32_t pixel_clock; 417771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4185b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4195bccf5e3SMarius Gröger uint32_t underscan_hborder; 4205bccf5e3SMarius Gröger uint32_t underscan_vborder; 421de2103e4SAlex Deucher struct drm_display_mode native_mode; 422771fe6b9SJerome Glisse void *enc_priv; 42358bd0863SChristian König int audio_polling_active; 4243e4b9982SAlex Deucher bool is_ext_encoder; 42536868bdaSAlex Deucher u16 caps; 426771fe6b9SJerome Glisse }; 427771fe6b9SJerome Glisse 428771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 429771fe6b9SJerome Glisse uint32_t igp_lane_info; 4304143e919SAlex Deucher /* displayport */ 431746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 4321a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4334143e919SAlex Deucher u8 dp_sink_type; 4345801ead6SAlex Deucher int dp_clock; 4355801ead6SAlex Deucher int dp_lane_count; 4368b834852SAlex Deucher bool edp_on; 437771fe6b9SJerome Glisse }; 438771fe6b9SJerome Glisse 439eed45b30SAlex Deucher struct radeon_gpio_rec { 440eed45b30SAlex Deucher bool valid; 441eed45b30SAlex Deucher u8 id; 442eed45b30SAlex Deucher u32 reg; 443eed45b30SAlex Deucher u32 mask; 444eed45b30SAlex Deucher }; 445eed45b30SAlex Deucher 446eed45b30SAlex Deucher struct radeon_hpd { 447eed45b30SAlex Deucher enum radeon_hpd_id hpd; 448eed45b30SAlex Deucher u8 plugged_state; 449eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 450eed45b30SAlex Deucher }; 451eed45b30SAlex Deucher 45226b5bc98SAlex Deucher struct radeon_router { 45326b5bc98SAlex Deucher u32 router_id; 45426b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 45526b5bc98SAlex Deucher u8 i2c_addr; 456fb939dfcSAlex Deucher /* i2c mux */ 457fb939dfcSAlex Deucher bool ddc_valid; 458fb939dfcSAlex Deucher u8 ddc_mux_type; 459fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 460fb939dfcSAlex Deucher u8 ddc_mux_state; 461fb939dfcSAlex Deucher /* clock/data mux */ 462fb939dfcSAlex Deucher bool cd_valid; 463fb939dfcSAlex Deucher u8 cd_mux_type; 464fb939dfcSAlex Deucher u8 cd_mux_control_pin; 465fb939dfcSAlex Deucher u8 cd_mux_state; 46626b5bc98SAlex Deucher }; 46726b5bc98SAlex Deucher 468771fe6b9SJerome Glisse struct radeon_connector { 469771fe6b9SJerome Glisse struct drm_connector base; 470771fe6b9SJerome Glisse uint32_t connector_id; 471771fe6b9SJerome Glisse uint32_t devices; 472771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4735b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4740294cf4fSAlex Deucher bool shared_ddc; 4754ce001abSDave Airlie bool use_digital; 4764ce001abSDave Airlie /* we need to mind the EDID between detect 4774ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4784ce001abSDave Airlie struct edid *edid; 479771fe6b9SJerome Glisse void *con_priv; 480445282dbSDave Airlie bool dac_load_detect; 481d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 482b75fad06SAlex Deucher uint16_t connector_object_id; 483eed45b30SAlex Deucher struct radeon_hpd hpd; 48426b5bc98SAlex Deucher struct radeon_router router; 48526b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 486771fe6b9SJerome Glisse }; 487771fe6b9SJerome Glisse 488771fe6b9SJerome Glisse struct radeon_framebuffer { 489771fe6b9SJerome Glisse struct drm_framebuffer base; 490771fe6b9SJerome Glisse struct drm_gem_object *obj; 491771fe6b9SJerome Glisse }; 492771fe6b9SJerome Glisse 493996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 494996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 4956383cf7dSMario Kleiner 4967062ab67SChristian König struct atom_clock_dividers { 4977062ab67SChristian König u32 post_div; 4987062ab67SChristian König union { 4997062ab67SChristian König struct { 5007062ab67SChristian König #ifdef __BIG_ENDIAN 5017062ab67SChristian König u32 reserved : 6; 5027062ab67SChristian König u32 whole_fb_div : 12; 5037062ab67SChristian König u32 frac_fb_div : 14; 5047062ab67SChristian König #else 5057062ab67SChristian König u32 frac_fb_div : 14; 5067062ab67SChristian König u32 whole_fb_div : 12; 5077062ab67SChristian König u32 reserved : 6; 5087062ab67SChristian König #endif 5097062ab67SChristian König }; 5107062ab67SChristian König u32 fb_div; 5117062ab67SChristian König }; 5127062ab67SChristian König u32 ref_div; 5137062ab67SChristian König bool enable_post_div; 5147062ab67SChristian König bool enable_dithen; 5157062ab67SChristian König u32 vco_mode; 5167062ab67SChristian König u32 real_clock; 5179219ed65SAlex Deucher /* added for CI */ 5189219ed65SAlex Deucher u32 post_divider; 5199219ed65SAlex Deucher u32 flags; 5207062ab67SChristian König }; 5217062ab67SChristian König 522eaa778afSAlex Deucher struct atom_mpll_param { 523eaa778afSAlex Deucher union { 524eaa778afSAlex Deucher struct { 525eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 526eaa778afSAlex Deucher u32 reserved : 8; 527eaa778afSAlex Deucher u32 clkfrac : 12; 528eaa778afSAlex Deucher u32 clkf : 12; 529eaa778afSAlex Deucher #else 530eaa778afSAlex Deucher u32 clkf : 12; 531eaa778afSAlex Deucher u32 clkfrac : 12; 532eaa778afSAlex Deucher u32 reserved : 8; 533eaa778afSAlex Deucher #endif 534eaa778afSAlex Deucher }; 535eaa778afSAlex Deucher u32 fb_div; 536eaa778afSAlex Deucher }; 537eaa778afSAlex Deucher u32 post_div; 538eaa778afSAlex Deucher u32 bwcntl; 539eaa778afSAlex Deucher u32 dll_speed; 540eaa778afSAlex Deucher u32 vco_mode; 541eaa778afSAlex Deucher u32 yclk_sel; 542eaa778afSAlex Deucher u32 qdr; 543eaa778afSAlex Deucher u32 half_rate; 544eaa778afSAlex Deucher }; 545eaa778afSAlex Deucher 546ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 547ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 548ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 549ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 550ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 551ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 552ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 553ae5b0abbSAlex Deucher 554ae5b0abbSAlex Deucher struct atom_memory_info { 555ae5b0abbSAlex Deucher u8 mem_vendor; 556ae5b0abbSAlex Deucher u8 mem_type; 557ae5b0abbSAlex Deucher }; 558ae5b0abbSAlex Deucher 559ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 560ae5b0abbSAlex Deucher 561ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 562ae5b0abbSAlex Deucher { 563ae5b0abbSAlex Deucher u8 num_entries; 564ae5b0abbSAlex Deucher u8 rsv[3]; 565ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 566ae5b0abbSAlex Deucher }; 567ae5b0abbSAlex Deucher 568ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 569ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 570ae5b0abbSAlex Deucher 571ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 572ae5b0abbSAlex Deucher u32 mclk_max; 573ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 574ae5b0abbSAlex Deucher }; 575ae5b0abbSAlex Deucher 576ae5b0abbSAlex Deucher struct atom_mc_register_address { 577ae5b0abbSAlex Deucher u16 s1; 578ae5b0abbSAlex Deucher u8 pre_reg_data; 579ae5b0abbSAlex Deucher }; 580ae5b0abbSAlex Deucher 581ae5b0abbSAlex Deucher struct atom_mc_reg_table { 582ae5b0abbSAlex Deucher u8 last; 583ae5b0abbSAlex Deucher u8 num_entries; 584ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 585ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 586ae5b0abbSAlex Deucher }; 587ae5b0abbSAlex Deucher 588ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 589ae5b0abbSAlex Deucher 590ae5b0abbSAlex Deucher struct atom_voltage_table_entry 591ae5b0abbSAlex Deucher { 592ae5b0abbSAlex Deucher u16 value; 593ae5b0abbSAlex Deucher u32 smio_low; 594ae5b0abbSAlex Deucher }; 595ae5b0abbSAlex Deucher 596ae5b0abbSAlex Deucher struct atom_voltage_table 597ae5b0abbSAlex Deucher { 598ae5b0abbSAlex Deucher u32 count; 599ae5b0abbSAlex Deucher u32 mask_low; 600ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 601ae5b0abbSAlex Deucher }; 602ae5b0abbSAlex Deucher 603d79766faSAlex Deucher extern enum radeon_tv_std 604d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 605d79766faSAlex Deucher extern enum radeon_tv_std 606d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 6074a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 6084a6369e9SAlex Deucher u16 *vddc, u16 *vddci); 609d79766faSAlex Deucher 6105b1714d3SAlex Deucher extern struct drm_connector * 6115b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 6129aa59993SAlex Deucher extern struct drm_connector * 6139aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 6149aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 6159aa59993SAlex Deucher u32 pixel_clock); 6165b1714d3SAlex Deucher 6171d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 6181d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 619d7fa8bb3SAlex Deucher extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 620d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 621eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 622d7fa8bb3SAlex Deucher 623d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 624224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 6255801ead6SAlex Deucher struct drm_display_mode *mode); 6265801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 627e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 628224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 6295801ead6SAlex Deucher struct drm_connector *connector); 630d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 6314143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 6329fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 633386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 634386d4d75SAlex Deucher struct drm_connector *connector); 635558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 636ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 637f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 6385801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 6395801ead6SAlex Deucher int action, uint8_t lane_num, 6405801ead6SAlex Deucher uint8_t lane_set); 641591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 6423f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 643746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 644834b2904SAlex Deucher u8 write_byte, u8 *read_byte); 645746c1aa4SDave Airlie 646f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 647f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 648f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 649f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 650f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 651f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 652f376b94fSAlex Deucher const char *name); 653f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 654f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 655746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 6566a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 6576a93cb25SAlex Deucher const char *name); 658771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 659771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 660771fe6b9SJerome Glisse const char *name); 661771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 6625a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 663fcec570bSAlex Deucher u8 slave_addr, 664fcec570bSAlex Deucher u8 addr, 665fcec570bSAlex Deucher u8 *val); 6665a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 667fcec570bSAlex Deucher u8 slave_addr, 668fcec570bSAlex Deucher u8 addr, 669fcec570bSAlex Deucher u8 val); 670fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 671fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 6720a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 673771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 674771fe6b9SJerome Glisse 675771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 676771fe6b9SJerome Glisse 677ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 678ba032a58SAlex Deucher struct radeon_atom_ss *ss, 679ba032a58SAlex Deucher int id); 680ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 681ba032a58SAlex Deucher struct radeon_atom_ss *ss, 682ba032a58SAlex Deucher int id, u32 clock); 683ba032a58SAlex Deucher 684f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 685771fe6b9SJerome Glisse uint64_t freq, 686771fe6b9SJerome Glisse uint32_t *dot_clock_p, 687771fe6b9SJerome Glisse uint32_t *fb_div_p, 688771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 689771fe6b9SJerome Glisse uint32_t *ref_div_p, 690fc10332bSAlex Deucher uint32_t *post_div_p); 691771fe6b9SJerome Glisse 692f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 693f523f74eSAlex Deucher u32 freq, 694f523f74eSAlex Deucher u32 *dot_clock_p, 695f523f74eSAlex Deucher u32 *fb_div_p, 696f523f74eSAlex Deucher u32 *frac_fb_div_p, 697f523f74eSAlex Deucher u32 *ref_div_p, 698f523f74eSAlex Deucher u32 *post_div_p); 699f523f74eSAlex Deucher 7001f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 7011f3b6a45SDave Airlie 702771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 703771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 704771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 705771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 706771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 70799999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 70832f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 709771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 7102dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 7114ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 712771fe6b9SJerome Glisse 713771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 714771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 715771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 7164dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 7174dd19b0dSChris Ball struct drm_framebuffer *fb, 71821c74a8eSJason Wessel int x, int y, 71921c74a8eSJason Wessel enum mode_set_atomic state); 720771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 721771fe6b9SJerome Glisse struct drm_display_mode *mode, 722771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 723771fe6b9SJerome Glisse int x, int y, 724771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 725771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 726771fe6b9SJerome Glisse 727771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 728771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 7294dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 7304dd19b0dSChris Ball struct drm_framebuffer *fb, 73121c74a8eSJason Wessel int x, int y, 73221c74a8eSJason Wessel enum mode_set_atomic state); 7334dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 7344dd19b0dSChris Ball struct drm_framebuffer *fb, 7354dd19b0dSChris Ball int x, int y, int atomic); 736771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 737771fe6b9SJerome Glisse struct drm_file *file_priv, 738771fe6b9SJerome Glisse uint32_t handle, 739771fe6b9SJerome Glisse uint32_t width, 740771fe6b9SJerome Glisse uint32_t height); 741771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 742771fe6b9SJerome Glisse int x, int y); 743771fe6b9SJerome Glisse 744f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 745f5a80209SMario Kleiner int *vpos, int *hpos); 7466383cf7dSMario Kleiner 7473c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 7483c537889SAlex Deucher extern struct edid * 749c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 750771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 751771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 752771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 753771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 754fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 755445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 756fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 757445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 758fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 759445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 760fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 761fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 762fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 763fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 7646fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 7656fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 7666fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 7676fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 768771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 769771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 770771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 771771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 772771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 773771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 774771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 775fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 776fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 777771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 778771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 779771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 780771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 781f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 782f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 783771fe6b9SJerome Glisse extern void 784771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 785771fe6b9SJerome Glisse extern void 786771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 787771fe6b9SJerome Glisse extern void 788771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 789771fe6b9SJerome Glisse extern void 790771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 791771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 792771fe6b9SJerome Glisse u16 blue, int regno); 793b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 794b8c00ac5SDave Airlie u16 *blue, int regno); 795aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 79638651674SDave Airlie struct radeon_framebuffer *rfb, 797308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 798771fe6b9SJerome Glisse struct drm_gem_object *obj); 799771fe6b9SJerome Glisse 800771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 801771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 802771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 803771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 804771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 805771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 806771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 807771fe6b9SJerome Glisse 808771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 809771fe6b9SJerome Glisse 810771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 811771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 812771fe6b9SJerome Glisse 813771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 814771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 815771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 816c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 817e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 818c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 8193515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 8203515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 8214ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 822771fe6b9SJerome Glisse 8234ce001abSDave Airlie /* legacy tv */ 8244ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 8254ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 8264ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 8274ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 8284ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 8294ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 8304ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 8314ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 8324ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 8334ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 8344ce001abSDave Airlie struct drm_display_mode *mode, 8354ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 83638651674SDave Airlie 83738651674SDave Airlie /* fbdev layer */ 83838651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 83938651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 84038651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 84138651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 84238651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 843eb1f8e4fSDave Airlie 844eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 8456f34be50SAlex Deucher 8466f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 8476f34be50SAlex Deucher 848ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 849771fe6b9SJerome Glisse #endif 850